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26f0fd2f0366385818a9e27a8a3d02922b53004c
[openwrt/openwrt.git] / target / linux / generic / files / drivers / ssb / fallback-sprom.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * SSB Fallback SPROM Driver
4 *
5 * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
6 * Copyright (C) 2014 Jonas Gorski <jonas.gorski@gmail.com>
7 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
8 * Copyright (C) 2008 Florian Fainelli <f.fainelli@gmail.com>
9 */
10
11 #include <linux/etherdevice.h>
12 #include <linux/firmware.h>
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/of_net.h>
17 #include <linux/of_platform.h>
18 #include <linux/ssb/ssb.h>
19
20 #define SSB_FBS_MAX_SIZE 440
21
22 /* Get the word-offset for a SSB_SPROM_XXX define. */
23 #define SPOFF(offset) ((offset) / sizeof(u16))
24 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
25 #define SPEX16(_outvar, _offset, _mask, _shift) \
26 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
27 #define SPEX32(_outvar, _offset, _mask, _shift) \
28 out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
29 in[SPOFF(_offset)]) & (_mask)) >> (_shift))
30 #define SPEX(_outvar, _offset, _mask, _shift) \
31 SPEX16(_outvar, _offset, _mask, _shift)
32
33 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
34 do { \
35 SPEX(_field[0], _offset + 0, _mask, _shift); \
36 SPEX(_field[1], _offset + 2, _mask, _shift); \
37 SPEX(_field[2], _offset + 4, _mask, _shift); \
38 SPEX(_field[3], _offset + 6, _mask, _shift); \
39 SPEX(_field[4], _offset + 8, _mask, _shift); \
40 SPEX(_field[5], _offset + 10, _mask, _shift); \
41 SPEX(_field[6], _offset + 12, _mask, _shift); \
42 SPEX(_field[7], _offset + 14, _mask, _shift); \
43 } while (0)
44
45 struct ssb_fbs {
46 struct device *dev;
47 struct list_head list;
48 struct ssb_sprom sprom;
49 u32 pci_bus;
50 u32 pci_dev;
51 bool devid_override;
52 };
53
54 static DEFINE_SPINLOCK(ssb_fbs_lock);
55 static struct list_head ssb_fbs_list = LIST_HEAD_INIT(ssb_fbs_list);
56
57 int ssb_get_fallback_sprom(struct ssb_bus *bus, struct ssb_sprom *out)
58 {
59 struct ssb_fbs *pos;
60 u32 pci_bus, pci_dev;
61
62 if (bus->bustype != SSB_BUSTYPE_PCI)
63 return -ENOENT;
64
65 pci_bus = bus->host_pci->bus->number;
66 pci_dev = PCI_SLOT(bus->host_pci->devfn);
67
68 list_for_each_entry(pos, &ssb_fbs_list, list) {
69 if (pos->pci_bus != pci_bus ||
70 pos->pci_dev != pci_dev)
71 continue;
72
73 if (pos->devid_override)
74 bus->host_pci->device = pos->sprom.dev_id;
75
76 memcpy(out, &pos->sprom, sizeof(struct ssb_sprom));
77 dev_info(pos->dev, "requested by [%x:%x]",
78 pos->pci_bus, pos->pci_dev);
79
80 return 0;
81 }
82
83 pr_err("unable to fill SPROM for [%x:%x]\n", pci_bus, pci_dev);
84
85 return -EINVAL;
86 }
87
88 static s8 sprom_extract_antgain(u8 sprom_revision, const u16 *in, u16 offset,
89 u16 mask, u16 shift)
90 {
91 u16 v;
92 u8 gain;
93
94 v = in[SPOFF(offset)];
95 gain = (v & mask) >> shift;
96 if (gain == 0xFF)
97 gain = 2; /* If unset use 2dBm */
98 if (sprom_revision == 1) {
99 /* Convert to Q5.2 */
100 gain <<= 2;
101 } else {
102 /* Q5.2 Fractional part is stored in 0xC0 */
103 gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
104 }
105
106 return (s8)gain;
107 }
108
109 static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
110 {
111 SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
112 SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
113 SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
114 SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
115 SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
116 SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
117 SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
118 SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
119 SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
120 SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
121 SSB_SPROM2_MAXP_A_LO_SHIFT);
122 }
123
124 static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
125 {
126 SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
127 SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
128 SSB_SPROM1_ETHPHY_ET1A_SHIFT);
129 SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
130 SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
131 SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
132 SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
133 if (out->revision == 1)
134 SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
135 SSB_SPROM1_BINF_CCODE_SHIFT);
136 SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
137 SSB_SPROM1_BINF_ANTA_SHIFT);
138 SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
139 SSB_SPROM1_BINF_ANTBG_SHIFT);
140 SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0);
141 SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0);
142 SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0);
143 SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0);
144 SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0);
145 SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0);
146 SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0);
147 SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1,
148 SSB_SPROM1_GPIOA_P1_SHIFT);
149 SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0);
150 SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3,
151 SSB_SPROM1_GPIOB_P3_SHIFT);
152 SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A,
153 SSB_SPROM1_MAXPWR_A_SHIFT);
154 SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG, 0);
155 SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A,
156 SSB_SPROM1_ITSSI_A_SHIFT);
157 SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
158 SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
159
160 SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
161 SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
162
163 /* Extract the antenna gain values. */
164 out->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,
165 SSB_SPROM1_AGAIN,
166 SSB_SPROM1_AGAIN_BG,
167 SSB_SPROM1_AGAIN_BG_SHIFT);
168 out->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,
169 SSB_SPROM1_AGAIN,
170 SSB_SPROM1_AGAIN_A,
171 SSB_SPROM1_AGAIN_A_SHIFT);
172 if (out->revision >= 2)
173 sprom_extract_r23(out, in);
174 }
175
176 /* Revs 4 5 and 8 have partially shared layout */
177 static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
178 {
179 SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
180 SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
181 SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
182 SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
183 SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
184 SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
185 SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
186 SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
187
188 SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
189 SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
190 SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
191 SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
192 SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
193 SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
194 SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
195 SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
196
197 SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
198 SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
199 SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
200 SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
201 SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
202 SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
203 SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
204 SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
205
206 SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
207 SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
208 SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
209 SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
210 SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
211 SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
212 SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
213 SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
214 }
215
216 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
217 {
218 static const u16 pwr_info_offset[] = {
219 SSB_SPROM4_PWR_INFO_CORE0, SSB_SPROM4_PWR_INFO_CORE1,
220 SSB_SPROM4_PWR_INFO_CORE2, SSB_SPROM4_PWR_INFO_CORE3
221 };
222 int i;
223
224 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
225 ARRAY_SIZE(out->core_pwr_info));
226
227 SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
228 SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
229 SSB_SPROM4_ETHPHY_ET1A_SHIFT);
230 SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
231 SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
232 if (out->revision == 4) {
233 SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
234 SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
235 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
236 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
237 SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
238 SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
239 } else {
240 SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
241 SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
242 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
243 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
244 SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
245 SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
246 }
247 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
248 SSB_SPROM4_ANTAVAIL_A_SHIFT);
249 SPEX(ant_available_bg, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_BG,
250 SSB_SPROM4_ANTAVAIL_BG_SHIFT);
251 SPEX(maxpwr_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_MAXP_BG_MASK, 0);
252 SPEX(itssi_bg, SSB_SPROM4_MAXP_BG, SSB_SPROM4_ITSSI_BG,
253 SSB_SPROM4_ITSSI_BG_SHIFT);
254 SPEX(maxpwr_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_MAXP_A_MASK, 0);
255 SPEX(itssi_a, SSB_SPROM4_MAXP_A, SSB_SPROM4_ITSSI_A,
256 SSB_SPROM4_ITSSI_A_SHIFT);
257 if (out->revision == 4) {
258 SPEX(gpio0, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P0, 0);
259 SPEX(gpio1, SSB_SPROM4_GPIOA, SSB_SPROM4_GPIOA_P1,
260 SSB_SPROM4_GPIOA_P1_SHIFT);
261 SPEX(gpio2, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P2, 0);
262 SPEX(gpio3, SSB_SPROM4_GPIOB, SSB_SPROM4_GPIOB_P3,
263 SSB_SPROM4_GPIOB_P3_SHIFT);
264 } else {
265 SPEX(gpio0, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P0, 0);
266 SPEX(gpio1, SSB_SPROM5_GPIOA, SSB_SPROM5_GPIOA_P1,
267 SSB_SPROM5_GPIOA_P1_SHIFT);
268 SPEX(gpio2, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P2, 0);
269 SPEX(gpio3, SSB_SPROM5_GPIOB, SSB_SPROM5_GPIOB_P3,
270 SSB_SPROM5_GPIOB_P3_SHIFT);
271 }
272
273 /* Extract the antenna gain values. */
274 out->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,
275 SSB_SPROM4_AGAIN01,
276 SSB_SPROM4_AGAIN0,
277 SSB_SPROM4_AGAIN0_SHIFT);
278 out->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,
279 SSB_SPROM4_AGAIN01,
280 SSB_SPROM4_AGAIN1,
281 SSB_SPROM4_AGAIN1_SHIFT);
282 out->antenna_gain.a2 = sprom_extract_antgain(out->revision, in,
283 SSB_SPROM4_AGAIN23,
284 SSB_SPROM4_AGAIN2,
285 SSB_SPROM4_AGAIN2_SHIFT);
286 out->antenna_gain.a3 = sprom_extract_antgain(out->revision, in,
287 SSB_SPROM4_AGAIN23,
288 SSB_SPROM4_AGAIN3,
289 SSB_SPROM4_AGAIN3_SHIFT);
290
291 /* Extract cores power info info */
292 for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
293 u16 o = pwr_info_offset[i];
294
295 SPEX(core_pwr_info[i].itssi_2g, o + SSB_SPROM4_2G_MAXP_ITSSI,
296 SSB_SPROM4_2G_ITSSI, SSB_SPROM4_2G_ITSSI_SHIFT);
297 SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SPROM4_2G_MAXP_ITSSI,
298 SSB_SPROM4_2G_MAXP, 0);
299
300 SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SPROM4_2G_PA_0, ~0, 0);
301 SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SPROM4_2G_PA_1, ~0, 0);
302 SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SPROM4_2G_PA_2, ~0, 0);
303 SPEX(core_pwr_info[i].pa_2g[3], o + SSB_SPROM4_2G_PA_3, ~0, 0);
304
305 SPEX(core_pwr_info[i].itssi_5g, o + SSB_SPROM4_5G_MAXP_ITSSI,
306 SSB_SPROM4_5G_ITSSI, SSB_SPROM4_5G_ITSSI_SHIFT);
307 SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SPROM4_5G_MAXP_ITSSI,
308 SSB_SPROM4_5G_MAXP, 0);
309 SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM4_5GHL_MAXP,
310 SSB_SPROM4_5GH_MAXP, 0);
311 SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM4_5GHL_MAXP,
312 SSB_SPROM4_5GL_MAXP, SSB_SPROM4_5GL_MAXP_SHIFT);
313
314 SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SPROM4_5GL_PA_0, ~0, 0);
315 SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SPROM4_5GL_PA_1, ~0, 0);
316 SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SPROM4_5GL_PA_2, ~0, 0);
317 SPEX(core_pwr_info[i].pa_5gl[3], o + SSB_SPROM4_5GL_PA_3, ~0, 0);
318 SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SPROM4_5G_PA_0, ~0, 0);
319 SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SPROM4_5G_PA_1, ~0, 0);
320 SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SPROM4_5G_PA_2, ~0, 0);
321 SPEX(core_pwr_info[i].pa_5g[3], o + SSB_SPROM4_5G_PA_3, ~0, 0);
322 SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SPROM4_5GH_PA_0, ~0, 0);
323 SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SPROM4_5GH_PA_1, ~0, 0);
324 SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SPROM4_5GH_PA_2, ~0, 0);
325 SPEX(core_pwr_info[i].pa_5gh[3], o + SSB_SPROM4_5GH_PA_3, ~0, 0);
326 }
327
328 sprom_extract_r458(out, in);
329
330 /* TODO - get remaining rev 4 stuff needed */
331 }
332
333 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
334 {
335 int i;
336 u16 o;
337 static const u16 pwr_info_offset[] = {
338 SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
339 SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
340 };
341 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
342 ARRAY_SIZE(out->core_pwr_info));
343
344 SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
345 SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
346 SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
347 SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
348 SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
349 SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
350 SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
351 SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);
352 SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
353 SSB_SPROM8_ANTAVAIL_A_SHIFT);
354 SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
355 SSB_SPROM8_ANTAVAIL_BG_SHIFT);
356 SPEX(maxpwr_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_MAXP_BG_MASK, 0);
357 SPEX(itssi_bg, SSB_SPROM8_MAXP_BG, SSB_SPROM8_ITSSI_BG,
358 SSB_SPROM8_ITSSI_BG_SHIFT);
359 SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
360 SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
361 SSB_SPROM8_ITSSI_A_SHIFT);
362 SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
363 SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
364 SSB_SPROM8_MAXP_AL_SHIFT);
365 SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
366 SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
367 SSB_SPROM8_GPIOA_P1_SHIFT);
368 SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
369 SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
370 SSB_SPROM8_GPIOB_P3_SHIFT);
371 SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
372 SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
373 SSB_SPROM8_TRI5G_SHIFT);
374 SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
375 SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
376 SSB_SPROM8_TRI5GH_SHIFT);
377 SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);
378 SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
379 SSB_SPROM8_RXPO5G_SHIFT);
380 SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
381 SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
382 SSB_SPROM8_RSSISMC2G_SHIFT);
383 SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
384 SSB_SPROM8_RSSISAV2G_SHIFT);
385 SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
386 SSB_SPROM8_BXA2G_SHIFT);
387 SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
388 SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
389 SSB_SPROM8_RSSISMC5G_SHIFT);
390 SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
391 SSB_SPROM8_RSSISAV5G_SHIFT);
392 SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
393 SSB_SPROM8_BXA5G_SHIFT);
394 SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);
395 SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);
396 SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);
397 SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);
398 SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);
399 SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);
400 SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);
401 SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);
402 SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);
403 SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);
404 SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);
405 SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);
406 SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);
407 SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);
408 SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);
409 SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);
410 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
411
412 /* Extract the antenna gain values. */
413 out->antenna_gain.a0 = sprom_extract_antgain(out->revision, in,
414 SSB_SPROM8_AGAIN01,
415 SSB_SPROM8_AGAIN0,
416 SSB_SPROM8_AGAIN0_SHIFT);
417 out->antenna_gain.a1 = sprom_extract_antgain(out->revision, in,
418 SSB_SPROM8_AGAIN01,
419 SSB_SPROM8_AGAIN1,
420 SSB_SPROM8_AGAIN1_SHIFT);
421 out->antenna_gain.a2 = sprom_extract_antgain(out->revision, in,
422 SSB_SPROM8_AGAIN23,
423 SSB_SPROM8_AGAIN2,
424 SSB_SPROM8_AGAIN2_SHIFT);
425 out->antenna_gain.a3 = sprom_extract_antgain(out->revision, in,
426 SSB_SPROM8_AGAIN23,
427 SSB_SPROM8_AGAIN3,
428 SSB_SPROM8_AGAIN3_SHIFT);
429
430 /* Extract cores power info info */
431 for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
432 o = pwr_info_offset[i];
433 SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
434 SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
435 SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
436 SSB_SPROM8_2G_MAXP, 0);
437
438 SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
439 SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
440 SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
441
442 SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
443 SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
444 SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
445 SSB_SPROM8_5G_MAXP, 0);
446 SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
447 SSB_SPROM8_5GH_MAXP, 0);
448 SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
449 SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
450
451 SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
452 SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
453 SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
454 SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
455 SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
456 SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
457 SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
458 SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
459 SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
460 }
461
462 /* Extract FEM info */
463 SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
464 SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
465 SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
466 SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
467 SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
468 SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
469 SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
470 SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
471 SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
472 SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
473
474 SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
475 SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
476 SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
477 SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
478 SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
479 SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
480 SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
481 SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
482 SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
483 SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
484
485 SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
486 SSB_SPROM8_LEDDC_ON_SHIFT);
487 SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
488 SSB_SPROM8_LEDDC_OFF_SHIFT);
489
490 SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
491 SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
492 SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
493 SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
494 SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
495 SSB_SPROM8_TXRXC_SWITCH_SHIFT);
496
497 SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
498
499 SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
500 SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
501 SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
502 SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
503
504 SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
505 SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
506 SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
507 SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
508 SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
509 SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
510 SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
511 SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
512 SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
513 SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
514 SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
515 SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
516 SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
517 SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
518 SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
519 SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
520 SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
521 SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
522 SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
523 SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
524
525 SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
526 SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
527 SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
528 SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
529
530 SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
531 SSB_SPROM8_THERMAL_TRESH_SHIFT);
532 SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
533 SSB_SPROM8_THERMAL_OFFSET_SHIFT);
534 SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
535 SSB_SPROM8_TEMPDELTA_PHYCAL,
536 SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
537 SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
538 SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
539 SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
540 SSB_SPROM8_TEMPDELTA_HYSTERESIS,
541 SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
542 sprom_extract_r458(out, in);
543
544 /* TODO - get remaining rev 8 stuff needed */
545 }
546
547 static int sprom_extract(struct ssb_fbs *priv, const u16 *in, u16 size)
548 {
549 struct ssb_sprom *out = &priv->sprom;
550
551 memset(out, 0, sizeof(*out));
552
553 out->revision = in[size - 1] & 0x00FF;
554
555 switch (out->revision) {
556 case 1:
557 case 2:
558 case 3:
559 sprom_extract_r123(out, in);
560 break;
561 case 4:
562 case 5:
563 sprom_extract_r45(out, in);
564 break;
565 case 8:
566 sprom_extract_r8(out, in);
567 break;
568 default:
569 dev_warn(priv->dev,
570 "Unsupported SPROM revision %d detected."
571 " Will extract v1\n",
572 out->revision);
573 out->revision = 1;
574 sprom_extract_r123(out, in);
575 }
576
577 if (out->boardflags_lo == 0xFFFF)
578 out->boardflags_lo = 0; /* per specs */
579 if (out->boardflags_hi == 0xFFFF)
580 out->boardflags_hi = 0; /* per specs */
581
582 return 0;
583 }
584
585 static void ssb_fbs_fixup(struct ssb_fbs *priv, u16 *sprom)
586 {
587 struct device_node *node = priv->dev->of_node;
588 u32 fixups, off, val;
589 int i = 0;
590
591 if (!of_get_property(node, "brcm,sprom-fixups", &fixups))
592 return;
593
594 fixups /= sizeof(u32);
595
596 dev_info(priv->dev, "patching SPROM with %u fixups...\n", fixups >> 1);
597
598 while (i < fixups) {
599 if (of_property_read_u32_index(node, "brcm,sprom-fixups",
600 i++, &off)) {
601 dev_err(priv->dev, "error reading fixup[%u] offset\n",
602 i - 1);
603 return;
604 }
605
606 if (of_property_read_u32_index(node, "brcm,sprom-fixups",
607 i++, &val)) {
608 dev_err(priv->dev, "error reading fixup[%u] value\n",
609 i - 1);
610 return;
611 }
612
613 dev_dbg(priv->dev, "fixup[%d]=0x%04x\n", off, val);
614
615 sprom[off] = val;
616 }
617 }
618
619 static bool sprom_override_devid(struct ssb_fbs *priv, struct ssb_sprom *out,
620 const u16 *in)
621 {
622 SPEX(dev_id, SSB_SPROM1_PID, 0xFFFF, 0);
623 return !!out->dev_id;
624 }
625
626 static int ssb_fbs_set(struct ssb_fbs *priv, struct device_node *node)
627 {
628 struct ssb_sprom *sprom = &priv->sprom;
629 const struct firmware *fw;
630 const char *sprom_name;
631 int err;
632
633 if (of_property_read_string(node, "brcm,sprom", &sprom_name))
634 sprom_name = NULL;
635
636 if (sprom_name) {
637 err = request_firmware_direct(&fw, sprom_name, priv->dev);
638 if (err)
639 dev_err(priv->dev, "%s load error\n", sprom_name);
640 } else {
641 err = -ENOENT;
642 }
643
644 if (err) {
645 sprom->revision = 0x02;
646 sprom->board_rev = 0x0017;
647 sprom->country_code = 0x00;
648 sprom->ant_available_bg = 0x03;
649 sprom->pa0b0 = 0x15ae;
650 sprom->pa0b1 = 0xfa85;
651 sprom->pa0b2 = 0xfe8d;
652 sprom->pa1b0 = 0xffff;
653 sprom->pa1b1 = 0xffff;
654 sprom->pa1b2 = 0xffff;
655 sprom->gpio0 = 0xff;
656 sprom->gpio1 = 0xff;
657 sprom->gpio2 = 0xff;
658 sprom->gpio3 = 0xff;
659 sprom->maxpwr_bg = 0x4c;
660 sprom->itssi_bg = 0x00;
661 sprom->boardflags_lo = 0x2848;
662 sprom->boardflags_hi = 0x0000;
663 priv->devid_override = false;
664
665 dev_warn(priv->dev, "using basic SPROM\n");
666 } else {
667 size_t size = min(fw->size, (size_t) SSB_FBS_MAX_SIZE);
668 u16 tmp_sprom[SSB_FBS_MAX_SIZE >> 1];
669 u32 i, j;
670
671 for (i = 0, j = 0; i < size; i += 2, j++)
672 tmp_sprom[j] = (fw->data[i] << 8) | fw->data[i + 1];
673
674 release_firmware(fw);
675 ssb_fbs_fixup(priv, tmp_sprom);
676 sprom_extract(priv, tmp_sprom, size >> 1);
677
678 priv->devid_override = sprom_override_devid(priv, sprom,
679 tmp_sprom);
680 }
681
682 return 0;
683 }
684
685 static int ssb_fbs_probe(struct platform_device *pdev)
686 {
687 struct device *dev = &pdev->dev;
688 struct device_node *node = dev->of_node;
689 struct ssb_fbs *priv;
690 unsigned long flags;
691 u8 mac[ETH_ALEN];
692
693 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
694 if (!priv)
695 return -ENOMEM;
696
697 priv->dev = dev;
698
699 ssb_fbs_set(priv, node);
700
701 of_property_read_u32(node, "pci-bus", &priv->pci_bus);
702 of_property_read_u32(node, "pci-dev", &priv->pci_dev);
703
704 of_get_mac_address(node, mac);
705 if (is_valid_ether_addr(mac)) {
706 dev_info(dev, "mtd mac %pM\n", mac);
707 } else {
708 random_ether_addr(mac);
709 dev_info(dev, "random mac %pM\n", mac);
710 }
711
712 memcpy(priv->sprom.il0mac, mac, ETH_ALEN);
713 memcpy(priv->sprom.et0mac, mac, ETH_ALEN);
714 memcpy(priv->sprom.et1mac, mac, ETH_ALEN);
715 memcpy(priv->sprom.et2mac, mac, ETH_ALEN);
716
717 spin_lock_irqsave(&ssb_fbs_lock, flags);
718 list_add(&priv->list, &ssb_fbs_list);
719 spin_unlock_irqrestore(&ssb_fbs_lock, flags);
720
721 dev_info(dev, "registered SPROM for [%x:%x]\n",
722 priv->pci_bus, priv->pci_dev);
723
724 return 0;
725 }
726
727 static const struct of_device_id ssb_fbs_of_match[] = {
728 { .compatible = "brcm,ssb-sprom", },
729 { /* sentinel */ }
730 };
731 MODULE_DEVICE_TABLE(of, ssb_fbs_of_match);
732
733 static struct platform_driver ssb_fbs_driver = {
734 .probe = ssb_fbs_probe,
735 .driver = {
736 .name = "ssb-sprom",
737 .of_match_table = ssb_fbs_of_match,
738 },
739 };
740
741 int __init ssb_fbs_register(void)
742 {
743 return platform_driver_register(&ssb_fbs_driver);
744 }
OpenWrt Source Repository