2 * Platform driver for the Realtek RTL8367R/M ethernet switches
4 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/device.h>
16 #include <linux/of_platform.h>
17 #include <linux/delay.h>
18 #include <linux/skbuff.h>
19 #include <linux/rtl8367.h>
21 #include "rtl8366_smi.h"
23 #define RTL8367_RESET_DELAY 1000 /* msecs*/
25 #define RTL8367_PHY_ADDR_MAX 8
26 #define RTL8367_PHY_REG_MAX 31
28 #define RTL8367_VID_MASK 0xffff
29 #define RTL8367_FID_MASK 0xfff
30 #define RTL8367_UNTAG_MASK 0xffff
31 #define RTL8367_MEMBER_MASK 0xffff
33 #define RTL8367_PORT_CFG_REG(_p) (0x000e + 0x20 * (_p))
34 #define RTL8367_PORT_CFG_EGRESS_MODE_SHIFT 4
35 #define RTL8367_PORT_CFG_EGRESS_MODE_MASK 0x3
36 #define RTL8367_PORT_CFG_EGRESS_MODE_ORIGINAL 0
37 #define RTL8367_PORT_CFG_EGRESS_MODE_KEEP 1
38 #define RTL8367_PORT_CFG_EGRESS_MODE_PRI 2
39 #define RTL8367_PORT_CFG_EGRESS_MODE_REAL 3
41 #define RTL8367_BYPASS_LINE_RATE_REG 0x03f7
43 #define RTL8367_TA_CTRL_REG 0x0500
44 #define RTL8367_TA_CTRL_STATUS BIT(12)
45 #define RTL8367_TA_CTRL_METHOD BIT(5)
46 #define RTL8367_TA_CTRL_CMD_SHIFT 4
47 #define RTL8367_TA_CTRL_CMD_READ 0
48 #define RTL8367_TA_CTRL_CMD_WRITE 1
49 #define RTL8367_TA_CTRL_TABLE_SHIFT 0
50 #define RTL8367_TA_CTRL_TABLE_ACLRULE 1
51 #define RTL8367_TA_CTRL_TABLE_ACLACT 2
52 #define RTL8367_TA_CTRL_TABLE_CVLAN 3
53 #define RTL8367_TA_CTRL_TABLE_L2 4
54 #define RTL8367_TA_CTRL_CVLAN_READ \
55 ((RTL8367_TA_CTRL_CMD_READ << RTL8367_TA_CTRL_CMD_SHIFT) | \
56 RTL8367_TA_CTRL_TABLE_CVLAN)
57 #define RTL8367_TA_CTRL_CVLAN_WRITE \
58 ((RTL8367_TA_CTRL_CMD_WRITE << RTL8367_TA_CTRL_CMD_SHIFT) | \
59 RTL8367_TA_CTRL_TABLE_CVLAN)
61 #define RTL8367_TA_ADDR_REG 0x0501
62 #define RTL8367_TA_ADDR_MASK 0x3fff
64 #define RTL8367_TA_DATA_REG(_x) (0x0503 + (_x))
65 #define RTL8367_TA_VLAN_DATA_SIZE 4
66 #define RTL8367_TA_VLAN_VID_MASK RTL8367_VID_MASK
67 #define RTL8367_TA_VLAN_MEMBER_SHIFT 0
68 #define RTL8367_TA_VLAN_MEMBER_MASK RTL8367_MEMBER_MASK
69 #define RTL8367_TA_VLAN_FID_SHIFT 0
70 #define RTL8367_TA_VLAN_FID_MASK RTL8367_FID_MASK
71 #define RTL8367_TA_VLAN_UNTAG1_SHIFT 14
72 #define RTL8367_TA_VLAN_UNTAG1_MASK 0x3
73 #define RTL8367_TA_VLAN_UNTAG2_SHIFT 0
74 #define RTL8367_TA_VLAN_UNTAG2_MASK 0x3fff
76 #define RTL8367_VLAN_PVID_CTRL_REG(_p) (0x0700 + (_p) / 2)
77 #define RTL8367_VLAN_PVID_CTRL_MASK 0x1f
78 #define RTL8367_VLAN_PVID_CTRL_SHIFT(_p) (8 * ((_p) % 2))
80 #define RTL8367_VLAN_MC_BASE(_x) (0x0728 + (_x) * 4)
81 #define RTL8367_VLAN_MC_DATA_SIZE 4
82 #define RTL8367_VLAN_MC_MEMBER_SHIFT 0
83 #define RTL8367_VLAN_MC_MEMBER_MASK RTL8367_MEMBER_MASK
84 #define RTL8367_VLAN_MC_FID_SHIFT 0
85 #define RTL8367_VLAN_MC_FID_MASK RTL8367_FID_MASK
86 #define RTL8367_VLAN_MC_EVID_SHIFT 0
87 #define RTL8367_VLAN_MC_EVID_MASK RTL8367_VID_MASK
89 #define RTL8367_VLAN_CTRL_REG 0x07a8
90 #define RTL8367_VLAN_CTRL_ENABLE BIT(0)
92 #define RTL8367_VLAN_INGRESS_REG 0x07a9
94 #define RTL8367_PORT_ISOLATION_REG(_p) (0x08a2 + (_p))
96 #define RTL8367_MIB_COUNTER_REG(_x) (0x1000 + (_x))
98 #define RTL8367_MIB_ADDRESS_REG 0x1004
100 #define RTL8367_MIB_CTRL_REG(_x) (0x1005 + (_x))
101 #define RTL8367_MIB_CTRL_GLOBAL_RESET_MASK BIT(11)
102 #define RTL8367_MIB_CTRL_QM_RESET_MASK BIT(10)
103 #define RTL8367_MIB_CTRL_PORT_RESET_MASK(_p) BIT(2 + (_p))
104 #define RTL8367_MIB_CTRL_RESET_MASK BIT(1)
105 #define RTL8367_MIB_CTRL_BUSY_MASK BIT(0)
107 #define RTL8367_MIB_COUNT 36
108 #define RTL8367_MIB_COUNTER_PORT_OFFSET 0x0050
110 #define RTL8367_SWC0_REG 0x1200
111 #define RTL8367_SWC0_MAX_LENGTH_SHIFT 13
112 #define RTL8367_SWC0_MAX_LENGTH(_x) ((_x) << 13)
113 #define RTL8367_SWC0_MAX_LENGTH_MASK RTL8367_SWC0_MAX_LENGTH(0x3)
114 #define RTL8367_SWC0_MAX_LENGTH_1522 RTL8367_SWC0_MAX_LENGTH(0)
115 #define RTL8367_SWC0_MAX_LENGTH_1536 RTL8367_SWC0_MAX_LENGTH(1)
116 #define RTL8367_SWC0_MAX_LENGTH_1552 RTL8367_SWC0_MAX_LENGTH(2)
117 #define RTL8367_SWC0_MAX_LENGTH_16000 RTL8367_SWC0_MAX_LENGTH(3)
119 #define RTL8367_CHIP_NUMBER_REG 0x1300
121 #define RTL8367_CHIP_VER_REG 0x1301
122 #define RTL8367_CHIP_VER_RLVID_SHIFT 12
123 #define RTL8367_CHIP_VER_RLVID_MASK 0xf
124 #define RTL8367_CHIP_VER_MCID_SHIFT 8
125 #define RTL8367_CHIP_VER_MCID_MASK 0xf
126 #define RTL8367_CHIP_VER_BOID_SHIFT 4
127 #define RTL8367_CHIP_VER_BOID_MASK 0xf
129 #define RTL8367_CHIP_MODE_REG 0x1302
130 #define RTL8367_CHIP_MODE_MASK 0x7
132 #define RTL8367_CHIP_DEBUG0_REG 0x1303
133 #define RTL8367_CHIP_DEBUG0_DUMMY0(_x) BIT(8 + (_x))
135 #define RTL8367_CHIP_DEBUG1_REG 0x1304
137 #define RTL8367_DIS_REG 0x1305
138 #define RTL8367_DIS_SKIP_MII_RXER(_x) BIT(12 + (_x))
139 #define RTL8367_DIS_RGMII_SHIFT(_x) (4 * (_x))
140 #define RTL8367_DIS_RGMII_MASK 0x7
142 #define RTL8367_EXT_RGMXF_REG(_x) (0x1306 + (_x))
143 #define RTL8367_EXT_RGMXF_DUMMY0_SHIFT 5
144 #define RTL8367_EXT_RGMXF_DUMMY0_MASK 0x7ff
145 #define RTL8367_EXT_RGMXF_TXDELAY_SHIFT 3
146 #define RTL8367_EXT_RGMXF_TXDELAY_MASK 1
147 #define RTL8367_EXT_RGMXF_RXDELAY_MASK 0x7
149 #define RTL8367_DI_FORCE_REG(_x) (0x1310 + (_x))
150 #define RTL8367_DI_FORCE_MODE BIT(12)
151 #define RTL8367_DI_FORCE_NWAY BIT(7)
152 #define RTL8367_DI_FORCE_TXPAUSE BIT(6)
153 #define RTL8367_DI_FORCE_RXPAUSE BIT(5)
154 #define RTL8367_DI_FORCE_LINK BIT(4)
155 #define RTL8367_DI_FORCE_DUPLEX BIT(2)
156 #define RTL8367_DI_FORCE_SPEED_MASK 3
157 #define RTL8367_DI_FORCE_SPEED_10 0
158 #define RTL8367_DI_FORCE_SPEED_100 1
159 #define RTL8367_DI_FORCE_SPEED_1000 2
161 #define RTL8367_MAC_FORCE_REG(_x) (0x1312 + (_x))
163 #define RTL8367_CHIP_RESET_REG 0x1322
164 #define RTL8367_CHIP_RESET_SW BIT(1)
165 #define RTL8367_CHIP_RESET_HW BIT(0)
167 #define RTL8367_PORT_STATUS_REG(_p) (0x1352 + (_p))
168 #define RTL8367_PORT_STATUS_NWAY BIT(7)
169 #define RTL8367_PORT_STATUS_TXPAUSE BIT(6)
170 #define RTL8367_PORT_STATUS_RXPAUSE BIT(5)
171 #define RTL8367_PORT_STATUS_LINK BIT(4)
172 #define RTL8367_PORT_STATUS_DUPLEX BIT(2)
173 #define RTL8367_PORT_STATUS_SPEED_MASK 0x0003
174 #define RTL8367_PORT_STATUS_SPEED_10 0
175 #define RTL8367_PORT_STATUS_SPEED_100 1
176 #define RTL8367_PORT_STATUS_SPEED_1000 2
178 #define RTL8367_RTL_NO_REG 0x13c0
179 #define RTL8367_RTL_NO_8367R 0x3670
180 #define RTL8367_RTL_NO_8367M 0x3671
182 #define RTL8367_RTL_VER_REG 0x13c1
183 #define RTL8367_RTL_VER_MASK 0xf
185 #define RTL8367_RTL_MAGIC_ID_REG 0x13c2
186 #define RTL8367_RTL_MAGIC_ID_VAL 0x0249
188 #define RTL8367_LED_SYS_CONFIG_REG 0x1b00
189 #define RTL8367_LED_MODE_REG 0x1b02
190 #define RTL8367_LED_MODE_RATE_M 0x7
191 #define RTL8367_LED_MODE_RATE_S 1
193 #define RTL8367_LED_CONFIG_REG 0x1b03
194 #define RTL8367_LED_CONFIG_DATA_S 12
195 #define RTL8367_LED_CONFIG_DATA_M 0x3
196 #define RTL8367_LED_CONFIG_SEL BIT(14)
197 #define RTL8367_LED_CONFIG_LED_CFG_M 0xf
199 #define RTL8367_PARA_LED_IO_EN1_REG 0x1b24
200 #define RTL8367_PARA_LED_IO_EN2_REG 0x1b25
201 #define RTL8367_PARA_LED_IO_EN_PMASK 0xff
203 #define RTL8367_IA_CTRL_REG 0x1f00
204 #define RTL8367_IA_CTRL_RW(_x) ((_x) << 1)
205 #define RTL8367_IA_CTRL_RW_READ RTL8367_IA_CTRL_RW(0)
206 #define RTL8367_IA_CTRL_RW_WRITE RTL8367_IA_CTRL_RW(1)
207 #define RTL8367_IA_CTRL_CMD_MASK BIT(0)
209 #define RTL8367_IA_STATUS_REG 0x1f01
210 #define RTL8367_IA_STATUS_PHY_BUSY BIT(2)
211 #define RTL8367_IA_STATUS_SDS_BUSY BIT(1)
212 #define RTL8367_IA_STATUS_MDX_BUSY BIT(0)
214 #define RTL8367_IA_ADDRESS_REG 0x1f02
216 #define RTL8367_IA_WRITE_DATA_REG 0x1f03
217 #define RTL8367_IA_READ_DATA_REG 0x1f04
219 #define RTL8367_INTERNAL_PHY_REG(_a, _r) (0x2000 + 32 * (_a) + (_r))
221 #define RTL8367_CPU_PORT_NUM 9
222 #define RTL8367_NUM_PORTS 10
223 #define RTL8367_NUM_VLANS 32
224 #define RTL8367_NUM_LEDGROUPS 4
225 #define RTL8367_NUM_VIDS 4096
226 #define RTL8367_PRIORITYMAX 7
227 #define RTL8367_FIDMAX 7
229 #define RTL8367_PORT_0 BIT(0)
230 #define RTL8367_PORT_1 BIT(1)
231 #define RTL8367_PORT_2 BIT(2)
232 #define RTL8367_PORT_3 BIT(3)
233 #define RTL8367_PORT_4 BIT(4)
234 #define RTL8367_PORT_5 BIT(5)
235 #define RTL8367_PORT_6 BIT(6)
236 #define RTL8367_PORT_7 BIT(7)
237 #define RTL8367_PORT_E1 BIT(8) /* external port 1 */
238 #define RTL8367_PORT_E0 BIT(9) /* external port 0 */
240 #define RTL8367_PORTS_ALL \
241 (RTL8367_PORT_0 | RTL8367_PORT_1 | RTL8367_PORT_2 | \
242 RTL8367_PORT_3 | RTL8367_PORT_4 | RTL8367_PORT_5 | \
243 RTL8367_PORT_6 | RTL8367_PORT_7 | RTL8367_PORT_E1 | \
246 #define RTL8367_PORTS_ALL_BUT_CPU \
247 (RTL8367_PORT_0 | RTL8367_PORT_1 | RTL8367_PORT_2 | \
248 RTL8367_PORT_3 | RTL8367_PORT_4 | RTL8367_PORT_5 | \
249 RTL8367_PORT_6 | RTL8367_PORT_7 | RTL8367_PORT_E1)
251 struct rtl8367_initval
{
256 #define RTL8367_MIB_RXB_ID 0 /* IfInOctets */
257 #define RTL8367_MIB_TXB_ID 20 /* IfOutOctets */
259 static struct rtl8366_mib_counter rtl8367_mib_counters
[] = {
260 { 0, 0, 4, "IfInOctets" },
261 { 0, 4, 2, "Dot3StatsFCSErrors" },
262 { 0, 6, 2, "Dot3StatsSymbolErrors" },
263 { 0, 8, 2, "Dot3InPauseFrames" },
264 { 0, 10, 2, "Dot3ControlInUnknownOpcodes" },
265 { 0, 12, 2, "EtherStatsFragments" },
266 { 0, 14, 2, "EtherStatsJabbers" },
267 { 0, 16, 2, "IfInUcastPkts" },
268 { 0, 18, 2, "EtherStatsDropEvents" },
269 { 0, 20, 4, "EtherStatsOctets" },
271 { 0, 24, 2, "EtherStatsUnderSizePkts" },
272 { 0, 26, 2, "EtherOversizeStats" },
273 { 0, 28, 2, "EtherStatsPkts64Octets" },
274 { 0, 30, 2, "EtherStatsPkts65to127Octets" },
275 { 0, 32, 2, "EtherStatsPkts128to255Octets" },
276 { 0, 34, 2, "EtherStatsPkts256to511Octets" },
277 { 0, 36, 2, "EtherStatsPkts512to1023Octets" },
278 { 0, 38, 2, "EtherStatsPkts1024to1518Octets" },
279 { 0, 40, 2, "EtherStatsMulticastPkts" },
280 { 0, 42, 2, "EtherStatsBroadcastPkts" },
282 { 0, 44, 4, "IfOutOctets" },
284 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
285 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
286 { 0, 52, 2, "Dot3sDeferredTransmissions" },
287 { 0, 54, 2, "Dot3StatsLateCollisions" },
288 { 0, 56, 2, "EtherStatsCollisions" },
289 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
290 { 0, 60, 2, "Dot3OutPauseFrames" },
291 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
292 { 0, 64, 2, "Dot1dTpPortInDiscards" },
293 { 0, 66, 2, "IfOutUcastPkts" },
294 { 0, 68, 2, "IfOutMulticastPkts" },
295 { 0, 70, 2, "IfOutBroadcastPkts" },
296 { 0, 72, 2, "OutOampduPkts" },
297 { 0, 74, 2, "InOampduPkts" },
298 { 0, 76, 2, "PktgenPkts" },
301 #define REG_RD(_smi, _reg, _val) \
303 err = rtl8366_smi_read_reg(_smi, _reg, _val); \
308 #define REG_WR(_smi, _reg, _val) \
310 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
315 #define REG_RMW(_smi, _reg, _mask, _val) \
317 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
322 static const struct rtl8367_initval rtl8367_initvals_0_0
[] = {
323 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0000}, {0x2215, 0x1006},
324 {0x221f, 0x0005}, {0x2200, 0x00c6}, {0x221f, 0x0007}, {0x221e, 0x0048},
325 {0x2215, 0x6412}, {0x2216, 0x6412}, {0x2217, 0x6412}, {0x2218, 0x6412},
326 {0x2219, 0x6412}, {0x221A, 0x6412}, {0x221f, 0x0001}, {0x220c, 0xdbf0},
327 {0x2209, 0x2576}, {0x2207, 0x287E}, {0x220A, 0x68E5}, {0x221D, 0x3DA4},
328 {0x221C, 0xE7F7}, {0x2214, 0x7F52}, {0x2218, 0x7FCE}, {0x2208, 0x04B7},
329 {0x2206, 0x4072}, {0x2210, 0xF05E}, {0x221B, 0xB414}, {0x221F, 0x0003},
330 {0x221A, 0x06A6}, {0x2210, 0xF05E}, {0x2213, 0x06EB}, {0x2212, 0xF4D2},
331 {0x220E, 0xE120}, {0x2200, 0x7C00}, {0x2202, 0x5FD0}, {0x220D, 0x0207},
332 {0x221f, 0x0002}, {0x2205, 0x0978}, {0x2202, 0x8C01}, {0x2207, 0x3620},
333 {0x221C, 0x0001}, {0x2203, 0x0420}, {0x2204, 0x80C8}, {0x133e, 0x0ede},
334 {0x221f, 0x0002}, {0x220c, 0x0073}, {0x220d, 0xEB65}, {0x220e, 0x51d1},
335 {0x220f, 0x5dcb}, {0x2210, 0x3044}, {0x2211, 0x1800}, {0x2212, 0x7E00},
336 {0x2213, 0x0000}, {0x133f, 0x0010}, {0x133e, 0x0ffe}, {0x207f, 0x0002},
337 {0x2074, 0x3D22}, {0x2075, 0x2000}, {0x2076, 0x6040}, {0x2077, 0x0000},
338 {0x2078, 0x0f0a}, {0x2079, 0x50AB}, {0x207a, 0x0000}, {0x207b, 0x0f0f},
339 {0x205f, 0x0002}, {0x2054, 0xFF00}, {0x2055, 0x000A}, {0x2056, 0x000A},
340 {0x2057, 0x0005}, {0x2058, 0x0005}, {0x2059, 0x0000}, {0x205A, 0x0005},
341 {0x205B, 0x0005}, {0x205C, 0x0005}, {0x209f, 0x0002}, {0x2094, 0x00AA},
342 {0x2095, 0x00AA}, {0x2096, 0x00AA}, {0x2097, 0x00AA}, {0x2098, 0x0055},
343 {0x2099, 0x00AA}, {0x209A, 0x00AA}, {0x209B, 0x00AA}, {0x1363, 0x8354},
344 {0x1270, 0x3333}, {0x1271, 0x3333}, {0x1272, 0x3333}, {0x1330, 0x00DB},
345 {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x1006}, {0x121e, 0x03e8},
346 {0x121f, 0x02b3}, {0x1220, 0x028f}, {0x1221, 0x029b}, {0x1222, 0x0277},
347 {0x1223, 0x02b3}, {0x1224, 0x028f}, {0x1225, 0x029b}, {0x1226, 0x0277},
348 {0x1227, 0x00c0}, {0x1228, 0x00b4}, {0x122f, 0x00c0}, {0x1230, 0x00b4},
349 {0x1229, 0x0020}, {0x122a, 0x000c}, {0x1231, 0x0030}, {0x1232, 0x0024},
350 {0x0219, 0x0032}, {0x0200, 0x03e8}, {0x0201, 0x03e8}, {0x0202, 0x03e8},
351 {0x0203, 0x03e8}, {0x0204, 0x03e8}, {0x0205, 0x03e8}, {0x0206, 0x03e8},
352 {0x0207, 0x03e8}, {0x0218, 0x0032}, {0x0208, 0x029b}, {0x0209, 0x029b},
353 {0x020a, 0x029b}, {0x020b, 0x029b}, {0x020c, 0x029b}, {0x020d, 0x029b},
354 {0x020e, 0x029b}, {0x020f, 0x029b}, {0x0210, 0x029b}, {0x0211, 0x029b},
355 {0x0212, 0x029b}, {0x0213, 0x029b}, {0x0214, 0x029b}, {0x0215, 0x029b},
356 {0x0216, 0x029b}, {0x0217, 0x029b}, {0x0900, 0x0000}, {0x0901, 0x0000},
357 {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000},
358 {0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100},
359 {0x0802, 0x0100}, {0x1700, 0x014C}, {0x0301, 0x00FF}, {0x12AA, 0x0096},
360 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0005}, {0x2200, 0x00C4},
361 {0x221f, 0x0000}, {0x2210, 0x05EF}, {0x2204, 0x05E1}, {0x2200, 0x1340},
362 {0x133f, 0x0010}, {0x20A0, 0x1940}, {0x20C0, 0x1940}, {0x20E0, 0x1940},
365 static const struct rtl8367_initval rtl8367_initvals_0_1
[] = {
366 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0000}, {0x2215, 0x1006},
367 {0x221f, 0x0005}, {0x2200, 0x00c6}, {0x221f, 0x0007}, {0x221e, 0x0048},
368 {0x2215, 0x6412}, {0x2216, 0x6412}, {0x2217, 0x6412}, {0x2218, 0x6412},
369 {0x2219, 0x6412}, {0x221A, 0x6412}, {0x221f, 0x0001}, {0x220c, 0xdbf0},
370 {0x2209, 0x2576}, {0x2207, 0x287E}, {0x220A, 0x68E5}, {0x221D, 0x3DA4},
371 {0x221C, 0xE7F7}, {0x2214, 0x7F52}, {0x2218, 0x7FCE}, {0x2208, 0x04B7},
372 {0x2206, 0x4072}, {0x2210, 0xF05E}, {0x221B, 0xB414}, {0x221F, 0x0003},
373 {0x221A, 0x06A6}, {0x2210, 0xF05E}, {0x2213, 0x06EB}, {0x2212, 0xF4D2},
374 {0x220E, 0xE120}, {0x2200, 0x7C00}, {0x2202, 0x5FD0}, {0x220D, 0x0207},
375 {0x221f, 0x0002}, {0x2205, 0x0978}, {0x2202, 0x8C01}, {0x2207, 0x3620},
376 {0x221C, 0x0001}, {0x2203, 0x0420}, {0x2204, 0x80C8}, {0x133e, 0x0ede},
377 {0x221f, 0x0002}, {0x220c, 0x0073}, {0x220d, 0xEB65}, {0x220e, 0x51d1},
378 {0x220f, 0x5dcb}, {0x2210, 0x3044}, {0x2211, 0x1800}, {0x2212, 0x7E00},
379 {0x2213, 0x0000}, {0x133f, 0x0010}, {0x133e, 0x0ffe}, {0x207f, 0x0002},
380 {0x2074, 0x3D22}, {0x2075, 0x2000}, {0x2076, 0x6040}, {0x2077, 0x0000},
381 {0x2078, 0x0f0a}, {0x2079, 0x50AB}, {0x207a, 0x0000}, {0x207b, 0x0f0f},
382 {0x205f, 0x0002}, {0x2054, 0xFF00}, {0x2055, 0x000A}, {0x2056, 0x000A},
383 {0x2057, 0x0005}, {0x2058, 0x0005}, {0x2059, 0x0000}, {0x205A, 0x0005},
384 {0x205B, 0x0005}, {0x205C, 0x0005}, {0x209f, 0x0002}, {0x2094, 0x00AA},
385 {0x2095, 0x00AA}, {0x2096, 0x00AA}, {0x2097, 0x00AA}, {0x2098, 0x0055},
386 {0x2099, 0x00AA}, {0x209A, 0x00AA}, {0x209B, 0x00AA}, {0x1363, 0x8354},
387 {0x1270, 0x3333}, {0x1271, 0x3333}, {0x1272, 0x3333}, {0x1330, 0x00DB},
388 {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x1b06}, {0x121e, 0x07f0},
389 {0x121f, 0x0438}, {0x1220, 0x040f}, {0x1221, 0x040f}, {0x1222, 0x03eb},
390 {0x1223, 0x0438}, {0x1224, 0x040f}, {0x1225, 0x040f}, {0x1226, 0x03eb},
391 {0x1227, 0x0144}, {0x1228, 0x0138}, {0x122f, 0x0144}, {0x1230, 0x0138},
392 {0x1229, 0x0020}, {0x122a, 0x000c}, {0x1231, 0x0030}, {0x1232, 0x0024},
393 {0x0219, 0x0032}, {0x0200, 0x07d0}, {0x0201, 0x07d0}, {0x0202, 0x07d0},
394 {0x0203, 0x07d0}, {0x0204, 0x07d0}, {0x0205, 0x07d0}, {0x0206, 0x07d0},
395 {0x0207, 0x07d0}, {0x0218, 0x0032}, {0x0208, 0x0190}, {0x0209, 0x0190},
396 {0x020a, 0x0190}, {0x020b, 0x0190}, {0x020c, 0x0190}, {0x020d, 0x0190},
397 {0x020e, 0x0190}, {0x020f, 0x0190}, {0x0210, 0x0190}, {0x0211, 0x0190},
398 {0x0212, 0x0190}, {0x0213, 0x0190}, {0x0214, 0x0190}, {0x0215, 0x0190},
399 {0x0216, 0x0190}, {0x0217, 0x0190}, {0x0900, 0x0000}, {0x0901, 0x0000},
400 {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000},
401 {0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100},
402 {0x0802, 0x0100}, {0x1700, 0x0125}, {0x0301, 0x00FF}, {0x12AA, 0x0096},
403 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0005}, {0x2200, 0x00C4},
404 {0x221f, 0x0000}, {0x2210, 0x05EF}, {0x2204, 0x05E1}, {0x2200, 0x1340},
408 static const struct rtl8367_initval rtl8367_initvals_1_0
[] = {
409 {0x1B24, 0x0000}, {0x1B25, 0x0000}, {0x1B26, 0x0000}, {0x1B27, 0x0000},
410 {0x207F, 0x0002}, {0x2079, 0x0200}, {0x207F, 0x0000}, {0x133F, 0x0030},
411 {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2201, 0x0700}, {0x2205, 0x8B82},
412 {0x2206, 0x05CB}, {0x221F, 0x0002}, {0x2204, 0x80C2}, {0x2205, 0x0938},
413 {0x221F, 0x0003}, {0x2212, 0xC4D2}, {0x220D, 0x0207}, {0x221F, 0x0001},
414 {0x2207, 0x267E}, {0x221C, 0xE5F7}, {0x221B, 0x0424}, {0x221F, 0x0007},
415 {0x221E, 0x0040}, {0x2218, 0x0000}, {0x221F, 0x0007}, {0x221E, 0x002C},
416 {0x2218, 0x008B}, {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080},
417 {0x2205, 0x8000}, {0x2206, 0xF8E0}, {0x2206, 0xE000}, {0x2206, 0xE1E0},
418 {0x2206, 0x01AC}, {0x2206, 0x2408}, {0x2206, 0xE08B}, {0x2206, 0x84F7},
419 {0x2206, 0x20E4}, {0x2206, 0x8B84}, {0x2206, 0xFC05}, {0x2206, 0xF8FA},
420 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AC}, {0x2206, 0x201A},
421 {0x2206, 0xBF80}, {0x2206, 0x59D0}, {0x2206, 0x2402}, {0x2206, 0x803D},
422 {0x2206, 0xE0E0}, {0x2206, 0xE4E1}, {0x2206, 0xE0E5}, {0x2206, 0x5806},
423 {0x2206, 0x68C0}, {0x2206, 0xD1D2}, {0x2206, 0xE4E0}, {0x2206, 0xE4E5},
424 {0x2206, 0xE0E5}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x05FB},
425 {0x2206, 0x0BFB}, {0x2206, 0x58FF}, {0x2206, 0x9E11}, {0x2206, 0x06F0},
426 {0x2206, 0x0C81}, {0x2206, 0x8AE0}, {0x2206, 0x0019}, {0x2206, 0x1B89},
427 {0x2206, 0xCFEB}, {0x2206, 0x19EB}, {0x2206, 0x19B0}, {0x2206, 0xEFFF},
428 {0x2206, 0x0BFF}, {0x2206, 0x0425}, {0x2206, 0x0807}, {0x2206, 0x2640},
429 {0x2206, 0x7227}, {0x2206, 0x267E}, {0x2206, 0x2804}, {0x2206, 0xB729},
430 {0x2206, 0x2576}, {0x2206, 0x2A68}, {0x2206, 0xE52B}, {0x2206, 0xAD00},
431 {0x2206, 0x2CDB}, {0x2206, 0xF02D}, {0x2206, 0x67BB}, {0x2206, 0x2E7B},
432 {0x2206, 0x0F2F}, {0x2206, 0x7365}, {0x2206, 0x31AC}, {0x2206, 0xCC32},
433 {0x2206, 0x2300}, {0x2206, 0x332D}, {0x2206, 0x1734}, {0x2206, 0x7F52},
434 {0x2206, 0x3510}, {0x2206, 0x0036}, {0x2206, 0x0600}, {0x2206, 0x370C},
435 {0x2206, 0xC038}, {0x2206, 0x7FCE}, {0x2206, 0x3CE5}, {0x2206, 0xF73D},
436 {0x2206, 0x3DA4}, {0x2206, 0x6530}, {0x2206, 0x3E67}, {0x2206, 0x0053},
437 {0x2206, 0x69D2}, {0x2206, 0x0F6A}, {0x2206, 0x012C}, {0x2206, 0x6C2B},
438 {0x2206, 0x136E}, {0x2206, 0xE100}, {0x2206, 0x6F12}, {0x2206, 0xF771},
439 {0x2206, 0x006B}, {0x2206, 0x7306}, {0x2206, 0xEB74}, {0x2206, 0x94C7},
440 {0x2206, 0x7698}, {0x2206, 0x0A77}, {0x2206, 0x5000}, {0x2206, 0x788A},
441 {0x2206, 0x1579}, {0x2206, 0x7F6F}, {0x2206, 0x7A06}, {0x2206, 0xA600},
442 {0x2205, 0x8B90}, {0x2206, 0x8000}, {0x2205, 0x8B92}, {0x2206, 0x8000},
443 {0x2205, 0x8B94}, {0x2206, 0x8014}, {0x2208, 0xFFFA}, {0x2202, 0x3C65},
444 {0x2205, 0xFFF6}, {0x2206, 0x00F7}, {0x221F, 0x0000}, {0x221F, 0x0007},
445 {0x221E, 0x0042}, {0x2218, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},
446 {0x221E, 0x0020}, {0x2215, 0x0000}, {0x221E, 0x0023}, {0x2216, 0x8000},
447 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x1362, 0x0115},
448 {0x1363, 0x0002}, {0x1363, 0x0000}, {0x1306, 0x000C}, {0x1307, 0x000C},
449 {0x1303, 0x0067}, {0x1304, 0x4444}, {0x1203, 0xFF00}, {0x1200, 0x7FC4},
450 {0x121D, 0x7D16}, {0x121E, 0x03E8}, {0x121F, 0x024E}, {0x1220, 0x0230},
451 {0x1221, 0x0244}, {0x1222, 0x0226}, {0x1223, 0x024E}, {0x1224, 0x0230},
452 {0x1225, 0x0244}, {0x1226, 0x0226}, {0x1227, 0x00C0}, {0x1228, 0x00B4},
453 {0x122F, 0x00C0}, {0x1230, 0x00B4}, {0x0208, 0x03E8}, {0x0209, 0x03E8},
454 {0x020A, 0x03E8}, {0x020B, 0x03E8}, {0x020C, 0x03E8}, {0x020D, 0x03E8},
455 {0x020E, 0x03E8}, {0x020F, 0x03E8}, {0x0210, 0x03E8}, {0x0211, 0x03E8},
456 {0x0212, 0x03E8}, {0x0213, 0x03E8}, {0x0214, 0x03E8}, {0x0215, 0x03E8},
457 {0x0216, 0x03E8}, {0x0217, 0x03E8}, {0x0900, 0x0000}, {0x0901, 0x0000},
458 {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087B, 0x0000},
459 {0x087C, 0xFF00}, {0x087D, 0x0000}, {0x087E, 0x0000}, {0x0801, 0x0100},
460 {0x0802, 0x0100}, {0x0A20, 0x2040}, {0x0A21, 0x2040}, {0x0A22, 0x2040},
461 {0x0A23, 0x2040}, {0x0A24, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040},
462 {0x133F, 0x0030}, {0x133E, 0x000E}, {0x221F, 0x0000}, {0x2200, 0x1340},
463 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x20A0, 0x1940},
464 {0x20C0, 0x1940}, {0x20E0, 0x1940}, {0x130c, 0x0050},
467 static const struct rtl8367_initval rtl8367_initvals_1_1
[] = {
468 {0x1B24, 0x0000}, {0x1B25, 0x0000}, {0x1B26, 0x0000}, {0x1B27, 0x0000},
469 {0x207F, 0x0002}, {0x2079, 0x0200}, {0x207F, 0x0000}, {0x133F, 0x0030},
470 {0x133E, 0x000E}, {0x221F, 0x0005}, {0x2201, 0x0700}, {0x2205, 0x8B82},
471 {0x2206, 0x05CB}, {0x221F, 0x0002}, {0x2204, 0x80C2}, {0x2205, 0x0938},
472 {0x221F, 0x0003}, {0x2212, 0xC4D2}, {0x220D, 0x0207}, {0x221F, 0x0001},
473 {0x2207, 0x267E}, {0x221C, 0xE5F7}, {0x221B, 0x0424}, {0x221F, 0x0007},
474 {0x221E, 0x0040}, {0x2218, 0x0000}, {0x221F, 0x0007}, {0x221E, 0x002C},
475 {0x2218, 0x008B}, {0x221F, 0x0005}, {0x2205, 0xFFF6}, {0x2206, 0x0080},
476 {0x2205, 0x8000}, {0x2206, 0xF8E0}, {0x2206, 0xE000}, {0x2206, 0xE1E0},
477 {0x2206, 0x01AC}, {0x2206, 0x2408}, {0x2206, 0xE08B}, {0x2206, 0x84F7},
478 {0x2206, 0x20E4}, {0x2206, 0x8B84}, {0x2206, 0xFC05}, {0x2206, 0xF8FA},
479 {0x2206, 0xEF69}, {0x2206, 0xE08B}, {0x2206, 0x86AC}, {0x2206, 0x201A},
480 {0x2206, 0xBF80}, {0x2206, 0x59D0}, {0x2206, 0x2402}, {0x2206, 0x803D},
481 {0x2206, 0xE0E0}, {0x2206, 0xE4E1}, {0x2206, 0xE0E5}, {0x2206, 0x5806},
482 {0x2206, 0x68C0}, {0x2206, 0xD1D2}, {0x2206, 0xE4E0}, {0x2206, 0xE4E5},
483 {0x2206, 0xE0E5}, {0x2206, 0xEF96}, {0x2206, 0xFEFC}, {0x2206, 0x05FB},
484 {0x2206, 0x0BFB}, {0x2206, 0x58FF}, {0x2206, 0x9E11}, {0x2206, 0x06F0},
485 {0x2206, 0x0C81}, {0x2206, 0x8AE0}, {0x2206, 0x0019}, {0x2206, 0x1B89},
486 {0x2206, 0xCFEB}, {0x2206, 0x19EB}, {0x2206, 0x19B0}, {0x2206, 0xEFFF},
487 {0x2206, 0x0BFF}, {0x2206, 0x0425}, {0x2206, 0x0807}, {0x2206, 0x2640},
488 {0x2206, 0x7227}, {0x2206, 0x267E}, {0x2206, 0x2804}, {0x2206, 0xB729},
489 {0x2206, 0x2576}, {0x2206, 0x2A68}, {0x2206, 0xE52B}, {0x2206, 0xAD00},
490 {0x2206, 0x2CDB}, {0x2206, 0xF02D}, {0x2206, 0x67BB}, {0x2206, 0x2E7B},
491 {0x2206, 0x0F2F}, {0x2206, 0x7365}, {0x2206, 0x31AC}, {0x2206, 0xCC32},
492 {0x2206, 0x2300}, {0x2206, 0x332D}, {0x2206, 0x1734}, {0x2206, 0x7F52},
493 {0x2206, 0x3510}, {0x2206, 0x0036}, {0x2206, 0x0600}, {0x2206, 0x370C},
494 {0x2206, 0xC038}, {0x2206, 0x7FCE}, {0x2206, 0x3CE5}, {0x2206, 0xF73D},
495 {0x2206, 0x3DA4}, {0x2206, 0x6530}, {0x2206, 0x3E67}, {0x2206, 0x0053},
496 {0x2206, 0x69D2}, {0x2206, 0x0F6A}, {0x2206, 0x012C}, {0x2206, 0x6C2B},
497 {0x2206, 0x136E}, {0x2206, 0xE100}, {0x2206, 0x6F12}, {0x2206, 0xF771},
498 {0x2206, 0x006B}, {0x2206, 0x7306}, {0x2206, 0xEB74}, {0x2206, 0x94C7},
499 {0x2206, 0x7698}, {0x2206, 0x0A77}, {0x2206, 0x5000}, {0x2206, 0x788A},
500 {0x2206, 0x1579}, {0x2206, 0x7F6F}, {0x2206, 0x7A06}, {0x2206, 0xA600},
501 {0x2205, 0x8B90}, {0x2206, 0x8000}, {0x2205, 0x8B92}, {0x2206, 0x8000},
502 {0x2205, 0x8B94}, {0x2206, 0x8014}, {0x2208, 0xFFFA}, {0x2202, 0x3C65},
503 {0x2205, 0xFFF6}, {0x2206, 0x00F7}, {0x221F, 0x0000}, {0x221F, 0x0007},
504 {0x221E, 0x0042}, {0x2218, 0x0000}, {0x221E, 0x002D}, {0x2218, 0xF010},
505 {0x221E, 0x0020}, {0x2215, 0x0000}, {0x221E, 0x0023}, {0x2216, 0x8000},
506 {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE}, {0x1362, 0x0115},
507 {0x1363, 0x0002}, {0x1363, 0x0000}, {0x1306, 0x000C}, {0x1307, 0x000C},
508 {0x1303, 0x0067}, {0x1304, 0x4444}, {0x1203, 0xFF00}, {0x1200, 0x7FC4},
509 {0x0900, 0x0000}, {0x0901, 0x0000}, {0x0902, 0x0000}, {0x0903, 0x0000},
510 {0x0865, 0x3210}, {0x087B, 0x0000}, {0x087C, 0xFF00}, {0x087D, 0x0000},
511 {0x087E, 0x0000}, {0x0801, 0x0100}, {0x0802, 0x0100}, {0x0A20, 0x2040},
512 {0x0A21, 0x2040}, {0x0A22, 0x2040}, {0x0A23, 0x2040}, {0x0A24, 0x2040},
513 {0x0A25, 0x2040}, {0x0A26, 0x2040}, {0x0A27, 0x2040}, {0x0A28, 0x2040},
514 {0x0A29, 0x2040}, {0x133F, 0x0030}, {0x133E, 0x000E}, {0x221F, 0x0000},
515 {0x2200, 0x1340}, {0x221F, 0x0000}, {0x133F, 0x0010}, {0x133E, 0x0FFE},
519 static const struct rtl8367_initval rtl8367_initvals_2_0
[] = {
520 {0x1b24, 0x0000}, {0x1b25, 0x0000}, {0x1b26, 0x0000}, {0x1b27, 0x0000},
521 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0007}, {0x221e, 0x0048},
522 {0x2219, 0x4012}, {0x221f, 0x0003}, {0x2201, 0x3554}, {0x2202, 0x63e8},
523 {0x2203, 0x99c2}, {0x2204, 0x0113}, {0x2205, 0x303e}, {0x220d, 0x0207},
524 {0x220e, 0xe100}, {0x221f, 0x0007}, {0x221e, 0x0040}, {0x2218, 0x0000},
525 {0x221f, 0x0007}, {0x221e, 0x002c}, {0x2218, 0x008b}, {0x221f, 0x0005},
526 {0x2205, 0xfff6}, {0x2206, 0x0080}, {0x221f, 0x0005}, {0x2205, 0x8000},
527 {0x2206, 0x0280}, {0x2206, 0x2bf7}, {0x2206, 0x00e0}, {0x2206, 0xfff7},
528 {0x2206, 0xa080}, {0x2206, 0x02ae}, {0x2206, 0xf602}, {0x2206, 0x804e},
529 {0x2206, 0x0201}, {0x2206, 0x5002}, {0x2206, 0x0163}, {0x2206, 0x0201},
530 {0x2206, 0x79e0}, {0x2206, 0x8b8c}, {0x2206, 0xe18b}, {0x2206, 0x8d1e},
531 {0x2206, 0x01e1}, {0x2206, 0x8b8e}, {0x2206, 0x1e01}, {0x2206, 0xa000},
532 {0x2206, 0xe4ae}, {0x2206, 0xd8bf}, {0x2206, 0x8b88}, {0x2206, 0xec00},
533 {0x2206, 0x19a9}, {0x2206, 0x8b90}, {0x2206, 0xf9ee}, {0x2206, 0xfff6},
534 {0x2206, 0x00ee}, {0x2206, 0xfff7}, {0x2206, 0xfce0}, {0x2206, 0xe140},
535 {0x2206, 0xe1e1}, {0x2206, 0x41f7}, {0x2206, 0x2ff6}, {0x2206, 0x28e4},
536 {0x2206, 0xe140}, {0x2206, 0xe5e1}, {0x2206, 0x4104}, {0x2206, 0xf8fa},
537 {0x2206, 0xef69}, {0x2206, 0xe08b}, {0x2206, 0x86ac}, {0x2206, 0x201a},
538 {0x2206, 0xbf80}, {0x2206, 0x77d0}, {0x2206, 0x6c02}, {0x2206, 0x2978},
539 {0x2206, 0xe0e0}, {0x2206, 0xe4e1}, {0x2206, 0xe0e5}, {0x2206, 0x5806},
540 {0x2206, 0x68c0}, {0x2206, 0xd1d2}, {0x2206, 0xe4e0}, {0x2206, 0xe4e5},
541 {0x2206, 0xe0e5}, {0x2206, 0xef96}, {0x2206, 0xfefc}, {0x2206, 0x0425},
542 {0x2206, 0x0807}, {0x2206, 0x2640}, {0x2206, 0x7227}, {0x2206, 0x267e},
543 {0x2206, 0x2804}, {0x2206, 0xb729}, {0x2206, 0x2576}, {0x2206, 0x2a68},
544 {0x2206, 0xe52b}, {0x2206, 0xad00}, {0x2206, 0x2cdb}, {0x2206, 0xf02d},
545 {0x2206, 0x67bb}, {0x2206, 0x2e7b}, {0x2206, 0x0f2f}, {0x2206, 0x7365},
546 {0x2206, 0x31ac}, {0x2206, 0xcc32}, {0x2206, 0x2300}, {0x2206, 0x332d},
547 {0x2206, 0x1734}, {0x2206, 0x7f52}, {0x2206, 0x3510}, {0x2206, 0x0036},
548 {0x2206, 0x0600}, {0x2206, 0x370c}, {0x2206, 0xc038}, {0x2206, 0x7fce},
549 {0x2206, 0x3ce5}, {0x2206, 0xf73d}, {0x2206, 0x3da4}, {0x2206, 0x6530},
550 {0x2206, 0x3e67}, {0x2206, 0x0053}, {0x2206, 0x69d2}, {0x2206, 0x0f6a},
551 {0x2206, 0x012c}, {0x2206, 0x6c2b}, {0x2206, 0x136e}, {0x2206, 0xe100},
552 {0x2206, 0x6f12}, {0x2206, 0xf771}, {0x2206, 0x006b}, {0x2206, 0x7306},
553 {0x2206, 0xeb74}, {0x2206, 0x94c7}, {0x2206, 0x7698}, {0x2206, 0x0a77},
554 {0x2206, 0x5000}, {0x2206, 0x788a}, {0x2206, 0x1579}, {0x2206, 0x7f6f},
555 {0x2206, 0x7a06}, {0x2206, 0xa600}, {0x2201, 0x0701}, {0x2200, 0x0405},
556 {0x221f, 0x0000}, {0x2200, 0x1340}, {0x221f, 0x0000}, {0x133f, 0x0010},
557 {0x133e, 0x0ffe}, {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x121d, 0x7D16},
558 {0x121e, 0x03e8}, {0x121f, 0x024e}, {0x1220, 0x0230}, {0x1221, 0x0244},
559 {0x1222, 0x0226}, {0x1223, 0x024e}, {0x1224, 0x0230}, {0x1225, 0x0244},
560 {0x1226, 0x0226}, {0x1227, 0x00c0}, {0x1228, 0x00b4}, {0x122f, 0x00c0},
561 {0x1230, 0x00b4}, {0x0208, 0x03e8}, {0x0209, 0x03e8}, {0x020a, 0x03e8},
562 {0x020b, 0x03e8}, {0x020c, 0x03e8}, {0x020d, 0x03e8}, {0x020e, 0x03e8},
563 {0x020f, 0x03e8}, {0x0210, 0x03e8}, {0x0211, 0x03e8}, {0x0212, 0x03e8},
564 {0x0213, 0x03e8}, {0x0214, 0x03e8}, {0x0215, 0x03e8}, {0x0216, 0x03e8},
565 {0x0217, 0x03e8}, {0x0900, 0x0000}, {0x0901, 0x0000}, {0x0902, 0x0000},
566 {0x0903, 0x0000}, {0x0865, 0x3210}, {0x087b, 0x0000}, {0x087c, 0xff00},
567 {0x087d, 0x0000}, {0x087e, 0x0000}, {0x0801, 0x0100}, {0x0802, 0x0100},
568 {0x0A20, 0x2040}, {0x0A21, 0x2040}, {0x0A22, 0x2040}, {0x0A23, 0x2040},
569 {0x0A24, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040}, {0x20A0, 0x1940},
570 {0x20C0, 0x1940}, {0x20E0, 0x1940}, {0x130c, 0x0050},
573 static const struct rtl8367_initval rtl8367_initvals_2_1
[] = {
574 {0x1b24, 0x0000}, {0x1b25, 0x0000}, {0x1b26, 0x0000}, {0x1b27, 0x0000},
575 {0x133f, 0x0030}, {0x133e, 0x000e}, {0x221f, 0x0007}, {0x221e, 0x0048},
576 {0x2219, 0x4012}, {0x221f, 0x0003}, {0x2201, 0x3554}, {0x2202, 0x63e8},
577 {0x2203, 0x99c2}, {0x2204, 0x0113}, {0x2205, 0x303e}, {0x220d, 0x0207},
578 {0x220e, 0xe100}, {0x221f, 0x0007}, {0x221e, 0x0040}, {0x2218, 0x0000},
579 {0x221f, 0x0007}, {0x221e, 0x002c}, {0x2218, 0x008b}, {0x221f, 0x0005},
580 {0x2205, 0xfff6}, {0x2206, 0x0080}, {0x221f, 0x0005}, {0x2205, 0x8000},
581 {0x2206, 0x0280}, {0x2206, 0x2bf7}, {0x2206, 0x00e0}, {0x2206, 0xfff7},
582 {0x2206, 0xa080}, {0x2206, 0x02ae}, {0x2206, 0xf602}, {0x2206, 0x804e},
583 {0x2206, 0x0201}, {0x2206, 0x5002}, {0x2206, 0x0163}, {0x2206, 0x0201},
584 {0x2206, 0x79e0}, {0x2206, 0x8b8c}, {0x2206, 0xe18b}, {0x2206, 0x8d1e},
585 {0x2206, 0x01e1}, {0x2206, 0x8b8e}, {0x2206, 0x1e01}, {0x2206, 0xa000},
586 {0x2206, 0xe4ae}, {0x2206, 0xd8bf}, {0x2206, 0x8b88}, {0x2206, 0xec00},
587 {0x2206, 0x19a9}, {0x2206, 0x8b90}, {0x2206, 0xf9ee}, {0x2206, 0xfff6},
588 {0x2206, 0x00ee}, {0x2206, 0xfff7}, {0x2206, 0xfce0}, {0x2206, 0xe140},
589 {0x2206, 0xe1e1}, {0x2206, 0x41f7}, {0x2206, 0x2ff6}, {0x2206, 0x28e4},
590 {0x2206, 0xe140}, {0x2206, 0xe5e1}, {0x2206, 0x4104}, {0x2206, 0xf8fa},
591 {0x2206, 0xef69}, {0x2206, 0xe08b}, {0x2206, 0x86ac}, {0x2206, 0x201a},
592 {0x2206, 0xbf80}, {0x2206, 0x77d0}, {0x2206, 0x6c02}, {0x2206, 0x2978},
593 {0x2206, 0xe0e0}, {0x2206, 0xe4e1}, {0x2206, 0xe0e5}, {0x2206, 0x5806},
594 {0x2206, 0x68c0}, {0x2206, 0xd1d2}, {0x2206, 0xe4e0}, {0x2206, 0xe4e5},
595 {0x2206, 0xe0e5}, {0x2206, 0xef96}, {0x2206, 0xfefc}, {0x2206, 0x0425},
596 {0x2206, 0x0807}, {0x2206, 0x2640}, {0x2206, 0x7227}, {0x2206, 0x267e},
597 {0x2206, 0x2804}, {0x2206, 0xb729}, {0x2206, 0x2576}, {0x2206, 0x2a68},
598 {0x2206, 0xe52b}, {0x2206, 0xad00}, {0x2206, 0x2cdb}, {0x2206, 0xf02d},
599 {0x2206, 0x67bb}, {0x2206, 0x2e7b}, {0x2206, 0x0f2f}, {0x2206, 0x7365},
600 {0x2206, 0x31ac}, {0x2206, 0xcc32}, {0x2206, 0x2300}, {0x2206, 0x332d},
601 {0x2206, 0x1734}, {0x2206, 0x7f52}, {0x2206, 0x3510}, {0x2206, 0x0036},
602 {0x2206, 0x0600}, {0x2206, 0x370c}, {0x2206, 0xc038}, {0x2206, 0x7fce},
603 {0x2206, 0x3ce5}, {0x2206, 0xf73d}, {0x2206, 0x3da4}, {0x2206, 0x6530},
604 {0x2206, 0x3e67}, {0x2206, 0x0053}, {0x2206, 0x69d2}, {0x2206, 0x0f6a},
605 {0x2206, 0x012c}, {0x2206, 0x6c2b}, {0x2206, 0x136e}, {0x2206, 0xe100},
606 {0x2206, 0x6f12}, {0x2206, 0xf771}, {0x2206, 0x006b}, {0x2206, 0x7306},
607 {0x2206, 0xeb74}, {0x2206, 0x94c7}, {0x2206, 0x7698}, {0x2206, 0x0a77},
608 {0x2206, 0x5000}, {0x2206, 0x788a}, {0x2206, 0x1579}, {0x2206, 0x7f6f},
609 {0x2206, 0x7a06}, {0x2206, 0xa600}, {0x2201, 0x0701}, {0x2200, 0x0405},
610 {0x221f, 0x0000}, {0x2200, 0x1340}, {0x221f, 0x0000}, {0x133f, 0x0010},
611 {0x133e, 0x0ffe}, {0x1203, 0xff00}, {0x1200, 0x7fc4}, {0x0900, 0x0000},
612 {0x0901, 0x0000}, {0x0902, 0x0000}, {0x0903, 0x0000}, {0x0865, 0x3210},
613 {0x087b, 0x0000}, {0x087c, 0xff00}, {0x087d, 0x0000}, {0x087e, 0x0000},
614 {0x0801, 0x0100}, {0x0802, 0x0100}, {0x0A20, 0x2040}, {0x0A21, 0x2040},
615 {0x0A22, 0x2040}, {0x0A23, 0x2040}, {0x0A24, 0x2040}, {0x0A25, 0x2040},
616 {0x0A26, 0x2040}, {0x0A27, 0x2040}, {0x0A28, 0x2040}, {0x0A29, 0x2040},
620 static int rtl8367_write_initvals(struct rtl8366_smi
*smi
,
621 const struct rtl8367_initval
*initvals
,
627 for (i
= 0; i
< count
; i
++)
628 REG_WR(smi
, initvals
[i
].reg
, initvals
[i
].val
);
633 static int rtl8367_read_phy_reg(struct rtl8366_smi
*smi
,
634 u32 phy_addr
, u32 phy_reg
, u32
*val
)
640 if (phy_addr
> RTL8367_PHY_ADDR_MAX
)
643 if (phy_reg
> RTL8367_PHY_REG_MAX
)
646 REG_RD(smi
, RTL8367_IA_STATUS_REG
, &data
);
647 if (data
& RTL8367_IA_STATUS_PHY_BUSY
)
650 /* prepare address */
651 REG_WR(smi
, RTL8367_IA_ADDRESS_REG
,
652 RTL8367_INTERNAL_PHY_REG(phy_addr
, phy_reg
));
654 /* send read command */
655 REG_WR(smi
, RTL8367_IA_CTRL_REG
,
656 RTL8367_IA_CTRL_CMD_MASK
| RTL8367_IA_CTRL_RW_READ
);
660 REG_RD(smi
, RTL8367_IA_STATUS_REG
, &data
);
661 if ((data
& RTL8367_IA_STATUS_PHY_BUSY
) == 0)
665 dev_err(smi
->parent
, "phy read timed out\n");
673 REG_RD(smi
, RTL8367_IA_READ_DATA_REG
, val
);
675 dev_dbg(smi
->parent
, "phy_read: addr:%02x, reg:%02x, val:%04x\n",
676 phy_addr
, phy_reg
, *val
);
680 static int rtl8367_write_phy_reg(struct rtl8366_smi
*smi
,
681 u32 phy_addr
, u32 phy_reg
, u32 val
)
687 dev_dbg(smi
->parent
, "phy_write: addr:%02x, reg:%02x, val:%04x\n",
688 phy_addr
, phy_reg
, val
);
690 if (phy_addr
> RTL8367_PHY_ADDR_MAX
)
693 if (phy_reg
> RTL8367_PHY_REG_MAX
)
696 REG_RD(smi
, RTL8367_IA_STATUS_REG
, &data
);
697 if (data
& RTL8367_IA_STATUS_PHY_BUSY
)
701 REG_WR(smi
, RTL8367_IA_WRITE_DATA_REG
, val
);
703 /* prepare address */
704 REG_WR(smi
, RTL8367_IA_ADDRESS_REG
,
705 RTL8367_INTERNAL_PHY_REG(phy_addr
, phy_reg
));
707 /* send write command */
708 REG_WR(smi
, RTL8367_IA_CTRL_REG
,
709 RTL8367_IA_CTRL_CMD_MASK
| RTL8367_IA_CTRL_RW_WRITE
);
713 REG_RD(smi
, RTL8367_IA_STATUS_REG
, &data
);
714 if ((data
& RTL8367_IA_STATUS_PHY_BUSY
) == 0)
718 dev_err(smi
->parent
, "phy write timed out\n");
728 static int rtl8367_init_regs0(struct rtl8366_smi
*smi
, unsigned mode
)
730 const struct rtl8367_initval
*initvals
;
736 initvals
= rtl8367_initvals_0_0
;
737 count
= ARRAY_SIZE(rtl8367_initvals_0_0
);
742 initvals
= rtl8367_initvals_0_1
;
743 count
= ARRAY_SIZE(rtl8367_initvals_0_1
);
747 dev_err(smi
->parent
, "%s: unknow mode %u\n", __func__
, mode
);
751 err
= rtl8367_write_initvals(smi
, initvals
, count
);
755 /* TODO: complete this */
760 static int rtl8367_init_regs1(struct rtl8366_smi
*smi
, unsigned mode
)
762 const struct rtl8367_initval
*initvals
;
767 initvals
= rtl8367_initvals_1_0
;
768 count
= ARRAY_SIZE(rtl8367_initvals_1_0
);
773 initvals
= rtl8367_initvals_1_1
;
774 count
= ARRAY_SIZE(rtl8367_initvals_1_1
);
778 dev_err(smi
->parent
, "%s: unknow mode %u\n", __func__
, mode
);
782 return rtl8367_write_initvals(smi
, initvals
, count
);
785 static int rtl8367_init_regs2(struct rtl8366_smi
*smi
, unsigned mode
)
787 const struct rtl8367_initval
*initvals
;
792 initvals
= rtl8367_initvals_2_0
;
793 count
= ARRAY_SIZE(rtl8367_initvals_2_0
);
798 initvals
= rtl8367_initvals_2_1
;
799 count
= ARRAY_SIZE(rtl8367_initvals_2_1
);
803 dev_err(smi
->parent
, "%s: unknow mode %u\n", __func__
, mode
);
807 return rtl8367_write_initvals(smi
, initvals
, count
);
810 static int rtl8367_init_regs(struct rtl8366_smi
*smi
)
817 REG_WR(smi
, RTL8367_RTL_MAGIC_ID_REG
, RTL8367_RTL_MAGIC_ID_VAL
);
819 REG_RD(smi
, RTL8367_CHIP_VER_REG
, &data
);
820 rlvid
= (data
>> RTL8367_CHIP_VER_RLVID_SHIFT
) &
821 RTL8367_CHIP_VER_RLVID_MASK
;
823 REG_RD(smi
, RTL8367_CHIP_MODE_REG
, &data
);
824 mode
= data
& RTL8367_CHIP_MODE_MASK
;
828 err
= rtl8367_init_regs0(smi
, mode
);
832 err
= rtl8367_write_phy_reg(smi
, 0, 31, 5);
836 err
= rtl8367_write_phy_reg(smi
, 0, 5, 0x3ffe);
840 err
= rtl8367_read_phy_reg(smi
, 0, 6, &data
);
844 if (data
== 0x94eb) {
845 err
= rtl8367_init_regs1(smi
, mode
);
846 } else if (data
== 0x2104) {
847 err
= rtl8367_init_regs2(smi
, mode
);
849 dev_err(smi
->parent
, "unknow phy data %04x\n", data
);
856 dev_err(smi
->parent
, "unknow rlvid %u\n", rlvid
);
864 static int rtl8367_reset_chip(struct rtl8366_smi
*smi
)
870 REG_WR(smi
, RTL8367_CHIP_RESET_REG
, RTL8367_CHIP_RESET_HW
);
871 msleep(RTL8367_RESET_DELAY
);
874 REG_RD(smi
, RTL8367_CHIP_RESET_REG
, &data
);
875 if (!(data
& RTL8367_CHIP_RESET_HW
))
882 dev_err(smi
->parent
, "chip reset timed out\n");
889 static int rtl8367_extif_set_mode(struct rtl8366_smi
*smi
, int id
,
890 enum rtl8367_extif_mode mode
)
896 case RTL8367_EXTIF_MODE_RGMII
:
897 case RTL8367_EXTIF_MODE_RGMII_33V
:
898 REG_WR(smi
, RTL8367_CHIP_DEBUG0_REG
, 0x0367);
899 REG_WR(smi
, RTL8367_CHIP_DEBUG1_REG
, 0x7777);
902 case RTL8367_EXTIF_MODE_TMII_MAC
:
903 case RTL8367_EXTIF_MODE_TMII_PHY
:
904 REG_RMW(smi
, RTL8367_BYPASS_LINE_RATE_REG
,
905 BIT((id
+ 1) % 2), BIT((id
+ 1) % 2));
908 case RTL8367_EXTIF_MODE_GMII
:
909 REG_RMW(smi
, RTL8367_CHIP_DEBUG0_REG
,
910 RTL8367_CHIP_DEBUG0_DUMMY0(id
),
911 RTL8367_CHIP_DEBUG0_DUMMY0(id
));
912 REG_RMW(smi
, RTL8367_EXT_RGMXF_REG(id
), BIT(6), BIT(6));
915 case RTL8367_EXTIF_MODE_MII_MAC
:
916 case RTL8367_EXTIF_MODE_MII_PHY
:
917 case RTL8367_EXTIF_MODE_DISABLED
:
918 REG_RMW(smi
, RTL8367_BYPASS_LINE_RATE_REG
,
919 BIT((id
+ 1) % 2), 0);
920 REG_RMW(smi
, RTL8367_EXT_RGMXF_REG(id
), BIT(6), 0);
925 "invalid mode for external interface %d\n", id
);
929 REG_RMW(smi
, RTL8367_DIS_REG
,
930 RTL8367_DIS_RGMII_MASK
<< RTL8367_DIS_RGMII_SHIFT(id
),
931 mode
<< RTL8367_DIS_RGMII_SHIFT(id
));
936 static int rtl8367_extif_set_force(struct rtl8366_smi
*smi
, int id
,
937 struct rtl8367_port_ability
*pa
)
943 mask
= (RTL8367_DI_FORCE_MODE
|
944 RTL8367_DI_FORCE_NWAY
|
945 RTL8367_DI_FORCE_TXPAUSE
|
946 RTL8367_DI_FORCE_RXPAUSE
|
947 RTL8367_DI_FORCE_LINK
|
948 RTL8367_DI_FORCE_DUPLEX
|
949 RTL8367_DI_FORCE_SPEED_MASK
);
952 val
|= pa
->force_mode
? RTL8367_DI_FORCE_MODE
: 0;
953 val
|= pa
->nway
? RTL8367_DI_FORCE_NWAY
: 0;
954 val
|= pa
->txpause
? RTL8367_DI_FORCE_TXPAUSE
: 0;
955 val
|= pa
->rxpause
? RTL8367_DI_FORCE_RXPAUSE
: 0;
956 val
|= pa
->link
? RTL8367_DI_FORCE_LINK
: 0;
957 val
|= pa
->duplex
? RTL8367_DI_FORCE_DUPLEX
: 0;
959 REG_RMW(smi
, RTL8367_DI_FORCE_REG(id
), mask
, val
);
964 static int rtl8367_extif_set_rgmii_delay(struct rtl8366_smi
*smi
, int id
,
965 unsigned txdelay
, unsigned rxdelay
)
971 mask
= (RTL8367_EXT_RGMXF_RXDELAY_MASK
|
972 (RTL8367_EXT_RGMXF_TXDELAY_MASK
<<
973 RTL8367_EXT_RGMXF_TXDELAY_SHIFT
));
976 val
|= txdelay
<< RTL8367_EXT_RGMXF_TXDELAY_SHIFT
;
978 REG_RMW(smi
, RTL8367_EXT_RGMXF_REG(id
), mask
, val
);
983 static int rtl8367_extif_init(struct rtl8366_smi
*smi
, int id
,
984 struct rtl8367_extif_config
*cfg
)
986 enum rtl8367_extif_mode mode
;
989 mode
= (cfg
) ? cfg
->mode
: RTL8367_EXTIF_MODE_DISABLED
;
991 err
= rtl8367_extif_set_mode(smi
, id
, mode
);
995 if (mode
!= RTL8367_EXTIF_MODE_DISABLED
) {
996 err
= rtl8367_extif_set_force(smi
, id
, &cfg
->ability
);
1000 err
= rtl8367_extif_set_rgmii_delay(smi
, id
, cfg
->txdelay
,
1009 static int rtl8367_led_group_set_ports(struct rtl8366_smi
*smi
,
1010 unsigned int group
, u16 port_mask
)
1016 port_mask
&= RTL8367_PARA_LED_IO_EN_PMASK
;
1017 s
= (group
% 2) * 8;
1018 reg
= RTL8367_PARA_LED_IO_EN1_REG
+ (group
/ 2);
1020 REG_RMW(smi
, reg
, (RTL8367_PARA_LED_IO_EN_PMASK
<< s
), port_mask
<< s
);
1025 static int rtl8367_led_group_set_mode(struct rtl8366_smi
*smi
,
1032 mode
&= RTL8367_LED_CONFIG_DATA_M
;
1034 mask
= (RTL8367_LED_CONFIG_DATA_M
<< RTL8367_LED_CONFIG_DATA_S
) |
1035 RTL8367_LED_CONFIG_SEL
;
1036 set
= (mode
<< RTL8367_LED_CONFIG_DATA_S
) | RTL8367_LED_CONFIG_SEL
;
1038 REG_RMW(smi
, RTL8367_LED_CONFIG_REG
, mask
, set
);
1043 static int rtl8367_led_group_set_config(struct rtl8366_smi
*smi
,
1044 unsigned int led
, unsigned int cfg
)
1050 mask
= (RTL8367_LED_CONFIG_LED_CFG_M
<< (led
* 4)) |
1051 RTL8367_LED_CONFIG_SEL
;
1052 set
= (cfg
& RTL8367_LED_CONFIG_LED_CFG_M
) << (led
* 4);
1054 REG_RMW(smi
, RTL8367_LED_CONFIG_REG
, mask
, set
);
1058 static int rtl8367_led_op_select_parallel(struct rtl8366_smi
*smi
)
1062 REG_WR(smi
, RTL8367_LED_SYS_CONFIG_REG
, 0x1472);
1066 static int rtl8367_led_blinkrate_set(struct rtl8366_smi
*smi
, unsigned int rate
)
1072 mask
= RTL8367_LED_MODE_RATE_M
<< RTL8367_LED_MODE_RATE_S
;
1073 set
= (rate
& RTL8367_LED_MODE_RATE_M
) << RTL8367_LED_MODE_RATE_S
;
1074 REG_RMW(smi
, RTL8367_LED_MODE_REG
, mask
, set
);
1080 static int rtl8367_extif_init_of(struct rtl8366_smi
*smi
, int id
,
1083 struct rtl8367_extif_config
*cfg
;
1088 prop
= of_get_property(smi
->parent
->of_node
, name
, &size
);
1090 return rtl8367_extif_init(smi
, id
, NULL
);
1092 if (size
!= (9 * sizeof(*prop
))) {
1093 dev_err(smi
->parent
, "%s property is invalid\n", name
);
1097 cfg
= kzalloc(sizeof(struct rtl8367_extif_config
), GFP_KERNEL
);
1101 cfg
->txdelay
= be32_to_cpup(prop
++);
1102 cfg
->rxdelay
= be32_to_cpup(prop
++);
1103 cfg
->mode
= be32_to_cpup(prop
++);
1104 cfg
->ability
.force_mode
= be32_to_cpup(prop
++);
1105 cfg
->ability
.txpause
= be32_to_cpup(prop
++);
1106 cfg
->ability
.rxpause
= be32_to_cpup(prop
++);
1107 cfg
->ability
.link
= be32_to_cpup(prop
++);
1108 cfg
->ability
.duplex
= be32_to_cpup(prop
++);
1109 cfg
->ability
.speed
= be32_to_cpup(prop
++);
1111 err
= rtl8367_extif_init(smi
, id
, cfg
);
1117 static int rtl8367_extif_init_of(struct rtl8366_smi
*smi
, int id
,
1124 static int rtl8367_setup(struct rtl8366_smi
*smi
)
1126 struct rtl8367_platform_data
*pdata
;
1130 pdata
= smi
->parent
->platform_data
;
1132 err
= rtl8367_init_regs(smi
);
1136 /* initialize external interfaces */
1137 if (smi
->parent
->of_node
) {
1138 err
= rtl8367_extif_init_of(smi
, 0, "realtek,extif0");
1142 err
= rtl8367_extif_init_of(smi
, 1, "realtek,extif1");
1146 err
= rtl8367_extif_init(smi
, 0, pdata
->extif0_cfg
);
1150 err
= rtl8367_extif_init(smi
, 1, pdata
->extif1_cfg
);
1155 /* set maximum packet length to 1536 bytes */
1156 REG_RMW(smi
, RTL8367_SWC0_REG
, RTL8367_SWC0_MAX_LENGTH_MASK
,
1157 RTL8367_SWC0_MAX_LENGTH_1536
);
1160 * discard VLAN tagged packets if the port is not a member of
1161 * the VLAN with which the packets is associated.
1163 REG_WR(smi
, RTL8367_VLAN_INGRESS_REG
, RTL8367_PORTS_ALL
);
1166 * Setup egress tag mode for each port.
1168 for (i
= 0; i
< RTL8367_NUM_PORTS
; i
++)
1170 RTL8367_PORT_CFG_REG(i
),
1171 RTL8367_PORT_CFG_EGRESS_MODE_MASK
<<
1172 RTL8367_PORT_CFG_EGRESS_MODE_SHIFT
,
1173 RTL8367_PORT_CFG_EGRESS_MODE_ORIGINAL
<<
1174 RTL8367_PORT_CFG_EGRESS_MODE_SHIFT
);
1177 err
= rtl8367_led_group_set_ports(smi
, 0, RTL8367_PORTS_ALL
);
1181 err
= rtl8367_led_group_set_mode(smi
, 0);
1185 err
= rtl8367_led_op_select_parallel(smi
);
1189 err
= rtl8367_led_blinkrate_set(smi
, 1);
1193 err
= rtl8367_led_group_set_config(smi
, 0, 2);
1200 static int rtl8367_get_mib_counter(struct rtl8366_smi
*smi
, int counter
,
1201 int port
, unsigned long long *val
)
1203 struct rtl8366_mib_counter
*mib
;
1210 if (port
> RTL8367_NUM_PORTS
|| counter
>= RTL8367_MIB_COUNT
)
1213 mib
= &rtl8367_mib_counters
[counter
];
1214 addr
= RTL8367_MIB_COUNTER_PORT_OFFSET
* port
+ mib
->offset
;
1217 * Writing access counter address first
1218 * then ASIC will prepare 64bits counter wait for being retrived
1220 REG_WR(smi
, RTL8367_MIB_ADDRESS_REG
, addr
>> 2);
1222 /* read MIB control register */
1223 REG_RD(smi
, RTL8367_MIB_CTRL_REG(0), &data
);
1225 if (data
& RTL8367_MIB_CTRL_BUSY_MASK
)
1228 if (data
& RTL8367_MIB_CTRL_RESET_MASK
)
1231 if (mib
->length
== 4)
1234 offset
= (mib
->offset
+ 1) % 4;
1237 for (i
= 0; i
< mib
->length
; i
++) {
1238 REG_RD(smi
, RTL8367_MIB_COUNTER_REG(offset
- i
), &data
);
1239 mibvalue
= (mibvalue
<< 16) | (data
& 0xFFFF);
1246 static int rtl8367_get_vlan_4k(struct rtl8366_smi
*smi
, u32 vid
,
1247 struct rtl8366_vlan_4k
*vlan4k
)
1249 u32 data
[RTL8367_TA_VLAN_DATA_SIZE
];
1253 memset(vlan4k
, '\0', sizeof(struct rtl8366_vlan_4k
));
1255 if (vid
>= RTL8367_NUM_VIDS
)
1259 REG_WR(smi
, RTL8367_TA_ADDR_REG
, vid
);
1261 /* write table access control word */
1262 REG_WR(smi
, RTL8367_TA_CTRL_REG
, RTL8367_TA_CTRL_CVLAN_READ
);
1264 for (i
= 0; i
< ARRAY_SIZE(data
); i
++)
1265 REG_RD(smi
, RTL8367_TA_DATA_REG(i
), &data
[i
]);
1268 vlan4k
->member
= (data
[0] >> RTL8367_TA_VLAN_MEMBER_SHIFT
) &
1269 RTL8367_TA_VLAN_MEMBER_MASK
;
1270 vlan4k
->fid
= (data
[1] >> RTL8367_TA_VLAN_FID_SHIFT
) &
1271 RTL8367_TA_VLAN_FID_MASK
;
1272 vlan4k
->untag
= (data
[2] >> RTL8367_TA_VLAN_UNTAG1_SHIFT
) &
1273 RTL8367_TA_VLAN_UNTAG1_MASK
;
1274 vlan4k
->untag
|= ((data
[3] >> RTL8367_TA_VLAN_UNTAG2_SHIFT
) &
1275 RTL8367_TA_VLAN_UNTAG2_MASK
) << 2;
1280 static int rtl8367_set_vlan_4k(struct rtl8366_smi
*smi
,
1281 const struct rtl8366_vlan_4k
*vlan4k
)
1283 u32 data
[RTL8367_TA_VLAN_DATA_SIZE
];
1287 if (vlan4k
->vid
>= RTL8367_NUM_VIDS
||
1288 vlan4k
->member
> RTL8367_TA_VLAN_MEMBER_MASK
||
1289 vlan4k
->untag
> RTL8367_UNTAG_MASK
||
1290 vlan4k
->fid
> RTL8367_FIDMAX
)
1293 data
[0] = (vlan4k
->member
& RTL8367_TA_VLAN_MEMBER_MASK
) <<
1294 RTL8367_TA_VLAN_MEMBER_SHIFT
;
1295 data
[1] = (vlan4k
->fid
& RTL8367_TA_VLAN_FID_MASK
) <<
1296 RTL8367_TA_VLAN_FID_SHIFT
;
1297 data
[2] = (vlan4k
->untag
& RTL8367_TA_VLAN_UNTAG1_MASK
) <<
1298 RTL8367_TA_VLAN_UNTAG1_SHIFT
;
1299 data
[3] = ((vlan4k
->untag
>> 2) & RTL8367_TA_VLAN_UNTAG2_MASK
) <<
1300 RTL8367_TA_VLAN_UNTAG2_SHIFT
;
1302 for (i
= 0; i
< ARRAY_SIZE(data
); i
++)
1303 REG_WR(smi
, RTL8367_TA_DATA_REG(i
), data
[i
]);
1306 REG_WR(smi
, RTL8367_TA_ADDR_REG
,
1307 vlan4k
->vid
& RTL8367_TA_VLAN_VID_MASK
);
1309 /* write table access control word */
1310 REG_WR(smi
, RTL8367_TA_CTRL_REG
, RTL8367_TA_CTRL_CVLAN_WRITE
);
1315 static int rtl8367_get_vlan_mc(struct rtl8366_smi
*smi
, u32 index
,
1316 struct rtl8366_vlan_mc
*vlanmc
)
1318 u32 data
[RTL8367_VLAN_MC_DATA_SIZE
];
1322 memset(vlanmc
, '\0', sizeof(struct rtl8366_vlan_mc
));
1324 if (index
>= RTL8367_NUM_VLANS
)
1327 for (i
= 0; i
< ARRAY_SIZE(data
); i
++)
1328 REG_RD(smi
, RTL8367_VLAN_MC_BASE(index
) + i
, &data
[i
]);
1330 vlanmc
->member
= (data
[0] >> RTL8367_VLAN_MC_MEMBER_SHIFT
) &
1331 RTL8367_VLAN_MC_MEMBER_MASK
;
1332 vlanmc
->fid
= (data
[1] >> RTL8367_VLAN_MC_FID_SHIFT
) &
1333 RTL8367_VLAN_MC_FID_MASK
;
1334 vlanmc
->vid
= (data
[3] >> RTL8367_VLAN_MC_EVID_SHIFT
) &
1335 RTL8367_VLAN_MC_EVID_MASK
;
1340 static int rtl8367_set_vlan_mc(struct rtl8366_smi
*smi
, u32 index
,
1341 const struct rtl8366_vlan_mc
*vlanmc
)
1343 u32 data
[RTL8367_VLAN_MC_DATA_SIZE
];
1347 if (index
>= RTL8367_NUM_VLANS
||
1348 vlanmc
->vid
>= RTL8367_NUM_VIDS
||
1349 vlanmc
->priority
> RTL8367_PRIORITYMAX
||
1350 vlanmc
->member
> RTL8367_VLAN_MC_MEMBER_MASK
||
1351 vlanmc
->untag
> RTL8367_UNTAG_MASK
||
1352 vlanmc
->fid
> RTL8367_FIDMAX
)
1355 data
[0] = (vlanmc
->member
& RTL8367_VLAN_MC_MEMBER_MASK
) <<
1356 RTL8367_VLAN_MC_MEMBER_SHIFT
;
1357 data
[1] = (vlanmc
->fid
& RTL8367_VLAN_MC_FID_MASK
) <<
1358 RTL8367_VLAN_MC_FID_SHIFT
;
1360 data
[3] = (vlanmc
->vid
& RTL8367_VLAN_MC_EVID_MASK
) <<
1361 RTL8367_VLAN_MC_EVID_SHIFT
;
1363 for (i
= 0; i
< ARRAY_SIZE(data
); i
++)
1364 REG_WR(smi
, RTL8367_VLAN_MC_BASE(index
) + i
, data
[i
]);
1369 static int rtl8367_get_mc_index(struct rtl8366_smi
*smi
, int port
, int *val
)
1374 if (port
>= RTL8367_NUM_PORTS
)
1377 REG_RD(smi
, RTL8367_VLAN_PVID_CTRL_REG(port
), &data
);
1379 *val
= (data
>> RTL8367_VLAN_PVID_CTRL_SHIFT(port
)) &
1380 RTL8367_VLAN_PVID_CTRL_MASK
;
1385 static int rtl8367_set_mc_index(struct rtl8366_smi
*smi
, int port
, int index
)
1387 if (port
>= RTL8367_NUM_PORTS
|| index
>= RTL8367_NUM_VLANS
)
1390 return rtl8366_smi_rmwr(smi
, RTL8367_VLAN_PVID_CTRL_REG(port
),
1391 RTL8367_VLAN_PVID_CTRL_MASK
<<
1392 RTL8367_VLAN_PVID_CTRL_SHIFT(port
),
1393 (index
& RTL8367_VLAN_PVID_CTRL_MASK
) <<
1394 RTL8367_VLAN_PVID_CTRL_SHIFT(port
));
1397 static int rtl8367_enable_vlan(struct rtl8366_smi
*smi
, int enable
)
1399 return rtl8366_smi_rmwr(smi
, RTL8367_VLAN_CTRL_REG
,
1400 RTL8367_VLAN_CTRL_ENABLE
,
1401 (enable
) ? RTL8367_VLAN_CTRL_ENABLE
: 0);
1404 static int rtl8367_enable_vlan4k(struct rtl8366_smi
*smi
, int enable
)
1409 static int rtl8367_is_vlan_valid(struct rtl8366_smi
*smi
, unsigned vlan
)
1411 unsigned max
= RTL8367_NUM_VLANS
;
1413 if (smi
->vlan4k_enabled
)
1414 max
= RTL8367_NUM_VIDS
- 1;
1416 if (vlan
== 0 || vlan
>= max
)
1422 static int rtl8367_enable_port(struct rtl8366_smi
*smi
, int port
, int enable
)
1426 REG_WR(smi
, RTL8367_PORT_ISOLATION_REG(port
),
1427 (enable
) ? RTL8367_PORTS_ALL
: 0);
1432 static int rtl8367_sw_reset_mibs(struct switch_dev
*dev
,
1433 const struct switch_attr
*attr
,
1434 struct switch_val
*val
)
1436 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1438 return rtl8366_smi_rmwr(smi
, RTL8367_MIB_CTRL_REG(0), 0,
1439 RTL8367_MIB_CTRL_GLOBAL_RESET_MASK
);
1442 static int rtl8367_sw_get_port_link(struct switch_dev
*dev
,
1444 struct switch_port_link
*link
)
1446 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1450 if (port
>= RTL8367_NUM_PORTS
)
1453 rtl8366_smi_read_reg(smi
, RTL8367_PORT_STATUS_REG(port
), &data
);
1455 link
->link
= !!(data
& RTL8367_PORT_STATUS_LINK
);
1459 link
->duplex
= !!(data
& RTL8367_PORT_STATUS_DUPLEX
);
1460 link
->rx_flow
= !!(data
& RTL8367_PORT_STATUS_RXPAUSE
);
1461 link
->tx_flow
= !!(data
& RTL8367_PORT_STATUS_TXPAUSE
);
1462 link
->aneg
= !!(data
& RTL8367_PORT_STATUS_NWAY
);
1464 speed
= (data
& RTL8367_PORT_STATUS_SPEED_MASK
);
1467 link
->speed
= SWITCH_PORT_SPEED_10
;
1470 link
->speed
= SWITCH_PORT_SPEED_100
;
1473 link
->speed
= SWITCH_PORT_SPEED_1000
;
1476 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
1483 static int rtl8367_sw_get_max_length(struct switch_dev
*dev
,
1484 const struct switch_attr
*attr
,
1485 struct switch_val
*val
)
1487 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1490 rtl8366_smi_read_reg(smi
, RTL8367_SWC0_REG
, &data
);
1491 val
->value
.i
= (data
& RTL8367_SWC0_MAX_LENGTH_MASK
) >>
1492 RTL8367_SWC0_MAX_LENGTH_SHIFT
;
1497 static int rtl8367_sw_set_max_length(struct switch_dev
*dev
,
1498 const struct switch_attr
*attr
,
1499 struct switch_val
*val
)
1501 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1504 switch (val
->value
.i
) {
1506 max_len
= RTL8367_SWC0_MAX_LENGTH_1522
;
1509 max_len
= RTL8367_SWC0_MAX_LENGTH_1536
;
1512 max_len
= RTL8367_SWC0_MAX_LENGTH_1552
;
1515 max_len
= RTL8367_SWC0_MAX_LENGTH_16000
;
1521 return rtl8366_smi_rmwr(smi
, RTL8367_SWC0_REG
,
1522 RTL8367_SWC0_MAX_LENGTH_MASK
, max_len
);
1526 static int rtl8367_sw_reset_port_mibs(struct switch_dev
*dev
,
1527 const struct switch_attr
*attr
,
1528 struct switch_val
*val
)
1530 struct rtl8366_smi
*smi
= sw_to_rtl8366_smi(dev
);
1533 port
= val
->port_vlan
;
1534 if (port
>= RTL8367_NUM_PORTS
)
1537 return rtl8366_smi_rmwr(smi
, RTL8367_MIB_CTRL_REG(port
/ 8), 0,
1538 RTL8367_MIB_CTRL_PORT_RESET_MASK(port
% 8));
1541 static int rtl8367_sw_get_port_stats(struct switch_dev
*dev
, int port
,
1542 struct switch_port_stats
*stats
)
1544 return (rtl8366_sw_get_port_stats(dev
, port
, stats
,
1545 RTL8367_MIB_TXB_ID
, RTL8367_MIB_RXB_ID
));
1548 static struct switch_attr rtl8367_globals
[] = {
1550 .type
= SWITCH_TYPE_INT
,
1551 .name
= "enable_vlan",
1552 .description
= "Enable VLAN mode",
1553 .set
= rtl8366_sw_set_vlan_enable
,
1554 .get
= rtl8366_sw_get_vlan_enable
,
1558 .type
= SWITCH_TYPE_INT
,
1559 .name
= "enable_vlan4k",
1560 .description
= "Enable VLAN 4K mode",
1561 .set
= rtl8366_sw_set_vlan_enable
,
1562 .get
= rtl8366_sw_get_vlan_enable
,
1566 .type
= SWITCH_TYPE_NOVAL
,
1567 .name
= "reset_mibs",
1568 .description
= "Reset all MIB counters",
1569 .set
= rtl8367_sw_reset_mibs
,
1571 .type
= SWITCH_TYPE_INT
,
1572 .name
= "max_length",
1573 .description
= "Get/Set the maximum length of valid packets"
1574 "(0:1522, 1:1536, 2:1552, 3:16000)",
1575 .set
= rtl8367_sw_set_max_length
,
1576 .get
= rtl8367_sw_get_max_length
,
1581 static struct switch_attr rtl8367_port
[] = {
1583 .type
= SWITCH_TYPE_NOVAL
,
1584 .name
= "reset_mib",
1585 .description
= "Reset single port MIB counters",
1586 .set
= rtl8367_sw_reset_port_mibs
,
1588 .type
= SWITCH_TYPE_STRING
,
1590 .description
= "Get MIB counters for port",
1593 .get
= rtl8366_sw_get_port_mib
,
1597 static struct switch_attr rtl8367_vlan
[] = {
1599 .type
= SWITCH_TYPE_STRING
,
1601 .description
= "Get vlan information",
1604 .get
= rtl8366_sw_get_vlan_info
,
1606 .type
= SWITCH_TYPE_INT
,
1608 .description
= "Get/Set vlan FID",
1609 .max
= RTL8367_FIDMAX
,
1610 .set
= rtl8366_sw_set_vlan_fid
,
1611 .get
= rtl8366_sw_get_vlan_fid
,
1615 static const struct switch_dev_ops rtl8367_sw_ops
= {
1617 .attr
= rtl8367_globals
,
1618 .n_attr
= ARRAY_SIZE(rtl8367_globals
),
1621 .attr
= rtl8367_port
,
1622 .n_attr
= ARRAY_SIZE(rtl8367_port
),
1625 .attr
= rtl8367_vlan
,
1626 .n_attr
= ARRAY_SIZE(rtl8367_vlan
),
1629 .get_vlan_ports
= rtl8366_sw_get_vlan_ports
,
1630 .set_vlan_ports
= rtl8366_sw_set_vlan_ports
,
1631 .get_port_pvid
= rtl8366_sw_get_port_pvid
,
1632 .set_port_pvid
= rtl8366_sw_set_port_pvid
,
1633 .reset_switch
= rtl8366_sw_reset_switch
,
1634 .get_port_link
= rtl8367_sw_get_port_link
,
1635 .get_port_stats
= rtl8367_sw_get_port_stats
,
1638 static int rtl8367_switch_init(struct rtl8366_smi
*smi
)
1640 struct switch_dev
*dev
= &smi
->sw_dev
;
1643 dev
->name
= "RTL8367";
1644 dev
->cpu_port
= RTL8367_CPU_PORT_NUM
;
1645 dev
->ports
= RTL8367_NUM_PORTS
;
1646 dev
->vlans
= RTL8367_NUM_VIDS
;
1647 dev
->ops
= &rtl8367_sw_ops
;
1648 dev
->alias
= dev_name(smi
->parent
);
1650 err
= register_switch(dev
, NULL
);
1652 dev_err(smi
->parent
, "switch registration failed\n");
1657 static void rtl8367_switch_cleanup(struct rtl8366_smi
*smi
)
1659 unregister_switch(&smi
->sw_dev
);
1662 static int rtl8367_mii_read(struct mii_bus
*bus
, int addr
, int reg
)
1664 struct rtl8366_smi
*smi
= bus
->priv
;
1668 err
= rtl8367_read_phy_reg(smi
, addr
, reg
, &val
);
1675 static int rtl8367_mii_write(struct mii_bus
*bus
, int addr
, int reg
, u16 val
)
1677 struct rtl8366_smi
*smi
= bus
->priv
;
1681 err
= rtl8367_write_phy_reg(smi
, addr
, reg
, val
);
1686 (void) rtl8367_read_phy_reg(smi
, addr
, reg
, &t
);
1691 static int rtl8367_detect(struct rtl8366_smi
*smi
)
1698 ret
= rtl8366_smi_read_reg(smi
, RTL8367_RTL_NO_REG
, &rtl_no
);
1700 dev_err(smi
->parent
, "unable to read chip number\n");
1705 case RTL8367_RTL_NO_8367R
:
1706 chip_name
= "8367R";
1708 case RTL8367_RTL_NO_8367M
:
1709 chip_name
= "8367M";
1712 dev_err(smi
->parent
, "unknown chip number (%04x)\n", rtl_no
);
1716 ret
= rtl8366_smi_read_reg(smi
, RTL8367_RTL_VER_REG
, &rtl_ver
);
1718 dev_err(smi
->parent
, "unable to read chip version\n");
1722 dev_info(smi
->parent
, "RTL%s ver. %u chip found\n",
1723 chip_name
, rtl_ver
& RTL8367_RTL_VER_MASK
);
1728 static struct rtl8366_smi_ops rtl8367_smi_ops
= {
1729 .detect
= rtl8367_detect
,
1730 .reset_chip
= rtl8367_reset_chip
,
1731 .setup
= rtl8367_setup
,
1733 .mii_read
= rtl8367_mii_read
,
1734 .mii_write
= rtl8367_mii_write
,
1736 .get_vlan_mc
= rtl8367_get_vlan_mc
,
1737 .set_vlan_mc
= rtl8367_set_vlan_mc
,
1738 .get_vlan_4k
= rtl8367_get_vlan_4k
,
1739 .set_vlan_4k
= rtl8367_set_vlan_4k
,
1740 .get_mc_index
= rtl8367_get_mc_index
,
1741 .set_mc_index
= rtl8367_set_mc_index
,
1742 .get_mib_counter
= rtl8367_get_mib_counter
,
1743 .is_vlan_valid
= rtl8367_is_vlan_valid
,
1744 .enable_vlan
= rtl8367_enable_vlan
,
1745 .enable_vlan4k
= rtl8367_enable_vlan4k
,
1746 .enable_port
= rtl8367_enable_port
,
1749 static int rtl8367_probe(struct platform_device
*pdev
)
1751 struct rtl8366_smi
*smi
;
1754 smi
= rtl8366_smi_probe(pdev
);
1758 smi
->clk_delay
= 1500;
1759 smi
->cmd_read
= 0xb9;
1760 smi
->cmd_write
= 0xb8;
1761 smi
->ops
= &rtl8367_smi_ops
;
1762 smi
->cpu_port
= RTL8367_CPU_PORT_NUM
;
1763 smi
->num_ports
= RTL8367_NUM_PORTS
;
1764 smi
->num_vlan_mc
= RTL8367_NUM_VLANS
;
1765 smi
->mib_counters
= rtl8367_mib_counters
;
1766 smi
->num_mib_counters
= ARRAY_SIZE(rtl8367_mib_counters
);
1768 err
= rtl8366_smi_init(smi
);
1772 platform_set_drvdata(pdev
, smi
);
1774 err
= rtl8367_switch_init(smi
);
1776 goto err_clear_drvdata
;
1781 platform_set_drvdata(pdev
, NULL
);
1782 rtl8366_smi_cleanup(smi
);
1788 static int rtl8367_remove(struct platform_device
*pdev
)
1790 struct rtl8366_smi
*smi
= platform_get_drvdata(pdev
);
1793 rtl8367_switch_cleanup(smi
);
1794 platform_set_drvdata(pdev
, NULL
);
1795 rtl8366_smi_cleanup(smi
);
1802 static void rtl8367_shutdown(struct platform_device
*pdev
)
1804 struct rtl8366_smi
*smi
= platform_get_drvdata(pdev
);
1807 rtl8367_reset_chip(smi
);
1811 static const struct of_device_id rtl8367_match
[] = {
1812 { .compatible
= "realtek,rtl8367" },
1815 MODULE_DEVICE_TABLE(of
, rtl8367_match
);
1818 static struct platform_driver rtl8367_driver
= {
1820 .name
= RTL8367_DRIVER_NAME
,
1821 .owner
= THIS_MODULE
,
1823 .of_match_table
= of_match_ptr(rtl8367_match
),
1826 .probe
= rtl8367_probe
,
1827 .remove
= rtl8367_remove
,
1828 .shutdown
= rtl8367_shutdown
,
1831 static int __init
rtl8367_module_init(void)
1833 return platform_driver_register(&rtl8367_driver
);
1835 module_init(rtl8367_module_init
);
1837 static void __exit
rtl8367_module_exit(void)
1839 platform_driver_unregister(&rtl8367_driver
);
1841 module_exit(rtl8367_module_exit
);
1843 MODULE_DESCRIPTION("Realtek RTL8367 ethernet switch driver");
1844 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1845 MODULE_LICENSE("GPL v2");
1846 MODULE_ALIAS("platform:" RTL8367_DRIVER_NAME
);