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generic: rtl8366: use SWITCH_TYPE_NOVAL for reset_mib attributes
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / rtl8366rb.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366rb.h>
20
21 #include "rtl8366_smi.h"
22
23 #define RTL8366RB_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
24 #define RTL8366RB_DRIVER_VER "0.2.2"
25
26 #define RTL8366RB_PHY_NO_MAX 4
27 #define RTL8366RB_PHY_PAGE_MAX 7
28 #define RTL8366RB_PHY_ADDR_MAX 31
29
30 /* Switch Global Configuration register */
31 #define RTL8366RB_SGCR 0x0000
32 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0)
33 #define RTL8366RB_SGCR_MAX_LENGTH(_x) (_x << 4)
34 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3)
35 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0)
36 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1)
37 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2)
38 #define RTL8366RB_SGCR_MAX_LENGTH_9216 RTL8366RB_SGCR_MAX_LENGTH(0x3)
39 #define RTL8366RB_SGCR_EN_VLAN BIT(13)
40 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14)
41
42 /* Port Enable Control register */
43 #define RTL8366RB_PECR 0x0001
44
45 /* Switch Security Control registers */
46 #define RTL8366RB_SSCR0 0x0002
47 #define RTL8366RB_SSCR1 0x0003
48 #define RTL8366RB_SSCR2 0x0004
49 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0)
50
51 #define RTL8366RB_RESET_CTRL_REG 0x0100
52 #define RTL8366RB_CHIP_CTRL_RESET_HW 1
53 #define RTL8366RB_CHIP_CTRL_RESET_SW (1 << 1)
54
55 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A
56 #define RTL8366RB_CHIP_VERSION_MASK 0xf
57 #define RTL8366RB_CHIP_ID_REG 0x0509
58 #define RTL8366RB_CHIP_ID_8366 0x5937
59
60 /* PHY registers control */
61 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000
62 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002
63
64 #define RTL8366RB_PHY_CTRL_READ 1
65 #define RTL8366RB_PHY_CTRL_WRITE 0
66
67 #define RTL8366RB_PHY_REG_MASK 0x1f
68 #define RTL8366RB_PHY_PAGE_OFFSET 5
69 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5)
70 #define RTL8366RB_PHY_NO_OFFSET 9
71 #define RTL8366RB_PHY_NO_MASK (0x1f << 9)
72
73 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f
74
75 /* LED control registers */
76 #define RTL8366RB_LED_BLINKRATE_REG 0x0430
77 #define RTL8366RB_LED_BLINKRATE_BIT 0
78 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007
79
80 #define RTL8366RB_LED_CTRL_REG 0x0431
81 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432
82 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433
83
84 #define RTL8366RB_MIB_COUNT 33
85 #define RTL8366RB_GLOBAL_MIB_COUNT 1
86 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050
87 #define RTL8366RB_MIB_COUNTER_BASE 0x1000
88 #define RTL8366RB_MIB_CTRL_REG 0x13F0
89 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC
90 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0)
91 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1)
92 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p))
93 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11)
94
95 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063
96 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \
97 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
98 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf
99 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
100
101
102 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C
103 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185
104
105
106 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180
107 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01
108 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01
109
110 #define RTL8366RB_VLAN_MEMCONF_BASE 0x0020
111
112
113 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014
114 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003
115 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004
116 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010
117 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020
118 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040
119 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080
120
121
122 #define RTL8366RB_PORT_NUM_CPU 5
123 #define RTL8366RB_NUM_PORTS 6
124 #define RTL8366RB_NUM_VLANS 16
125 #define RTL8366RB_NUM_LEDGROUPS 4
126 #define RTL8366RB_NUM_VIDS 4096
127 #define RTL8366RB_PRIORITYMAX 7
128 #define RTL8366RB_FIDMAX 7
129
130
131 #define RTL8366RB_PORT_1 (1 << 0) /* In userspace port 0 */
132 #define RTL8366RB_PORT_2 (1 << 1) /* In userspace port 1 */
133 #define RTL8366RB_PORT_3 (1 << 2) /* In userspace port 2 */
134 #define RTL8366RB_PORT_4 (1 << 3) /* In userspace port 3 */
135 #define RTL8366RB_PORT_5 (1 << 4) /* In userspace port 4 */
136
137 #define RTL8366RB_PORT_CPU (1 << 5) /* CPU port */
138
139 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \
140 RTL8366RB_PORT_2 | \
141 RTL8366RB_PORT_3 | \
142 RTL8366RB_PORT_4 | \
143 RTL8366RB_PORT_5 | \
144 RTL8366RB_PORT_CPU)
145
146 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \
147 RTL8366RB_PORT_2 | \
148 RTL8366RB_PORT_3 | \
149 RTL8366RB_PORT_4 | \
150 RTL8366RB_PORT_5)
151
152 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \
153 RTL8366RB_PORT_2 | \
154 RTL8366RB_PORT_3 | \
155 RTL8366RB_PORT_4)
156
157 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU
158
159 struct rtl8366rb {
160 struct device *parent;
161 struct rtl8366_smi smi;
162 struct switch_dev dev;
163 };
164
165 struct rtl8366rb_vlan_mc {
166 u16 reserved2:1;
167 u16 priority:3;
168 u16 vid:12;
169 u16 untag:8;
170 u16 member:8;
171 u16 stag_mbr:8;
172 u16 stag_idx:3;
173 u16 reserved1:2;
174 u16 fid:3;
175 };
176
177 struct rtl8366rb_vlan_4k {
178 u16 reserved1:4;
179 u16 vid:12;
180 u16 untag:8;
181 u16 member:8;
182 u16 reserved2:13;
183 u16 fid:3;
184 };
185
186 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
187 { 0, 0, 4, "IfInOctets" },
188 { 0, 4, 4, "EtherStatsOctets" },
189 { 0, 8, 2, "EtherStatsUnderSizePkts" },
190 { 0, 10, 2, "EtherFragments" },
191 { 0, 12, 2, "EtherStatsPkts64Octets" },
192 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
193 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
194 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
195 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
196 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
197 { 0, 24, 2, "EtherOversizeStats" },
198 { 0, 26, 2, "EtherStatsJabbers" },
199 { 0, 28, 2, "IfInUcastPkts" },
200 { 0, 30, 2, "EtherStatsMulticastPkts" },
201 { 0, 32, 2, "EtherStatsBroadcastPkts" },
202 { 0, 34, 2, "EtherStatsDropEvents" },
203 { 0, 36, 2, "Dot3StatsFCSErrors" },
204 { 0, 38, 2, "Dot3StatsSymbolErrors" },
205 { 0, 40, 2, "Dot3InPauseFrames" },
206 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
207 { 0, 44, 4, "IfOutOctets" },
208 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
209 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
210 { 0, 52, 2, "Dot3sDeferredTransmissions" },
211 { 0, 54, 2, "Dot3StatsLateCollisions" },
212 { 0, 56, 2, "EtherStatsCollisions" },
213 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
214 { 0, 60, 2, "Dot3OutPauseFrames" },
215 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
216 { 0, 64, 2, "Dot1dTpPortInDiscards" },
217 { 0, 66, 2, "IfOutUcastPkts" },
218 { 0, 68, 2, "IfOutMulticastPkts" },
219 { 0, 70, 2, "IfOutBroadcastPkts" },
220 };
221
222 #define REG_WR(_smi, _reg, _val) \
223 do { \
224 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
225 if (err) \
226 return err; \
227 } while (0)
228
229 #define REG_RMW(_smi, _reg, _mask, _val) \
230 do { \
231 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
232 if (err) \
233 return err; \
234 } while (0)
235
236 static inline struct rtl8366rb *smi_to_rtl8366rb(struct rtl8366_smi *smi)
237 {
238 return container_of(smi, struct rtl8366rb, smi);
239 }
240
241 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
242 {
243 return container_of(sw, struct rtl8366rb, dev);
244 }
245
246 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
247 {
248 struct rtl8366rb *rtl = sw_to_rtl8366rb(sw);
249 return &rtl->smi;
250 }
251
252 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
253 {
254 int timeout = 10;
255 u32 data;
256
257 rtl8366_smi_write_reg(smi, RTL8366RB_RESET_CTRL_REG,
258 RTL8366RB_CHIP_CTRL_RESET_HW);
259 do {
260 msleep(1);
261 if (rtl8366_smi_read_reg(smi, RTL8366RB_RESET_CTRL_REG, &data))
262 return -EIO;
263
264 if (!(data & RTL8366RB_CHIP_CTRL_RESET_HW))
265 break;
266 } while (--timeout);
267
268 if (!timeout) {
269 printk("Timeout waiting for the switch to reset\n");
270 return -EIO;
271 }
272
273 return 0;
274 }
275
276 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
277 {
278 int err;
279
280 /* set maximum packet length to 1536 bytes */
281 REG_RMW(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_MAX_LENGTH_MASK,
282 RTL8366RB_SGCR_MAX_LENGTH_1536);
283
284 /* enable all ports */
285 REG_WR(smi, RTL8366RB_PECR, 0);
286
287 /* disable learning for all ports */
288 REG_WR(smi, RTL8366RB_SSCR0, RTL8366RB_PORT_ALL);
289
290 /* disable auto ageing for all ports */
291 REG_WR(smi, RTL8366RB_SSCR1, RTL8366RB_PORT_ALL);
292
293 /*
294 * discard VLAN tagged packets if the port is not a member of
295 * the VLAN with which the packets is associated.
296 */
297 REG_WR(smi, RTL8366RB_VLAN_INGRESS_CTRL2_REG, RTL8366RB_PORT_ALL);
298
299 /* don't drop packets whose DA has not been learned */
300 REG_RMW(smi, RTL8366RB_SSCR2, RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
301
302 return 0;
303 }
304
305 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
306 u32 phy_no, u32 page, u32 addr, u32 *data)
307 {
308 u32 reg;
309 int ret;
310
311 if (phy_no > RTL8366RB_PHY_NO_MAX)
312 return -EINVAL;
313
314 if (page > RTL8366RB_PHY_PAGE_MAX)
315 return -EINVAL;
316
317 if (addr > RTL8366RB_PHY_ADDR_MAX)
318 return -EINVAL;
319
320 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
321 RTL8366RB_PHY_CTRL_READ);
322 if (ret)
323 return ret;
324
325 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
326 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
327 (addr & RTL8366RB_PHY_REG_MASK);
328
329 ret = rtl8366_smi_write_reg(smi, reg, 0);
330 if (ret)
331 return ret;
332
333 ret = rtl8366_smi_read_reg(smi, RTL8366RB_PHY_ACCESS_DATA_REG, data);
334 if (ret)
335 return ret;
336
337 return 0;
338 }
339
340 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
341 u32 phy_no, u32 page, u32 addr, u32 data)
342 {
343 u32 reg;
344 int ret;
345
346 if (phy_no > RTL8366RB_PHY_NO_MAX)
347 return -EINVAL;
348
349 if (page > RTL8366RB_PHY_PAGE_MAX)
350 return -EINVAL;
351
352 if (addr > RTL8366RB_PHY_ADDR_MAX)
353 return -EINVAL;
354
355 ret = rtl8366_smi_write_reg(smi, RTL8366RB_PHY_ACCESS_CTRL_REG,
356 RTL8366RB_PHY_CTRL_WRITE);
357 if (ret)
358 return ret;
359
360 reg = 0x8000 | (1 << (phy_no + RTL8366RB_PHY_NO_OFFSET)) |
361 ((page << RTL8366RB_PHY_PAGE_OFFSET) & RTL8366RB_PHY_PAGE_MASK) |
362 (addr & RTL8366RB_PHY_REG_MASK);
363
364 ret = rtl8366_smi_write_reg(smi, reg, data);
365 if (ret)
366 return ret;
367
368 return 0;
369 }
370
371 static int rtl8366rb_get_mib_counter(struct rtl8366_smi *smi, int counter,
372 int port, unsigned long long *val)
373 {
374 int i;
375 int err;
376 u32 addr, data;
377 u64 mibvalue;
378
379 if (port > RTL8366RB_NUM_PORTS || counter >= RTL8366RB_MIB_COUNT)
380 return -EINVAL;
381
382 addr = RTL8366RB_MIB_COUNTER_BASE +
383 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
384 rtl8366rb_mib_counters[counter].offset;
385
386 /*
387 * Writing access counter address first
388 * then ASIC will prepare 64bits counter wait for being retrived
389 */
390 data = 0; /* writing data will be discard by ASIC */
391 err = rtl8366_smi_write_reg(smi, addr, data);
392 if (err)
393 return err;
394
395 /* read MIB control register */
396 err = rtl8366_smi_read_reg(smi, RTL8366RB_MIB_CTRL_REG, &data);
397 if (err)
398 return err;
399
400 if (data & RTL8366RB_MIB_CTRL_BUSY_MASK)
401 return -EBUSY;
402
403 if (data & RTL8366RB_MIB_CTRL_RESET_MASK)
404 return -EIO;
405
406 mibvalue = 0;
407 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
408 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
409 if (err)
410 return err;
411
412 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
413 }
414
415 *val = mibvalue;
416 return 0;
417 }
418
419 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
420 struct rtl8366_vlan_4k *vlan4k)
421 {
422 struct rtl8366rb_vlan_4k vlan4k_priv;
423 int err;
424 u32 data;
425 u16 *tableaddr;
426
427 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
428 vlan4k_priv.vid = vid;
429
430 if (vid >= RTL8366RB_NUM_VIDS)
431 return -EINVAL;
432
433 tableaddr = (u16 *)&vlan4k_priv;
434
435 /* write VID */
436 data = *tableaddr;
437 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
438 if (err)
439 return err;
440
441 /* write table access control word */
442 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
443 RTL8366RB_TABLE_VLAN_READ_CTRL);
444 if (err)
445 return err;
446
447 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE, &data);
448 if (err)
449 return err;
450
451 *tableaddr = data;
452 tableaddr++;
453
454 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 1,
455 &data);
456 if (err)
457 return err;
458
459 *tableaddr = data;
460 tableaddr++;
461
462 err = rtl8366_smi_read_reg(smi, RTL8366RB_VLAN_TABLE_READ_BASE + 2,
463 &data);
464 if (err)
465 return err;
466 *tableaddr = data;
467
468 vlan4k->vid = vid;
469 vlan4k->untag = vlan4k_priv.untag;
470 vlan4k->member = vlan4k_priv.member;
471 vlan4k->fid = vlan4k_priv.fid;
472
473 return 0;
474 }
475
476 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
477 const struct rtl8366_vlan_4k *vlan4k)
478 {
479 struct rtl8366rb_vlan_4k vlan4k_priv;
480 int err;
481 u32 data;
482 u16 *tableaddr;
483
484 if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
485 vlan4k->member > RTL8366RB_PORT_ALL ||
486 vlan4k->untag > RTL8366RB_PORT_ALL ||
487 vlan4k->fid > RTL8366RB_FIDMAX)
488 return -EINVAL;
489
490 vlan4k_priv.vid = vlan4k->vid;
491 vlan4k_priv.untag = vlan4k->untag;
492 vlan4k_priv.member = vlan4k->member;
493 vlan4k_priv.fid = vlan4k->fid;
494
495 tableaddr = (u16 *)&vlan4k_priv;
496
497 data = *tableaddr;
498
499 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE, data);
500 if (err)
501 return err;
502
503 tableaddr++;
504
505 data = *tableaddr;
506
507 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 1,
508 data);
509 if (err)
510 return err;
511
512 tableaddr++;
513
514 data = *tableaddr;
515
516 err = rtl8366_smi_write_reg(smi, RTL8366RB_VLAN_TABLE_WRITE_BASE + 2,
517 data);
518 if (err)
519 return err;
520
521 /* write table access control word */
522 err = rtl8366_smi_write_reg(smi, RTL8366RB_TABLE_ACCESS_CTRL_REG,
523 RTL8366RB_TABLE_VLAN_WRITE_CTRL);
524
525 return err;
526 }
527
528 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
529 struct rtl8366_vlan_mc *vlanmc)
530 {
531 struct rtl8366rb_vlan_mc vlanmc_priv;
532 int err;
533 u32 addr;
534 u32 data;
535 u16 *tableaddr;
536
537 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
538
539 if (index >= RTL8366RB_NUM_VLANS)
540 return -EINVAL;
541
542 tableaddr = (u16 *)&vlanmc_priv;
543
544 addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
545 err = rtl8366_smi_read_reg(smi, addr, &data);
546 if (err)
547 return err;
548
549 *tableaddr = data;
550 tableaddr++;
551
552 addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
553 err = rtl8366_smi_read_reg(smi, addr, &data);
554 if (err)
555 return err;
556
557 *tableaddr = data;
558 tableaddr++;
559
560 addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
561 err = rtl8366_smi_read_reg(smi, addr, &data);
562 if (err)
563 return err;
564
565 *tableaddr = data;
566
567 vlanmc->vid = vlanmc_priv.vid;
568 vlanmc->priority = vlanmc_priv.priority;
569 vlanmc->untag = vlanmc_priv.untag;
570 vlanmc->member = vlanmc_priv.member;
571 vlanmc->fid = vlanmc_priv.fid;
572
573 return 0;
574 }
575
576 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
577 const struct rtl8366_vlan_mc *vlanmc)
578 {
579 struct rtl8366rb_vlan_mc vlanmc_priv;
580 int err;
581 u32 addr;
582 u32 data;
583 u16 *tableaddr;
584
585 if (index >= RTL8366RB_NUM_VLANS ||
586 vlanmc->vid >= RTL8366RB_NUM_VIDS ||
587 vlanmc->priority > RTL8366RB_PRIORITYMAX ||
588 vlanmc->member > RTL8366RB_PORT_ALL ||
589 vlanmc->untag > RTL8366RB_PORT_ALL ||
590 vlanmc->fid > RTL8366RB_FIDMAX)
591 return -EINVAL;
592
593 vlanmc_priv.vid = vlanmc->vid;
594 vlanmc_priv.priority = vlanmc->priority;
595 vlanmc_priv.untag = vlanmc->untag;
596 vlanmc_priv.member = vlanmc->member;
597 vlanmc_priv.stag_mbr = 0;
598 vlanmc_priv.stag_idx = 0;
599 vlanmc_priv.fid = vlanmc->fid;
600
601 addr = RTL8366RB_VLAN_MEMCONF_BASE + (index * 3);
602
603 tableaddr = (u16 *)&vlanmc_priv;
604 data = *tableaddr;
605
606 err = rtl8366_smi_write_reg(smi, addr, data);
607 if (err)
608 return err;
609
610 addr = RTL8366RB_VLAN_MEMCONF_BASE + 1 + (index * 3);
611
612 tableaddr++;
613 data = *tableaddr;
614
615 err = rtl8366_smi_write_reg(smi, addr, data);
616 if (err)
617 return err;
618
619 addr = RTL8366RB_VLAN_MEMCONF_BASE + 2 + (index * 3);
620
621 tableaddr++;
622 data = *tableaddr;
623
624 err = rtl8366_smi_write_reg(smi, addr, data);
625 if (err)
626 return err;
627 return 0;
628 }
629
630 static int rtl8366rb_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
631 {
632 u32 data;
633 int err;
634
635 if (port >= RTL8366RB_NUM_PORTS)
636 return -EINVAL;
637
638 err = rtl8366_smi_read_reg(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
639 &data);
640 if (err)
641 return err;
642
643 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
644 RTL8366RB_PORT_VLAN_CTRL_MASK;
645
646 return 0;
647
648 }
649
650 static int rtl8366rb_set_mc_index(struct rtl8366_smi *smi, int port, int index)
651 {
652 if (port >= RTL8366RB_NUM_PORTS || index >= RTL8366RB_NUM_VLANS)
653 return -EINVAL;
654
655 return rtl8366_smi_rmwr(smi, RTL8366RB_PORT_VLAN_CTRL_REG(port),
656 RTL8366RB_PORT_VLAN_CTRL_MASK <<
657 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
658 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
659 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
660 }
661
662 static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
663 {
664 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
665 (enable) ? RTL8366RB_SGCR_EN_VLAN : 0);
666 }
667
668 static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
669 {
670 return rtl8366_smi_rmwr(smi, RTL8366RB_SGCR,
671 RTL8366RB_SGCR_EN_VLAN_4KTB,
672 (enable) ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
673 }
674
675 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
676 const struct switch_attr *attr,
677 struct switch_val *val)
678 {
679 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
680
681 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
682 RTL8366RB_MIB_CTRL_GLOBAL_RESET);
683 }
684
685 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
686 const struct switch_attr *attr,
687 struct switch_val *val)
688 {
689 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
690 u32 data;
691
692 if (attr->ofs == 1) {
693 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
694
695 if (data & RTL8366RB_SGCR_EN_VLAN)
696 val->value.i = 1;
697 else
698 val->value.i = 0;
699 } else if (attr->ofs == 2) {
700 rtl8366_smi_read_reg(smi, RTL8366RB_SGCR, &data);
701
702 if (data & RTL8366RB_SGCR_EN_VLAN_4KTB)
703 val->value.i = 1;
704 else
705 val->value.i = 0;
706 }
707
708 return 0;
709 }
710
711 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
712 const struct switch_attr *attr,
713 struct switch_val *val)
714 {
715 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
716 u32 data;
717
718 rtl8366_smi_read_reg(smi, RTL8366RB_LED_BLINKRATE_REG, &data);
719
720 val->value.i = (data & (RTL8366RB_LED_BLINKRATE_MASK));
721
722 return 0;
723 }
724
725 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
726 const struct switch_attr *attr,
727 struct switch_val *val)
728 {
729 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
730
731 if (val->value.i >= 6)
732 return -EINVAL;
733
734 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG,
735 RTL8366RB_LED_BLINKRATE_MASK,
736 val->value.i);
737 }
738
739 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
740 const struct switch_attr *attr,
741 struct switch_val *val)
742 {
743 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
744
745 if (attr->ofs == 1)
746 return rtl8366rb_vlan_set_vlan(smi, val->value.i);
747 else
748 return rtl8366rb_vlan_set_4ktable(smi, val->value.i);
749 }
750
751 static const char *rtl8366rb_speed_str(unsigned speed)
752 {
753 switch (speed) {
754 case 0:
755 return "10baseT";
756 case 1:
757 return "100baseT";
758 case 2:
759 return "1000baseT";
760 }
761
762 return "unknown";
763 }
764
765 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
766 const struct switch_attr *attr,
767 struct switch_val *val)
768 {
769 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
770 u32 len = 0, data = 0;
771
772 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
773 return -EINVAL;
774
775 memset(smi->buf, '\0', sizeof(smi->buf));
776 rtl8366_smi_read_reg(smi, RTL8366RB_PORT_LINK_STATUS_BASE +
777 (val->port_vlan / 2), &data);
778
779 if (val->port_vlan % 2)
780 data = data >> 8;
781
782 if (data & RTL8366RB_PORT_STATUS_LINK_MASK) {
783 len = snprintf(smi->buf, sizeof(smi->buf),
784 "port:%d link:up speed:%s %s-duplex %s%s%s",
785 val->port_vlan,
786 rtl8366rb_speed_str(data &
787 RTL8366RB_PORT_STATUS_SPEED_MASK),
788 (data & RTL8366RB_PORT_STATUS_DUPLEX_MASK) ?
789 "full" : "half",
790 (data & RTL8366RB_PORT_STATUS_TXPAUSE_MASK) ?
791 "tx-pause ": "",
792 (data & RTL8366RB_PORT_STATUS_RXPAUSE_MASK) ?
793 "rx-pause " : "",
794 (data & RTL8366RB_PORT_STATUS_AN_MASK) ?
795 "nway ": "");
796 } else {
797 len = snprintf(smi->buf, sizeof(smi->buf), "port:%d link: down",
798 val->port_vlan);
799 }
800
801 val->value.s = smi->buf;
802 val->len = len;
803
804 return 0;
805 }
806
807 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
808 const struct switch_attr *attr,
809 struct switch_val *val)
810 {
811 int i;
812 u32 len = 0;
813 struct rtl8366_vlan_4k vlan4k;
814 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
815 char *buf = smi->buf;
816 int err;
817
818 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
819 return -EINVAL;
820
821 memset(buf, '\0', sizeof(smi->buf));
822
823 err = rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
824 if (err)
825 return err;
826
827 len += snprintf(buf + len, sizeof(smi->buf) - len,
828 "VLAN %d: Ports: '", vlan4k.vid);
829
830 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
831 if (!(vlan4k.member & (1 << i)))
832 continue;
833
834 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d%s", i,
835 (vlan4k.untag & (1 << i)) ? "" : "t");
836 }
837
838 len += snprintf(buf + len, sizeof(smi->buf) - len,
839 "', members=%04x, untag=%04x, fid=%u",
840 vlan4k.member, vlan4k.untag, vlan4k.fid);
841
842 val->value.s = buf;
843 val->len = len;
844
845 return 0;
846 }
847
848 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
849 const struct switch_attr *attr,
850 struct switch_val *val)
851 {
852 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
853 u32 data;
854 u32 mask;
855 u32 reg;
856
857 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
858 return -EINVAL;
859
860 if (val->port_vlan == RTL8366RB_PORT_NUM_CPU) {
861 reg = RTL8366RB_LED_BLINKRATE_REG;
862 mask = 0xF << 4;
863 data = val->value.i << 4;
864 } else {
865 reg = RTL8366RB_LED_CTRL_REG;
866 mask = 0xF << (val->port_vlan * 4),
867 data = val->value.i << (val->port_vlan * 4);
868 }
869
870 return rtl8366_smi_rmwr(smi, RTL8366RB_LED_BLINKRATE_REG, mask, data);
871 }
872
873 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
874 const struct switch_attr *attr,
875 struct switch_val *val)
876 {
877 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
878 u32 data = 0;
879
880 if (val->port_vlan >= RTL8366RB_NUM_LEDGROUPS)
881 return -EINVAL;
882
883 rtl8366_smi_read_reg(smi, RTL8366RB_LED_CTRL_REG, &data);
884 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
885
886 return 0;
887 }
888
889 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
890 const struct switch_attr *attr,
891 struct switch_val *val)
892 {
893 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
894
895 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
896 return -EINVAL;
897
898 return rtl8366_smi_rmwr(smi, RTL8366RB_MIB_CTRL_REG, 0,
899 RTL8366RB_MIB_CTRL_PORT_RESET(val->port_vlan));
900 }
901
902 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
903 const struct switch_attr *attr,
904 struct switch_val *val)
905 {
906 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
907 int i, len = 0;
908 unsigned long long counter = 0;
909 char *buf = smi->buf;
910
911 if (val->port_vlan >= RTL8366RB_NUM_PORTS)
912 return -EINVAL;
913
914 len += snprintf(buf + len, sizeof(smi->buf) - len,
915 "Port %d MIB counters\n",
916 val->port_vlan);
917
918 for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
919 len += snprintf(buf + len, sizeof(smi->buf) - len,
920 "%-36s: ", rtl8366rb_mib_counters[i].name);
921 if (!rtl8366rb_get_mib_counter(smi, i, val->port_vlan, &counter))
922 len += snprintf(buf + len, sizeof(smi->buf) - len,
923 "%llu\n", counter);
924 else
925 len += snprintf(buf + len, sizeof(smi->buf) - len,
926 "%s\n", "error");
927 }
928
929 val->value.s = buf;
930 val->len = len;
931 return 0;
932 }
933
934 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
935 struct switch_val *val)
936 {
937 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
938 struct switch_port *port;
939 struct rtl8366_vlan_4k vlan4k;
940 int i;
941
942 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
943 return -EINVAL;
944
945 rtl8366rb_get_vlan_4k(smi, val->port_vlan, &vlan4k);
946
947 port = &val->value.ports[0];
948 val->len = 0;
949 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
950 if (!(vlan4k.member & BIT(i)))
951 continue;
952
953 port->id = i;
954 port->flags = (vlan4k.untag & BIT(i)) ?
955 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
956 val->len++;
957 port++;
958 }
959 return 0;
960 }
961
962 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
963 struct switch_val *val)
964 {
965 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
966 struct switch_port *port;
967 u32 member = 0;
968 u32 untag = 0;
969 int i;
970
971 if (val->port_vlan == 0 || val->port_vlan >= RTL8366RB_NUM_VLANS)
972 return -EINVAL;
973
974 port = &val->value.ports[0];
975 for (i = 0; i < val->len; i++, port++) {
976 member |= BIT(port->id);
977
978 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
979 untag |= BIT(port->id);
980 }
981
982 return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
983 }
984
985 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
986 {
987 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
988 return rtl8366_get_pvid(smi, port, val);
989 }
990
991 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
992 {
993 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
994 return rtl8366_set_pvid(smi, port, val);
995 }
996
997 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
998 {
999 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1000 int err;
1001
1002 err = rtl8366rb_reset_chip(smi);
1003 if (err)
1004 return err;
1005
1006 err = rtl8366rb_hw_init(smi);
1007 if (err)
1008 return err;
1009
1010 return rtl8366_reset_vlan(smi);
1011 }
1012
1013 static struct switch_attr rtl8366rb_globals[] = {
1014 {
1015 .type = SWITCH_TYPE_INT,
1016 .name = "enable_vlan",
1017 .description = "Enable VLAN mode",
1018 .set = rtl8366rb_sw_set_vlan_enable,
1019 .get = rtl8366rb_sw_get_vlan_enable,
1020 .max = 1,
1021 .ofs = 1
1022 }, {
1023 .type = SWITCH_TYPE_INT,
1024 .name = "enable_vlan4k",
1025 .description = "Enable VLAN 4K mode",
1026 .set = rtl8366rb_sw_set_vlan_enable,
1027 .get = rtl8366rb_sw_get_vlan_enable,
1028 .max = 1,
1029 .ofs = 2
1030 }, {
1031 .type = SWITCH_TYPE_NOVAL,
1032 .name = "reset_mibs",
1033 .description = "Reset all MIB counters",
1034 .set = rtl8366rb_sw_reset_mibs,
1035 }, {
1036 .type = SWITCH_TYPE_INT,
1037 .name = "blinkrate",
1038 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1039 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1040 .set = rtl8366rb_sw_set_blinkrate,
1041 .get = rtl8366rb_sw_get_blinkrate,
1042 .max = 5
1043 },
1044 };
1045
1046 static struct switch_attr rtl8366rb_port[] = {
1047 {
1048 .type = SWITCH_TYPE_STRING,
1049 .name = "link",
1050 .description = "Get port link information",
1051 .max = 1,
1052 .set = NULL,
1053 .get = rtl8366rb_sw_get_port_link,
1054 }, {
1055 .type = SWITCH_TYPE_NOVAL,
1056 .name = "reset_mib",
1057 .description = "Reset single port MIB counters",
1058 .set = rtl8366rb_sw_reset_port_mibs,
1059 }, {
1060 .type = SWITCH_TYPE_STRING,
1061 .name = "mib",
1062 .description = "Get MIB counters for port",
1063 .max = 33,
1064 .set = NULL,
1065 .get = rtl8366rb_sw_get_port_mib,
1066 }, {
1067 .type = SWITCH_TYPE_INT,
1068 .name = "led",
1069 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1070 .max = 15,
1071 .set = rtl8366rb_sw_set_port_led,
1072 .get = rtl8366rb_sw_get_port_led,
1073 },
1074 };
1075
1076 static struct switch_attr rtl8366rb_vlan[] = {
1077 {
1078 .type = SWITCH_TYPE_STRING,
1079 .name = "info",
1080 .description = "Get vlan information",
1081 .max = 1,
1082 .set = NULL,
1083 .get = rtl8366rb_sw_get_vlan_info,
1084 },
1085 };
1086
1087 /* template */
1088 static struct switch_dev rtl8366_switch_dev = {
1089 .name = "RTL8366S",
1090 .cpu_port = RTL8366RB_PORT_NUM_CPU,
1091 .ports = RTL8366RB_NUM_PORTS,
1092 .vlans = RTL8366RB_NUM_VLANS,
1093 .attr_global = {
1094 .attr = rtl8366rb_globals,
1095 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1096 },
1097 .attr_port = {
1098 .attr = rtl8366rb_port,
1099 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1100 },
1101 .attr_vlan = {
1102 .attr = rtl8366rb_vlan,
1103 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1104 },
1105
1106 .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1107 .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1108 .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1109 .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1110 .reset_switch = rtl8366rb_sw_reset_switch,
1111 };
1112
1113 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1114 {
1115 struct switch_dev *dev = &rtl->dev;
1116 int err;
1117
1118 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1119 dev->priv = rtl;
1120 dev->devname = dev_name(rtl->parent);
1121
1122 err = register_switch(dev, NULL);
1123 if (err)
1124 dev_err(rtl->parent, "switch registration failed\n");
1125
1126 return err;
1127 }
1128
1129 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1130 {
1131 unregister_switch(&rtl->dev);
1132 }
1133
1134 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1135 {
1136 struct rtl8366_smi *smi = bus->priv;
1137 u32 val = 0;
1138 int err;
1139
1140 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1141 if (err)
1142 return 0xffff;
1143
1144 return val;
1145 }
1146
1147 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1148 {
1149 struct rtl8366_smi *smi = bus->priv;
1150 u32 t;
1151 int err;
1152
1153 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1154 /* flush write */
1155 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1156
1157 return err;
1158 }
1159
1160 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1161 {
1162 return (bus->read == rtl8366rb_mii_read &&
1163 bus->write == rtl8366rb_mii_write);
1164 }
1165
1166 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1167 {
1168 struct rtl8366_smi *smi = &rtl->smi;
1169 int ret;
1170
1171 ret = rtl8366rb_reset_chip(smi);
1172 if (ret)
1173 return ret;
1174
1175 ret = rtl8366rb_hw_init(smi);
1176 return ret;
1177 }
1178
1179 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1180 {
1181 u32 chip_id = 0;
1182 u32 chip_ver = 0;
1183 int ret;
1184
1185 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_ID_REG, &chip_id);
1186 if (ret) {
1187 dev_err(smi->parent, "unable to read chip id\n");
1188 return ret;
1189 }
1190
1191 switch (chip_id) {
1192 case RTL8366RB_CHIP_ID_8366:
1193 break;
1194 default:
1195 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1196 return -ENODEV;
1197 }
1198
1199 ret = rtl8366_smi_read_reg(smi, RTL8366RB_CHIP_VERSION_CTRL_REG,
1200 &chip_ver);
1201 if (ret) {
1202 dev_err(smi->parent, "unable to read chip version\n");
1203 return ret;
1204 }
1205
1206 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1207 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
1208
1209 return 0;
1210 }
1211
1212 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1213 .detect = rtl8366rb_detect,
1214 .mii_read = rtl8366rb_mii_read,
1215 .mii_write = rtl8366rb_mii_write,
1216
1217 .get_vlan_mc = rtl8366rb_get_vlan_mc,
1218 .set_vlan_mc = rtl8366rb_set_vlan_mc,
1219 .get_vlan_4k = rtl8366rb_get_vlan_4k,
1220 .set_vlan_4k = rtl8366rb_set_vlan_4k,
1221 .get_mc_index = rtl8366rb_get_mc_index,
1222 .set_mc_index = rtl8366rb_set_mc_index,
1223 .get_mib_counter = rtl8366rb_get_mib_counter,
1224 };
1225
1226 static int __init rtl8366rb_probe(struct platform_device *pdev)
1227 {
1228 static int rtl8366_smi_version_printed;
1229 struct rtl8366rb_platform_data *pdata;
1230 struct rtl8366rb *rtl;
1231 struct rtl8366_smi *smi;
1232 int err;
1233
1234 if (!rtl8366_smi_version_printed++)
1235 printk(KERN_NOTICE RTL8366RB_DRIVER_DESC
1236 " version " RTL8366RB_DRIVER_VER"\n");
1237
1238 pdata = pdev->dev.platform_data;
1239 if (!pdata) {
1240 dev_err(&pdev->dev, "no platform data specified\n");
1241 err = -EINVAL;
1242 goto err_out;
1243 }
1244
1245 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1246 if (!rtl) {
1247 dev_err(&pdev->dev, "no memory for private data\n");
1248 err = -ENOMEM;
1249 goto err_out;
1250 }
1251
1252 rtl->parent = &pdev->dev;
1253
1254 smi = &rtl->smi;
1255 smi->parent = &pdev->dev;
1256 smi->gpio_sda = pdata->gpio_sda;
1257 smi->gpio_sck = pdata->gpio_sck;
1258 smi->ops = &rtl8366rb_smi_ops;
1259 smi->cpu_port = RTL8366RB_PORT_NUM_CPU;
1260 smi->num_ports = RTL8366RB_NUM_PORTS;
1261 smi->num_vlan_mc = RTL8366RB_NUM_VLANS;
1262 smi->mib_counters = rtl8366rb_mib_counters;
1263 smi->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1264
1265 err = rtl8366_smi_init(smi);
1266 if (err)
1267 goto err_free_rtl;
1268
1269 platform_set_drvdata(pdev, rtl);
1270
1271 err = rtl8366rb_setup(rtl);
1272 if (err)
1273 goto err_clear_drvdata;
1274
1275 err = rtl8366rb_switch_init(rtl);
1276 if (err)
1277 goto err_clear_drvdata;
1278
1279 return 0;
1280
1281 err_clear_drvdata:
1282 platform_set_drvdata(pdev, NULL);
1283 rtl8366_smi_cleanup(smi);
1284 err_free_rtl:
1285 kfree(rtl);
1286 err_out:
1287 return err;
1288 }
1289
1290 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1291 {
1292 if (!rtl8366rb_mii_bus_match(phydev->bus))
1293 return -EINVAL;
1294
1295 return 0;
1296 }
1297
1298 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1299 {
1300 return 0;
1301 }
1302
1303 static struct phy_driver rtl8366rb_phy_driver = {
1304 .phy_id = 0x001cc960,
1305 .name = "Realtek RTL8366RB",
1306 .phy_id_mask = 0x1ffffff0,
1307 .features = PHY_GBIT_FEATURES,
1308 .config_aneg = rtl8366rb_phy_config_aneg,
1309 .config_init = rtl8366rb_phy_config_init,
1310 .read_status = genphy_read_status,
1311 .driver = {
1312 .owner = THIS_MODULE,
1313 },
1314 };
1315
1316 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1317 {
1318 struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1319
1320 if (rtl) {
1321 rtl8366rb_switch_cleanup(rtl);
1322 platform_set_drvdata(pdev, NULL);
1323 rtl8366_smi_cleanup(&rtl->smi);
1324 kfree(rtl);
1325 }
1326
1327 return 0;
1328 }
1329
1330 static struct platform_driver rtl8366rb_driver = {
1331 .driver = {
1332 .name = RTL8366RB_DRIVER_NAME,
1333 .owner = THIS_MODULE,
1334 },
1335 .probe = rtl8366rb_probe,
1336 .remove = __devexit_p(rtl8366rb_remove),
1337 };
1338
1339 static int __init rtl8366rb_module_init(void)
1340 {
1341 int ret;
1342 ret = platform_driver_register(&rtl8366rb_driver);
1343 if (ret)
1344 return ret;
1345
1346 ret = phy_driver_register(&rtl8366rb_phy_driver);
1347 if (ret)
1348 goto err_platform_unregister;
1349
1350 return 0;
1351
1352 err_platform_unregister:
1353 platform_driver_unregister(&rtl8366rb_driver);
1354 return ret;
1355 }
1356 module_init(rtl8366rb_module_init);
1357
1358 static void __exit rtl8366rb_module_exit(void)
1359 {
1360 phy_driver_unregister(&rtl8366rb_phy_driver);
1361 platform_driver_unregister(&rtl8366rb_driver);
1362 }
1363 module_exit(rtl8366rb_module_exit);
1364
1365 MODULE_DESCRIPTION(RTL8366RB_DRIVER_DESC);
1366 MODULE_VERSION(RTL8366RB_DRIVER_VER);
1367 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1368 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1369 MODULE_LICENSE("GPL v2");
1370 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
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