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generic: b53: rename exported symbols to avoid upstream conflict
[openwrt/staging/hauke.git] / target / linux / generic / files / drivers / net / phy / b53 / b53_common.c
1 /*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21 #include <linux/delay.h>
22 #include <linux/export.h>
23 #include <linux/gpio.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/switch.h>
27 #include <linux/phy.h>
28 #include <linux/of.h>
29 #include <linux/of_net.h>
30 #include <linux/platform_data/b53.h>
31
32 #include "b53_regs.h"
33 #include "b53_priv.h"
34
35 /* buffer size needed for displaying all MIBs with max'd values */
36 #define B53_BUF_SIZE 1188
37
38 struct b53_mib_desc {
39 u8 size;
40 u8 offset;
41 const char *name;
42 };
43
44 /* BCM5365 MIB counters */
45 static const struct b53_mib_desc b53_mibs_65[] = {
46 { 8, 0x00, "TxOctets" },
47 { 4, 0x08, "TxDropPkts" },
48 { 4, 0x10, "TxBroadcastPkts" },
49 { 4, 0x14, "TxMulticastPkts" },
50 { 4, 0x18, "TxUnicastPkts" },
51 { 4, 0x1c, "TxCollisions" },
52 { 4, 0x20, "TxSingleCollision" },
53 { 4, 0x24, "TxMultipleCollision" },
54 { 4, 0x28, "TxDeferredTransmit" },
55 { 4, 0x2c, "TxLateCollision" },
56 { 4, 0x30, "TxExcessiveCollision" },
57 { 4, 0x38, "TxPausePkts" },
58 { 8, 0x44, "RxOctets" },
59 { 4, 0x4c, "RxUndersizePkts" },
60 { 4, 0x50, "RxPausePkts" },
61 { 4, 0x54, "Pkts64Octets" },
62 { 4, 0x58, "Pkts65to127Octets" },
63 { 4, 0x5c, "Pkts128to255Octets" },
64 { 4, 0x60, "Pkts256to511Octets" },
65 { 4, 0x64, "Pkts512to1023Octets" },
66 { 4, 0x68, "Pkts1024to1522Octets" },
67 { 4, 0x6c, "RxOversizePkts" },
68 { 4, 0x70, "RxJabbers" },
69 { 4, 0x74, "RxAlignmentErrors" },
70 { 4, 0x78, "RxFCSErrors" },
71 { 8, 0x7c, "RxGoodOctets" },
72 { 4, 0x84, "RxDropPkts" },
73 { 4, 0x88, "RxUnicastPkts" },
74 { 4, 0x8c, "RxMulticastPkts" },
75 { 4, 0x90, "RxBroadcastPkts" },
76 { 4, 0x94, "RxSAChanges" },
77 { 4, 0x98, "RxFragments" },
78 { },
79 };
80
81 #define B63XX_MIB_TXB_ID 0 /* TxOctets */
82 #define B63XX_MIB_RXB_ID 14 /* RxOctets */
83
84 /* BCM63xx MIB counters */
85 static const struct b53_mib_desc b53_mibs_63xx[] = {
86 { 8, 0x00, "TxOctets" },
87 { 4, 0x08, "TxDropPkts" },
88 { 4, 0x0c, "TxQoSPkts" },
89 { 4, 0x10, "TxBroadcastPkts" },
90 { 4, 0x14, "TxMulticastPkts" },
91 { 4, 0x18, "TxUnicastPkts" },
92 { 4, 0x1c, "TxCollisions" },
93 { 4, 0x20, "TxSingleCollision" },
94 { 4, 0x24, "TxMultipleCollision" },
95 { 4, 0x28, "TxDeferredTransmit" },
96 { 4, 0x2c, "TxLateCollision" },
97 { 4, 0x30, "TxExcessiveCollision" },
98 { 4, 0x38, "TxPausePkts" },
99 { 8, 0x3c, "TxQoSOctets" },
100 { 8, 0x44, "RxOctets" },
101 { 4, 0x4c, "RxUndersizePkts" },
102 { 4, 0x50, "RxPausePkts" },
103 { 4, 0x54, "Pkts64Octets" },
104 { 4, 0x58, "Pkts65to127Octets" },
105 { 4, 0x5c, "Pkts128to255Octets" },
106 { 4, 0x60, "Pkts256to511Octets" },
107 { 4, 0x64, "Pkts512to1023Octets" },
108 { 4, 0x68, "Pkts1024to1522Octets" },
109 { 4, 0x6c, "RxOversizePkts" },
110 { 4, 0x70, "RxJabbers" },
111 { 4, 0x74, "RxAlignmentErrors" },
112 { 4, 0x78, "RxFCSErrors" },
113 { 8, 0x7c, "RxGoodOctets" },
114 { 4, 0x84, "RxDropPkts" },
115 { 4, 0x88, "RxUnicastPkts" },
116 { 4, 0x8c, "RxMulticastPkts" },
117 { 4, 0x90, "RxBroadcastPkts" },
118 { 4, 0x94, "RxSAChanges" },
119 { 4, 0x98, "RxFragments" },
120 { 4, 0xa0, "RxSymbolErrors" },
121 { 4, 0xa4, "RxQoSPkts" },
122 { 8, 0xa8, "RxQoSOctets" },
123 { 4, 0xb0, "Pkts1523to2047Octets" },
124 { 4, 0xb4, "Pkts2048to4095Octets" },
125 { 4, 0xb8, "Pkts4096to8191Octets" },
126 { 4, 0xbc, "Pkts8192to9728Octets" },
127 { 4, 0xc0, "RxDiscarded" },
128 { }
129 };
130
131 #define B53XX_MIB_TXB_ID 0 /* TxOctets */
132 #define B53XX_MIB_RXB_ID 12 /* RxOctets */
133
134 /* MIB counters */
135 static const struct b53_mib_desc b53_mibs[] = {
136 { 8, 0x00, "TxOctets" },
137 { 4, 0x08, "TxDropPkts" },
138 { 4, 0x10, "TxBroadcastPkts" },
139 { 4, 0x14, "TxMulticastPkts" },
140 { 4, 0x18, "TxUnicastPkts" },
141 { 4, 0x1c, "TxCollisions" },
142 { 4, 0x20, "TxSingleCollision" },
143 { 4, 0x24, "TxMultipleCollision" },
144 { 4, 0x28, "TxDeferredTransmit" },
145 { 4, 0x2c, "TxLateCollision" },
146 { 4, 0x30, "TxExcessiveCollision" },
147 { 4, 0x38, "TxPausePkts" },
148 { 8, 0x50, "RxOctets" },
149 { 4, 0x58, "RxUndersizePkts" },
150 { 4, 0x5c, "RxPausePkts" },
151 { 4, 0x60, "Pkts64Octets" },
152 { 4, 0x64, "Pkts65to127Octets" },
153 { 4, 0x68, "Pkts128to255Octets" },
154 { 4, 0x6c, "Pkts256to511Octets" },
155 { 4, 0x70, "Pkts512to1023Octets" },
156 { 4, 0x74, "Pkts1024to1522Octets" },
157 { 4, 0x78, "RxOversizePkts" },
158 { 4, 0x7c, "RxJabbers" },
159 { 4, 0x80, "RxAlignmentErrors" },
160 { 4, 0x84, "RxFCSErrors" },
161 { 8, 0x88, "RxGoodOctets" },
162 { 4, 0x90, "RxDropPkts" },
163 { 4, 0x94, "RxUnicastPkts" },
164 { 4, 0x98, "RxMulticastPkts" },
165 { 4, 0x9c, "RxBroadcastPkts" },
166 { 4, 0xa0, "RxSAChanges" },
167 { 4, 0xa4, "RxFragments" },
168 { 4, 0xa8, "RxJumboPkts" },
169 { 4, 0xac, "RxSymbolErrors" },
170 { 4, 0xc0, "RxDiscarded" },
171 { }
172 };
173
174 static int b53_do_vlan_op(struct b53_device *dev, u8 op)
175 {
176 unsigned int i;
177
178 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
179
180 for (i = 0; i < 10; i++) {
181 u8 vta;
182
183 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
184 if (!(vta & VTA_START_CMD))
185 return 0;
186
187 usleep_range(100, 200);
188 }
189
190 return -EIO;
191 }
192
193 static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, u16 members,
194 u16 untag)
195 {
196 if (is5325(dev)) {
197 u32 entry = 0;
198
199 if (members) {
200 entry = ((untag & VA_UNTAG_MASK_25) << VA_UNTAG_S_25) |
201 members;
202 if (dev->core_rev >= 3)
203 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
204 else
205 entry |= VA_VALID_25;
206 }
207
208 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
209 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
210 VTA_RW_STATE_WR | VTA_RW_OP_EN);
211 } else if (is5365(dev)) {
212 u16 entry = 0;
213
214 if (members)
215 entry = ((untag & VA_UNTAG_MASK_65) << VA_UNTAG_S_65) |
216 members | VA_VALID_65;
217
218 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
219 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
220 VTA_RW_STATE_WR | VTA_RW_OP_EN);
221 } else {
222 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
223 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
224 (untag << VTE_UNTAG_S) | members);
225
226 b53_do_vlan_op(dev, VTA_CMD_WRITE);
227 }
228 }
229
230 void b53_set_forwarding(struct b53_device *dev, int enable)
231 {
232 u8 mgmt;
233
234 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
235
236 if (enable)
237 mgmt |= SM_SW_FWD_EN;
238 else
239 mgmt &= ~SM_SW_FWD_EN;
240
241 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
242 }
243
244 static void b53_enable_vlan(struct b53_device *dev, int enable)
245 {
246 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
247
248 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
249 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
250 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
251
252 if (is5325(dev) || is5365(dev)) {
253 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
254 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
255 } else if (is63xx(dev)) {
256 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
257 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
258 } else {
259 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
260 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
261 }
262
263 mgmt &= ~SM_SW_FWD_MODE;
264
265 if (enable) {
266 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
267 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
268 vc4 &= ~VC4_ING_VID_CHECK_MASK;
269 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
270 vc5 |= VC5_DROP_VTABLE_MISS;
271
272 if (is5325(dev))
273 vc0 &= ~VC0_RESERVED_1;
274
275 if (is5325(dev) || is5365(dev))
276 vc1 |= VC1_RX_MCST_TAG_EN;
277
278 if (!is5325(dev) && !is5365(dev)) {
279 if (dev->allow_vid_4095)
280 vc5 |= VC5_VID_FFF_EN;
281 else
282 vc5 &= ~VC5_VID_FFF_EN;
283 }
284 } else {
285 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
286 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
287 vc4 &= ~VC4_ING_VID_CHECK_MASK;
288 vc5 &= ~VC5_DROP_VTABLE_MISS;
289
290 if (is5325(dev) || is5365(dev))
291 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
292 else
293 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
294
295 if (is5325(dev) || is5365(dev))
296 vc1 &= ~VC1_RX_MCST_TAG_EN;
297
298 if (!is5325(dev) && !is5365(dev))
299 vc5 &= ~VC5_VID_FFF_EN;
300 }
301
302 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
303 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
304
305 if (is5325(dev) || is5365(dev)) {
306 /* enable the high 8 bit vid check on 5325 */
307 if (is5325(dev) && enable)
308 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
309 VC3_HIGH_8BIT_EN);
310 else
311 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
312
313 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
314 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
315 } else if (is63xx(dev)) {
316 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
317 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
318 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
319 } else {
320 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
321 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
322 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
323 }
324
325 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
326 }
327
328 static int b53_set_jumbo(struct b53_device *dev, int enable, int allow_10_100)
329 {
330 u32 port_mask = 0;
331 u16 max_size = JMS_MIN_SIZE;
332
333 if (is5325(dev) || is5365(dev))
334 return -EINVAL;
335
336 if (enable) {
337 port_mask = dev->enabled_ports;
338 max_size = JMS_MAX_SIZE;
339 if (allow_10_100)
340 port_mask |= JPM_10_100_JUMBO_EN;
341 }
342
343 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
344 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
345 }
346
347 static int b53_flush_arl(struct b53_device *dev)
348 {
349 unsigned int i;
350
351 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
352 FAST_AGE_DONE | FAST_AGE_DYNAMIC | FAST_AGE_STATIC);
353
354 for (i = 0; i < 10; i++) {
355 u8 fast_age_ctrl;
356
357 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
358 &fast_age_ctrl);
359
360 if (!(fast_age_ctrl & FAST_AGE_DONE))
361 return 0;
362
363 mdelay(1);
364 }
365
366 pr_warn("time out while flushing ARL\n");
367
368 return -EINVAL;
369 }
370
371 static void b53_enable_ports(struct b53_device *dev)
372 {
373 unsigned i;
374
375 b53_for_each_port(dev, i) {
376 u8 port_ctrl;
377 u16 pvlan_mask;
378
379 /*
380 * prevent leaking packets between wan and lan in unmanaged
381 * mode through port vlans.
382 */
383 if (dev->enable_vlan || is_cpu_port(dev, i))
384 pvlan_mask = 0x1ff;
385 else if (is531x5(dev) || is5301x(dev))
386 /* BCM53115 may use a different port as cpu port */
387 pvlan_mask = BIT(dev->sw_dev.cpu_port);
388 else
389 pvlan_mask = BIT(B53_CPU_PORT);
390
391 /* BCM5325 CPU port is at 8 */
392 if ((is5325(dev) || is5365(dev)) && i == B53_CPU_PORT_25)
393 i = B53_CPU_PORT;
394
395 if (dev->chip_id == BCM5398_DEVICE_ID && (i == 6 || i == 7))
396 /* disable unused ports 6 & 7 */
397 port_ctrl = PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
398 else if (i == B53_CPU_PORT)
399 port_ctrl = PORT_CTRL_RX_BCST_EN |
400 PORT_CTRL_RX_MCST_EN |
401 PORT_CTRL_RX_UCST_EN;
402 else
403 port_ctrl = 0;
404
405 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i),
406 pvlan_mask);
407
408 /* port state is handled by bcm63xx_enet driver */
409 if (!is63xx(dev) && !(is5301x(dev) && i == 6))
410 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(i),
411 port_ctrl);
412 }
413 }
414
415 static void b53_enable_mib(struct b53_device *dev)
416 {
417 u8 gc;
418
419 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
420
421 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
422
423 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
424 }
425
426 static int b53_apply(struct b53_device *dev)
427 {
428 int i;
429
430 /* clear all vlan entries */
431 if (is5325(dev) || is5365(dev)) {
432 for (i = 1; i < dev->sw_dev.vlans; i++)
433 b53_set_vlan_entry(dev, i, 0, 0);
434 } else {
435 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
436 }
437
438 b53_enable_vlan(dev, dev->enable_vlan);
439
440 /* fill VLAN table */
441 if (dev->enable_vlan) {
442 for (i = 0; i < dev->sw_dev.vlans; i++) {
443 struct b53_vlan *vlan = &dev->vlans[i];
444
445 if (!vlan->members)
446 continue;
447
448 b53_set_vlan_entry(dev, i, vlan->members, vlan->untag);
449 }
450
451 b53_for_each_port(dev, i)
452 b53_write16(dev, B53_VLAN_PAGE,
453 B53_VLAN_PORT_DEF_TAG(i),
454 dev->ports[i].pvid);
455 } else {
456 b53_for_each_port(dev, i)
457 b53_write16(dev, B53_VLAN_PAGE,
458 B53_VLAN_PORT_DEF_TAG(i), 1);
459
460 }
461
462 b53_enable_ports(dev);
463
464 if (!is5325(dev) && !is5365(dev))
465 b53_set_jumbo(dev, dev->enable_jumbo, 1);
466
467 return 0;
468 }
469
470 static void b53_switch_reset_gpio(struct b53_device *dev)
471 {
472 int gpio = dev->reset_gpio;
473
474 if (gpio < 0)
475 return;
476
477 /*
478 * Reset sequence: RESET low(50ms)->high(20ms)
479 */
480 gpio_set_value(gpio, 0);
481 mdelay(50);
482
483 gpio_set_value(gpio, 1);
484 mdelay(20);
485
486 dev->current_page = 0xff;
487 }
488
489 static int b53_configure_ports_of(struct b53_device *dev)
490 {
491 struct device_node *dn, *pn;
492 u32 port_num;
493
494 dn = of_get_child_by_name(dev_of_node(dev->dev), "ports");
495
496 for_each_available_child_of_node(dn, pn) {
497 struct device_node *fixed_link;
498
499 if (of_property_read_u32(pn, "reg", &port_num))
500 continue;
501
502 if (port_num > B53_CPU_PORT)
503 continue;
504
505 fixed_link = of_get_child_by_name(pn, "fixed-link");
506 if (fixed_link) {
507 u32 spd;
508 u8 po = GMII_PO_LINK;
509 phy_interface_t mode;
510
511 of_get_phy_mode(pn, &mode);
512
513 if (!of_property_read_u32(fixed_link, "speed", &spd)) {
514 switch (spd) {
515 case 10:
516 po |= GMII_PO_SPEED_10M;
517 break;
518 case 100:
519 po |= GMII_PO_SPEED_100M;
520 break;
521 case 2000:
522 if (is_imp_port(dev, port_num))
523 po |= PORT_OVERRIDE_SPEED_2000M;
524 else
525 po |= GMII_PO_SPEED_2000M;
526 fallthrough;
527 case 1000:
528 po |= GMII_PO_SPEED_1000M;
529 break;
530 }
531 }
532
533 if (of_property_read_bool(fixed_link, "full-duplex"))
534 po |= PORT_OVERRIDE_FULL_DUPLEX;
535 if (of_property_read_bool(fixed_link, "pause"))
536 po |= GMII_PO_RX_FLOW;
537 if (of_property_read_bool(fixed_link, "asym-pause"))
538 po |= GMII_PO_TX_FLOW;
539
540 if (is_imp_port(dev, port_num)) {
541 po |= PORT_OVERRIDE_EN;
542
543 if (is5325(dev) &&
544 mode == PHY_INTERFACE_MODE_REVMII)
545 po |= PORT_OVERRIDE_RV_MII_25;
546
547 b53_write8(dev, B53_CTRL_PAGE,
548 B53_PORT_OVERRIDE_CTRL, po);
549
550 if (is5325(dev) &&
551 mode == PHY_INTERFACE_MODE_REVMII) {
552 b53_read8(dev, B53_CTRL_PAGE,
553 B53_PORT_OVERRIDE_CTRL, &po);
554 if (!(po & PORT_OVERRIDE_RV_MII_25))
555 pr_err("Failed to enable reverse MII mode\n");
556 return -EINVAL;
557 }
558 } else {
559 po |= GMII_PO_EN;
560 b53_write8(dev, B53_CTRL_PAGE,
561 B53_GMII_PORT_OVERRIDE_CTRL(port_num),
562 po);
563 }
564 }
565 }
566
567 return 0;
568 }
569
570 static int b53_configure_ports(struct b53_device *dev)
571 {
572 u8 cpu_port = dev->sw_dev.cpu_port;
573
574 /* configure MII port if necessary */
575 if (is5325(dev)) {
576 u8 mii_port_override;
577
578 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
579 &mii_port_override);
580 /* reverse mii needs to be enabled */
581 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
582 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
583 mii_port_override | PORT_OVERRIDE_RV_MII_25);
584 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
585 &mii_port_override);
586
587 if (!(mii_port_override & PORT_OVERRIDE_RV_MII_25)) {
588 pr_err("Failed to enable reverse MII mode\n");
589 return -EINVAL;
590 }
591 }
592 } else if (is531x5(dev) && cpu_port == B53_CPU_PORT) {
593 u8 mii_port_override;
594
595 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
596 &mii_port_override);
597 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
598 mii_port_override | PORT_OVERRIDE_EN |
599 PORT_OVERRIDE_LINK);
600
601 /* BCM47189 has another interface connected to the port 5 */
602 if (dev->enabled_ports & BIT(5)) {
603 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(5);
604 u8 gmii_po;
605
606 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
607 gmii_po |= GMII_PO_LINK |
608 GMII_PO_RX_FLOW |
609 GMII_PO_TX_FLOW |
610 GMII_PO_EN;
611 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
612 }
613 } else if (is5301x(dev)) {
614 if (cpu_port == 8) {
615 u8 mii_port_override;
616
617 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
618 &mii_port_override);
619 mii_port_override |= PORT_OVERRIDE_LINK |
620 PORT_OVERRIDE_RX_FLOW |
621 PORT_OVERRIDE_TX_FLOW |
622 PORT_OVERRIDE_SPEED_2000M |
623 PORT_OVERRIDE_EN;
624 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
625 mii_port_override);
626
627 /* TODO: Ports 5 & 7 require some extra handling */
628 } else {
629 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(cpu_port);
630 u8 gmii_po;
631
632 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
633 gmii_po |= GMII_PO_LINK |
634 GMII_PO_RX_FLOW |
635 GMII_PO_TX_FLOW |
636 GMII_PO_EN |
637 GMII_PO_SPEED_2000M;
638 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
639 }
640 }
641
642 return 0;
643 }
644
645 static int b53_switch_reset(struct b53_device *dev)
646 {
647 int ret = 0;
648 u8 mgmt;
649
650 b53_switch_reset_gpio(dev);
651
652 if (is539x(dev)) {
653 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
654 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
655 }
656
657 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
658
659 if (!(mgmt & SM_SW_FWD_EN)) {
660 mgmt &= ~SM_SW_FWD_MODE;
661 mgmt |= SM_SW_FWD_EN;
662
663 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
664 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
665
666 if (!(mgmt & SM_SW_FWD_EN)) {
667 pr_err("Failed to enable switch!\n");
668 return -EINVAL;
669 }
670 }
671
672 /* enable all ports */
673 b53_enable_ports(dev);
674
675 if (dev->dev->of_node)
676 ret = b53_configure_ports_of(dev);
677 else
678 ret = b53_configure_ports(dev);
679
680 if (ret)
681 return ret;
682
683 b53_enable_mib(dev);
684
685 return b53_flush_arl(dev);
686 }
687
688 /*
689 * Swconfig glue functions
690 */
691
692 static int b53_global_get_vlan_enable(struct switch_dev *dev,
693 const struct switch_attr *attr,
694 struct switch_val *val)
695 {
696 struct b53_device *priv = sw_to_b53(dev);
697
698 val->value.i = priv->enable_vlan;
699
700 return 0;
701 }
702
703 static int b53_global_set_vlan_enable(struct switch_dev *dev,
704 const struct switch_attr *attr,
705 struct switch_val *val)
706 {
707 struct b53_device *priv = sw_to_b53(dev);
708
709 priv->enable_vlan = val->value.i;
710
711 return 0;
712 }
713
714 static int b53_global_get_jumbo_enable(struct switch_dev *dev,
715 const struct switch_attr *attr,
716 struct switch_val *val)
717 {
718 struct b53_device *priv = sw_to_b53(dev);
719
720 val->value.i = priv->enable_jumbo;
721
722 return 0;
723 }
724
725 static int b53_global_set_jumbo_enable(struct switch_dev *dev,
726 const struct switch_attr *attr,
727 struct switch_val *val)
728 {
729 struct b53_device *priv = sw_to_b53(dev);
730
731 priv->enable_jumbo = val->value.i;
732
733 return 0;
734 }
735
736 static int b53_global_get_4095_enable(struct switch_dev *dev,
737 const struct switch_attr *attr,
738 struct switch_val *val)
739 {
740 struct b53_device *priv = sw_to_b53(dev);
741
742 val->value.i = priv->allow_vid_4095;
743
744 return 0;
745 }
746
747 static int b53_global_set_4095_enable(struct switch_dev *dev,
748 const struct switch_attr *attr,
749 struct switch_val *val)
750 {
751 struct b53_device *priv = sw_to_b53(dev);
752
753 priv->allow_vid_4095 = val->value.i;
754
755 return 0;
756 }
757
758 static int b53_global_get_ports(struct switch_dev *dev,
759 const struct switch_attr *attr,
760 struct switch_val *val)
761 {
762 struct b53_device *priv = sw_to_b53(dev);
763
764 val->len = snprintf(priv->buf, B53_BUF_SIZE, "0x%04x",
765 priv->enabled_ports);
766 val->value.s = priv->buf;
767
768 return 0;
769 }
770
771 static int b53_port_get_pvid(struct switch_dev *dev, int port, int *val)
772 {
773 struct b53_device *priv = sw_to_b53(dev);
774
775 *val = priv->ports[port].pvid;
776
777 return 0;
778 }
779
780 static int b53_port_set_pvid(struct switch_dev *dev, int port, int val)
781 {
782 struct b53_device *priv = sw_to_b53(dev);
783
784 if (val > 15 && is5325(priv))
785 return -EINVAL;
786 if (val == 4095 && !priv->allow_vid_4095)
787 return -EINVAL;
788
789 priv->ports[port].pvid = val;
790
791 return 0;
792 }
793
794 static int b53_vlan_get_ports(struct switch_dev *dev, struct switch_val *val)
795 {
796 struct b53_device *priv = sw_to_b53(dev);
797 struct switch_port *port = &val->value.ports[0];
798 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
799 int i;
800
801 val->len = 0;
802
803 if (!vlan->members)
804 return 0;
805
806 for (i = 0; i < dev->ports; i++) {
807 if (!(vlan->members & BIT(i)))
808 continue;
809
810
811 if (!(vlan->untag & BIT(i)))
812 port->flags = BIT(SWITCH_PORT_FLAG_TAGGED);
813 else
814 port->flags = 0;
815
816 port->id = i;
817 val->len++;
818 port++;
819 }
820
821 return 0;
822 }
823
824 static int b53_vlan_set_ports(struct switch_dev *dev, struct switch_val *val)
825 {
826 struct b53_device *priv = sw_to_b53(dev);
827 struct switch_port *port;
828 struct b53_vlan *vlan = &priv->vlans[val->port_vlan];
829 int i;
830
831 /* only BCM5325 and BCM5365 supports VID 0 */
832 if (val->port_vlan == 0 && !is5325(priv) && !is5365(priv))
833 return -EINVAL;
834
835 /* VLAN 4095 needs special handling */
836 if (val->port_vlan == 4095 && !priv->allow_vid_4095)
837 return -EINVAL;
838
839 port = &val->value.ports[0];
840 vlan->members = 0;
841 vlan->untag = 0;
842 for (i = 0; i < val->len; i++, port++) {
843 vlan->members |= BIT(port->id);
844
845 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED))) {
846 vlan->untag |= BIT(port->id);
847 priv->ports[port->id].pvid = val->port_vlan;
848 };
849 }
850
851 /* ignore disabled ports */
852 vlan->members &= priv->enabled_ports;
853 vlan->untag &= priv->enabled_ports;
854
855 return 0;
856 }
857
858 static int b53_port_get_link(struct switch_dev *dev, int port,
859 struct switch_port_link *link)
860 {
861 struct b53_device *priv = sw_to_b53(dev);
862
863 if (is_cpu_port(priv, port)) {
864 link->link = 1;
865 link->duplex = 1;
866 link->speed = is5325(priv) || is5365(priv) ?
867 SWITCH_PORT_SPEED_100 : SWITCH_PORT_SPEED_1000;
868 link->aneg = 0;
869 } else if (priv->enabled_ports & BIT(port)) {
870 u32 speed;
871 u16 lnk, duplex;
872
873 b53_read16(priv, B53_STAT_PAGE, B53_LINK_STAT, &lnk);
874 b53_read16(priv, B53_STAT_PAGE, priv->duplex_reg, &duplex);
875
876 lnk = (lnk >> port) & 1;
877 duplex = (duplex >> port) & 1;
878
879 if (is5325(priv) || is5365(priv)) {
880 u16 tmp;
881
882 b53_read16(priv, B53_STAT_PAGE, B53_SPEED_STAT, &tmp);
883 speed = SPEED_PORT_FE(tmp, port);
884 } else {
885 b53_read32(priv, B53_STAT_PAGE, B53_SPEED_STAT, &speed);
886 speed = SPEED_PORT_GE(speed, port);
887 }
888
889 link->link = lnk;
890 if (lnk) {
891 link->duplex = duplex;
892 switch (speed) {
893 case SPEED_STAT_10M:
894 link->speed = SWITCH_PORT_SPEED_10;
895 break;
896 case SPEED_STAT_100M:
897 link->speed = SWITCH_PORT_SPEED_100;
898 break;
899 case SPEED_STAT_1000M:
900 link->speed = SWITCH_PORT_SPEED_1000;
901 break;
902 }
903 }
904
905 link->aneg = 1;
906 } else {
907 link->link = 0;
908 }
909
910 return 0;
911
912 }
913
914 static int b53_port_set_link(struct switch_dev *sw_dev, int port,
915 struct switch_port_link *link)
916 {
917 struct b53_device *dev = sw_to_b53(sw_dev);
918
919 /*
920 * TODO: BCM63XX requires special handling as it can have external phys
921 * and ports might be GE or only FE
922 */
923 if (is63xx(dev))
924 return -ENOTSUPP;
925
926 if (port == sw_dev->cpu_port)
927 return -EINVAL;
928
929 if (!(BIT(port) & dev->enabled_ports))
930 return -EINVAL;
931
932 if (link->speed == SWITCH_PORT_SPEED_1000 &&
933 (is5325(dev) || is5365(dev)))
934 return -EINVAL;
935
936 if (link->speed == SWITCH_PORT_SPEED_1000 && !link->duplex)
937 return -EINVAL;
938
939 return switch_generic_set_link(sw_dev, port, link);
940 }
941
942 static int b53_phy_read16(struct switch_dev *dev, int addr, u8 reg, u16 *value)
943 {
944 struct b53_device *priv = sw_to_b53(dev);
945
946 if (priv->ops->phy_read16)
947 return priv->ops->phy_read16(priv, addr, reg, value);
948
949 return b53_read16(priv, B53_PORT_MII_PAGE(addr), reg, value);
950 }
951
952 static int b53_phy_write16(struct switch_dev *dev, int addr, u8 reg, u16 value)
953 {
954 struct b53_device *priv = sw_to_b53(dev);
955
956 if (priv->ops->phy_write16)
957 return priv->ops->phy_write16(priv, addr, reg, value);
958
959 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg, value);
960 }
961
962 static int b53_global_reset_switch(struct switch_dev *dev)
963 {
964 struct b53_device *priv = sw_to_b53(dev);
965
966 /* reset vlans */
967 priv->enable_vlan = 0;
968 priv->enable_jumbo = 0;
969 priv->allow_vid_4095 = 0;
970
971 memset(priv->vlans, 0, sizeof(*priv->vlans) * dev->vlans);
972 memset(priv->ports, 0, sizeof(*priv->ports) * dev->ports);
973
974 return b53_switch_reset(priv);
975 }
976
977 static int b53_global_apply_config(struct switch_dev *dev)
978 {
979 struct b53_device *priv = sw_to_b53(dev);
980
981 /* disable switching */
982 b53_set_forwarding(priv, 0);
983
984 b53_apply(priv);
985
986 /* enable switching */
987 b53_set_forwarding(priv, 1);
988
989 return 0;
990 }
991
992
993 static int b53_global_reset_mib(struct switch_dev *dev,
994 const struct switch_attr *attr,
995 struct switch_val *val)
996 {
997 struct b53_device *priv = sw_to_b53(dev);
998 u8 gc;
999
1000 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
1001
1002 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
1003 mdelay(1);
1004 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
1005 mdelay(1);
1006
1007 return 0;
1008 }
1009
1010 static int b53_port_get_mib(struct switch_dev *sw_dev,
1011 const struct switch_attr *attr,
1012 struct switch_val *val)
1013 {
1014 struct b53_device *dev = sw_to_b53(sw_dev);
1015 const struct b53_mib_desc *mibs;
1016 int port = val->port_vlan;
1017 int len = 0;
1018
1019 if (!(BIT(port) & dev->enabled_ports))
1020 return -1;
1021
1022 if (is5365(dev)) {
1023 if (port == 5)
1024 port = 8;
1025
1026 mibs = b53_mibs_65;
1027 } else if (is63xx(dev)) {
1028 mibs = b53_mibs_63xx;
1029 } else {
1030 mibs = b53_mibs;
1031 }
1032
1033 dev->buf[0] = 0;
1034
1035 for (; mibs->size > 0; mibs++) {
1036 u64 val;
1037
1038 if (mibs->size == 8) {
1039 b53_read64(dev, B53_MIB_PAGE(port), mibs->offset, &val);
1040 } else {
1041 u32 val32;
1042
1043 b53_read32(dev, B53_MIB_PAGE(port), mibs->offset,
1044 &val32);
1045 val = val32;
1046 }
1047
1048 len += snprintf(dev->buf + len, B53_BUF_SIZE - len,
1049 "%-20s: %llu\n", mibs->name, val);
1050 }
1051
1052 val->len = len;
1053 val->value.s = dev->buf;
1054
1055 return 0;
1056 }
1057
1058 static int b53_port_get_stats(struct switch_dev *sw_dev, int port,
1059 struct switch_port_stats *stats)
1060 {
1061 struct b53_device *dev = sw_to_b53(sw_dev);
1062 const struct b53_mib_desc *mibs;
1063 int txb_id, rxb_id;
1064 u64 rxb, txb;
1065
1066 if (!(BIT(port) & dev->enabled_ports))
1067 return -EINVAL;
1068
1069 txb_id = B53XX_MIB_TXB_ID;
1070 rxb_id = B53XX_MIB_RXB_ID;
1071
1072 if (is5365(dev)) {
1073 if (port == 5)
1074 port = 8;
1075
1076 mibs = b53_mibs_65;
1077 } else if (is63xx(dev)) {
1078 mibs = b53_mibs_63xx;
1079 txb_id = B63XX_MIB_TXB_ID;
1080 rxb_id = B63XX_MIB_RXB_ID;
1081 } else {
1082 mibs = b53_mibs;
1083 }
1084
1085 dev->buf[0] = 0;
1086
1087 if (mibs->size == 8) {
1088 b53_read64(dev, B53_MIB_PAGE(port), mibs[txb_id].offset, &txb);
1089 b53_read64(dev, B53_MIB_PAGE(port), mibs[rxb_id].offset, &rxb);
1090 } else {
1091 u32 val32;
1092
1093 b53_read32(dev, B53_MIB_PAGE(port), mibs[txb_id].offset, &val32);
1094 txb = val32;
1095
1096 b53_read32(dev, B53_MIB_PAGE(port), mibs[rxb_id].offset, &val32);
1097 rxb = val32;
1098 }
1099
1100 stats->tx_bytes = txb;
1101 stats->rx_bytes = rxb;
1102
1103 return 0;
1104 }
1105
1106 static struct switch_attr b53_global_ops_25[] = {
1107 {
1108 .type = SWITCH_TYPE_INT,
1109 .name = "enable_vlan",
1110 .description = "Enable VLAN mode",
1111 .set = b53_global_set_vlan_enable,
1112 .get = b53_global_get_vlan_enable,
1113 .max = 1,
1114 },
1115 {
1116 .type = SWITCH_TYPE_STRING,
1117 .name = "ports",
1118 .description = "Available ports (as bitmask)",
1119 .get = b53_global_get_ports,
1120 },
1121 };
1122
1123 static struct switch_attr b53_global_ops_65[] = {
1124 {
1125 .type = SWITCH_TYPE_INT,
1126 .name = "enable_vlan",
1127 .description = "Enable VLAN mode",
1128 .set = b53_global_set_vlan_enable,
1129 .get = b53_global_get_vlan_enable,
1130 .max = 1,
1131 },
1132 {
1133 .type = SWITCH_TYPE_STRING,
1134 .name = "ports",
1135 .description = "Available ports (as bitmask)",
1136 .get = b53_global_get_ports,
1137 },
1138 {
1139 .type = SWITCH_TYPE_INT,
1140 .name = "reset_mib",
1141 .description = "Reset MIB counters",
1142 .set = b53_global_reset_mib,
1143 },
1144 };
1145
1146 static struct switch_attr b53_global_ops[] = {
1147 {
1148 .type = SWITCH_TYPE_INT,
1149 .name = "enable_vlan",
1150 .description = "Enable VLAN mode",
1151 .set = b53_global_set_vlan_enable,
1152 .get = b53_global_get_vlan_enable,
1153 .max = 1,
1154 },
1155 {
1156 .type = SWITCH_TYPE_STRING,
1157 .name = "ports",
1158 .description = "Available Ports (as bitmask)",
1159 .get = b53_global_get_ports,
1160 },
1161 {
1162 .type = SWITCH_TYPE_INT,
1163 .name = "reset_mib",
1164 .description = "Reset MIB counters",
1165 .set = b53_global_reset_mib,
1166 },
1167 {
1168 .type = SWITCH_TYPE_INT,
1169 .name = "enable_jumbo",
1170 .description = "Enable Jumbo Frames",
1171 .set = b53_global_set_jumbo_enable,
1172 .get = b53_global_get_jumbo_enable,
1173 .max = 1,
1174 },
1175 {
1176 .type = SWITCH_TYPE_INT,
1177 .name = "allow_vid_4095",
1178 .description = "Allow VID 4095",
1179 .set = b53_global_set_4095_enable,
1180 .get = b53_global_get_4095_enable,
1181 .max = 1,
1182 },
1183 };
1184
1185 static struct switch_attr b53_port_ops[] = {
1186 {
1187 .type = SWITCH_TYPE_STRING,
1188 .name = "mib",
1189 .description = "Get port's MIB counters",
1190 .get = b53_port_get_mib,
1191 },
1192 };
1193
1194 static struct switch_attr b53_no_ops[] = {
1195 };
1196
1197 static const struct switch_dev_ops b53_switch_ops_25 = {
1198 .attr_global = {
1199 .attr = b53_global_ops_25,
1200 .n_attr = ARRAY_SIZE(b53_global_ops_25),
1201 },
1202 .attr_port = {
1203 .attr = b53_no_ops,
1204 .n_attr = ARRAY_SIZE(b53_no_ops),
1205 },
1206 .attr_vlan = {
1207 .attr = b53_no_ops,
1208 .n_attr = ARRAY_SIZE(b53_no_ops),
1209 },
1210
1211 .get_vlan_ports = b53_vlan_get_ports,
1212 .set_vlan_ports = b53_vlan_set_ports,
1213 .get_port_pvid = b53_port_get_pvid,
1214 .set_port_pvid = b53_port_set_pvid,
1215 .apply_config = b53_global_apply_config,
1216 .reset_switch = b53_global_reset_switch,
1217 .get_port_link = b53_port_get_link,
1218 .set_port_link = b53_port_set_link,
1219 .get_port_stats = b53_port_get_stats,
1220 .phy_read16 = b53_phy_read16,
1221 .phy_write16 = b53_phy_write16,
1222 };
1223
1224 static const struct switch_dev_ops b53_switch_ops_65 = {
1225 .attr_global = {
1226 .attr = b53_global_ops_65,
1227 .n_attr = ARRAY_SIZE(b53_global_ops_65),
1228 },
1229 .attr_port = {
1230 .attr = b53_port_ops,
1231 .n_attr = ARRAY_SIZE(b53_port_ops),
1232 },
1233 .attr_vlan = {
1234 .attr = b53_no_ops,
1235 .n_attr = ARRAY_SIZE(b53_no_ops),
1236 },
1237
1238 .get_vlan_ports = b53_vlan_get_ports,
1239 .set_vlan_ports = b53_vlan_set_ports,
1240 .get_port_pvid = b53_port_get_pvid,
1241 .set_port_pvid = b53_port_set_pvid,
1242 .apply_config = b53_global_apply_config,
1243 .reset_switch = b53_global_reset_switch,
1244 .get_port_link = b53_port_get_link,
1245 .set_port_link = b53_port_set_link,
1246 .get_port_stats = b53_port_get_stats,
1247 .phy_read16 = b53_phy_read16,
1248 .phy_write16 = b53_phy_write16,
1249 };
1250
1251 static const struct switch_dev_ops b53_switch_ops = {
1252 .attr_global = {
1253 .attr = b53_global_ops,
1254 .n_attr = ARRAY_SIZE(b53_global_ops),
1255 },
1256 .attr_port = {
1257 .attr = b53_port_ops,
1258 .n_attr = ARRAY_SIZE(b53_port_ops),
1259 },
1260 .attr_vlan = {
1261 .attr = b53_no_ops,
1262 .n_attr = ARRAY_SIZE(b53_no_ops),
1263 },
1264
1265 .get_vlan_ports = b53_vlan_get_ports,
1266 .set_vlan_ports = b53_vlan_set_ports,
1267 .get_port_pvid = b53_port_get_pvid,
1268 .set_port_pvid = b53_port_set_pvid,
1269 .apply_config = b53_global_apply_config,
1270 .reset_switch = b53_global_reset_switch,
1271 .get_port_link = b53_port_get_link,
1272 .set_port_link = b53_port_set_link,
1273 .get_port_stats = b53_port_get_stats,
1274 .phy_read16 = b53_phy_read16,
1275 .phy_write16 = b53_phy_write16,
1276 };
1277
1278 struct b53_chip_data {
1279 u32 chip_id;
1280 const char *dev_name;
1281 const char *alias;
1282 u16 vlans;
1283 u16 enabled_ports;
1284 u8 cpu_port;
1285 u8 vta_regs[3];
1286 u8 duplex_reg;
1287 u8 jumbo_pm_reg;
1288 u8 jumbo_size_reg;
1289 const struct switch_dev_ops *sw_ops;
1290 };
1291
1292 #define B53_VTA_REGS \
1293 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1294 #define B53_VTA_REGS_9798 \
1295 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1296 #define B53_VTA_REGS_63XX \
1297 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1298
1299 static const struct b53_chip_data b53_switch_chips[] = {
1300 {
1301 .chip_id = BCM5325_DEVICE_ID,
1302 .dev_name = "BCM5325",
1303 .alias = "bcm5325",
1304 .vlans = 16,
1305 .enabled_ports = 0x1f,
1306 .cpu_port = B53_CPU_PORT_25,
1307 .duplex_reg = B53_DUPLEX_STAT_FE,
1308 .sw_ops = &b53_switch_ops_25,
1309 },
1310 {
1311 .chip_id = BCM5365_DEVICE_ID,
1312 .dev_name = "BCM5365",
1313 .alias = "bcm5365",
1314 .vlans = 256,
1315 .enabled_ports = 0x1f,
1316 .cpu_port = B53_CPU_PORT_25,
1317 .duplex_reg = B53_DUPLEX_STAT_FE,
1318 .sw_ops = &b53_switch_ops_65,
1319 },
1320 {
1321 .chip_id = BCM5395_DEVICE_ID,
1322 .dev_name = "BCM5395",
1323 .alias = "bcm5395",
1324 .vlans = 4096,
1325 .enabled_ports = 0x1f,
1326 .cpu_port = B53_CPU_PORT,
1327 .vta_regs = B53_VTA_REGS,
1328 .duplex_reg = B53_DUPLEX_STAT_GE,
1329 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1330 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1331 .sw_ops = &b53_switch_ops,
1332 },
1333 {
1334 .chip_id = BCM5397_DEVICE_ID,
1335 .dev_name = "BCM5397",
1336 .alias = "bcm5397",
1337 .vlans = 4096,
1338 .enabled_ports = 0x1f,
1339 .cpu_port = B53_CPU_PORT,
1340 .vta_regs = B53_VTA_REGS_9798,
1341 .duplex_reg = B53_DUPLEX_STAT_GE,
1342 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1343 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1344 .sw_ops = &b53_switch_ops,
1345 },
1346 {
1347 .chip_id = BCM5398_DEVICE_ID,
1348 .dev_name = "BCM5398",
1349 .alias = "bcm5398",
1350 .vlans = 4096,
1351 .enabled_ports = 0x7f,
1352 .cpu_port = B53_CPU_PORT,
1353 .vta_regs = B53_VTA_REGS_9798,
1354 .duplex_reg = B53_DUPLEX_STAT_GE,
1355 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1356 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1357 .sw_ops = &b53_switch_ops,
1358 },
1359 {
1360 .chip_id = BCM53115_DEVICE_ID,
1361 .dev_name = "BCM53115",
1362 .alias = "bcm53115",
1363 .vlans = 4096,
1364 .enabled_ports = 0x1f,
1365 .vta_regs = B53_VTA_REGS,
1366 .cpu_port = B53_CPU_PORT,
1367 .duplex_reg = B53_DUPLEX_STAT_GE,
1368 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1369 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1370 .sw_ops = &b53_switch_ops,
1371 },
1372 {
1373 .chip_id = BCM53125_DEVICE_ID,
1374 .dev_name = "BCM53125",
1375 .alias = "bcm53125",
1376 .vlans = 4096,
1377 .enabled_ports = 0x1f,
1378 .cpu_port = B53_CPU_PORT,
1379 .vta_regs = B53_VTA_REGS,
1380 .duplex_reg = B53_DUPLEX_STAT_GE,
1381 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1382 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1383 .sw_ops = &b53_switch_ops,
1384 },
1385 {
1386 .chip_id = BCM53128_DEVICE_ID,
1387 .dev_name = "BCM53128",
1388 .alias = "bcm53128",
1389 .vlans = 4096,
1390 .enabled_ports = 0x1ff,
1391 .cpu_port = B53_CPU_PORT,
1392 .vta_regs = B53_VTA_REGS,
1393 .duplex_reg = B53_DUPLEX_STAT_GE,
1394 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1395 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1396 .sw_ops = &b53_switch_ops,
1397 },
1398 {
1399 .chip_id = BCM63XX_DEVICE_ID,
1400 .dev_name = "BCM63xx",
1401 .alias = "bcm63xx",
1402 .vlans = 4096,
1403 .enabled_ports = 0, /* pdata must provide them */
1404 .cpu_port = B53_CPU_PORT,
1405 .vta_regs = B53_VTA_REGS_63XX,
1406 .duplex_reg = B53_DUPLEX_STAT_63XX,
1407 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1408 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1409 .sw_ops = &b53_switch_ops,
1410 },
1411 {
1412 .chip_id = BCM53010_DEVICE_ID,
1413 .dev_name = "BCM53010",
1414 .alias = "bcm53011",
1415 .vlans = 4096,
1416 .enabled_ports = 0x1f,
1417 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1418 .vta_regs = B53_VTA_REGS,
1419 .duplex_reg = B53_DUPLEX_STAT_GE,
1420 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1421 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1422 .sw_ops = &b53_switch_ops,
1423 },
1424 {
1425 .chip_id = BCM53011_DEVICE_ID,
1426 .dev_name = "BCM53011",
1427 .alias = "bcm53011",
1428 .vlans = 4096,
1429 .enabled_ports = 0x1bf,
1430 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1431 .vta_regs = B53_VTA_REGS,
1432 .duplex_reg = B53_DUPLEX_STAT_GE,
1433 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1434 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1435 .sw_ops = &b53_switch_ops,
1436 },
1437 {
1438 .chip_id = BCM53012_DEVICE_ID,
1439 .dev_name = "BCM53012",
1440 .alias = "bcm53011",
1441 .vlans = 4096,
1442 .enabled_ports = 0x1bf,
1443 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1444 .vta_regs = B53_VTA_REGS,
1445 .duplex_reg = B53_DUPLEX_STAT_GE,
1446 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1447 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1448 .sw_ops = &b53_switch_ops,
1449 },
1450 {
1451 .chip_id = BCM53018_DEVICE_ID,
1452 .dev_name = "BCM53018",
1453 .alias = "bcm53018",
1454 .vlans = 4096,
1455 .enabled_ports = 0x1f,
1456 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1457 .vta_regs = B53_VTA_REGS,
1458 .duplex_reg = B53_DUPLEX_STAT_GE,
1459 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1460 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1461 .sw_ops = &b53_switch_ops,
1462 },
1463 {
1464 .chip_id = BCM53019_DEVICE_ID,
1465 .dev_name = "BCM53019",
1466 .alias = "bcm53019",
1467 .vlans = 4096,
1468 .enabled_ports = 0x1f,
1469 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1470 .vta_regs = B53_VTA_REGS,
1471 .duplex_reg = B53_DUPLEX_STAT_GE,
1472 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1473 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1474 .sw_ops = &b53_switch_ops,
1475 },
1476 };
1477
1478 static int b53_switch_init_of(struct b53_device *dev)
1479 {
1480 struct device_node *dn, *pn;
1481 const char *alias;
1482 u32 port_num;
1483 u16 ports = 0;
1484
1485 dn = of_get_child_by_name(dev_of_node(dev->dev), "ports");
1486 if (!dn)
1487 return -EINVAL;
1488
1489 for_each_available_child_of_node(dn, pn) {
1490 const char *label;
1491 int len;
1492
1493 if (of_property_read_u32(pn, "reg", &port_num))
1494 continue;
1495
1496 if (port_num > B53_CPU_PORT)
1497 continue;
1498
1499 ports |= BIT(port_num);
1500
1501 label = of_get_property(pn, "label", &len);
1502 if (label && !strcmp(label, "cpu"))
1503 dev->sw_dev.cpu_port = port_num;
1504 }
1505
1506 dev->enabled_ports = ports;
1507
1508 if (!of_property_read_string(dev_of_node(dev->dev), "lede,alias",
1509 &alias))
1510 dev->sw_dev.alias = devm_kstrdup(dev->dev, alias, GFP_KERNEL);
1511
1512 return 0;
1513 }
1514
1515 static int b53_switch_init(struct b53_device *dev)
1516 {
1517 struct switch_dev *sw_dev = &dev->sw_dev;
1518 unsigned i;
1519 int ret;
1520
1521 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1522 const struct b53_chip_data *chip = &b53_switch_chips[i];
1523
1524 if (chip->chip_id == dev->chip_id) {
1525 sw_dev->name = chip->dev_name;
1526 if (!sw_dev->alias)
1527 sw_dev->alias = chip->alias;
1528 if (!dev->enabled_ports)
1529 dev->enabled_ports = chip->enabled_ports;
1530 dev->duplex_reg = chip->duplex_reg;
1531 dev->vta_regs[0] = chip->vta_regs[0];
1532 dev->vta_regs[1] = chip->vta_regs[1];
1533 dev->vta_regs[2] = chip->vta_regs[2];
1534 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1535 sw_dev->ops = chip->sw_ops;
1536 sw_dev->cpu_port = chip->cpu_port;
1537 sw_dev->vlans = chip->vlans;
1538 break;
1539 }
1540 }
1541
1542 if (!sw_dev->name)
1543 return -EINVAL;
1544
1545 /* check which BCM5325x version we have */
1546 if (is5325(dev)) {
1547 u8 vc4;
1548
1549 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1550
1551 /* check reserved bits */
1552 switch (vc4 & 3) {
1553 case 1:
1554 /* BCM5325E */
1555 break;
1556 case 3:
1557 /* BCM5325F - do not use port 4 */
1558 dev->enabled_ports &= ~BIT(4);
1559 break;
1560 default:
1561 /* On the BCM47XX SoCs this is the supported internal switch.*/
1562 #ifndef CONFIG_BCM47XX
1563 /* BCM5325M */
1564 return -EINVAL;
1565 #else
1566 break;
1567 #endif
1568 }
1569 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1570 u64 strap_value;
1571
1572 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1573 /* use second IMP port if GMII is enabled */
1574 if (strap_value & SV_GMII_CTRL_115)
1575 sw_dev->cpu_port = 5;
1576 }
1577
1578 if (dev_of_node(dev->dev)) {
1579 ret = b53_switch_init_of(dev);
1580 if (ret)
1581 return ret;
1582 }
1583
1584 dev->enabled_ports |= BIT(sw_dev->cpu_port);
1585 sw_dev->ports = fls(dev->enabled_ports);
1586
1587 dev->ports = devm_kzalloc(dev->dev,
1588 sizeof(struct b53_port) * sw_dev->ports,
1589 GFP_KERNEL);
1590 if (!dev->ports)
1591 return -ENOMEM;
1592
1593 dev->vlans = devm_kzalloc(dev->dev,
1594 sizeof(struct b53_vlan) * sw_dev->vlans,
1595 GFP_KERNEL);
1596 if (!dev->vlans)
1597 return -ENOMEM;
1598
1599 dev->buf = devm_kzalloc(dev->dev, B53_BUF_SIZE, GFP_KERNEL);
1600 if (!dev->buf)
1601 return -ENOMEM;
1602
1603 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1604 if (dev->reset_gpio >= 0) {
1605 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1606 GPIOF_OUT_INIT_HIGH, "robo_reset");
1607 if (ret)
1608 return ret;
1609 }
1610
1611 return b53_switch_reset(dev);
1612 }
1613
1614 struct b53_device *b53_swconfig_switch_alloc(struct device *base, struct b53_io_ops *ops,
1615 void *priv)
1616 {
1617 struct b53_device *dev;
1618
1619 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
1620 if (!dev)
1621 return NULL;
1622
1623 dev->dev = base;
1624 dev->ops = ops;
1625 dev->priv = priv;
1626 mutex_init(&dev->reg_mutex);
1627
1628 return dev;
1629 }
1630 EXPORT_SYMBOL(b53_swconfig_switch_alloc);
1631
1632 int b53_swconfig_switch_detect(struct b53_device *dev)
1633 {
1634 u32 id32;
1635 u16 tmp;
1636 u8 id8;
1637 int ret;
1638
1639 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1640 if (ret)
1641 return ret;
1642
1643 switch (id8) {
1644 case 0:
1645 /*
1646 * BCM5325 and BCM5365 do not have this register so reads
1647 * return 0. But the read operation did succeed, so assume
1648 * this is one of them.
1649 *
1650 * Next check if we can write to the 5325's VTA register; for
1651 * 5365 it is read only.
1652 */
1653
1654 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1655 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1656
1657 if (tmp == 0xf)
1658 dev->chip_id = BCM5325_DEVICE_ID;
1659 else
1660 dev->chip_id = BCM5365_DEVICE_ID;
1661 break;
1662 case BCM5395_DEVICE_ID:
1663 case BCM5397_DEVICE_ID:
1664 case BCM5398_DEVICE_ID:
1665 dev->chip_id = id8;
1666 break;
1667 default:
1668 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1669 if (ret)
1670 return ret;
1671
1672 switch (id32) {
1673 case BCM53115_DEVICE_ID:
1674 case BCM53125_DEVICE_ID:
1675 case BCM53128_DEVICE_ID:
1676 case BCM53010_DEVICE_ID:
1677 case BCM53011_DEVICE_ID:
1678 case BCM53012_DEVICE_ID:
1679 case BCM53018_DEVICE_ID:
1680 case BCM53019_DEVICE_ID:
1681 dev->chip_id = id32;
1682 break;
1683 default:
1684 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1685 id8, id32);
1686 return -ENODEV;
1687 }
1688 }
1689
1690 if (dev->chip_id == BCM5325_DEVICE_ID)
1691 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1692 &dev->core_rev);
1693 else
1694 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1695 &dev->core_rev);
1696 }
1697 EXPORT_SYMBOL(b53_swconfig_switch_detect);
1698
1699 int b53_swconfig_switch_register(struct b53_device *dev)
1700 {
1701 int ret;
1702
1703 if (dev->pdata) {
1704 dev->chip_id = dev->pdata->chip_id;
1705 dev->enabled_ports = dev->pdata->enabled_ports;
1706 dev->sw_dev.alias = dev->pdata->alias;
1707 }
1708
1709 if (!dev->chip_id && b53_swconfig_switch_detect(dev))
1710 return -EINVAL;
1711
1712 ret = b53_switch_init(dev);
1713 if (ret)
1714 return ret;
1715
1716 pr_info("found switch: %s, rev %i\n", dev->sw_dev.name, dev->core_rev);
1717
1718 return register_switch(&dev->sw_dev, NULL);
1719 }
1720 EXPORT_SYMBOL(b53_swconfig_switch_register);
1721
1722 MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1723 MODULE_DESCRIPTION("B53 switch library");
1724 MODULE_LICENSE("Dual BSD/GPL");
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