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ar8216: Fix issue with autoneg being disabled under 3.14, revert 43332
[openwrt/staging/lynxis.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37 #include <linux/leds.h>
38 #include <linux/gpio.h>
39 #include <linux/version.h>
40
41 #include "ar8216.h"
42
43 /* size of the vlan table */
44 #define AR8X16_MAX_VLANS 128
45 #define AR8X16_PROBE_RETRIES 10
46 #define AR8X16_MAX_PORTS 8
47
48 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
49
50 struct ar8xxx_priv;
51
52 #define AR8XXX_CAP_GIGE BIT(0)
53 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
54
55 #define AR8XXX_NUM_PHYS 5
56
57 enum {
58 AR8XXX_VER_AR8216 = 0x01,
59 AR8XXX_VER_AR8236 = 0x03,
60 AR8XXX_VER_AR8316 = 0x10,
61 AR8XXX_VER_AR8327 = 0x12,
62 AR8XXX_VER_AR8337 = 0x13,
63 };
64
65 struct ar8xxx_mib_desc {
66 unsigned int size;
67 unsigned int offset;
68 const char *name;
69 };
70
71 struct ar8xxx_chip {
72 unsigned long caps;
73
74 int (*hw_init)(struct ar8xxx_priv *priv);
75 void (*cleanup)(struct ar8xxx_priv *priv);
76
77 void (*init_globals)(struct ar8xxx_priv *priv);
78 void (*init_port)(struct ar8xxx_priv *priv, int port);
79 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
80 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
81 int (*atu_flush)(struct ar8xxx_priv *priv);
82 void (*vtu_flush)(struct ar8xxx_priv *priv);
83 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
84 void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
85
86 const struct ar8xxx_mib_desc *mib_decs;
87 unsigned num_mibs;
88 };
89
90 enum ar8327_led_pattern {
91 AR8327_LED_PATTERN_OFF = 0,
92 AR8327_LED_PATTERN_BLINK,
93 AR8327_LED_PATTERN_ON,
94 AR8327_LED_PATTERN_RULE,
95 };
96
97 struct ar8327_led_entry {
98 unsigned reg;
99 unsigned shift;
100 };
101
102 struct ar8327_led {
103 struct led_classdev cdev;
104 struct ar8xxx_priv *sw_priv;
105
106 char *name;
107 bool active_low;
108 u8 led_num;
109 enum ar8327_led_mode mode;
110
111 struct mutex mutex;
112 spinlock_t lock;
113 struct work_struct led_work;
114 bool enable_hw_mode;
115 enum ar8327_led_pattern pattern;
116 };
117
118 struct ar8327_data {
119 u32 port0_status;
120 u32 port6_status;
121
122 struct ar8327_led **leds;
123 unsigned int num_leds;
124 };
125
126 struct ar8xxx_priv {
127 struct switch_dev dev;
128 struct mii_bus *mii_bus;
129 struct phy_device *phy;
130
131 u32 (*read)(struct ar8xxx_priv *priv, int reg);
132 void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
133 u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
134
135 int (*get_port_link)(unsigned port);
136
137 const struct net_device_ops *ndo_old;
138 struct net_device_ops ndo;
139 struct mutex reg_mutex;
140 u8 chip_ver;
141 u8 chip_rev;
142 const struct ar8xxx_chip *chip;
143 union {
144 struct ar8327_data ar8327;
145 } chip_data;
146 bool initialized;
147 bool port4_phy;
148 char buf[2048];
149
150 bool init;
151 bool mii_lo_first;
152
153 struct mutex mib_lock;
154 struct delayed_work mib_work;
155 int mib_next_port;
156 u64 *mib_stats;
157
158 struct list_head list;
159 unsigned int use_count;
160
161 /* all fields below are cleared on reset */
162 bool vlan;
163 u16 vlan_id[AR8X16_MAX_VLANS];
164 u8 vlan_table[AR8X16_MAX_VLANS];
165 u8 vlan_tagged;
166 u16 pvid[AR8X16_MAX_PORTS];
167
168 /* mirroring */
169 bool mirror_rx;
170 bool mirror_tx;
171 int source_port;
172 int monitor_port;
173 };
174
175 #define MIB_DESC(_s , _o, _n) \
176 { \
177 .size = (_s), \
178 .offset = (_o), \
179 .name = (_n), \
180 }
181
182 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
183 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
184 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
185 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
186 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
187 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
188 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
189 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
190 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
191 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
192 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
193 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
194 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
195 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
196 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
197 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
198 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
199 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
200 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
201 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
202 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
203 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
204 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
205 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
206 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
207 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
208 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
209 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
210 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
211 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
212 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
213 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
214 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
215 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
216 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
217 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
218 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
219 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
220 };
221
222 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
223 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
224 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
225 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
226 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
227 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
228 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
229 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
230 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
231 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
232 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
233 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
234 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
235 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
236 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
237 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
238 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
239 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
240 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
241 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
242 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
243 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
244 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
245 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
246 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
247 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
248 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
249 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
250 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
251 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
252 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
253 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
254 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
255 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
256 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
257 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
258 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
259 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
260 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
261 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
262 };
263
264 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
265 static LIST_HEAD(ar8xxx_dev_list);
266
267 static inline struct ar8xxx_priv *
268 swdev_to_ar8xxx(struct switch_dev *swdev)
269 {
270 return container_of(swdev, struct ar8xxx_priv, dev);
271 }
272
273 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
274 {
275 return priv->chip->caps & AR8XXX_CAP_GIGE;
276 }
277
278 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
279 {
280 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
281 }
282
283 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
284 {
285 return priv->chip_ver == AR8XXX_VER_AR8216;
286 }
287
288 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
289 {
290 return priv->chip_ver == AR8XXX_VER_AR8236;
291 }
292
293 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
294 {
295 return priv->chip_ver == AR8XXX_VER_AR8316;
296 }
297
298 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
299 {
300 return priv->chip_ver == AR8XXX_VER_AR8327;
301 }
302
303 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
304 {
305 return priv->chip_ver == AR8XXX_VER_AR8337;
306 }
307
308 static inline void
309 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
310 {
311 regaddr >>= 1;
312 *r1 = regaddr & 0x1e;
313
314 regaddr >>= 5;
315 *r2 = regaddr & 0x7;
316
317 regaddr >>= 3;
318 *page = regaddr & 0x1ff;
319 }
320
321 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
322 static int
323 ar8xxx_phy_poll_reset(struct mii_bus *bus)
324 {
325 unsigned int sleep_msecs = 20;
326 int ret, elapsed, i;
327
328 for (elapsed = sleep_msecs; elapsed <= 600;
329 elapsed += sleep_msecs) {
330 msleep(sleep_msecs);
331 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
332 ret = mdiobus_read(bus, i, MII_BMCR);
333 if (ret < 0)
334 return ret;
335 if (ret & BMCR_RESET)
336 break;
337 if (i == AR8XXX_NUM_PHYS - 1) {
338 usleep_range(1000, 2000);
339 return 0;
340 }
341 }
342 }
343 return -ETIMEDOUT;
344 }
345
346 static int
347 ar8xxx_phy_check_aneg(struct phy_device *phydev)
348 {
349 int ret;
350
351 if (phydev->autoneg != AUTONEG_ENABLE)
352 return 0;
353 /*
354 * BMCR_ANENABLE might have been cleared
355 * by phy_init_hw in certain kernel versions
356 * therefore check for it
357 */
358 ret = phy_read(phydev, MII_BMCR);
359 if (ret < 0)
360 return ret;
361 if (ret & BMCR_ANENABLE)
362 return 0;
363
364 dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
365 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
366 return phy_write(phydev, MII_BMCR, ret);
367 }
368
369 static void
370 ar8xxx_phy_init(struct ar8xxx_priv *priv)
371 {
372 int i;
373 struct mii_bus *bus;
374
375 bus = priv->mii_bus;
376 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
377 if (priv->chip->phy_fixup)
378 priv->chip->phy_fixup(priv, i);
379
380 /* initialize the port itself */
381 mdiobus_write(bus, i, MII_ADVERTISE,
382 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
383 if (ar8xxx_has_gige(priv))
384 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
385 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
386 }
387
388 ar8xxx_phy_poll_reset(bus);
389 }
390
391 static u32
392 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
393 {
394 struct mii_bus *bus = priv->mii_bus;
395 u16 r1, r2, page;
396 u16 lo, hi;
397
398 split_addr((u32) reg, &r1, &r2, &page);
399
400 mutex_lock(&bus->mdio_lock);
401
402 bus->write(bus, 0x18, 0, page);
403 usleep_range(1000, 2000); /* wait for the page switch to propagate */
404 lo = bus->read(bus, 0x10 | r2, r1);
405 hi = bus->read(bus, 0x10 | r2, r1 + 1);
406
407 mutex_unlock(&bus->mdio_lock);
408
409 return (hi << 16) | lo;
410 }
411
412 static void
413 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
414 {
415 struct mii_bus *bus = priv->mii_bus;
416 u16 r1, r2, r3;
417 u16 lo, hi;
418
419 split_addr((u32) reg, &r1, &r2, &r3);
420 lo = val & 0xffff;
421 hi = (u16) (val >> 16);
422
423 mutex_lock(&bus->mdio_lock);
424
425 bus->write(bus, 0x18, 0, r3);
426 usleep_range(1000, 2000); /* wait for the page switch to propagate */
427 if (priv->mii_lo_first) {
428 bus->write(bus, 0x10 | r2, r1, lo);
429 bus->write(bus, 0x10 | r2, r1 + 1, hi);
430 } else {
431 bus->write(bus, 0x10 | r2, r1 + 1, hi);
432 bus->write(bus, 0x10 | r2, r1, lo);
433 }
434
435 mutex_unlock(&bus->mdio_lock);
436 }
437
438 static u32
439 ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
440 {
441 struct mii_bus *bus = priv->mii_bus;
442 u16 r1, r2, page;
443 u16 lo, hi;
444 u32 ret;
445
446 split_addr((u32) reg, &r1, &r2, &page);
447
448 mutex_lock(&bus->mdio_lock);
449
450 bus->write(bus, 0x18, 0, page);
451 usleep_range(1000, 2000); /* wait for the page switch to propagate */
452
453 lo = bus->read(bus, 0x10 | r2, r1);
454 hi = bus->read(bus, 0x10 | r2, r1 + 1);
455
456 ret = hi << 16 | lo;
457 ret &= ~mask;
458 ret |= val;
459
460 lo = ret & 0xffff;
461 hi = (u16) (ret >> 16);
462
463 if (priv->mii_lo_first) {
464 bus->write(bus, 0x10 | r2, r1, lo);
465 bus->write(bus, 0x10 | r2, r1 + 1, hi);
466 } else {
467 bus->write(bus, 0x10 | r2, r1 + 1, hi);
468 bus->write(bus, 0x10 | r2, r1, lo);
469 }
470
471 mutex_unlock(&bus->mdio_lock);
472
473 return ret;
474 }
475
476
477 static void
478 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
479 u16 dbg_addr, u16 dbg_data)
480 {
481 struct mii_bus *bus = priv->mii_bus;
482
483 mutex_lock(&bus->mdio_lock);
484 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
485 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
486 mutex_unlock(&bus->mdio_lock);
487 }
488
489 static void
490 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
491 {
492 struct mii_bus *bus = priv->mii_bus;
493
494 mutex_lock(&bus->mdio_lock);
495 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
496 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
497 mutex_unlock(&bus->mdio_lock);
498 }
499
500 static inline u32
501 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
502 {
503 return priv->rmw(priv, reg, mask, val);
504 }
505
506 static inline void
507 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
508 {
509 priv->rmw(priv, reg, 0, val);
510 }
511
512 static int
513 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
514 unsigned timeout)
515 {
516 int i;
517
518 for (i = 0; i < timeout; i++) {
519 u32 t;
520
521 t = priv->read(priv, reg);
522 if ((t & mask) == val)
523 return 0;
524
525 usleep_range(1000, 2000);
526 }
527
528 return -ETIMEDOUT;
529 }
530
531 static int
532 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
533 {
534 unsigned mib_func;
535 int ret;
536
537 lockdep_assert_held(&priv->mib_lock);
538
539 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
540 mib_func = AR8327_REG_MIB_FUNC;
541 else
542 mib_func = AR8216_REG_MIB_FUNC;
543
544 /* Capture the hardware statistics for all ports */
545 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
546
547 /* Wait for the capturing to complete. */
548 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
549 if (ret)
550 goto out;
551
552 ret = 0;
553
554 out:
555 return ret;
556 }
557
558 static int
559 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
560 {
561 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
562 }
563
564 static int
565 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
566 {
567 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
568 }
569
570 static void
571 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
572 {
573 unsigned int base;
574 u64 *mib_stats;
575 int i;
576
577 WARN_ON(port >= priv->dev.ports);
578
579 lockdep_assert_held(&priv->mib_lock);
580
581 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
582 base = AR8327_REG_PORT_STATS_BASE(port);
583 else if (chip_is_ar8236(priv) ||
584 chip_is_ar8316(priv))
585 base = AR8236_REG_PORT_STATS_BASE(port);
586 else
587 base = AR8216_REG_PORT_STATS_BASE(port);
588
589 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
590 for (i = 0; i < priv->chip->num_mibs; i++) {
591 const struct ar8xxx_mib_desc *mib;
592 u64 t;
593
594 mib = &priv->chip->mib_decs[i];
595 t = priv->read(priv, base + mib->offset);
596 if (mib->size == 2) {
597 u64 hi;
598
599 hi = priv->read(priv, base + mib->offset + 4);
600 t |= hi << 32;
601 }
602
603 if (flush)
604 mib_stats[i] = 0;
605 else
606 mib_stats[i] += t;
607 }
608 }
609
610 static void
611 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
612 struct switch_port_link *link)
613 {
614 u32 status;
615 u32 speed;
616
617 memset(link, '\0', sizeof(*link));
618
619 status = priv->chip->read_port_status(priv, port);
620
621 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
622 if (link->aneg) {
623 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
624 } else {
625 link->link = true;
626
627 if (priv->get_port_link) {
628 int err;
629
630 err = priv->get_port_link(port);
631 if (err >= 0)
632 link->link = !!err;
633 }
634 }
635
636 if (!link->link)
637 return;
638
639 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
640 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
641 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
642
643 speed = (status & AR8216_PORT_STATUS_SPEED) >>
644 AR8216_PORT_STATUS_SPEED_S;
645
646 switch (speed) {
647 case AR8216_PORT_SPEED_10M:
648 link->speed = SWITCH_PORT_SPEED_10;
649 break;
650 case AR8216_PORT_SPEED_100M:
651 link->speed = SWITCH_PORT_SPEED_100;
652 break;
653 case AR8216_PORT_SPEED_1000M:
654 link->speed = SWITCH_PORT_SPEED_1000;
655 break;
656 default:
657 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
658 break;
659 }
660 }
661
662 static struct sk_buff *
663 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
664 {
665 struct ar8xxx_priv *priv = dev->phy_ptr;
666 unsigned char *buf;
667
668 if (unlikely(!priv))
669 goto error;
670
671 if (!priv->vlan)
672 goto send;
673
674 if (unlikely(skb_headroom(skb) < 2)) {
675 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
676 goto error;
677 }
678
679 buf = skb_push(skb, 2);
680 buf[0] = 0x10;
681 buf[1] = 0x80;
682
683 send:
684 return skb;
685
686 error:
687 dev_kfree_skb_any(skb);
688 return NULL;
689 }
690
691 static void
692 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
693 {
694 struct ar8xxx_priv *priv;
695 unsigned char *buf;
696 int port, vlan;
697
698 priv = dev->phy_ptr;
699 if (!priv)
700 return;
701
702 /* don't strip the header if vlan mode is disabled */
703 if (!priv->vlan)
704 return;
705
706 /* strip header, get vlan id */
707 buf = skb->data;
708 skb_pull(skb, 2);
709
710 /* check for vlan header presence */
711 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
712 return;
713
714 port = buf[0] & 0xf;
715
716 /* no need to fix up packets coming from a tagged source */
717 if (priv->vlan_tagged & (1 << port))
718 return;
719
720 /* lookup port vid from local table, the switch passes an invalid vlan id */
721 vlan = priv->vlan_id[priv->pvid[port]];
722
723 buf[14 + 2] &= 0xf0;
724 buf[14 + 2] |= vlan >> 8;
725 buf[15 + 2] = vlan & 0xff;
726 }
727
728 static int
729 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
730 {
731 int timeout = 20;
732 u32 t = 0;
733
734 while (1) {
735 t = priv->read(priv, reg);
736 if ((t & mask) == val)
737 return 0;
738
739 if (timeout-- <= 0)
740 break;
741
742 udelay(10);
743 }
744
745 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
746 (unsigned int) reg, t, mask, val);
747 return -ETIMEDOUT;
748 }
749
750 static void
751 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
752 {
753 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
754 return;
755 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
756 val &= AR8216_VTUDATA_MEMBER;
757 val |= AR8216_VTUDATA_VALID;
758 priv->write(priv, AR8216_REG_VTU_DATA, val);
759 }
760 op |= AR8216_VTU_ACTIVE;
761 priv->write(priv, AR8216_REG_VTU, op);
762 }
763
764 static void
765 ar8216_vtu_flush(struct ar8xxx_priv *priv)
766 {
767 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
768 }
769
770 static void
771 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
772 {
773 u32 op;
774
775 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
776 ar8216_vtu_op(priv, op, port_mask);
777 }
778
779 static int
780 ar8216_atu_flush(struct ar8xxx_priv *priv)
781 {
782 int ret;
783
784 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
785 if (!ret)
786 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
787
788 return ret;
789 }
790
791 static u32
792 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
793 {
794 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
795 }
796
797 static void
798 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
799 {
800 u32 header;
801 u32 egress, ingress;
802 u32 pvid;
803
804 if (priv->vlan) {
805 pvid = priv->vlan_id[priv->pvid[port]];
806 if (priv->vlan_tagged & (1 << port))
807 egress = AR8216_OUT_ADD_VLAN;
808 else
809 egress = AR8216_OUT_STRIP_VLAN;
810 ingress = AR8216_IN_SECURE;
811 } else {
812 pvid = port;
813 egress = AR8216_OUT_KEEP;
814 ingress = AR8216_IN_PORT_ONLY;
815 }
816
817 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
818 header = AR8216_PORT_CTRL_HEADER;
819 else
820 header = 0;
821
822 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
823 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
824 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
825 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
826 AR8216_PORT_CTRL_LEARN | header |
827 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
828 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
829
830 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
831 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
832 AR8216_PORT_VLAN_DEFAULT_ID,
833 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
834 (ingress << AR8216_PORT_VLAN_MODE_S) |
835 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
836 }
837
838 static int
839 ar8216_hw_init(struct ar8xxx_priv *priv)
840 {
841 if (priv->initialized)
842 return 0;
843
844 ar8xxx_phy_init(priv);
845
846 priv->initialized = true;
847 return 0;
848 }
849
850 static void
851 ar8216_init_globals(struct ar8xxx_priv *priv)
852 {
853 /* standard atheros magic */
854 priv->write(priv, 0x38, 0xc000050e);
855
856 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
857 AR8216_GCTRL_MTU, 1518 + 8 + 2);
858 }
859
860 static void
861 ar8216_init_port(struct ar8xxx_priv *priv, int port)
862 {
863 /* Enable port learning and tx */
864 priv->write(priv, AR8216_REG_PORT_CTRL(port),
865 AR8216_PORT_CTRL_LEARN |
866 (4 << AR8216_PORT_CTRL_STATE_S));
867
868 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
869
870 if (port == AR8216_PORT_CPU) {
871 priv->write(priv, AR8216_REG_PORT_STATUS(port),
872 AR8216_PORT_STATUS_LINK_UP |
873 (ar8xxx_has_gige(priv) ?
874 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
875 AR8216_PORT_STATUS_TXMAC |
876 AR8216_PORT_STATUS_RXMAC |
877 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
878 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
879 AR8216_PORT_STATUS_DUPLEX);
880 } else {
881 priv->write(priv, AR8216_REG_PORT_STATUS(port),
882 AR8216_PORT_STATUS_LINK_AUTO);
883 }
884 }
885
886 static const struct ar8xxx_chip ar8216_chip = {
887 .caps = AR8XXX_CAP_MIB_COUNTERS,
888
889 .hw_init = ar8216_hw_init,
890 .init_globals = ar8216_init_globals,
891 .init_port = ar8216_init_port,
892 .setup_port = ar8216_setup_port,
893 .read_port_status = ar8216_read_port_status,
894 .atu_flush = ar8216_atu_flush,
895 .vtu_flush = ar8216_vtu_flush,
896 .vtu_load_vlan = ar8216_vtu_load_vlan,
897
898 .num_mibs = ARRAY_SIZE(ar8216_mibs),
899 .mib_decs = ar8216_mibs,
900 };
901
902 static void
903 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
904 {
905 u32 egress, ingress;
906 u32 pvid;
907
908 if (priv->vlan) {
909 pvid = priv->vlan_id[priv->pvid[port]];
910 if (priv->vlan_tagged & (1 << port))
911 egress = AR8216_OUT_ADD_VLAN;
912 else
913 egress = AR8216_OUT_STRIP_VLAN;
914 ingress = AR8216_IN_SECURE;
915 } else {
916 pvid = port;
917 egress = AR8216_OUT_KEEP;
918 ingress = AR8216_IN_PORT_ONLY;
919 }
920
921 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
922 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
923 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
924 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
925 AR8216_PORT_CTRL_LEARN |
926 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
927 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
928
929 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
930 AR8236_PORT_VLAN_DEFAULT_ID,
931 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
932
933 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
934 AR8236_PORT_VLAN2_VLAN_MODE |
935 AR8236_PORT_VLAN2_MEMBER,
936 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
937 (members << AR8236_PORT_VLAN2_MEMBER_S));
938 }
939
940 static void
941 ar8236_init_globals(struct ar8xxx_priv *priv)
942 {
943 /* enable jumbo frames */
944 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
945 AR8316_GCTRL_MTU, 9018 + 8 + 2);
946
947 /* Enable MIB counters */
948 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
949 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
950 AR8236_MIB_EN);
951 }
952
953 static const struct ar8xxx_chip ar8236_chip = {
954 .caps = AR8XXX_CAP_MIB_COUNTERS,
955 .hw_init = ar8216_hw_init,
956 .init_globals = ar8236_init_globals,
957 .init_port = ar8216_init_port,
958 .setup_port = ar8236_setup_port,
959 .read_port_status = ar8216_read_port_status,
960 .atu_flush = ar8216_atu_flush,
961 .vtu_flush = ar8216_vtu_flush,
962 .vtu_load_vlan = ar8216_vtu_load_vlan,
963
964 .num_mibs = ARRAY_SIZE(ar8236_mibs),
965 .mib_decs = ar8236_mibs,
966 };
967
968 static int
969 ar8316_hw_init(struct ar8xxx_priv *priv)
970 {
971 u32 val, newval;
972
973 val = priv->read(priv, AR8316_REG_POSTRIP);
974
975 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
976 if (priv->port4_phy) {
977 /* value taken from Ubiquiti RouterStation Pro */
978 newval = 0x81461bea;
979 pr_info("ar8316: Using port 4 as PHY\n");
980 } else {
981 newval = 0x01261be2;
982 pr_info("ar8316: Using port 4 as switch port\n");
983 }
984 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
985 /* value taken from AVM Fritz!Box 7390 sources */
986 newval = 0x010e5b71;
987 } else {
988 /* no known value for phy interface */
989 pr_err("ar8316: unsupported mii mode: %d.\n",
990 priv->phy->interface);
991 return -EINVAL;
992 }
993
994 if (val == newval)
995 goto out;
996
997 priv->write(priv, AR8316_REG_POSTRIP, newval);
998
999 if (priv->port4_phy &&
1000 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1001 /* work around for phy4 rgmii mode */
1002 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
1003 /* rx delay */
1004 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
1005 /* tx delay */
1006 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
1007 msleep(1000);
1008 }
1009
1010 ar8xxx_phy_init(priv);
1011
1012 out:
1013 priv->initialized = true;
1014 return 0;
1015 }
1016
1017 static void
1018 ar8316_init_globals(struct ar8xxx_priv *priv)
1019 {
1020 /* standard atheros magic */
1021 priv->write(priv, 0x38, 0xc000050e);
1022
1023 /* enable cpu port to receive multicast and broadcast frames */
1024 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1025
1026 /* enable jumbo frames */
1027 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1028 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1029
1030 /* Enable MIB counters */
1031 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1032 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1033 AR8236_MIB_EN);
1034 }
1035
1036 static const struct ar8xxx_chip ar8316_chip = {
1037 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1038 .hw_init = ar8316_hw_init,
1039 .init_globals = ar8316_init_globals,
1040 .init_port = ar8216_init_port,
1041 .setup_port = ar8216_setup_port,
1042 .read_port_status = ar8216_read_port_status,
1043 .atu_flush = ar8216_atu_flush,
1044 .vtu_flush = ar8216_vtu_flush,
1045 .vtu_load_vlan = ar8216_vtu_load_vlan,
1046
1047 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1048 .mib_decs = ar8236_mibs,
1049 };
1050
1051 static u32
1052 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
1053 {
1054 u32 t;
1055
1056 if (!cfg)
1057 return 0;
1058
1059 t = 0;
1060 switch (cfg->mode) {
1061 case AR8327_PAD_NC:
1062 break;
1063
1064 case AR8327_PAD_MAC2MAC_MII:
1065 t = AR8327_PAD_MAC_MII_EN;
1066 if (cfg->rxclk_sel)
1067 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
1068 if (cfg->txclk_sel)
1069 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
1070 break;
1071
1072 case AR8327_PAD_MAC2MAC_GMII:
1073 t = AR8327_PAD_MAC_GMII_EN;
1074 if (cfg->rxclk_sel)
1075 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
1076 if (cfg->txclk_sel)
1077 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
1078 break;
1079
1080 case AR8327_PAD_MAC_SGMII:
1081 t = AR8327_PAD_SGMII_EN;
1082
1083 /*
1084 * WAR for the QUalcomm Atheros AP136 board.
1085 * It seems that RGMII TX/RX delay settings needs to be
1086 * applied for SGMII mode as well, The ethernet is not
1087 * reliable without this.
1088 */
1089 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1090 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1091 if (cfg->rxclk_delay_en)
1092 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1093 if (cfg->txclk_delay_en)
1094 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1095
1096 if (cfg->sgmii_delay_en)
1097 t |= AR8327_PAD_SGMII_DELAY_EN;
1098
1099 break;
1100
1101 case AR8327_PAD_MAC2PHY_MII:
1102 t = AR8327_PAD_PHY_MII_EN;
1103 if (cfg->rxclk_sel)
1104 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
1105 if (cfg->txclk_sel)
1106 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
1107 break;
1108
1109 case AR8327_PAD_MAC2PHY_GMII:
1110 t = AR8327_PAD_PHY_GMII_EN;
1111 if (cfg->pipe_rxclk_sel)
1112 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1113 if (cfg->rxclk_sel)
1114 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1115 if (cfg->txclk_sel)
1116 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1117 break;
1118
1119 case AR8327_PAD_MAC_RGMII:
1120 t = AR8327_PAD_RGMII_EN;
1121 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1122 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1123 if (cfg->rxclk_delay_en)
1124 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1125 if (cfg->txclk_delay_en)
1126 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1127 break;
1128
1129 case AR8327_PAD_PHY_GMII:
1130 t = AR8327_PAD_PHYX_GMII_EN;
1131 break;
1132
1133 case AR8327_PAD_PHY_RGMII:
1134 t = AR8327_PAD_PHYX_RGMII_EN;
1135 break;
1136
1137 case AR8327_PAD_PHY_MII:
1138 t = AR8327_PAD_PHYX_MII_EN;
1139 break;
1140 }
1141
1142 return t;
1143 }
1144
1145 static void
1146 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1147 {
1148 switch (priv->chip_rev) {
1149 case 1:
1150 /* For 100M waveform */
1151 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1152 /* Turn on Gigabit clock */
1153 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1154 break;
1155
1156 case 2:
1157 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1158 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1159 /* fallthrough */
1160 case 4:
1161 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1162 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1163
1164 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1165 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1166 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1167 break;
1168 }
1169 }
1170
1171 static u32
1172 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1173 {
1174 u32 t;
1175
1176 if (!cfg->force_link)
1177 return AR8216_PORT_STATUS_LINK_AUTO;
1178
1179 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1180 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1181 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1182 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1183
1184 switch (cfg->speed) {
1185 case AR8327_PORT_SPEED_10:
1186 t |= AR8216_PORT_SPEED_10M;
1187 break;
1188 case AR8327_PORT_SPEED_100:
1189 t |= AR8216_PORT_SPEED_100M;
1190 break;
1191 case AR8327_PORT_SPEED_1000:
1192 t |= AR8216_PORT_SPEED_1000M;
1193 break;
1194 }
1195
1196 return t;
1197 }
1198
1199 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1200 [_num] = { .reg = (_reg), .shift = (_shift) }
1201
1202 static const struct ar8327_led_entry
1203 ar8327_led_map[AR8327_NUM_LEDS] = {
1204 AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
1205 AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
1206 AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
1207
1208 AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
1209 AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
1210 AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
1211
1212 AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
1213 AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
1214 AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
1215
1216 AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1217 AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1218 AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1219
1220 AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1221 AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1222 AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1223 };
1224
1225 static void
1226 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1227 enum ar8327_led_pattern pattern)
1228 {
1229 const struct ar8327_led_entry *entry;
1230
1231 entry = &ar8327_led_map[led_num];
1232 ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1233 (3 << entry->shift), pattern << entry->shift);
1234 }
1235
1236 static void
1237 ar8327_led_work_func(struct work_struct *work)
1238 {
1239 struct ar8327_led *aled;
1240 u8 pattern;
1241
1242 aled = container_of(work, struct ar8327_led, led_work);
1243
1244 spin_lock(&aled->lock);
1245 pattern = aled->pattern;
1246 spin_unlock(&aled->lock);
1247
1248 ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1249 pattern);
1250 }
1251
1252 static void
1253 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1254 {
1255 if (aled->pattern == pattern)
1256 return;
1257
1258 aled->pattern = pattern;
1259 schedule_work(&aled->led_work);
1260 }
1261
1262 static inline struct ar8327_led *
1263 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1264 {
1265 return container_of(led_cdev, struct ar8327_led, cdev);
1266 }
1267
1268 static int
1269 ar8327_led_blink_set(struct led_classdev *led_cdev,
1270 unsigned long *delay_on,
1271 unsigned long *delay_off)
1272 {
1273 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1274
1275 if (*delay_on == 0 && *delay_off == 0) {
1276 *delay_on = 125;
1277 *delay_off = 125;
1278 }
1279
1280 if (*delay_on != 125 || *delay_off != 125) {
1281 /*
1282 * The hardware only supports blinking at 4Hz. Fall back
1283 * to software implementation in other cases.
1284 */
1285 return -EINVAL;
1286 }
1287
1288 spin_lock(&aled->lock);
1289
1290 aled->enable_hw_mode = false;
1291 ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1292
1293 spin_unlock(&aled->lock);
1294
1295 return 0;
1296 }
1297
1298 static void
1299 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1300 enum led_brightness brightness)
1301 {
1302 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1303 u8 pattern;
1304 bool active;
1305
1306 active = (brightness != LED_OFF);
1307 active ^= aled->active_low;
1308
1309 pattern = (active) ? AR8327_LED_PATTERN_ON :
1310 AR8327_LED_PATTERN_OFF;
1311
1312 spin_lock(&aled->lock);
1313
1314 aled->enable_hw_mode = false;
1315 ar8327_led_schedule_change(aled, pattern);
1316
1317 spin_unlock(&aled->lock);
1318 }
1319
1320 static ssize_t
1321 ar8327_led_enable_hw_mode_show(struct device *dev,
1322 struct device_attribute *attr,
1323 char *buf)
1324 {
1325 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1326 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1327 ssize_t ret = 0;
1328
1329 spin_lock(&aled->lock);
1330 ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1331 spin_unlock(&aled->lock);
1332
1333 return ret;
1334 }
1335
1336 static ssize_t
1337 ar8327_led_enable_hw_mode_store(struct device *dev,
1338 struct device_attribute *attr,
1339 const char *buf,
1340 size_t size)
1341 {
1342 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1343 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1344 u8 pattern;
1345 u8 value;
1346 int ret;
1347
1348 ret = kstrtou8(buf, 10, &value);
1349 if (ret < 0)
1350 return -EINVAL;
1351
1352 spin_lock(&aled->lock);
1353
1354 aled->enable_hw_mode = !!value;
1355 if (aled->enable_hw_mode)
1356 pattern = AR8327_LED_PATTERN_RULE;
1357 else
1358 pattern = AR8327_LED_PATTERN_OFF;
1359
1360 ar8327_led_schedule_change(aled, pattern);
1361
1362 spin_unlock(&aled->lock);
1363
1364 return size;
1365 }
1366
1367 static DEVICE_ATTR(enable_hw_mode, S_IRUGO | S_IWUSR,
1368 ar8327_led_enable_hw_mode_show,
1369 ar8327_led_enable_hw_mode_store);
1370
1371 static int
1372 ar8327_led_register(struct ar8xxx_priv *priv, struct ar8327_led *aled)
1373 {
1374 int ret;
1375
1376 ret = led_classdev_register(NULL, &aled->cdev);
1377 if (ret < 0)
1378 return ret;
1379
1380 if (aled->mode == AR8327_LED_MODE_HW) {
1381 ret = device_create_file(aled->cdev.dev,
1382 &dev_attr_enable_hw_mode);
1383 if (ret)
1384 goto err_unregister;
1385 }
1386
1387 return 0;
1388
1389 err_unregister:
1390 led_classdev_unregister(&aled->cdev);
1391 return ret;
1392 }
1393
1394 static void
1395 ar8327_led_unregister(struct ar8327_led *aled)
1396 {
1397 if (aled->mode == AR8327_LED_MODE_HW)
1398 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1399
1400 led_classdev_unregister(&aled->cdev);
1401 cancel_work_sync(&aled->led_work);
1402 }
1403
1404 static int
1405 ar8327_led_create(struct ar8xxx_priv *priv,
1406 const struct ar8327_led_info *led_info)
1407 {
1408 struct ar8327_data *data = &priv->chip_data.ar8327;
1409 struct ar8327_led *aled;
1410 int ret;
1411
1412 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1413 return 0;
1414
1415 if (!led_info->name)
1416 return -EINVAL;
1417
1418 if (led_info->led_num >= AR8327_NUM_LEDS)
1419 return -EINVAL;
1420
1421 aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1422 GFP_KERNEL);
1423 if (!aled)
1424 return -ENOMEM;
1425
1426 aled->sw_priv = priv;
1427 aled->led_num = led_info->led_num;
1428 aled->active_low = led_info->active_low;
1429 aled->mode = led_info->mode;
1430
1431 if (aled->mode == AR8327_LED_MODE_HW)
1432 aled->enable_hw_mode = true;
1433
1434 aled->name = (char *)(aled + 1);
1435 strcpy(aled->name, led_info->name);
1436
1437 aled->cdev.name = aled->name;
1438 aled->cdev.brightness_set = ar8327_led_set_brightness;
1439 aled->cdev.blink_set = ar8327_led_blink_set;
1440 aled->cdev.default_trigger = led_info->default_trigger;
1441
1442 spin_lock_init(&aled->lock);
1443 mutex_init(&aled->mutex);
1444 INIT_WORK(&aled->led_work, ar8327_led_work_func);
1445
1446 ret = ar8327_led_register(priv, aled);
1447 if (ret)
1448 goto err_free;
1449
1450 data->leds[data->num_leds++] = aled;
1451
1452 return 0;
1453
1454 err_free:
1455 kfree(aled);
1456 return ret;
1457 }
1458
1459 static void
1460 ar8327_led_destroy(struct ar8327_led *aled)
1461 {
1462 ar8327_led_unregister(aled);
1463 kfree(aled);
1464 }
1465
1466 static void
1467 ar8327_leds_init(struct ar8xxx_priv *priv)
1468 {
1469 struct ar8327_data *data;
1470 unsigned i;
1471
1472 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1473 return;
1474
1475 data = &priv->chip_data.ar8327;
1476
1477 for (i = 0; i < data->num_leds; i++) {
1478 struct ar8327_led *aled;
1479
1480 aled = data->leds[i];
1481
1482 if (aled->enable_hw_mode)
1483 aled->pattern = AR8327_LED_PATTERN_RULE;
1484 else
1485 aled->pattern = AR8327_LED_PATTERN_OFF;
1486
1487 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1488 }
1489 }
1490
1491 static void
1492 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1493 {
1494 struct ar8327_data *data = &priv->chip_data.ar8327;
1495 unsigned i;
1496
1497 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1498 return;
1499
1500 for (i = 0; i < data->num_leds; i++) {
1501 struct ar8327_led *aled;
1502
1503 aled = data->leds[i];
1504 ar8327_led_destroy(aled);
1505 }
1506
1507 kfree(data->leds);
1508 }
1509
1510 static int
1511 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1512 struct ar8327_platform_data *pdata)
1513 {
1514 struct ar8327_led_cfg *led_cfg;
1515 struct ar8327_data *data;
1516 u32 pos, new_pos;
1517 u32 t;
1518
1519 if (!pdata)
1520 return -EINVAL;
1521
1522 priv->get_port_link = pdata->get_port_link;
1523
1524 data = &priv->chip_data.ar8327;
1525
1526 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1527 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1528
1529 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1530 if (chip_is_ar8337(priv))
1531 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1532
1533 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1534 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1535 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1536 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1537 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1538
1539 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1540 new_pos = pos;
1541
1542 led_cfg = pdata->led_cfg;
1543 if (led_cfg) {
1544 if (led_cfg->open_drain)
1545 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1546 else
1547 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1548
1549 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1550 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1551 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1552 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1553
1554 if (new_pos != pos)
1555 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1556 }
1557
1558 if (pdata->sgmii_cfg) {
1559 t = pdata->sgmii_cfg->sgmii_ctrl;
1560 if (priv->chip_rev == 1)
1561 t |= AR8327_SGMII_CTRL_EN_PLL |
1562 AR8327_SGMII_CTRL_EN_RX |
1563 AR8327_SGMII_CTRL_EN_TX;
1564 else
1565 t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1566 AR8327_SGMII_CTRL_EN_RX |
1567 AR8327_SGMII_CTRL_EN_TX);
1568
1569 priv->write(priv, AR8327_REG_SGMII_CTRL, t);
1570
1571 if (pdata->sgmii_cfg->serdes_aen)
1572 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1573 else
1574 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1575 }
1576
1577 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1578
1579 if (pdata->leds && pdata->num_leds) {
1580 int i;
1581
1582 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1583 GFP_KERNEL);
1584 if (!data->leds)
1585 return -ENOMEM;
1586
1587 for (i = 0; i < pdata->num_leds; i++)
1588 ar8327_led_create(priv, &pdata->leds[i]);
1589 }
1590
1591 return 0;
1592 }
1593
1594 #ifdef CONFIG_OF
1595 static int
1596 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1597 {
1598 const __be32 *paddr;
1599 int len;
1600 int i;
1601
1602 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1603 if (!paddr || len < (2 * sizeof(*paddr)))
1604 return -EINVAL;
1605
1606 len /= sizeof(*paddr);
1607
1608 for (i = 0; i < len - 1; i += 2) {
1609 u32 reg;
1610 u32 val;
1611
1612 reg = be32_to_cpup(paddr + i);
1613 val = be32_to_cpup(paddr + i + 1);
1614
1615 switch (reg) {
1616 case AR8327_REG_PORT_STATUS(0):
1617 priv->chip_data.ar8327.port0_status = val;
1618 break;
1619 case AR8327_REG_PORT_STATUS(6):
1620 priv->chip_data.ar8327.port6_status = val;
1621 break;
1622 default:
1623 priv->write(priv, reg, val);
1624 break;
1625 }
1626 }
1627
1628 return 0;
1629 }
1630 #else
1631 static inline int
1632 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1633 {
1634 return -EINVAL;
1635 }
1636 #endif
1637
1638 static int
1639 ar8327_hw_init(struct ar8xxx_priv *priv)
1640 {
1641 int ret;
1642
1643 if (priv->phy->dev.of_node)
1644 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1645 else
1646 ret = ar8327_hw_config_pdata(priv,
1647 priv->phy->dev.platform_data);
1648
1649 if (ret)
1650 return ret;
1651
1652 ar8327_leds_init(priv);
1653
1654 ar8xxx_phy_init(priv);
1655
1656 return 0;
1657 }
1658
1659 static void
1660 ar8327_cleanup(struct ar8xxx_priv *priv)
1661 {
1662 ar8327_leds_cleanup(priv);
1663 }
1664
1665 static void
1666 ar8327_init_globals(struct ar8xxx_priv *priv)
1667 {
1668 u32 t;
1669
1670 /* enable CPU port and disable mirror port */
1671 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1672 AR8327_FWD_CTRL0_MIRROR_PORT;
1673 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1674
1675 /* forward multicast and broadcast frames to CPU */
1676 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1677 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1678 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1679 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1680
1681 /* enable jumbo frames */
1682 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1683 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1684
1685 /* Enable MIB counters */
1686 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1687 AR8327_MODULE_EN_MIB);
1688
1689 /* Disable EEE on all ports due to stability issues */
1690 t = priv->read(priv, AR8327_REG_EEE_CTRL);
1691 t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1692 AR8327_EEE_CTRL_DISABLE_PHY(1) |
1693 AR8327_EEE_CTRL_DISABLE_PHY(2) |
1694 AR8327_EEE_CTRL_DISABLE_PHY(3) |
1695 AR8327_EEE_CTRL_DISABLE_PHY(4);
1696 priv->write(priv, AR8327_REG_EEE_CTRL, t);
1697 }
1698
1699 static void
1700 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1701 {
1702 u32 t;
1703
1704 if (port == AR8216_PORT_CPU)
1705 t = priv->chip_data.ar8327.port0_status;
1706 else if (port == 6)
1707 t = priv->chip_data.ar8327.port6_status;
1708 else
1709 t = AR8216_PORT_STATUS_LINK_AUTO;
1710
1711 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1712 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1713
1714 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1715 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1716 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1717
1718 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1719 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1720
1721 t = AR8327_PORT_LOOKUP_LEARN;
1722 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1723 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1724 }
1725
1726 static u32
1727 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1728 {
1729 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1730 }
1731
1732 static int
1733 ar8327_atu_flush(struct ar8xxx_priv *priv)
1734 {
1735 int ret;
1736
1737 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1738 AR8327_ATU_FUNC_BUSY, 0);
1739 if (!ret)
1740 priv->write(priv, AR8327_REG_ATU_FUNC,
1741 AR8327_ATU_FUNC_OP_FLUSH);
1742
1743 return ret;
1744 }
1745
1746 static void
1747 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1748 {
1749 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1750 AR8327_VTU_FUNC1_BUSY, 0))
1751 return;
1752
1753 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1754 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1755
1756 op |= AR8327_VTU_FUNC1_BUSY;
1757 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1758 }
1759
1760 static void
1761 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1762 {
1763 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1764 }
1765
1766 static void
1767 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1768 {
1769 u32 op;
1770 u32 val;
1771 int i;
1772
1773 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1774 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1775 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1776 u32 mode;
1777
1778 if ((port_mask & BIT(i)) == 0)
1779 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1780 else if (priv->vlan == 0)
1781 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1782 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
1783 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1784 else
1785 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1786
1787 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1788 }
1789 ar8327_vtu_op(priv, op, val);
1790 }
1791
1792 static void
1793 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1794 {
1795 u32 t;
1796 u32 egress, ingress;
1797 u32 pvid = priv->vlan_id[priv->pvid[port]];
1798
1799 if (priv->vlan) {
1800 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1801 ingress = AR8216_IN_SECURE;
1802 } else {
1803 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1804 ingress = AR8216_IN_PORT_ONLY;
1805 }
1806
1807 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1808 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1809 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1810
1811 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1812 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
1813 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1814
1815 t = members;
1816 t |= AR8327_PORT_LOOKUP_LEARN;
1817 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1818 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1819 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1820 }
1821
1822 static const struct ar8xxx_chip ar8327_chip = {
1823 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1824 .hw_init = ar8327_hw_init,
1825 .cleanup = ar8327_cleanup,
1826 .init_globals = ar8327_init_globals,
1827 .init_port = ar8327_init_port,
1828 .setup_port = ar8327_setup_port,
1829 .read_port_status = ar8327_read_port_status,
1830 .atu_flush = ar8327_atu_flush,
1831 .vtu_flush = ar8327_vtu_flush,
1832 .vtu_load_vlan = ar8327_vtu_load_vlan,
1833 .phy_fixup = ar8327_phy_fixup,
1834
1835 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1836 .mib_decs = ar8236_mibs,
1837 };
1838
1839 static int
1840 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1841 struct switch_val *val)
1842 {
1843 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1844 priv->vlan = !!val->value.i;
1845 return 0;
1846 }
1847
1848 static int
1849 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1850 struct switch_val *val)
1851 {
1852 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1853 val->value.i = priv->vlan;
1854 return 0;
1855 }
1856
1857
1858 static int
1859 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1860 {
1861 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1862
1863 /* make sure no invalid PVIDs get set */
1864
1865 if (vlan >= dev->vlans)
1866 return -EINVAL;
1867
1868 priv->pvid[port] = vlan;
1869 return 0;
1870 }
1871
1872 static int
1873 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1874 {
1875 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1876 *vlan = priv->pvid[port];
1877 return 0;
1878 }
1879
1880 static int
1881 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1882 struct switch_val *val)
1883 {
1884 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1885 priv->vlan_id[val->port_vlan] = val->value.i;
1886 return 0;
1887 }
1888
1889 static int
1890 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1891 struct switch_val *val)
1892 {
1893 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1894 val->value.i = priv->vlan_id[val->port_vlan];
1895 return 0;
1896 }
1897
1898 static int
1899 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1900 struct switch_port_link *link)
1901 {
1902 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1903
1904 ar8216_read_port_link(priv, port, link);
1905 return 0;
1906 }
1907
1908 static int
1909 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1910 {
1911 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1912 u8 ports = priv->vlan_table[val->port_vlan];
1913 int i;
1914
1915 val->len = 0;
1916 for (i = 0; i < dev->ports; i++) {
1917 struct switch_port *p;
1918
1919 if (!(ports & (1 << i)))
1920 continue;
1921
1922 p = &val->value.ports[val->len++];
1923 p->id = i;
1924 if (priv->vlan_tagged & (1 << i))
1925 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1926 else
1927 p->flags = 0;
1928 }
1929 return 0;
1930 }
1931
1932 static int
1933 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1934 {
1935 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1936 u8 ports = priv->vlan_table[val->port_vlan];
1937 int i;
1938
1939 val->len = 0;
1940 for (i = 0; i < dev->ports; i++) {
1941 struct switch_port *p;
1942
1943 if (!(ports & (1 << i)))
1944 continue;
1945
1946 p = &val->value.ports[val->len++];
1947 p->id = i;
1948 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
1949 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1950 else
1951 p->flags = 0;
1952 }
1953 return 0;
1954 }
1955
1956 static int
1957 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1958 {
1959 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1960 u8 *vt = &priv->vlan_table[val->port_vlan];
1961 int i, j;
1962
1963 *vt = 0;
1964 for (i = 0; i < val->len; i++) {
1965 struct switch_port *p = &val->value.ports[i];
1966
1967 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1968 priv->vlan_tagged |= (1 << p->id);
1969 } else {
1970 priv->vlan_tagged &= ~(1 << p->id);
1971 priv->pvid[p->id] = val->port_vlan;
1972
1973 /* make sure that an untagged port does not
1974 * appear in other vlans */
1975 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1976 if (j == val->port_vlan)
1977 continue;
1978 priv->vlan_table[j] &= ~(1 << p->id);
1979 }
1980 }
1981
1982 *vt |= 1 << p->id;
1983 }
1984 return 0;
1985 }
1986
1987 static int
1988 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1989 {
1990 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1991 u8 *vt = &priv->vlan_table[val->port_vlan];
1992 int i;
1993
1994 *vt = 0;
1995 for (i = 0; i < val->len; i++) {
1996 struct switch_port *p = &val->value.ports[i];
1997
1998 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1999 if (val->port_vlan == priv->pvid[p->id]) {
2000 priv->vlan_tagged |= (1 << p->id);
2001 }
2002 } else {
2003 priv->vlan_tagged &= ~(1 << p->id);
2004 priv->pvid[p->id] = val->port_vlan;
2005 }
2006
2007 *vt |= 1 << p->id;
2008 }
2009 return 0;
2010 }
2011
2012 static void
2013 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
2014 {
2015 int port;
2016
2017 /* reset all mirror registers */
2018 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2019 AR8327_FWD_CTRL0_MIRROR_PORT,
2020 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2021 for (port = 0; port < AR8327_NUM_PORTS; port++) {
2022 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
2023 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2024 0);
2025
2026 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
2027 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2028 0);
2029 }
2030
2031 /* now enable mirroring if necessary */
2032 if (priv->source_port >= AR8327_NUM_PORTS ||
2033 priv->monitor_port >= AR8327_NUM_PORTS ||
2034 priv->source_port == priv->monitor_port) {
2035 return;
2036 }
2037
2038 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2039 AR8327_FWD_CTRL0_MIRROR_PORT,
2040 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2041
2042 if (priv->mirror_rx)
2043 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
2044 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2045 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
2046
2047 if (priv->mirror_tx)
2048 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
2049 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2050 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
2051 }
2052
2053 static void
2054 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
2055 {
2056 int port;
2057
2058 /* reset all mirror registers */
2059 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2060 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2061 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2062 for (port = 0; port < AR8216_NUM_PORTS; port++) {
2063 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2064 AR8216_PORT_CTRL_MIRROR_RX,
2065 0);
2066
2067 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2068 AR8216_PORT_CTRL_MIRROR_TX,
2069 0);
2070 }
2071
2072 /* now enable mirroring if necessary */
2073 if (priv->source_port >= AR8216_NUM_PORTS ||
2074 priv->monitor_port >= AR8216_NUM_PORTS ||
2075 priv->source_port == priv->monitor_port) {
2076 return;
2077 }
2078
2079 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2080 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2081 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2082
2083 if (priv->mirror_rx)
2084 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2085 AR8216_PORT_CTRL_MIRROR_RX,
2086 AR8216_PORT_CTRL_MIRROR_RX);
2087
2088 if (priv->mirror_tx)
2089 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2090 AR8216_PORT_CTRL_MIRROR_TX,
2091 AR8216_PORT_CTRL_MIRROR_TX);
2092 }
2093
2094 static void
2095 ar8xxx_set_mirror_regs(struct ar8xxx_priv *priv)
2096 {
2097 if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2098 ar8327_set_mirror_regs(priv);
2099 } else {
2100 ar8216_set_mirror_regs(priv);
2101 }
2102 }
2103
2104 static int
2105 ar8xxx_sw_hw_apply(struct switch_dev *dev)
2106 {
2107 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2108 u8 portmask[AR8X16_MAX_PORTS];
2109 int i, j;
2110
2111 mutex_lock(&priv->reg_mutex);
2112 /* flush all vlan translation unit entries */
2113 priv->chip->vtu_flush(priv);
2114
2115 memset(portmask, 0, sizeof(portmask));
2116 if (!priv->init) {
2117 /* calculate the port destination masks and load vlans
2118 * into the vlan translation unit */
2119 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2120 u8 vp = priv->vlan_table[j];
2121
2122 if (!vp)
2123 continue;
2124
2125 for (i = 0; i < dev->ports; i++) {
2126 u8 mask = (1 << i);
2127 if (vp & mask)
2128 portmask[i] |= vp & ~mask;
2129 }
2130
2131 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
2132 priv->vlan_table[j]);
2133 }
2134 } else {
2135 /* vlan disabled:
2136 * isolate all ports, but connect them to the cpu port */
2137 for (i = 0; i < dev->ports; i++) {
2138 if (i == AR8216_PORT_CPU)
2139 continue;
2140
2141 portmask[i] = 1 << AR8216_PORT_CPU;
2142 portmask[AR8216_PORT_CPU] |= (1 << i);
2143 }
2144 }
2145
2146 /* update the port destination mask registers and tag settings */
2147 for (i = 0; i < dev->ports; i++) {
2148 priv->chip->setup_port(priv, i, portmask[i]);
2149 }
2150
2151 ar8xxx_set_mirror_regs(priv);
2152
2153 mutex_unlock(&priv->reg_mutex);
2154 return 0;
2155 }
2156
2157 static int
2158 ar8xxx_sw_reset_switch(struct switch_dev *dev)
2159 {
2160 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2161 int i;
2162
2163 mutex_lock(&priv->reg_mutex);
2164 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
2165 offsetof(struct ar8xxx_priv, vlan));
2166
2167 for (i = 0; i < AR8X16_MAX_VLANS; i++)
2168 priv->vlan_id[i] = i;
2169
2170 /* Configure all ports */
2171 for (i = 0; i < dev->ports; i++)
2172 priv->chip->init_port(priv, i);
2173
2174 priv->mirror_rx = false;
2175 priv->mirror_tx = false;
2176 priv->source_port = 0;
2177 priv->monitor_port = 0;
2178
2179 priv->chip->init_globals(priv);
2180
2181 mutex_unlock(&priv->reg_mutex);
2182
2183 return ar8xxx_sw_hw_apply(dev);
2184 }
2185
2186 static int
2187 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
2188 const struct switch_attr *attr,
2189 struct switch_val *val)
2190 {
2191 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2192 unsigned int len;
2193 int ret;
2194
2195 if (!ar8xxx_has_mib_counters(priv))
2196 return -EOPNOTSUPP;
2197
2198 mutex_lock(&priv->mib_lock);
2199
2200 len = priv->dev.ports * priv->chip->num_mibs *
2201 sizeof(*priv->mib_stats);
2202 memset(priv->mib_stats, '\0', len);
2203 ret = ar8xxx_mib_flush(priv);
2204 if (ret)
2205 goto unlock;
2206
2207 ret = 0;
2208
2209 unlock:
2210 mutex_unlock(&priv->mib_lock);
2211 return ret;
2212 }
2213
2214 static int
2215 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
2216 const struct switch_attr *attr,
2217 struct switch_val *val)
2218 {
2219 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2220
2221 mutex_lock(&priv->reg_mutex);
2222 priv->mirror_rx = !!val->value.i;
2223 ar8xxx_set_mirror_regs(priv);
2224 mutex_unlock(&priv->reg_mutex);
2225
2226 return 0;
2227 }
2228
2229 static int
2230 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
2231 const struct switch_attr *attr,
2232 struct switch_val *val)
2233 {
2234 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2235 val->value.i = priv->mirror_rx;
2236 return 0;
2237 }
2238
2239 static int
2240 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
2241 const struct switch_attr *attr,
2242 struct switch_val *val)
2243 {
2244 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2245
2246 mutex_lock(&priv->reg_mutex);
2247 priv->mirror_tx = !!val->value.i;
2248 ar8xxx_set_mirror_regs(priv);
2249 mutex_unlock(&priv->reg_mutex);
2250
2251 return 0;
2252 }
2253
2254 static int
2255 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2256 const struct switch_attr *attr,
2257 struct switch_val *val)
2258 {
2259 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2260 val->value.i = priv->mirror_tx;
2261 return 0;
2262 }
2263
2264 static int
2265 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2266 const struct switch_attr *attr,
2267 struct switch_val *val)
2268 {
2269 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2270
2271 mutex_lock(&priv->reg_mutex);
2272 priv->monitor_port = val->value.i;
2273 ar8xxx_set_mirror_regs(priv);
2274 mutex_unlock(&priv->reg_mutex);
2275
2276 return 0;
2277 }
2278
2279 static int
2280 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2281 const struct switch_attr *attr,
2282 struct switch_val *val)
2283 {
2284 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2285 val->value.i = priv->monitor_port;
2286 return 0;
2287 }
2288
2289 static int
2290 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2291 const struct switch_attr *attr,
2292 struct switch_val *val)
2293 {
2294 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2295
2296 mutex_lock(&priv->reg_mutex);
2297 priv->source_port = val->value.i;
2298 ar8xxx_set_mirror_regs(priv);
2299 mutex_unlock(&priv->reg_mutex);
2300
2301 return 0;
2302 }
2303
2304 static int
2305 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2306 const struct switch_attr *attr,
2307 struct switch_val *val)
2308 {
2309 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2310 val->value.i = priv->source_port;
2311 return 0;
2312 }
2313
2314 static int
2315 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2316 const struct switch_attr *attr,
2317 struct switch_val *val)
2318 {
2319 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2320 int port;
2321 int ret;
2322
2323 if (!ar8xxx_has_mib_counters(priv))
2324 return -EOPNOTSUPP;
2325
2326 port = val->port_vlan;
2327 if (port >= dev->ports)
2328 return -EINVAL;
2329
2330 mutex_lock(&priv->mib_lock);
2331 ret = ar8xxx_mib_capture(priv);
2332 if (ret)
2333 goto unlock;
2334
2335 ar8xxx_mib_fetch_port_stat(priv, port, true);
2336
2337 ret = 0;
2338
2339 unlock:
2340 mutex_unlock(&priv->mib_lock);
2341 return ret;
2342 }
2343
2344 static int
2345 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2346 const struct switch_attr *attr,
2347 struct switch_val *val)
2348 {
2349 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2350 const struct ar8xxx_chip *chip = priv->chip;
2351 u64 *mib_stats;
2352 int port;
2353 int ret;
2354 char *buf = priv->buf;
2355 int i, len = 0;
2356
2357 if (!ar8xxx_has_mib_counters(priv))
2358 return -EOPNOTSUPP;
2359
2360 port = val->port_vlan;
2361 if (port >= dev->ports)
2362 return -EINVAL;
2363
2364 mutex_lock(&priv->mib_lock);
2365 ret = ar8xxx_mib_capture(priv);
2366 if (ret)
2367 goto unlock;
2368
2369 ar8xxx_mib_fetch_port_stat(priv, port, false);
2370
2371 len += snprintf(buf + len, sizeof(priv->buf) - len,
2372 "Port %d MIB counters\n",
2373 port);
2374
2375 mib_stats = &priv->mib_stats[port * chip->num_mibs];
2376 for (i = 0; i < chip->num_mibs; i++)
2377 len += snprintf(buf + len, sizeof(priv->buf) - len,
2378 "%-12s: %llu\n",
2379 chip->mib_decs[i].name,
2380 mib_stats[i]);
2381
2382 val->value.s = buf;
2383 val->len = len;
2384
2385 ret = 0;
2386
2387 unlock:
2388 mutex_unlock(&priv->mib_lock);
2389 return ret;
2390 }
2391
2392 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2393 {
2394 .type = SWITCH_TYPE_INT,
2395 .name = "enable_vlan",
2396 .description = "Enable VLAN mode",
2397 .set = ar8xxx_sw_set_vlan,
2398 .get = ar8xxx_sw_get_vlan,
2399 .max = 1
2400 },
2401 {
2402 .type = SWITCH_TYPE_NOVAL,
2403 .name = "reset_mibs",
2404 .description = "Reset all MIB counters",
2405 .set = ar8xxx_sw_set_reset_mibs,
2406 },
2407 {
2408 .type = SWITCH_TYPE_INT,
2409 .name = "enable_mirror_rx",
2410 .description = "Enable mirroring of RX packets",
2411 .set = ar8xxx_sw_set_mirror_rx_enable,
2412 .get = ar8xxx_sw_get_mirror_rx_enable,
2413 .max = 1
2414 },
2415 {
2416 .type = SWITCH_TYPE_INT,
2417 .name = "enable_mirror_tx",
2418 .description = "Enable mirroring of TX packets",
2419 .set = ar8xxx_sw_set_mirror_tx_enable,
2420 .get = ar8xxx_sw_get_mirror_tx_enable,
2421 .max = 1
2422 },
2423 {
2424 .type = SWITCH_TYPE_INT,
2425 .name = "mirror_monitor_port",
2426 .description = "Mirror monitor port",
2427 .set = ar8xxx_sw_set_mirror_monitor_port,
2428 .get = ar8xxx_sw_get_mirror_monitor_port,
2429 .max = AR8216_NUM_PORTS - 1
2430 },
2431 {
2432 .type = SWITCH_TYPE_INT,
2433 .name = "mirror_source_port",
2434 .description = "Mirror source port",
2435 .set = ar8xxx_sw_set_mirror_source_port,
2436 .get = ar8xxx_sw_get_mirror_source_port,
2437 .max = AR8216_NUM_PORTS - 1
2438 },
2439 };
2440
2441 static struct switch_attr ar8327_sw_attr_globals[] = {
2442 {
2443 .type = SWITCH_TYPE_INT,
2444 .name = "enable_vlan",
2445 .description = "Enable VLAN mode",
2446 .set = ar8xxx_sw_set_vlan,
2447 .get = ar8xxx_sw_get_vlan,
2448 .max = 1
2449 },
2450 {
2451 .type = SWITCH_TYPE_NOVAL,
2452 .name = "reset_mibs",
2453 .description = "Reset all MIB counters",
2454 .set = ar8xxx_sw_set_reset_mibs,
2455 },
2456 {
2457 .type = SWITCH_TYPE_INT,
2458 .name = "enable_mirror_rx",
2459 .description = "Enable mirroring of RX packets",
2460 .set = ar8xxx_sw_set_mirror_rx_enable,
2461 .get = ar8xxx_sw_get_mirror_rx_enable,
2462 .max = 1
2463 },
2464 {
2465 .type = SWITCH_TYPE_INT,
2466 .name = "enable_mirror_tx",
2467 .description = "Enable mirroring of TX packets",
2468 .set = ar8xxx_sw_set_mirror_tx_enable,
2469 .get = ar8xxx_sw_get_mirror_tx_enable,
2470 .max = 1
2471 },
2472 {
2473 .type = SWITCH_TYPE_INT,
2474 .name = "mirror_monitor_port",
2475 .description = "Mirror monitor port",
2476 .set = ar8xxx_sw_set_mirror_monitor_port,
2477 .get = ar8xxx_sw_get_mirror_monitor_port,
2478 .max = AR8327_NUM_PORTS - 1
2479 },
2480 {
2481 .type = SWITCH_TYPE_INT,
2482 .name = "mirror_source_port",
2483 .description = "Mirror source port",
2484 .set = ar8xxx_sw_set_mirror_source_port,
2485 .get = ar8xxx_sw_get_mirror_source_port,
2486 .max = AR8327_NUM_PORTS - 1
2487 },
2488 };
2489
2490 static struct switch_attr ar8xxx_sw_attr_port[] = {
2491 {
2492 .type = SWITCH_TYPE_NOVAL,
2493 .name = "reset_mib",
2494 .description = "Reset single port MIB counters",
2495 .set = ar8xxx_sw_set_port_reset_mib,
2496 },
2497 {
2498 .type = SWITCH_TYPE_STRING,
2499 .name = "mib",
2500 .description = "Get port's MIB counters",
2501 .set = NULL,
2502 .get = ar8xxx_sw_get_port_mib,
2503 },
2504 };
2505
2506 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2507 {
2508 .type = SWITCH_TYPE_INT,
2509 .name = "vid",
2510 .description = "VLAN ID (0-4094)",
2511 .set = ar8xxx_sw_set_vid,
2512 .get = ar8xxx_sw_get_vid,
2513 .max = 4094,
2514 },
2515 };
2516
2517 static const struct switch_dev_ops ar8xxx_sw_ops = {
2518 .attr_global = {
2519 .attr = ar8xxx_sw_attr_globals,
2520 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2521 },
2522 .attr_port = {
2523 .attr = ar8xxx_sw_attr_port,
2524 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2525 },
2526 .attr_vlan = {
2527 .attr = ar8xxx_sw_attr_vlan,
2528 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2529 },
2530 .get_port_pvid = ar8xxx_sw_get_pvid,
2531 .set_port_pvid = ar8xxx_sw_set_pvid,
2532 .get_vlan_ports = ar8xxx_sw_get_ports,
2533 .set_vlan_ports = ar8xxx_sw_set_ports,
2534 .apply_config = ar8xxx_sw_hw_apply,
2535 .reset_switch = ar8xxx_sw_reset_switch,
2536 .get_port_link = ar8xxx_sw_get_port_link,
2537 };
2538
2539 static const struct switch_dev_ops ar8327_sw_ops = {
2540 .attr_global = {
2541 .attr = ar8327_sw_attr_globals,
2542 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2543 },
2544 .attr_port = {
2545 .attr = ar8xxx_sw_attr_port,
2546 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2547 },
2548 .attr_vlan = {
2549 .attr = ar8xxx_sw_attr_vlan,
2550 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2551 },
2552 .get_port_pvid = ar8xxx_sw_get_pvid,
2553 .set_port_pvid = ar8xxx_sw_set_pvid,
2554 .get_vlan_ports = ar8327_sw_get_ports,
2555 .set_vlan_ports = ar8327_sw_set_ports,
2556 .apply_config = ar8xxx_sw_hw_apply,
2557 .reset_switch = ar8xxx_sw_reset_switch,
2558 .get_port_link = ar8xxx_sw_get_port_link,
2559 };
2560
2561 static int
2562 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2563 {
2564 u32 val;
2565 u16 id;
2566 int i;
2567
2568 val = priv->read(priv, AR8216_REG_CTRL);
2569 if (val == ~0)
2570 return -ENODEV;
2571
2572 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2573 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2574 u16 t;
2575
2576 val = priv->read(priv, AR8216_REG_CTRL);
2577 if (val == ~0)
2578 return -ENODEV;
2579
2580 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2581 if (t != id)
2582 return -ENODEV;
2583 }
2584
2585 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2586 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2587
2588 switch (priv->chip_ver) {
2589 case AR8XXX_VER_AR8216:
2590 priv->chip = &ar8216_chip;
2591 break;
2592 case AR8XXX_VER_AR8236:
2593 priv->chip = &ar8236_chip;
2594 break;
2595 case AR8XXX_VER_AR8316:
2596 priv->chip = &ar8316_chip;
2597 break;
2598 case AR8XXX_VER_AR8327:
2599 priv->mii_lo_first = true;
2600 priv->chip = &ar8327_chip;
2601 break;
2602 case AR8XXX_VER_AR8337:
2603 priv->mii_lo_first = true;
2604 priv->chip = &ar8327_chip;
2605 break;
2606 default:
2607 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2608 priv->chip_ver, priv->chip_rev);
2609
2610 return -ENODEV;
2611 }
2612
2613 return 0;
2614 }
2615
2616 static void
2617 ar8xxx_mib_work_func(struct work_struct *work)
2618 {
2619 struct ar8xxx_priv *priv;
2620 int err;
2621
2622 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2623
2624 mutex_lock(&priv->mib_lock);
2625
2626 err = ar8xxx_mib_capture(priv);
2627 if (err)
2628 goto next_port;
2629
2630 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2631
2632 next_port:
2633 priv->mib_next_port++;
2634 if (priv->mib_next_port >= priv->dev.ports)
2635 priv->mib_next_port = 0;
2636
2637 mutex_unlock(&priv->mib_lock);
2638 schedule_delayed_work(&priv->mib_work,
2639 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2640 }
2641
2642 static int
2643 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2644 {
2645 unsigned int len;
2646
2647 if (!ar8xxx_has_mib_counters(priv))
2648 return 0;
2649
2650 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2651
2652 len = priv->dev.ports * priv->chip->num_mibs *
2653 sizeof(*priv->mib_stats);
2654 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2655
2656 if (!priv->mib_stats)
2657 return -ENOMEM;
2658
2659 return 0;
2660 }
2661
2662 static void
2663 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2664 {
2665 if (!ar8xxx_has_mib_counters(priv))
2666 return;
2667
2668 schedule_delayed_work(&priv->mib_work,
2669 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2670 }
2671
2672 static void
2673 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2674 {
2675 if (!ar8xxx_has_mib_counters(priv))
2676 return;
2677
2678 cancel_delayed_work(&priv->mib_work);
2679 }
2680
2681 static struct ar8xxx_priv *
2682 ar8xxx_create(void)
2683 {
2684 struct ar8xxx_priv *priv;
2685
2686 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2687 if (priv == NULL)
2688 return NULL;
2689
2690 mutex_init(&priv->reg_mutex);
2691 mutex_init(&priv->mib_lock);
2692 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2693
2694 return priv;
2695 }
2696
2697 static void
2698 ar8xxx_free(struct ar8xxx_priv *priv)
2699 {
2700 if (priv->chip && priv->chip->cleanup)
2701 priv->chip->cleanup(priv);
2702
2703 kfree(priv->mib_stats);
2704 kfree(priv);
2705 }
2706
2707 static struct ar8xxx_priv *
2708 ar8xxx_create_mii(struct mii_bus *bus)
2709 {
2710 struct ar8xxx_priv *priv;
2711
2712 priv = ar8xxx_create();
2713 if (priv) {
2714 priv->mii_bus = bus;
2715 priv->read = ar8xxx_mii_read;
2716 priv->write = ar8xxx_mii_write;
2717 priv->rmw = ar8xxx_mii_rmw;
2718 }
2719
2720 return priv;
2721 }
2722
2723 static int
2724 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2725 {
2726 struct switch_dev *swdev;
2727 int ret;
2728
2729 ret = ar8xxx_id_chip(priv);
2730 if (ret)
2731 return ret;
2732
2733 swdev = &priv->dev;
2734 swdev->cpu_port = AR8216_PORT_CPU;
2735 swdev->ops = &ar8xxx_sw_ops;
2736
2737 if (chip_is_ar8316(priv)) {
2738 swdev->name = "Atheros AR8316";
2739 swdev->vlans = AR8X16_MAX_VLANS;
2740 swdev->ports = AR8216_NUM_PORTS;
2741 } else if (chip_is_ar8236(priv)) {
2742 swdev->name = "Atheros AR8236";
2743 swdev->vlans = AR8216_NUM_VLANS;
2744 swdev->ports = AR8216_NUM_PORTS;
2745 } else if (chip_is_ar8327(priv)) {
2746 swdev->name = "Atheros AR8327";
2747 swdev->vlans = AR8X16_MAX_VLANS;
2748 swdev->ports = AR8327_NUM_PORTS;
2749 swdev->ops = &ar8327_sw_ops;
2750 } else if (chip_is_ar8337(priv)) {
2751 swdev->name = "Atheros AR8337";
2752 swdev->vlans = AR8X16_MAX_VLANS;
2753 swdev->ports = AR8327_NUM_PORTS;
2754 swdev->ops = &ar8327_sw_ops;
2755 } else {
2756 swdev->name = "Atheros AR8216";
2757 swdev->vlans = AR8216_NUM_VLANS;
2758 swdev->ports = AR8216_NUM_PORTS;
2759 }
2760
2761 ret = ar8xxx_mib_init(priv);
2762 if (ret)
2763 return ret;
2764
2765 return 0;
2766 }
2767
2768 static int
2769 ar8xxx_start(struct ar8xxx_priv *priv)
2770 {
2771 int ret;
2772
2773 priv->init = true;
2774
2775 ret = priv->chip->hw_init(priv);
2776 if (ret)
2777 return ret;
2778
2779 ret = ar8xxx_sw_reset_switch(&priv->dev);
2780 if (ret)
2781 return ret;
2782
2783 priv->init = false;
2784
2785 ar8xxx_mib_start(priv);
2786
2787 return 0;
2788 }
2789
2790 static int
2791 ar8xxx_phy_config_init(struct phy_device *phydev)
2792 {
2793 struct ar8xxx_priv *priv = phydev->priv;
2794 struct net_device *dev = phydev->attached_dev;
2795 int ret;
2796
2797 if (WARN_ON(!priv))
2798 return -ENODEV;
2799
2800 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
2801 return ar8xxx_phy_check_aneg(phydev);
2802
2803 priv->phy = phydev;
2804
2805 if (phydev->addr != 0) {
2806 if (chip_is_ar8316(priv)) {
2807 /* switch device has been initialized, reinit */
2808 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2809 priv->initialized = false;
2810 priv->port4_phy = true;
2811 ar8316_hw_init(priv);
2812 return 0;
2813 }
2814
2815 return 0;
2816 }
2817
2818 ret = ar8xxx_start(priv);
2819 if (ret)
2820 return ret;
2821
2822 /* VID fixup only needed on ar8216 */
2823 if (chip_is_ar8216(priv)) {
2824 dev->phy_ptr = priv;
2825 dev->priv_flags |= IFF_NO_IP_ALIGN;
2826 dev->eth_mangle_rx = ar8216_mangle_rx;
2827 dev->eth_mangle_tx = ar8216_mangle_tx;
2828 }
2829
2830 return 0;
2831 }
2832
2833 static int
2834 ar8xxx_phy_read_status(struct phy_device *phydev)
2835 {
2836 struct ar8xxx_priv *priv = phydev->priv;
2837 struct switch_port_link link;
2838 int ret;
2839
2840 if (phydev->addr != 0)
2841 return genphy_read_status(phydev);
2842
2843 ar8216_read_port_link(priv, phydev->addr, &link);
2844 phydev->link = !!link.link;
2845 if (!phydev->link)
2846 return 0;
2847
2848 switch (link.speed) {
2849 case SWITCH_PORT_SPEED_10:
2850 phydev->speed = SPEED_10;
2851 break;
2852 case SWITCH_PORT_SPEED_100:
2853 phydev->speed = SPEED_100;
2854 break;
2855 case SWITCH_PORT_SPEED_1000:
2856 phydev->speed = SPEED_1000;
2857 break;
2858 default:
2859 phydev->speed = 0;
2860 }
2861 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2862
2863 /* flush the address translation unit */
2864 mutex_lock(&priv->reg_mutex);
2865 ret = priv->chip->atu_flush(priv);
2866 mutex_unlock(&priv->reg_mutex);
2867
2868 phydev->state = PHY_RUNNING;
2869 netif_carrier_on(phydev->attached_dev);
2870 phydev->adjust_link(phydev->attached_dev);
2871
2872 return ret;
2873 }
2874
2875 static int
2876 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2877 {
2878 if (phydev->addr == 0)
2879 return 0;
2880
2881 return genphy_config_aneg(phydev);
2882 }
2883
2884 static const u32 ar8xxx_phy_ids[] = {
2885 0x004dd033,
2886 0x004dd034, /* AR8327 */
2887 0x004dd036, /* AR8337 */
2888 0x004dd041,
2889 0x004dd042,
2890 0x004dd043, /* AR8236 */
2891 };
2892
2893 static bool
2894 ar8xxx_phy_match(u32 phy_id)
2895 {
2896 int i;
2897
2898 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2899 if (phy_id == ar8xxx_phy_ids[i])
2900 return true;
2901
2902 return false;
2903 }
2904
2905 static bool
2906 ar8xxx_is_possible(struct mii_bus *bus)
2907 {
2908 unsigned i;
2909
2910 for (i = 0; i < 4; i++) {
2911 u32 phy_id;
2912
2913 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2914 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2915 if (!ar8xxx_phy_match(phy_id)) {
2916 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2917 dev_name(&bus->dev), i, phy_id);
2918 return false;
2919 }
2920 }
2921
2922 return true;
2923 }
2924
2925 static int
2926 ar8xxx_phy_probe(struct phy_device *phydev)
2927 {
2928 struct ar8xxx_priv *priv;
2929 struct switch_dev *swdev;
2930 int ret;
2931
2932 /* skip PHYs at unused adresses */
2933 if (phydev->addr != 0 && phydev->addr != 4)
2934 return -ENODEV;
2935
2936 if (!ar8xxx_is_possible(phydev->bus))
2937 return -ENODEV;
2938
2939 mutex_lock(&ar8xxx_dev_list_lock);
2940 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2941 if (priv->mii_bus == phydev->bus)
2942 goto found;
2943
2944 priv = ar8xxx_create_mii(phydev->bus);
2945 if (priv == NULL) {
2946 ret = -ENOMEM;
2947 goto unlock;
2948 }
2949
2950 ret = ar8xxx_probe_switch(priv);
2951 if (ret)
2952 goto free_priv;
2953
2954 swdev = &priv->dev;
2955 swdev->alias = dev_name(&priv->mii_bus->dev);
2956 ret = register_switch(swdev, NULL);
2957 if (ret)
2958 goto free_priv;
2959
2960 pr_info("%s: %s rev. %u switch registered on %s\n",
2961 swdev->devname, swdev->name, priv->chip_rev,
2962 dev_name(&priv->mii_bus->dev));
2963
2964 found:
2965 priv->use_count++;
2966
2967 if (phydev->addr == 0) {
2968 if (ar8xxx_has_gige(priv)) {
2969 phydev->supported = SUPPORTED_1000baseT_Full;
2970 phydev->advertising = ADVERTISED_1000baseT_Full;
2971 } else {
2972 phydev->supported = SUPPORTED_100baseT_Full;
2973 phydev->advertising = ADVERTISED_100baseT_Full;
2974 }
2975
2976 if (chip_is_ar8327(priv) || chip_is_ar8337(priv)) {
2977 priv->phy = phydev;
2978
2979 ret = ar8xxx_start(priv);
2980 if (ret)
2981 goto err_unregister_switch;
2982 }
2983 } else {
2984 if (ar8xxx_has_gige(priv)) {
2985 phydev->supported |= SUPPORTED_1000baseT_Full;
2986 phydev->advertising |= ADVERTISED_1000baseT_Full;
2987 }
2988 }
2989
2990 phydev->priv = priv;
2991
2992 list_add(&priv->list, &ar8xxx_dev_list);
2993
2994 mutex_unlock(&ar8xxx_dev_list_lock);
2995
2996 return 0;
2997
2998 err_unregister_switch:
2999 if (--priv->use_count)
3000 goto unlock;
3001
3002 unregister_switch(&priv->dev);
3003
3004 free_priv:
3005 ar8xxx_free(priv);
3006 unlock:
3007 mutex_unlock(&ar8xxx_dev_list_lock);
3008 return ret;
3009 }
3010
3011 static void
3012 ar8xxx_phy_detach(struct phy_device *phydev)
3013 {
3014 struct net_device *dev = phydev->attached_dev;
3015
3016 if (!dev)
3017 return;
3018
3019 dev->phy_ptr = NULL;
3020 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
3021 dev->eth_mangle_rx = NULL;
3022 dev->eth_mangle_tx = NULL;
3023 }
3024
3025 static void
3026 ar8xxx_phy_remove(struct phy_device *phydev)
3027 {
3028 struct ar8xxx_priv *priv = phydev->priv;
3029
3030 if (WARN_ON(!priv))
3031 return;
3032
3033 phydev->priv = NULL;
3034 if (--priv->use_count > 0)
3035 return;
3036
3037 mutex_lock(&ar8xxx_dev_list_lock);
3038 list_del(&priv->list);
3039 mutex_unlock(&ar8xxx_dev_list_lock);
3040
3041 unregister_switch(&priv->dev);
3042 ar8xxx_mib_stop(priv);
3043 ar8xxx_free(priv);
3044 }
3045
3046 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0)
3047 static int
3048 ar8xxx_phy_soft_reset(struct phy_device *phydev)
3049 {
3050 /* we don't need an extra reset */
3051 return 0;
3052 }
3053 #endif
3054
3055 static struct phy_driver ar8xxx_phy_driver = {
3056 .phy_id = 0x004d0000,
3057 .name = "Atheros AR8216/AR8236/AR8316",
3058 .phy_id_mask = 0xffff0000,
3059 .features = PHY_BASIC_FEATURES,
3060 .probe = ar8xxx_phy_probe,
3061 .remove = ar8xxx_phy_remove,
3062 .detach = ar8xxx_phy_detach,
3063 .config_init = ar8xxx_phy_config_init,
3064 .config_aneg = ar8xxx_phy_config_aneg,
3065 .read_status = ar8xxx_phy_read_status,
3066 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0)
3067 .soft_reset = ar8xxx_phy_soft_reset,
3068 #endif
3069 .driver = { .owner = THIS_MODULE },
3070 };
3071
3072 int __init
3073 ar8xxx_init(void)
3074 {
3075 return phy_driver_register(&ar8xxx_phy_driver);
3076 }
3077
3078 void __exit
3079 ar8xxx_exit(void)
3080 {
3081 phy_driver_unregister(&ar8xxx_phy_driver);
3082 }
3083
3084 module_init(ar8xxx_init);
3085 module_exit(ar8xxx_exit);
3086 MODULE_LICENSE("GPL");
3087
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