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ar8216: factor out set_mirror_regs to ar8xxx_chip
[openwrt/staging/blogic.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37 #include <linux/leds.h>
38 #include <linux/gpio.h>
39 #include <linux/version.h>
40
41 #include "ar8216.h"
42
43 /* size of the vlan table */
44 #define AR8X16_MAX_VLANS 128
45 #define AR8X16_PROBE_RETRIES 10
46 #define AR8X16_MAX_PORTS 8
47
48 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
49
50 struct ar8xxx_priv;
51
52 #define AR8XXX_CAP_GIGE BIT(0)
53 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
54
55 #define AR8XXX_NUM_PHYS 5
56
57 static void ar8216_set_mirror_regs(struct ar8xxx_priv *priv);
58 static void ar8327_set_mirror_regs(struct ar8xxx_priv *priv);
59
60 enum {
61 AR8XXX_VER_AR8216 = 0x01,
62 AR8XXX_VER_AR8236 = 0x03,
63 AR8XXX_VER_AR8316 = 0x10,
64 AR8XXX_VER_AR8327 = 0x12,
65 AR8XXX_VER_AR8337 = 0x13,
66 };
67
68 struct ar8xxx_mib_desc {
69 unsigned int size;
70 unsigned int offset;
71 const char *name;
72 };
73
74 struct ar8xxx_chip {
75 unsigned long caps;
76 bool config_at_probe;
77
78 int (*hw_init)(struct ar8xxx_priv *priv);
79 void (*cleanup)(struct ar8xxx_priv *priv);
80
81 void (*init_globals)(struct ar8xxx_priv *priv);
82 void (*init_port)(struct ar8xxx_priv *priv, int port);
83 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
84 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
85 int (*atu_flush)(struct ar8xxx_priv *priv);
86 void (*vtu_flush)(struct ar8xxx_priv *priv);
87 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
88 void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
89 void (*set_mirror_regs)(struct ar8xxx_priv *priv);
90
91 const struct ar8xxx_mib_desc *mib_decs;
92 unsigned num_mibs;
93 unsigned mib_func;
94 };
95
96 enum ar8327_led_pattern {
97 AR8327_LED_PATTERN_OFF = 0,
98 AR8327_LED_PATTERN_BLINK,
99 AR8327_LED_PATTERN_ON,
100 AR8327_LED_PATTERN_RULE,
101 };
102
103 struct ar8327_led_entry {
104 unsigned reg;
105 unsigned shift;
106 };
107
108 struct ar8327_led {
109 struct led_classdev cdev;
110 struct ar8xxx_priv *sw_priv;
111
112 char *name;
113 bool active_low;
114 u8 led_num;
115 enum ar8327_led_mode mode;
116
117 struct mutex mutex;
118 spinlock_t lock;
119 struct work_struct led_work;
120 bool enable_hw_mode;
121 enum ar8327_led_pattern pattern;
122 };
123
124 struct ar8327_data {
125 u32 port0_status;
126 u32 port6_status;
127
128 struct ar8327_led **leds;
129 unsigned int num_leds;
130 };
131
132 struct ar8xxx_priv {
133 struct switch_dev dev;
134 struct mii_bus *mii_bus;
135 struct phy_device *phy;
136
137 u32 (*read)(struct ar8xxx_priv *priv, int reg);
138 void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
139 u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
140
141 int (*get_port_link)(unsigned port);
142
143 const struct net_device_ops *ndo_old;
144 struct net_device_ops ndo;
145 struct mutex reg_mutex;
146 u8 chip_ver;
147 u8 chip_rev;
148 const struct ar8xxx_chip *chip;
149 union {
150 struct ar8327_data ar8327;
151 } chip_data;
152 bool initialized;
153 bool port4_phy;
154 char buf[2048];
155
156 bool init;
157 bool mii_lo_first;
158
159 struct mutex mib_lock;
160 struct delayed_work mib_work;
161 int mib_next_port;
162 u64 *mib_stats;
163
164 struct list_head list;
165 unsigned int use_count;
166
167 /* all fields below are cleared on reset */
168 bool vlan;
169 u16 vlan_id[AR8X16_MAX_VLANS];
170 u8 vlan_table[AR8X16_MAX_VLANS];
171 u8 vlan_tagged;
172 u16 pvid[AR8X16_MAX_PORTS];
173
174 /* mirroring */
175 bool mirror_rx;
176 bool mirror_tx;
177 int source_port;
178 int monitor_port;
179 };
180
181 #define MIB_DESC(_s , _o, _n) \
182 { \
183 .size = (_s), \
184 .offset = (_o), \
185 .name = (_n), \
186 }
187
188 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
189 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
190 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
191 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
192 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
193 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
194 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
195 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
196 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
197 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
198 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
199 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
200 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
201 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
202 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
203 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
204 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
205 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
206 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
207 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
208 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
209 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
210 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
211 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
212 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
213 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
214 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
215 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
216 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
217 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
218 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
219 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
220 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
221 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
222 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
223 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
224 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
225 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
226 };
227
228 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
229 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
230 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
231 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
232 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
233 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
234 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
235 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
236 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
237 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
238 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
239 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
240 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
241 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
242 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
243 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
244 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
245 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
246 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
247 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
248 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
249 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
250 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
251 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
252 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
253 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
254 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
255 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
256 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
257 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
258 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
259 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
260 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
261 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
262 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
263 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
264 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
265 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
266 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
267 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
268 };
269
270 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
271 static LIST_HEAD(ar8xxx_dev_list);
272
273 static inline struct ar8xxx_priv *
274 swdev_to_ar8xxx(struct switch_dev *swdev)
275 {
276 return container_of(swdev, struct ar8xxx_priv, dev);
277 }
278
279 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
280 {
281 return priv->chip->caps & AR8XXX_CAP_GIGE;
282 }
283
284 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
285 {
286 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
287 }
288
289 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
290 {
291 return priv->chip_ver == AR8XXX_VER_AR8216;
292 }
293
294 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
295 {
296 return priv->chip_ver == AR8XXX_VER_AR8236;
297 }
298
299 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
300 {
301 return priv->chip_ver == AR8XXX_VER_AR8316;
302 }
303
304 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
305 {
306 return priv->chip_ver == AR8XXX_VER_AR8327;
307 }
308
309 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
310 {
311 return priv->chip_ver == AR8XXX_VER_AR8337;
312 }
313
314 static inline void
315 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
316 {
317 regaddr >>= 1;
318 *r1 = regaddr & 0x1e;
319
320 regaddr >>= 5;
321 *r2 = regaddr & 0x7;
322
323 regaddr >>= 3;
324 *page = regaddr & 0x1ff;
325 }
326
327 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
328 static int
329 ar8xxx_phy_poll_reset(struct mii_bus *bus)
330 {
331 unsigned int sleep_msecs = 20;
332 int ret, elapsed, i;
333
334 for (elapsed = sleep_msecs; elapsed <= 600;
335 elapsed += sleep_msecs) {
336 msleep(sleep_msecs);
337 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
338 ret = mdiobus_read(bus, i, MII_BMCR);
339 if (ret < 0)
340 return ret;
341 if (ret & BMCR_RESET)
342 break;
343 if (i == AR8XXX_NUM_PHYS - 1) {
344 usleep_range(1000, 2000);
345 return 0;
346 }
347 }
348 }
349 return -ETIMEDOUT;
350 }
351
352 static int
353 ar8xxx_phy_check_aneg(struct phy_device *phydev)
354 {
355 int ret;
356
357 if (phydev->autoneg != AUTONEG_ENABLE)
358 return 0;
359 /*
360 * BMCR_ANENABLE might have been cleared
361 * by phy_init_hw in certain kernel versions
362 * therefore check for it
363 */
364 ret = phy_read(phydev, MII_BMCR);
365 if (ret < 0)
366 return ret;
367 if (ret & BMCR_ANENABLE)
368 return 0;
369
370 dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
371 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
372 return phy_write(phydev, MII_BMCR, ret);
373 }
374
375 static void
376 ar8xxx_phy_init(struct ar8xxx_priv *priv)
377 {
378 int i;
379 struct mii_bus *bus;
380
381 bus = priv->mii_bus;
382 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
383 if (priv->chip->phy_fixup)
384 priv->chip->phy_fixup(priv, i);
385
386 /* initialize the port itself */
387 mdiobus_write(bus, i, MII_ADVERTISE,
388 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
389 if (ar8xxx_has_gige(priv))
390 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
391 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
392 }
393
394 ar8xxx_phy_poll_reset(bus);
395 }
396
397 static u32
398 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
399 {
400 struct mii_bus *bus = priv->mii_bus;
401 u16 r1, r2, page;
402 u16 lo, hi;
403
404 split_addr((u32) reg, &r1, &r2, &page);
405
406 mutex_lock(&bus->mdio_lock);
407
408 bus->write(bus, 0x18, 0, page);
409 usleep_range(1000, 2000); /* wait for the page switch to propagate */
410 lo = bus->read(bus, 0x10 | r2, r1);
411 hi = bus->read(bus, 0x10 | r2, r1 + 1);
412
413 mutex_unlock(&bus->mdio_lock);
414
415 return (hi << 16) | lo;
416 }
417
418 static void
419 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
420 {
421 struct mii_bus *bus = priv->mii_bus;
422 u16 r1, r2, r3;
423 u16 lo, hi;
424
425 split_addr((u32) reg, &r1, &r2, &r3);
426 lo = val & 0xffff;
427 hi = (u16) (val >> 16);
428
429 mutex_lock(&bus->mdio_lock);
430
431 bus->write(bus, 0x18, 0, r3);
432 usleep_range(1000, 2000); /* wait for the page switch to propagate */
433 if (priv->mii_lo_first) {
434 bus->write(bus, 0x10 | r2, r1, lo);
435 bus->write(bus, 0x10 | r2, r1 + 1, hi);
436 } else {
437 bus->write(bus, 0x10 | r2, r1 + 1, hi);
438 bus->write(bus, 0x10 | r2, r1, lo);
439 }
440
441 mutex_unlock(&bus->mdio_lock);
442 }
443
444 static u32
445 ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
446 {
447 struct mii_bus *bus = priv->mii_bus;
448 u16 r1, r2, page;
449 u16 lo, hi;
450 u32 ret;
451
452 split_addr((u32) reg, &r1, &r2, &page);
453
454 mutex_lock(&bus->mdio_lock);
455
456 bus->write(bus, 0x18, 0, page);
457 usleep_range(1000, 2000); /* wait for the page switch to propagate */
458
459 lo = bus->read(bus, 0x10 | r2, r1);
460 hi = bus->read(bus, 0x10 | r2, r1 + 1);
461
462 ret = hi << 16 | lo;
463 ret &= ~mask;
464 ret |= val;
465
466 lo = ret & 0xffff;
467 hi = (u16) (ret >> 16);
468
469 if (priv->mii_lo_first) {
470 bus->write(bus, 0x10 | r2, r1, lo);
471 bus->write(bus, 0x10 | r2, r1 + 1, hi);
472 } else {
473 bus->write(bus, 0x10 | r2, r1 + 1, hi);
474 bus->write(bus, 0x10 | r2, r1, lo);
475 }
476
477 mutex_unlock(&bus->mdio_lock);
478
479 return ret;
480 }
481
482
483 static void
484 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
485 u16 dbg_addr, u16 dbg_data)
486 {
487 struct mii_bus *bus = priv->mii_bus;
488
489 mutex_lock(&bus->mdio_lock);
490 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
491 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
492 mutex_unlock(&bus->mdio_lock);
493 }
494
495 static void
496 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
497 {
498 struct mii_bus *bus = priv->mii_bus;
499
500 mutex_lock(&bus->mdio_lock);
501 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
502 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
503 mutex_unlock(&bus->mdio_lock);
504 }
505
506 static inline u32
507 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
508 {
509 return priv->rmw(priv, reg, mask, val);
510 }
511
512 static inline void
513 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
514 {
515 priv->rmw(priv, reg, 0, val);
516 }
517
518 static int
519 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
520 unsigned timeout)
521 {
522 int i;
523
524 for (i = 0; i < timeout; i++) {
525 u32 t;
526
527 t = priv->read(priv, reg);
528 if ((t & mask) == val)
529 return 0;
530
531 usleep_range(1000, 2000);
532 }
533
534 return -ETIMEDOUT;
535 }
536
537 static int
538 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
539 {
540 unsigned mib_func = priv->chip->mib_func;
541 int ret;
542
543 lockdep_assert_held(&priv->mib_lock);
544
545 /* Capture the hardware statistics for all ports */
546 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
547
548 /* Wait for the capturing to complete. */
549 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
550 if (ret)
551 goto out;
552
553 ret = 0;
554
555 out:
556 return ret;
557 }
558
559 static int
560 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
561 {
562 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
563 }
564
565 static int
566 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
567 {
568 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
569 }
570
571 static void
572 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
573 {
574 unsigned int base;
575 u64 *mib_stats;
576 int i;
577
578 WARN_ON(port >= priv->dev.ports);
579
580 lockdep_assert_held(&priv->mib_lock);
581
582 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
583 base = AR8327_REG_PORT_STATS_BASE(port);
584 else if (chip_is_ar8236(priv) ||
585 chip_is_ar8316(priv))
586 base = AR8236_REG_PORT_STATS_BASE(port);
587 else
588 base = AR8216_REG_PORT_STATS_BASE(port);
589
590 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
591 for (i = 0; i < priv->chip->num_mibs; i++) {
592 const struct ar8xxx_mib_desc *mib;
593 u64 t;
594
595 mib = &priv->chip->mib_decs[i];
596 t = priv->read(priv, base + mib->offset);
597 if (mib->size == 2) {
598 u64 hi;
599
600 hi = priv->read(priv, base + mib->offset + 4);
601 t |= hi << 32;
602 }
603
604 if (flush)
605 mib_stats[i] = 0;
606 else
607 mib_stats[i] += t;
608 }
609 }
610
611 static void
612 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
613 struct switch_port_link *link)
614 {
615 u32 status;
616 u32 speed;
617
618 memset(link, '\0', sizeof(*link));
619
620 status = priv->chip->read_port_status(priv, port);
621
622 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
623 if (link->aneg) {
624 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
625 } else {
626 link->link = true;
627
628 if (priv->get_port_link) {
629 int err;
630
631 err = priv->get_port_link(port);
632 if (err >= 0)
633 link->link = !!err;
634 }
635 }
636
637 if (!link->link)
638 return;
639
640 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
641 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
642 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
643
644 speed = (status & AR8216_PORT_STATUS_SPEED) >>
645 AR8216_PORT_STATUS_SPEED_S;
646
647 switch (speed) {
648 case AR8216_PORT_SPEED_10M:
649 link->speed = SWITCH_PORT_SPEED_10;
650 break;
651 case AR8216_PORT_SPEED_100M:
652 link->speed = SWITCH_PORT_SPEED_100;
653 break;
654 case AR8216_PORT_SPEED_1000M:
655 link->speed = SWITCH_PORT_SPEED_1000;
656 break;
657 default:
658 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
659 break;
660 }
661 }
662
663 static struct sk_buff *
664 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
665 {
666 struct ar8xxx_priv *priv = dev->phy_ptr;
667 unsigned char *buf;
668
669 if (unlikely(!priv))
670 goto error;
671
672 if (!priv->vlan)
673 goto send;
674
675 if (unlikely(skb_headroom(skb) < 2)) {
676 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
677 goto error;
678 }
679
680 buf = skb_push(skb, 2);
681 buf[0] = 0x10;
682 buf[1] = 0x80;
683
684 send:
685 return skb;
686
687 error:
688 dev_kfree_skb_any(skb);
689 return NULL;
690 }
691
692 static void
693 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
694 {
695 struct ar8xxx_priv *priv;
696 unsigned char *buf;
697 int port, vlan;
698
699 priv = dev->phy_ptr;
700 if (!priv)
701 return;
702
703 /* don't strip the header if vlan mode is disabled */
704 if (!priv->vlan)
705 return;
706
707 /* strip header, get vlan id */
708 buf = skb->data;
709 skb_pull(skb, 2);
710
711 /* check for vlan header presence */
712 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
713 return;
714
715 port = buf[0] & 0xf;
716
717 /* no need to fix up packets coming from a tagged source */
718 if (priv->vlan_tagged & (1 << port))
719 return;
720
721 /* lookup port vid from local table, the switch passes an invalid vlan id */
722 vlan = priv->vlan_id[priv->pvid[port]];
723
724 buf[14 + 2] &= 0xf0;
725 buf[14 + 2] |= vlan >> 8;
726 buf[15 + 2] = vlan & 0xff;
727 }
728
729 static int
730 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
731 {
732 int timeout = 20;
733 u32 t = 0;
734
735 while (1) {
736 t = priv->read(priv, reg);
737 if ((t & mask) == val)
738 return 0;
739
740 if (timeout-- <= 0)
741 break;
742
743 udelay(10);
744 }
745
746 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
747 (unsigned int) reg, t, mask, val);
748 return -ETIMEDOUT;
749 }
750
751 static void
752 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
753 {
754 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
755 return;
756 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
757 val &= AR8216_VTUDATA_MEMBER;
758 val |= AR8216_VTUDATA_VALID;
759 priv->write(priv, AR8216_REG_VTU_DATA, val);
760 }
761 op |= AR8216_VTU_ACTIVE;
762 priv->write(priv, AR8216_REG_VTU, op);
763 }
764
765 static void
766 ar8216_vtu_flush(struct ar8xxx_priv *priv)
767 {
768 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
769 }
770
771 static void
772 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
773 {
774 u32 op;
775
776 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
777 ar8216_vtu_op(priv, op, port_mask);
778 }
779
780 static int
781 ar8216_atu_flush(struct ar8xxx_priv *priv)
782 {
783 int ret;
784
785 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
786 if (!ret)
787 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
788
789 return ret;
790 }
791
792 static u32
793 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
794 {
795 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
796 }
797
798 static void
799 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
800 {
801 u32 header;
802 u32 egress, ingress;
803 u32 pvid;
804
805 if (priv->vlan) {
806 pvid = priv->vlan_id[priv->pvid[port]];
807 if (priv->vlan_tagged & (1 << port))
808 egress = AR8216_OUT_ADD_VLAN;
809 else
810 egress = AR8216_OUT_STRIP_VLAN;
811 ingress = AR8216_IN_SECURE;
812 } else {
813 pvid = port;
814 egress = AR8216_OUT_KEEP;
815 ingress = AR8216_IN_PORT_ONLY;
816 }
817
818 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
819 header = AR8216_PORT_CTRL_HEADER;
820 else
821 header = 0;
822
823 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
824 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
825 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
826 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
827 AR8216_PORT_CTRL_LEARN | header |
828 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
829 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
830
831 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
832 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
833 AR8216_PORT_VLAN_DEFAULT_ID,
834 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
835 (ingress << AR8216_PORT_VLAN_MODE_S) |
836 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
837 }
838
839 static int
840 ar8216_hw_init(struct ar8xxx_priv *priv)
841 {
842 if (priv->initialized)
843 return 0;
844
845 ar8xxx_phy_init(priv);
846
847 priv->initialized = true;
848 return 0;
849 }
850
851 static void
852 ar8216_init_globals(struct ar8xxx_priv *priv)
853 {
854 /* standard atheros magic */
855 priv->write(priv, 0x38, 0xc000050e);
856
857 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
858 AR8216_GCTRL_MTU, 1518 + 8 + 2);
859 }
860
861 static void
862 ar8216_init_port(struct ar8xxx_priv *priv, int port)
863 {
864 /* Enable port learning and tx */
865 priv->write(priv, AR8216_REG_PORT_CTRL(port),
866 AR8216_PORT_CTRL_LEARN |
867 (4 << AR8216_PORT_CTRL_STATE_S));
868
869 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
870
871 if (port == AR8216_PORT_CPU) {
872 priv->write(priv, AR8216_REG_PORT_STATUS(port),
873 AR8216_PORT_STATUS_LINK_UP |
874 (ar8xxx_has_gige(priv) ?
875 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
876 AR8216_PORT_STATUS_TXMAC |
877 AR8216_PORT_STATUS_RXMAC |
878 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
879 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
880 AR8216_PORT_STATUS_DUPLEX);
881 } else {
882 priv->write(priv, AR8216_REG_PORT_STATUS(port),
883 AR8216_PORT_STATUS_LINK_AUTO);
884 }
885 }
886
887 static const struct ar8xxx_chip ar8216_chip = {
888 .caps = AR8XXX_CAP_MIB_COUNTERS,
889
890 .hw_init = ar8216_hw_init,
891 .init_globals = ar8216_init_globals,
892 .init_port = ar8216_init_port,
893 .setup_port = ar8216_setup_port,
894 .read_port_status = ar8216_read_port_status,
895 .atu_flush = ar8216_atu_flush,
896 .vtu_flush = ar8216_vtu_flush,
897 .vtu_load_vlan = ar8216_vtu_load_vlan,
898 .set_mirror_regs = ar8216_set_mirror_regs,
899
900 .num_mibs = ARRAY_SIZE(ar8216_mibs),
901 .mib_decs = ar8216_mibs,
902 .mib_func = AR8216_REG_MIB_FUNC
903 };
904
905 static void
906 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
907 {
908 u32 egress, ingress;
909 u32 pvid;
910
911 if (priv->vlan) {
912 pvid = priv->vlan_id[priv->pvid[port]];
913 if (priv->vlan_tagged & (1 << port))
914 egress = AR8216_OUT_ADD_VLAN;
915 else
916 egress = AR8216_OUT_STRIP_VLAN;
917 ingress = AR8216_IN_SECURE;
918 } else {
919 pvid = port;
920 egress = AR8216_OUT_KEEP;
921 ingress = AR8216_IN_PORT_ONLY;
922 }
923
924 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
925 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
926 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
927 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
928 AR8216_PORT_CTRL_LEARN |
929 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
930 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
931
932 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
933 AR8236_PORT_VLAN_DEFAULT_ID,
934 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
935
936 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
937 AR8236_PORT_VLAN2_VLAN_MODE |
938 AR8236_PORT_VLAN2_MEMBER,
939 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
940 (members << AR8236_PORT_VLAN2_MEMBER_S));
941 }
942
943 static void
944 ar8236_init_globals(struct ar8xxx_priv *priv)
945 {
946 /* enable jumbo frames */
947 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
948 AR8316_GCTRL_MTU, 9018 + 8 + 2);
949
950 /* Enable MIB counters */
951 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
952 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
953 AR8236_MIB_EN);
954 }
955
956 static const struct ar8xxx_chip ar8236_chip = {
957 .caps = AR8XXX_CAP_MIB_COUNTERS,
958 .hw_init = ar8216_hw_init,
959 .init_globals = ar8236_init_globals,
960 .init_port = ar8216_init_port,
961 .setup_port = ar8236_setup_port,
962 .read_port_status = ar8216_read_port_status,
963 .atu_flush = ar8216_atu_flush,
964 .vtu_flush = ar8216_vtu_flush,
965 .vtu_load_vlan = ar8216_vtu_load_vlan,
966 .set_mirror_regs = ar8216_set_mirror_regs,
967
968 .num_mibs = ARRAY_SIZE(ar8236_mibs),
969 .mib_decs = ar8236_mibs,
970 .mib_func = AR8216_REG_MIB_FUNC
971 };
972
973 static int
974 ar8316_hw_init(struct ar8xxx_priv *priv)
975 {
976 u32 val, newval;
977
978 val = priv->read(priv, AR8316_REG_POSTRIP);
979
980 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
981 if (priv->port4_phy) {
982 /* value taken from Ubiquiti RouterStation Pro */
983 newval = 0x81461bea;
984 pr_info("ar8316: Using port 4 as PHY\n");
985 } else {
986 newval = 0x01261be2;
987 pr_info("ar8316: Using port 4 as switch port\n");
988 }
989 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
990 /* value taken from AVM Fritz!Box 7390 sources */
991 newval = 0x010e5b71;
992 } else {
993 /* no known value for phy interface */
994 pr_err("ar8316: unsupported mii mode: %d.\n",
995 priv->phy->interface);
996 return -EINVAL;
997 }
998
999 if (val == newval)
1000 goto out;
1001
1002 priv->write(priv, AR8316_REG_POSTRIP, newval);
1003
1004 if (priv->port4_phy &&
1005 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1006 /* work around for phy4 rgmii mode */
1007 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
1008 /* rx delay */
1009 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
1010 /* tx delay */
1011 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
1012 msleep(1000);
1013 }
1014
1015 ar8xxx_phy_init(priv);
1016
1017 out:
1018 priv->initialized = true;
1019 return 0;
1020 }
1021
1022 static void
1023 ar8316_init_globals(struct ar8xxx_priv *priv)
1024 {
1025 /* standard atheros magic */
1026 priv->write(priv, 0x38, 0xc000050e);
1027
1028 /* enable cpu port to receive multicast and broadcast frames */
1029 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1030
1031 /* enable jumbo frames */
1032 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1033 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1034
1035 /* Enable MIB counters */
1036 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1037 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1038 AR8236_MIB_EN);
1039 }
1040
1041 static const struct ar8xxx_chip ar8316_chip = {
1042 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1043 .hw_init = ar8316_hw_init,
1044 .init_globals = ar8316_init_globals,
1045 .init_port = ar8216_init_port,
1046 .setup_port = ar8216_setup_port,
1047 .read_port_status = ar8216_read_port_status,
1048 .atu_flush = ar8216_atu_flush,
1049 .vtu_flush = ar8216_vtu_flush,
1050 .vtu_load_vlan = ar8216_vtu_load_vlan,
1051 .set_mirror_regs = ar8216_set_mirror_regs,
1052
1053 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1054 .mib_decs = ar8236_mibs,
1055 .mib_func = AR8216_REG_MIB_FUNC
1056 };
1057
1058 static u32
1059 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
1060 {
1061 u32 t;
1062
1063 if (!cfg)
1064 return 0;
1065
1066 t = 0;
1067 switch (cfg->mode) {
1068 case AR8327_PAD_NC:
1069 break;
1070
1071 case AR8327_PAD_MAC2MAC_MII:
1072 t = AR8327_PAD_MAC_MII_EN;
1073 if (cfg->rxclk_sel)
1074 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
1075 if (cfg->txclk_sel)
1076 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
1077 break;
1078
1079 case AR8327_PAD_MAC2MAC_GMII:
1080 t = AR8327_PAD_MAC_GMII_EN;
1081 if (cfg->rxclk_sel)
1082 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
1083 if (cfg->txclk_sel)
1084 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
1085 break;
1086
1087 case AR8327_PAD_MAC_SGMII:
1088 t = AR8327_PAD_SGMII_EN;
1089
1090 /*
1091 * WAR for the QUalcomm Atheros AP136 board.
1092 * It seems that RGMII TX/RX delay settings needs to be
1093 * applied for SGMII mode as well, The ethernet is not
1094 * reliable without this.
1095 */
1096 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1097 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1098 if (cfg->rxclk_delay_en)
1099 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1100 if (cfg->txclk_delay_en)
1101 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1102
1103 if (cfg->sgmii_delay_en)
1104 t |= AR8327_PAD_SGMII_DELAY_EN;
1105
1106 break;
1107
1108 case AR8327_PAD_MAC2PHY_MII:
1109 t = AR8327_PAD_PHY_MII_EN;
1110 if (cfg->rxclk_sel)
1111 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
1112 if (cfg->txclk_sel)
1113 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
1114 break;
1115
1116 case AR8327_PAD_MAC2PHY_GMII:
1117 t = AR8327_PAD_PHY_GMII_EN;
1118 if (cfg->pipe_rxclk_sel)
1119 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1120 if (cfg->rxclk_sel)
1121 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1122 if (cfg->txclk_sel)
1123 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1124 break;
1125
1126 case AR8327_PAD_MAC_RGMII:
1127 t = AR8327_PAD_RGMII_EN;
1128 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1129 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1130 if (cfg->rxclk_delay_en)
1131 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1132 if (cfg->txclk_delay_en)
1133 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1134 break;
1135
1136 case AR8327_PAD_PHY_GMII:
1137 t = AR8327_PAD_PHYX_GMII_EN;
1138 break;
1139
1140 case AR8327_PAD_PHY_RGMII:
1141 t = AR8327_PAD_PHYX_RGMII_EN;
1142 break;
1143
1144 case AR8327_PAD_PHY_MII:
1145 t = AR8327_PAD_PHYX_MII_EN;
1146 break;
1147 }
1148
1149 return t;
1150 }
1151
1152 static void
1153 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1154 {
1155 switch (priv->chip_rev) {
1156 case 1:
1157 /* For 100M waveform */
1158 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1159 /* Turn on Gigabit clock */
1160 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1161 break;
1162
1163 case 2:
1164 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1165 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1166 /* fallthrough */
1167 case 4:
1168 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1169 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1170
1171 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1172 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1173 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1174 break;
1175 }
1176 }
1177
1178 static u32
1179 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1180 {
1181 u32 t;
1182
1183 if (!cfg->force_link)
1184 return AR8216_PORT_STATUS_LINK_AUTO;
1185
1186 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1187 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1188 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1189 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1190
1191 switch (cfg->speed) {
1192 case AR8327_PORT_SPEED_10:
1193 t |= AR8216_PORT_SPEED_10M;
1194 break;
1195 case AR8327_PORT_SPEED_100:
1196 t |= AR8216_PORT_SPEED_100M;
1197 break;
1198 case AR8327_PORT_SPEED_1000:
1199 t |= AR8216_PORT_SPEED_1000M;
1200 break;
1201 }
1202
1203 return t;
1204 }
1205
1206 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1207 [_num] = { .reg = (_reg), .shift = (_shift) }
1208
1209 static const struct ar8327_led_entry
1210 ar8327_led_map[AR8327_NUM_LEDS] = {
1211 AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
1212 AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
1213 AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
1214
1215 AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
1216 AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
1217 AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
1218
1219 AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
1220 AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
1221 AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
1222
1223 AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1224 AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1225 AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1226
1227 AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1228 AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1229 AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1230 };
1231
1232 static void
1233 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1234 enum ar8327_led_pattern pattern)
1235 {
1236 const struct ar8327_led_entry *entry;
1237
1238 entry = &ar8327_led_map[led_num];
1239 ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1240 (3 << entry->shift), pattern << entry->shift);
1241 }
1242
1243 static void
1244 ar8327_led_work_func(struct work_struct *work)
1245 {
1246 struct ar8327_led *aled;
1247 u8 pattern;
1248
1249 aled = container_of(work, struct ar8327_led, led_work);
1250
1251 spin_lock(&aled->lock);
1252 pattern = aled->pattern;
1253 spin_unlock(&aled->lock);
1254
1255 ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1256 pattern);
1257 }
1258
1259 static void
1260 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1261 {
1262 if (aled->pattern == pattern)
1263 return;
1264
1265 aled->pattern = pattern;
1266 schedule_work(&aled->led_work);
1267 }
1268
1269 static inline struct ar8327_led *
1270 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1271 {
1272 return container_of(led_cdev, struct ar8327_led, cdev);
1273 }
1274
1275 static int
1276 ar8327_led_blink_set(struct led_classdev *led_cdev,
1277 unsigned long *delay_on,
1278 unsigned long *delay_off)
1279 {
1280 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1281
1282 if (*delay_on == 0 && *delay_off == 0) {
1283 *delay_on = 125;
1284 *delay_off = 125;
1285 }
1286
1287 if (*delay_on != 125 || *delay_off != 125) {
1288 /*
1289 * The hardware only supports blinking at 4Hz. Fall back
1290 * to software implementation in other cases.
1291 */
1292 return -EINVAL;
1293 }
1294
1295 spin_lock(&aled->lock);
1296
1297 aled->enable_hw_mode = false;
1298 ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1299
1300 spin_unlock(&aled->lock);
1301
1302 return 0;
1303 }
1304
1305 static void
1306 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1307 enum led_brightness brightness)
1308 {
1309 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1310 u8 pattern;
1311 bool active;
1312
1313 active = (brightness != LED_OFF);
1314 active ^= aled->active_low;
1315
1316 pattern = (active) ? AR8327_LED_PATTERN_ON :
1317 AR8327_LED_PATTERN_OFF;
1318
1319 spin_lock(&aled->lock);
1320
1321 aled->enable_hw_mode = false;
1322 ar8327_led_schedule_change(aled, pattern);
1323
1324 spin_unlock(&aled->lock);
1325 }
1326
1327 static ssize_t
1328 ar8327_led_enable_hw_mode_show(struct device *dev,
1329 struct device_attribute *attr,
1330 char *buf)
1331 {
1332 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1333 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1334 ssize_t ret = 0;
1335
1336 spin_lock(&aled->lock);
1337 ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1338 spin_unlock(&aled->lock);
1339
1340 return ret;
1341 }
1342
1343 static ssize_t
1344 ar8327_led_enable_hw_mode_store(struct device *dev,
1345 struct device_attribute *attr,
1346 const char *buf,
1347 size_t size)
1348 {
1349 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1350 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1351 u8 pattern;
1352 u8 value;
1353 int ret;
1354
1355 ret = kstrtou8(buf, 10, &value);
1356 if (ret < 0)
1357 return -EINVAL;
1358
1359 spin_lock(&aled->lock);
1360
1361 aled->enable_hw_mode = !!value;
1362 if (aled->enable_hw_mode)
1363 pattern = AR8327_LED_PATTERN_RULE;
1364 else
1365 pattern = AR8327_LED_PATTERN_OFF;
1366
1367 ar8327_led_schedule_change(aled, pattern);
1368
1369 spin_unlock(&aled->lock);
1370
1371 return size;
1372 }
1373
1374 static DEVICE_ATTR(enable_hw_mode, S_IRUGO | S_IWUSR,
1375 ar8327_led_enable_hw_mode_show,
1376 ar8327_led_enable_hw_mode_store);
1377
1378 static int
1379 ar8327_led_register(struct ar8xxx_priv *priv, struct ar8327_led *aled)
1380 {
1381 int ret;
1382
1383 ret = led_classdev_register(NULL, &aled->cdev);
1384 if (ret < 0)
1385 return ret;
1386
1387 if (aled->mode == AR8327_LED_MODE_HW) {
1388 ret = device_create_file(aled->cdev.dev,
1389 &dev_attr_enable_hw_mode);
1390 if (ret)
1391 goto err_unregister;
1392 }
1393
1394 return 0;
1395
1396 err_unregister:
1397 led_classdev_unregister(&aled->cdev);
1398 return ret;
1399 }
1400
1401 static void
1402 ar8327_led_unregister(struct ar8327_led *aled)
1403 {
1404 if (aled->mode == AR8327_LED_MODE_HW)
1405 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1406
1407 led_classdev_unregister(&aled->cdev);
1408 cancel_work_sync(&aled->led_work);
1409 }
1410
1411 static int
1412 ar8327_led_create(struct ar8xxx_priv *priv,
1413 const struct ar8327_led_info *led_info)
1414 {
1415 struct ar8327_data *data = &priv->chip_data.ar8327;
1416 struct ar8327_led *aled;
1417 int ret;
1418
1419 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1420 return 0;
1421
1422 if (!led_info->name)
1423 return -EINVAL;
1424
1425 if (led_info->led_num >= AR8327_NUM_LEDS)
1426 return -EINVAL;
1427
1428 aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1429 GFP_KERNEL);
1430 if (!aled)
1431 return -ENOMEM;
1432
1433 aled->sw_priv = priv;
1434 aled->led_num = led_info->led_num;
1435 aled->active_low = led_info->active_low;
1436 aled->mode = led_info->mode;
1437
1438 if (aled->mode == AR8327_LED_MODE_HW)
1439 aled->enable_hw_mode = true;
1440
1441 aled->name = (char *)(aled + 1);
1442 strcpy(aled->name, led_info->name);
1443
1444 aled->cdev.name = aled->name;
1445 aled->cdev.brightness_set = ar8327_led_set_brightness;
1446 aled->cdev.blink_set = ar8327_led_blink_set;
1447 aled->cdev.default_trigger = led_info->default_trigger;
1448
1449 spin_lock_init(&aled->lock);
1450 mutex_init(&aled->mutex);
1451 INIT_WORK(&aled->led_work, ar8327_led_work_func);
1452
1453 ret = ar8327_led_register(priv, aled);
1454 if (ret)
1455 goto err_free;
1456
1457 data->leds[data->num_leds++] = aled;
1458
1459 return 0;
1460
1461 err_free:
1462 kfree(aled);
1463 return ret;
1464 }
1465
1466 static void
1467 ar8327_led_destroy(struct ar8327_led *aled)
1468 {
1469 ar8327_led_unregister(aled);
1470 kfree(aled);
1471 }
1472
1473 static void
1474 ar8327_leds_init(struct ar8xxx_priv *priv)
1475 {
1476 struct ar8327_data *data;
1477 unsigned i;
1478
1479 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1480 return;
1481
1482 data = &priv->chip_data.ar8327;
1483
1484 for (i = 0; i < data->num_leds; i++) {
1485 struct ar8327_led *aled;
1486
1487 aled = data->leds[i];
1488
1489 if (aled->enable_hw_mode)
1490 aled->pattern = AR8327_LED_PATTERN_RULE;
1491 else
1492 aled->pattern = AR8327_LED_PATTERN_OFF;
1493
1494 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1495 }
1496 }
1497
1498 static void
1499 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1500 {
1501 struct ar8327_data *data = &priv->chip_data.ar8327;
1502 unsigned i;
1503
1504 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1505 return;
1506
1507 for (i = 0; i < data->num_leds; i++) {
1508 struct ar8327_led *aled;
1509
1510 aled = data->leds[i];
1511 ar8327_led_destroy(aled);
1512 }
1513
1514 kfree(data->leds);
1515 }
1516
1517 static int
1518 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1519 struct ar8327_platform_data *pdata)
1520 {
1521 struct ar8327_led_cfg *led_cfg;
1522 struct ar8327_data *data;
1523 u32 pos, new_pos;
1524 u32 t;
1525
1526 if (!pdata)
1527 return -EINVAL;
1528
1529 priv->get_port_link = pdata->get_port_link;
1530
1531 data = &priv->chip_data.ar8327;
1532
1533 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1534 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1535
1536 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1537 if (chip_is_ar8337(priv))
1538 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1539
1540 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1541 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1542 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1543 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1544 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1545
1546 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1547 new_pos = pos;
1548
1549 led_cfg = pdata->led_cfg;
1550 if (led_cfg) {
1551 if (led_cfg->open_drain)
1552 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1553 else
1554 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1555
1556 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1557 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1558 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1559 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1560
1561 if (new_pos != pos)
1562 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1563 }
1564
1565 if (pdata->sgmii_cfg) {
1566 t = pdata->sgmii_cfg->sgmii_ctrl;
1567 if (priv->chip_rev == 1)
1568 t |= AR8327_SGMII_CTRL_EN_PLL |
1569 AR8327_SGMII_CTRL_EN_RX |
1570 AR8327_SGMII_CTRL_EN_TX;
1571 else
1572 t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1573 AR8327_SGMII_CTRL_EN_RX |
1574 AR8327_SGMII_CTRL_EN_TX);
1575
1576 priv->write(priv, AR8327_REG_SGMII_CTRL, t);
1577
1578 if (pdata->sgmii_cfg->serdes_aen)
1579 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1580 else
1581 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1582 }
1583
1584 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1585
1586 if (pdata->leds && pdata->num_leds) {
1587 int i;
1588
1589 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1590 GFP_KERNEL);
1591 if (!data->leds)
1592 return -ENOMEM;
1593
1594 for (i = 0; i < pdata->num_leds; i++)
1595 ar8327_led_create(priv, &pdata->leds[i]);
1596 }
1597
1598 return 0;
1599 }
1600
1601 #ifdef CONFIG_OF
1602 static int
1603 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1604 {
1605 const __be32 *paddr;
1606 int len;
1607 int i;
1608
1609 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1610 if (!paddr || len < (2 * sizeof(*paddr)))
1611 return -EINVAL;
1612
1613 len /= sizeof(*paddr);
1614
1615 for (i = 0; i < len - 1; i += 2) {
1616 u32 reg;
1617 u32 val;
1618
1619 reg = be32_to_cpup(paddr + i);
1620 val = be32_to_cpup(paddr + i + 1);
1621
1622 switch (reg) {
1623 case AR8327_REG_PORT_STATUS(0):
1624 priv->chip_data.ar8327.port0_status = val;
1625 break;
1626 case AR8327_REG_PORT_STATUS(6):
1627 priv->chip_data.ar8327.port6_status = val;
1628 break;
1629 default:
1630 priv->write(priv, reg, val);
1631 break;
1632 }
1633 }
1634
1635 return 0;
1636 }
1637 #else
1638 static inline int
1639 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1640 {
1641 return -EINVAL;
1642 }
1643 #endif
1644
1645 static int
1646 ar8327_hw_init(struct ar8xxx_priv *priv)
1647 {
1648 int ret;
1649
1650 if (priv->phy->dev.of_node)
1651 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1652 else
1653 ret = ar8327_hw_config_pdata(priv,
1654 priv->phy->dev.platform_data);
1655
1656 if (ret)
1657 return ret;
1658
1659 ar8327_leds_init(priv);
1660
1661 ar8xxx_phy_init(priv);
1662
1663 return 0;
1664 }
1665
1666 static void
1667 ar8327_cleanup(struct ar8xxx_priv *priv)
1668 {
1669 ar8327_leds_cleanup(priv);
1670 }
1671
1672 static void
1673 ar8327_init_globals(struct ar8xxx_priv *priv)
1674 {
1675 u32 t;
1676
1677 /* enable CPU port and disable mirror port */
1678 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1679 AR8327_FWD_CTRL0_MIRROR_PORT;
1680 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1681
1682 /* forward multicast and broadcast frames to CPU */
1683 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1684 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1685 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1686 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1687
1688 /* enable jumbo frames */
1689 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1690 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1691
1692 /* Enable MIB counters */
1693 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1694 AR8327_MODULE_EN_MIB);
1695
1696 /* Disable EEE on all ports due to stability issues */
1697 t = priv->read(priv, AR8327_REG_EEE_CTRL);
1698 t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1699 AR8327_EEE_CTRL_DISABLE_PHY(1) |
1700 AR8327_EEE_CTRL_DISABLE_PHY(2) |
1701 AR8327_EEE_CTRL_DISABLE_PHY(3) |
1702 AR8327_EEE_CTRL_DISABLE_PHY(4);
1703 priv->write(priv, AR8327_REG_EEE_CTRL, t);
1704 }
1705
1706 static void
1707 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1708 {
1709 u32 t;
1710
1711 if (port == AR8216_PORT_CPU)
1712 t = priv->chip_data.ar8327.port0_status;
1713 else if (port == 6)
1714 t = priv->chip_data.ar8327.port6_status;
1715 else
1716 t = AR8216_PORT_STATUS_LINK_AUTO;
1717
1718 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1719 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1720
1721 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1722 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1723 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1724
1725 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1726 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1727
1728 t = AR8327_PORT_LOOKUP_LEARN;
1729 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1730 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1731 }
1732
1733 static u32
1734 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1735 {
1736 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1737 }
1738
1739 static int
1740 ar8327_atu_flush(struct ar8xxx_priv *priv)
1741 {
1742 int ret;
1743
1744 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1745 AR8327_ATU_FUNC_BUSY, 0);
1746 if (!ret)
1747 priv->write(priv, AR8327_REG_ATU_FUNC,
1748 AR8327_ATU_FUNC_OP_FLUSH);
1749
1750 return ret;
1751 }
1752
1753 static void
1754 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1755 {
1756 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1757 AR8327_VTU_FUNC1_BUSY, 0))
1758 return;
1759
1760 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1761 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1762
1763 op |= AR8327_VTU_FUNC1_BUSY;
1764 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1765 }
1766
1767 static void
1768 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1769 {
1770 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1771 }
1772
1773 static void
1774 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1775 {
1776 u32 op;
1777 u32 val;
1778 int i;
1779
1780 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1781 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1782 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1783 u32 mode;
1784
1785 if ((port_mask & BIT(i)) == 0)
1786 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1787 else if (priv->vlan == 0)
1788 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1789 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
1790 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1791 else
1792 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1793
1794 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1795 }
1796 ar8327_vtu_op(priv, op, val);
1797 }
1798
1799 static void
1800 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1801 {
1802 u32 t;
1803 u32 egress, ingress;
1804 u32 pvid = priv->vlan_id[priv->pvid[port]];
1805
1806 if (priv->vlan) {
1807 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1808 ingress = AR8216_IN_SECURE;
1809 } else {
1810 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1811 ingress = AR8216_IN_PORT_ONLY;
1812 }
1813
1814 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1815 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1816 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1817
1818 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1819 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
1820 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1821
1822 t = members;
1823 t |= AR8327_PORT_LOOKUP_LEARN;
1824 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1825 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1826 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1827 }
1828
1829 static const struct ar8xxx_chip ar8327_chip = {
1830 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1831 .config_at_probe = true,
1832 .hw_init = ar8327_hw_init,
1833 .cleanup = ar8327_cleanup,
1834 .init_globals = ar8327_init_globals,
1835 .init_port = ar8327_init_port,
1836 .setup_port = ar8327_setup_port,
1837 .read_port_status = ar8327_read_port_status,
1838 .atu_flush = ar8327_atu_flush,
1839 .vtu_flush = ar8327_vtu_flush,
1840 .vtu_load_vlan = ar8327_vtu_load_vlan,
1841 .phy_fixup = ar8327_phy_fixup,
1842 .set_mirror_regs = ar8327_set_mirror_regs,
1843
1844 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1845 .mib_decs = ar8236_mibs,
1846 .mib_func = AR8327_REG_MIB_FUNC
1847 };
1848
1849 static int
1850 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1851 struct switch_val *val)
1852 {
1853 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1854 priv->vlan = !!val->value.i;
1855 return 0;
1856 }
1857
1858 static int
1859 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1860 struct switch_val *val)
1861 {
1862 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1863 val->value.i = priv->vlan;
1864 return 0;
1865 }
1866
1867
1868 static int
1869 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1870 {
1871 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1872
1873 /* make sure no invalid PVIDs get set */
1874
1875 if (vlan >= dev->vlans)
1876 return -EINVAL;
1877
1878 priv->pvid[port] = vlan;
1879 return 0;
1880 }
1881
1882 static int
1883 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1884 {
1885 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1886 *vlan = priv->pvid[port];
1887 return 0;
1888 }
1889
1890 static int
1891 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1892 struct switch_val *val)
1893 {
1894 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1895 priv->vlan_id[val->port_vlan] = val->value.i;
1896 return 0;
1897 }
1898
1899 static int
1900 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1901 struct switch_val *val)
1902 {
1903 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1904 val->value.i = priv->vlan_id[val->port_vlan];
1905 return 0;
1906 }
1907
1908 static int
1909 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1910 struct switch_port_link *link)
1911 {
1912 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1913
1914 ar8216_read_port_link(priv, port, link);
1915 return 0;
1916 }
1917
1918 static int
1919 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1920 {
1921 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1922 u8 ports = priv->vlan_table[val->port_vlan];
1923 int i;
1924
1925 val->len = 0;
1926 for (i = 0; i < dev->ports; i++) {
1927 struct switch_port *p;
1928
1929 if (!(ports & (1 << i)))
1930 continue;
1931
1932 p = &val->value.ports[val->len++];
1933 p->id = i;
1934 if (priv->vlan_tagged & (1 << i))
1935 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1936 else
1937 p->flags = 0;
1938 }
1939 return 0;
1940 }
1941
1942 static int
1943 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1944 {
1945 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1946 u8 ports = priv->vlan_table[val->port_vlan];
1947 int i;
1948
1949 val->len = 0;
1950 for (i = 0; i < dev->ports; i++) {
1951 struct switch_port *p;
1952
1953 if (!(ports & (1 << i)))
1954 continue;
1955
1956 p = &val->value.ports[val->len++];
1957 p->id = i;
1958 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
1959 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1960 else
1961 p->flags = 0;
1962 }
1963 return 0;
1964 }
1965
1966 static int
1967 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1968 {
1969 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1970 u8 *vt = &priv->vlan_table[val->port_vlan];
1971 int i, j;
1972
1973 *vt = 0;
1974 for (i = 0; i < val->len; i++) {
1975 struct switch_port *p = &val->value.ports[i];
1976
1977 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1978 priv->vlan_tagged |= (1 << p->id);
1979 } else {
1980 priv->vlan_tagged &= ~(1 << p->id);
1981 priv->pvid[p->id] = val->port_vlan;
1982
1983 /* make sure that an untagged port does not
1984 * appear in other vlans */
1985 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1986 if (j == val->port_vlan)
1987 continue;
1988 priv->vlan_table[j] &= ~(1 << p->id);
1989 }
1990 }
1991
1992 *vt |= 1 << p->id;
1993 }
1994 return 0;
1995 }
1996
1997 static int
1998 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1999 {
2000 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2001 u8 *vt = &priv->vlan_table[val->port_vlan];
2002 int i;
2003
2004 *vt = 0;
2005 for (i = 0; i < val->len; i++) {
2006 struct switch_port *p = &val->value.ports[i];
2007
2008 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
2009 if (val->port_vlan == priv->pvid[p->id]) {
2010 priv->vlan_tagged |= (1 << p->id);
2011 }
2012 } else {
2013 priv->vlan_tagged &= ~(1 << p->id);
2014 priv->pvid[p->id] = val->port_vlan;
2015 }
2016
2017 *vt |= 1 << p->id;
2018 }
2019 return 0;
2020 }
2021
2022 static void
2023 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
2024 {
2025 int port;
2026
2027 /* reset all mirror registers */
2028 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2029 AR8327_FWD_CTRL0_MIRROR_PORT,
2030 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2031 for (port = 0; port < AR8327_NUM_PORTS; port++) {
2032 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
2033 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2034 0);
2035
2036 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
2037 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2038 0);
2039 }
2040
2041 /* now enable mirroring if necessary */
2042 if (priv->source_port >= AR8327_NUM_PORTS ||
2043 priv->monitor_port >= AR8327_NUM_PORTS ||
2044 priv->source_port == priv->monitor_port) {
2045 return;
2046 }
2047
2048 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2049 AR8327_FWD_CTRL0_MIRROR_PORT,
2050 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2051
2052 if (priv->mirror_rx)
2053 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
2054 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2055 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
2056
2057 if (priv->mirror_tx)
2058 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
2059 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2060 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
2061 }
2062
2063 static void
2064 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
2065 {
2066 int port;
2067
2068 /* reset all mirror registers */
2069 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2070 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2071 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2072 for (port = 0; port < AR8216_NUM_PORTS; port++) {
2073 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2074 AR8216_PORT_CTRL_MIRROR_RX,
2075 0);
2076
2077 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2078 AR8216_PORT_CTRL_MIRROR_TX,
2079 0);
2080 }
2081
2082 /* now enable mirroring if necessary */
2083 if (priv->source_port >= AR8216_NUM_PORTS ||
2084 priv->monitor_port >= AR8216_NUM_PORTS ||
2085 priv->source_port == priv->monitor_port) {
2086 return;
2087 }
2088
2089 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2090 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2091 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2092
2093 if (priv->mirror_rx)
2094 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2095 AR8216_PORT_CTRL_MIRROR_RX,
2096 AR8216_PORT_CTRL_MIRROR_RX);
2097
2098 if (priv->mirror_tx)
2099 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2100 AR8216_PORT_CTRL_MIRROR_TX,
2101 AR8216_PORT_CTRL_MIRROR_TX);
2102 }
2103
2104 static int
2105 ar8xxx_sw_hw_apply(struct switch_dev *dev)
2106 {
2107 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2108 u8 portmask[AR8X16_MAX_PORTS];
2109 int i, j;
2110
2111 mutex_lock(&priv->reg_mutex);
2112 /* flush all vlan translation unit entries */
2113 priv->chip->vtu_flush(priv);
2114
2115 memset(portmask, 0, sizeof(portmask));
2116 if (!priv->init) {
2117 /* calculate the port destination masks and load vlans
2118 * into the vlan translation unit */
2119 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2120 u8 vp = priv->vlan_table[j];
2121
2122 if (!vp)
2123 continue;
2124
2125 for (i = 0; i < dev->ports; i++) {
2126 u8 mask = (1 << i);
2127 if (vp & mask)
2128 portmask[i] |= vp & ~mask;
2129 }
2130
2131 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
2132 priv->vlan_table[j]);
2133 }
2134 } else {
2135 /* vlan disabled:
2136 * isolate all ports, but connect them to the cpu port */
2137 for (i = 0; i < dev->ports; i++) {
2138 if (i == AR8216_PORT_CPU)
2139 continue;
2140
2141 portmask[i] = 1 << AR8216_PORT_CPU;
2142 portmask[AR8216_PORT_CPU] |= (1 << i);
2143 }
2144 }
2145
2146 /* update the port destination mask registers and tag settings */
2147 for (i = 0; i < dev->ports; i++) {
2148 priv->chip->setup_port(priv, i, portmask[i]);
2149 }
2150
2151 priv->chip->set_mirror_regs(priv);
2152
2153 mutex_unlock(&priv->reg_mutex);
2154 return 0;
2155 }
2156
2157 static int
2158 ar8xxx_sw_reset_switch(struct switch_dev *dev)
2159 {
2160 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2161 int i;
2162
2163 mutex_lock(&priv->reg_mutex);
2164 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
2165 offsetof(struct ar8xxx_priv, vlan));
2166
2167 for (i = 0; i < AR8X16_MAX_VLANS; i++)
2168 priv->vlan_id[i] = i;
2169
2170 /* Configure all ports */
2171 for (i = 0; i < dev->ports; i++)
2172 priv->chip->init_port(priv, i);
2173
2174 priv->mirror_rx = false;
2175 priv->mirror_tx = false;
2176 priv->source_port = 0;
2177 priv->monitor_port = 0;
2178
2179 priv->chip->init_globals(priv);
2180
2181 mutex_unlock(&priv->reg_mutex);
2182
2183 return ar8xxx_sw_hw_apply(dev);
2184 }
2185
2186 static int
2187 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
2188 const struct switch_attr *attr,
2189 struct switch_val *val)
2190 {
2191 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2192 unsigned int len;
2193 int ret;
2194
2195 if (!ar8xxx_has_mib_counters(priv))
2196 return -EOPNOTSUPP;
2197
2198 mutex_lock(&priv->mib_lock);
2199
2200 len = priv->dev.ports * priv->chip->num_mibs *
2201 sizeof(*priv->mib_stats);
2202 memset(priv->mib_stats, '\0', len);
2203 ret = ar8xxx_mib_flush(priv);
2204 if (ret)
2205 goto unlock;
2206
2207 ret = 0;
2208
2209 unlock:
2210 mutex_unlock(&priv->mib_lock);
2211 return ret;
2212 }
2213
2214 static int
2215 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
2216 const struct switch_attr *attr,
2217 struct switch_val *val)
2218 {
2219 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2220
2221 mutex_lock(&priv->reg_mutex);
2222 priv->mirror_rx = !!val->value.i;
2223 priv->chip->set_mirror_regs(priv);
2224 mutex_unlock(&priv->reg_mutex);
2225
2226 return 0;
2227 }
2228
2229 static int
2230 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
2231 const struct switch_attr *attr,
2232 struct switch_val *val)
2233 {
2234 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2235 val->value.i = priv->mirror_rx;
2236 return 0;
2237 }
2238
2239 static int
2240 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
2241 const struct switch_attr *attr,
2242 struct switch_val *val)
2243 {
2244 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2245
2246 mutex_lock(&priv->reg_mutex);
2247 priv->mirror_tx = !!val->value.i;
2248 priv->chip->set_mirror_regs(priv);
2249 mutex_unlock(&priv->reg_mutex);
2250
2251 return 0;
2252 }
2253
2254 static int
2255 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2256 const struct switch_attr *attr,
2257 struct switch_val *val)
2258 {
2259 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2260 val->value.i = priv->mirror_tx;
2261 return 0;
2262 }
2263
2264 static int
2265 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2266 const struct switch_attr *attr,
2267 struct switch_val *val)
2268 {
2269 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2270
2271 mutex_lock(&priv->reg_mutex);
2272 priv->monitor_port = val->value.i;
2273 priv->chip->set_mirror_regs(priv);
2274 mutex_unlock(&priv->reg_mutex);
2275
2276 return 0;
2277 }
2278
2279 static int
2280 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2281 const struct switch_attr *attr,
2282 struct switch_val *val)
2283 {
2284 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2285 val->value.i = priv->monitor_port;
2286 return 0;
2287 }
2288
2289 static int
2290 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2291 const struct switch_attr *attr,
2292 struct switch_val *val)
2293 {
2294 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2295
2296 mutex_lock(&priv->reg_mutex);
2297 priv->source_port = val->value.i;
2298 priv->chip->set_mirror_regs(priv);
2299 mutex_unlock(&priv->reg_mutex);
2300
2301 return 0;
2302 }
2303
2304 static int
2305 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2306 const struct switch_attr *attr,
2307 struct switch_val *val)
2308 {
2309 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2310 val->value.i = priv->source_port;
2311 return 0;
2312 }
2313
2314 static int
2315 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2316 const struct switch_attr *attr,
2317 struct switch_val *val)
2318 {
2319 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2320 int port;
2321 int ret;
2322
2323 if (!ar8xxx_has_mib_counters(priv))
2324 return -EOPNOTSUPP;
2325
2326 port = val->port_vlan;
2327 if (port >= dev->ports)
2328 return -EINVAL;
2329
2330 mutex_lock(&priv->mib_lock);
2331 ret = ar8xxx_mib_capture(priv);
2332 if (ret)
2333 goto unlock;
2334
2335 ar8xxx_mib_fetch_port_stat(priv, port, true);
2336
2337 ret = 0;
2338
2339 unlock:
2340 mutex_unlock(&priv->mib_lock);
2341 return ret;
2342 }
2343
2344 static int
2345 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2346 const struct switch_attr *attr,
2347 struct switch_val *val)
2348 {
2349 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2350 const struct ar8xxx_chip *chip = priv->chip;
2351 u64 *mib_stats;
2352 int port;
2353 int ret;
2354 char *buf = priv->buf;
2355 int i, len = 0;
2356
2357 if (!ar8xxx_has_mib_counters(priv))
2358 return -EOPNOTSUPP;
2359
2360 port = val->port_vlan;
2361 if (port >= dev->ports)
2362 return -EINVAL;
2363
2364 mutex_lock(&priv->mib_lock);
2365 ret = ar8xxx_mib_capture(priv);
2366 if (ret)
2367 goto unlock;
2368
2369 ar8xxx_mib_fetch_port_stat(priv, port, false);
2370
2371 len += snprintf(buf + len, sizeof(priv->buf) - len,
2372 "Port %d MIB counters\n",
2373 port);
2374
2375 mib_stats = &priv->mib_stats[port * chip->num_mibs];
2376 for (i = 0; i < chip->num_mibs; i++)
2377 len += snprintf(buf + len, sizeof(priv->buf) - len,
2378 "%-12s: %llu\n",
2379 chip->mib_decs[i].name,
2380 mib_stats[i]);
2381
2382 val->value.s = buf;
2383 val->len = len;
2384
2385 ret = 0;
2386
2387 unlock:
2388 mutex_unlock(&priv->mib_lock);
2389 return ret;
2390 }
2391
2392 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2393 {
2394 .type = SWITCH_TYPE_INT,
2395 .name = "enable_vlan",
2396 .description = "Enable VLAN mode",
2397 .set = ar8xxx_sw_set_vlan,
2398 .get = ar8xxx_sw_get_vlan,
2399 .max = 1
2400 },
2401 {
2402 .type = SWITCH_TYPE_NOVAL,
2403 .name = "reset_mibs",
2404 .description = "Reset all MIB counters",
2405 .set = ar8xxx_sw_set_reset_mibs,
2406 },
2407 {
2408 .type = SWITCH_TYPE_INT,
2409 .name = "enable_mirror_rx",
2410 .description = "Enable mirroring of RX packets",
2411 .set = ar8xxx_sw_set_mirror_rx_enable,
2412 .get = ar8xxx_sw_get_mirror_rx_enable,
2413 .max = 1
2414 },
2415 {
2416 .type = SWITCH_TYPE_INT,
2417 .name = "enable_mirror_tx",
2418 .description = "Enable mirroring of TX packets",
2419 .set = ar8xxx_sw_set_mirror_tx_enable,
2420 .get = ar8xxx_sw_get_mirror_tx_enable,
2421 .max = 1
2422 },
2423 {
2424 .type = SWITCH_TYPE_INT,
2425 .name = "mirror_monitor_port",
2426 .description = "Mirror monitor port",
2427 .set = ar8xxx_sw_set_mirror_monitor_port,
2428 .get = ar8xxx_sw_get_mirror_monitor_port,
2429 .max = AR8216_NUM_PORTS - 1
2430 },
2431 {
2432 .type = SWITCH_TYPE_INT,
2433 .name = "mirror_source_port",
2434 .description = "Mirror source port",
2435 .set = ar8xxx_sw_set_mirror_source_port,
2436 .get = ar8xxx_sw_get_mirror_source_port,
2437 .max = AR8216_NUM_PORTS - 1
2438 },
2439 };
2440
2441 static struct switch_attr ar8327_sw_attr_globals[] = {
2442 {
2443 .type = SWITCH_TYPE_INT,
2444 .name = "enable_vlan",
2445 .description = "Enable VLAN mode",
2446 .set = ar8xxx_sw_set_vlan,
2447 .get = ar8xxx_sw_get_vlan,
2448 .max = 1
2449 },
2450 {
2451 .type = SWITCH_TYPE_NOVAL,
2452 .name = "reset_mibs",
2453 .description = "Reset all MIB counters",
2454 .set = ar8xxx_sw_set_reset_mibs,
2455 },
2456 {
2457 .type = SWITCH_TYPE_INT,
2458 .name = "enable_mirror_rx",
2459 .description = "Enable mirroring of RX packets",
2460 .set = ar8xxx_sw_set_mirror_rx_enable,
2461 .get = ar8xxx_sw_get_mirror_rx_enable,
2462 .max = 1
2463 },
2464 {
2465 .type = SWITCH_TYPE_INT,
2466 .name = "enable_mirror_tx",
2467 .description = "Enable mirroring of TX packets",
2468 .set = ar8xxx_sw_set_mirror_tx_enable,
2469 .get = ar8xxx_sw_get_mirror_tx_enable,
2470 .max = 1
2471 },
2472 {
2473 .type = SWITCH_TYPE_INT,
2474 .name = "mirror_monitor_port",
2475 .description = "Mirror monitor port",
2476 .set = ar8xxx_sw_set_mirror_monitor_port,
2477 .get = ar8xxx_sw_get_mirror_monitor_port,
2478 .max = AR8327_NUM_PORTS - 1
2479 },
2480 {
2481 .type = SWITCH_TYPE_INT,
2482 .name = "mirror_source_port",
2483 .description = "Mirror source port",
2484 .set = ar8xxx_sw_set_mirror_source_port,
2485 .get = ar8xxx_sw_get_mirror_source_port,
2486 .max = AR8327_NUM_PORTS - 1
2487 },
2488 };
2489
2490 static struct switch_attr ar8xxx_sw_attr_port[] = {
2491 {
2492 .type = SWITCH_TYPE_NOVAL,
2493 .name = "reset_mib",
2494 .description = "Reset single port MIB counters",
2495 .set = ar8xxx_sw_set_port_reset_mib,
2496 },
2497 {
2498 .type = SWITCH_TYPE_STRING,
2499 .name = "mib",
2500 .description = "Get port's MIB counters",
2501 .set = NULL,
2502 .get = ar8xxx_sw_get_port_mib,
2503 },
2504 };
2505
2506 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2507 {
2508 .type = SWITCH_TYPE_INT,
2509 .name = "vid",
2510 .description = "VLAN ID (0-4094)",
2511 .set = ar8xxx_sw_set_vid,
2512 .get = ar8xxx_sw_get_vid,
2513 .max = 4094,
2514 },
2515 };
2516
2517 static const struct switch_dev_ops ar8xxx_sw_ops = {
2518 .attr_global = {
2519 .attr = ar8xxx_sw_attr_globals,
2520 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2521 },
2522 .attr_port = {
2523 .attr = ar8xxx_sw_attr_port,
2524 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2525 },
2526 .attr_vlan = {
2527 .attr = ar8xxx_sw_attr_vlan,
2528 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2529 },
2530 .get_port_pvid = ar8xxx_sw_get_pvid,
2531 .set_port_pvid = ar8xxx_sw_set_pvid,
2532 .get_vlan_ports = ar8xxx_sw_get_ports,
2533 .set_vlan_ports = ar8xxx_sw_set_ports,
2534 .apply_config = ar8xxx_sw_hw_apply,
2535 .reset_switch = ar8xxx_sw_reset_switch,
2536 .get_port_link = ar8xxx_sw_get_port_link,
2537 };
2538
2539 static const struct switch_dev_ops ar8327_sw_ops = {
2540 .attr_global = {
2541 .attr = ar8327_sw_attr_globals,
2542 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2543 },
2544 .attr_port = {
2545 .attr = ar8xxx_sw_attr_port,
2546 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2547 },
2548 .attr_vlan = {
2549 .attr = ar8xxx_sw_attr_vlan,
2550 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2551 },
2552 .get_port_pvid = ar8xxx_sw_get_pvid,
2553 .set_port_pvid = ar8xxx_sw_set_pvid,
2554 .get_vlan_ports = ar8327_sw_get_ports,
2555 .set_vlan_ports = ar8327_sw_set_ports,
2556 .apply_config = ar8xxx_sw_hw_apply,
2557 .reset_switch = ar8xxx_sw_reset_switch,
2558 .get_port_link = ar8xxx_sw_get_port_link,
2559 };
2560
2561 static int
2562 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2563 {
2564 u32 val;
2565 u16 id;
2566 int i;
2567
2568 val = priv->read(priv, AR8216_REG_CTRL);
2569 if (val == ~0)
2570 return -ENODEV;
2571
2572 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2573 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2574 u16 t;
2575
2576 val = priv->read(priv, AR8216_REG_CTRL);
2577 if (val == ~0)
2578 return -ENODEV;
2579
2580 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2581 if (t != id)
2582 return -ENODEV;
2583 }
2584
2585 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2586 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2587
2588 switch (priv->chip_ver) {
2589 case AR8XXX_VER_AR8216:
2590 priv->chip = &ar8216_chip;
2591 break;
2592 case AR8XXX_VER_AR8236:
2593 priv->chip = &ar8236_chip;
2594 break;
2595 case AR8XXX_VER_AR8316:
2596 priv->chip = &ar8316_chip;
2597 break;
2598 case AR8XXX_VER_AR8327:
2599 priv->mii_lo_first = true;
2600 priv->chip = &ar8327_chip;
2601 break;
2602 case AR8XXX_VER_AR8337:
2603 priv->mii_lo_first = true;
2604 priv->chip = &ar8327_chip;
2605 break;
2606 default:
2607 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2608 priv->chip_ver, priv->chip_rev);
2609
2610 return -ENODEV;
2611 }
2612
2613 return 0;
2614 }
2615
2616 static void
2617 ar8xxx_mib_work_func(struct work_struct *work)
2618 {
2619 struct ar8xxx_priv *priv;
2620 int err;
2621
2622 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2623
2624 mutex_lock(&priv->mib_lock);
2625
2626 err = ar8xxx_mib_capture(priv);
2627 if (err)
2628 goto next_port;
2629
2630 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2631
2632 next_port:
2633 priv->mib_next_port++;
2634 if (priv->mib_next_port >= priv->dev.ports)
2635 priv->mib_next_port = 0;
2636
2637 mutex_unlock(&priv->mib_lock);
2638 schedule_delayed_work(&priv->mib_work,
2639 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2640 }
2641
2642 static int
2643 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2644 {
2645 unsigned int len;
2646
2647 if (!ar8xxx_has_mib_counters(priv))
2648 return 0;
2649
2650 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2651
2652 len = priv->dev.ports * priv->chip->num_mibs *
2653 sizeof(*priv->mib_stats);
2654 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2655
2656 if (!priv->mib_stats)
2657 return -ENOMEM;
2658
2659 return 0;
2660 }
2661
2662 static void
2663 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2664 {
2665 if (!ar8xxx_has_mib_counters(priv))
2666 return;
2667
2668 schedule_delayed_work(&priv->mib_work,
2669 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2670 }
2671
2672 static void
2673 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2674 {
2675 if (!ar8xxx_has_mib_counters(priv))
2676 return;
2677
2678 cancel_delayed_work(&priv->mib_work);
2679 }
2680
2681 static struct ar8xxx_priv *
2682 ar8xxx_create(void)
2683 {
2684 struct ar8xxx_priv *priv;
2685
2686 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2687 if (priv == NULL)
2688 return NULL;
2689
2690 mutex_init(&priv->reg_mutex);
2691 mutex_init(&priv->mib_lock);
2692 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2693
2694 return priv;
2695 }
2696
2697 static void
2698 ar8xxx_free(struct ar8xxx_priv *priv)
2699 {
2700 if (priv->chip && priv->chip->cleanup)
2701 priv->chip->cleanup(priv);
2702
2703 kfree(priv->mib_stats);
2704 kfree(priv);
2705 }
2706
2707 static struct ar8xxx_priv *
2708 ar8xxx_create_mii(struct mii_bus *bus)
2709 {
2710 struct ar8xxx_priv *priv;
2711
2712 priv = ar8xxx_create();
2713 if (priv) {
2714 priv->mii_bus = bus;
2715 priv->read = ar8xxx_mii_read;
2716 priv->write = ar8xxx_mii_write;
2717 priv->rmw = ar8xxx_mii_rmw;
2718 }
2719
2720 return priv;
2721 }
2722
2723 static int
2724 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2725 {
2726 struct switch_dev *swdev;
2727 int ret;
2728
2729 ret = ar8xxx_id_chip(priv);
2730 if (ret)
2731 return ret;
2732
2733 swdev = &priv->dev;
2734 swdev->cpu_port = AR8216_PORT_CPU;
2735 swdev->ops = &ar8xxx_sw_ops;
2736
2737 if (chip_is_ar8316(priv)) {
2738 swdev->name = "Atheros AR8316";
2739 swdev->vlans = AR8X16_MAX_VLANS;
2740 swdev->ports = AR8216_NUM_PORTS;
2741 } else if (chip_is_ar8236(priv)) {
2742 swdev->name = "Atheros AR8236";
2743 swdev->vlans = AR8216_NUM_VLANS;
2744 swdev->ports = AR8216_NUM_PORTS;
2745 } else if (chip_is_ar8327(priv)) {
2746 swdev->name = "Atheros AR8327";
2747 swdev->vlans = AR8X16_MAX_VLANS;
2748 swdev->ports = AR8327_NUM_PORTS;
2749 swdev->ops = &ar8327_sw_ops;
2750 } else if (chip_is_ar8337(priv)) {
2751 swdev->name = "Atheros AR8337";
2752 swdev->vlans = AR8X16_MAX_VLANS;
2753 swdev->ports = AR8327_NUM_PORTS;
2754 swdev->ops = &ar8327_sw_ops;
2755 } else {
2756 swdev->name = "Atheros AR8216";
2757 swdev->vlans = AR8216_NUM_VLANS;
2758 swdev->ports = AR8216_NUM_PORTS;
2759 }
2760
2761 ret = ar8xxx_mib_init(priv);
2762 if (ret)
2763 return ret;
2764
2765 return 0;
2766 }
2767
2768 static int
2769 ar8xxx_start(struct ar8xxx_priv *priv)
2770 {
2771 int ret;
2772
2773 priv->init = true;
2774
2775 ret = priv->chip->hw_init(priv);
2776 if (ret)
2777 return ret;
2778
2779 ret = ar8xxx_sw_reset_switch(&priv->dev);
2780 if (ret)
2781 return ret;
2782
2783 priv->init = false;
2784
2785 ar8xxx_mib_start(priv);
2786
2787 return 0;
2788 }
2789
2790 static int
2791 ar8xxx_phy_config_init(struct phy_device *phydev)
2792 {
2793 struct ar8xxx_priv *priv = phydev->priv;
2794 struct net_device *dev = phydev->attached_dev;
2795 int ret;
2796
2797 if (WARN_ON(!priv))
2798 return -ENODEV;
2799
2800 if (priv->chip->config_at_probe)
2801 return ar8xxx_phy_check_aneg(phydev);
2802
2803 priv->phy = phydev;
2804
2805 if (phydev->addr != 0) {
2806 if (chip_is_ar8316(priv)) {
2807 /* switch device has been initialized, reinit */
2808 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2809 priv->initialized = false;
2810 priv->port4_phy = true;
2811 ar8316_hw_init(priv);
2812 return 0;
2813 }
2814
2815 return 0;
2816 }
2817
2818 ret = ar8xxx_start(priv);
2819 if (ret)
2820 return ret;
2821
2822 /* VID fixup only needed on ar8216 */
2823 if (chip_is_ar8216(priv)) {
2824 dev->phy_ptr = priv;
2825 dev->priv_flags |= IFF_NO_IP_ALIGN;
2826 dev->eth_mangle_rx = ar8216_mangle_rx;
2827 dev->eth_mangle_tx = ar8216_mangle_tx;
2828 }
2829
2830 return 0;
2831 }
2832
2833 static int
2834 ar8xxx_phy_read_status(struct phy_device *phydev)
2835 {
2836 struct ar8xxx_priv *priv = phydev->priv;
2837 struct switch_port_link link;
2838 int ret;
2839
2840 if (phydev->addr != 0)
2841 return genphy_read_status(phydev);
2842
2843 ar8216_read_port_link(priv, phydev->addr, &link);
2844 phydev->link = !!link.link;
2845 if (!phydev->link)
2846 return 0;
2847
2848 switch (link.speed) {
2849 case SWITCH_PORT_SPEED_10:
2850 phydev->speed = SPEED_10;
2851 break;
2852 case SWITCH_PORT_SPEED_100:
2853 phydev->speed = SPEED_100;
2854 break;
2855 case SWITCH_PORT_SPEED_1000:
2856 phydev->speed = SPEED_1000;
2857 break;
2858 default:
2859 phydev->speed = 0;
2860 }
2861 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2862
2863 /* flush the address translation unit */
2864 mutex_lock(&priv->reg_mutex);
2865 ret = priv->chip->atu_flush(priv);
2866 mutex_unlock(&priv->reg_mutex);
2867
2868 phydev->state = PHY_RUNNING;
2869 netif_carrier_on(phydev->attached_dev);
2870 phydev->adjust_link(phydev->attached_dev);
2871
2872 return ret;
2873 }
2874
2875 static int
2876 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2877 {
2878 if (phydev->addr == 0)
2879 return 0;
2880
2881 return genphy_config_aneg(phydev);
2882 }
2883
2884 static const u32 ar8xxx_phy_ids[] = {
2885 0x004dd033,
2886 0x004dd034, /* AR8327 */
2887 0x004dd036, /* AR8337 */
2888 0x004dd041,
2889 0x004dd042,
2890 0x004dd043, /* AR8236 */
2891 };
2892
2893 static bool
2894 ar8xxx_phy_match(u32 phy_id)
2895 {
2896 int i;
2897
2898 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2899 if (phy_id == ar8xxx_phy_ids[i])
2900 return true;
2901
2902 return false;
2903 }
2904
2905 static bool
2906 ar8xxx_is_possible(struct mii_bus *bus)
2907 {
2908 unsigned i;
2909
2910 for (i = 0; i < 4; i++) {
2911 u32 phy_id;
2912
2913 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2914 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2915 if (!ar8xxx_phy_match(phy_id)) {
2916 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2917 dev_name(&bus->dev), i, phy_id);
2918 return false;
2919 }
2920 }
2921
2922 return true;
2923 }
2924
2925 static int
2926 ar8xxx_phy_probe(struct phy_device *phydev)
2927 {
2928 struct ar8xxx_priv *priv;
2929 struct switch_dev *swdev;
2930 int ret;
2931
2932 /* skip PHYs at unused adresses */
2933 if (phydev->addr != 0 && phydev->addr != 4)
2934 return -ENODEV;
2935
2936 if (!ar8xxx_is_possible(phydev->bus))
2937 return -ENODEV;
2938
2939 mutex_lock(&ar8xxx_dev_list_lock);
2940 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2941 if (priv->mii_bus == phydev->bus)
2942 goto found;
2943
2944 priv = ar8xxx_create_mii(phydev->bus);
2945 if (priv == NULL) {
2946 ret = -ENOMEM;
2947 goto unlock;
2948 }
2949
2950 ret = ar8xxx_probe_switch(priv);
2951 if (ret)
2952 goto free_priv;
2953
2954 swdev = &priv->dev;
2955 swdev->alias = dev_name(&priv->mii_bus->dev);
2956 ret = register_switch(swdev, NULL);
2957 if (ret)
2958 goto free_priv;
2959
2960 pr_info("%s: %s rev. %u switch registered on %s\n",
2961 swdev->devname, swdev->name, priv->chip_rev,
2962 dev_name(&priv->mii_bus->dev));
2963
2964 found:
2965 priv->use_count++;
2966
2967 if (phydev->addr == 0) {
2968 if (ar8xxx_has_gige(priv)) {
2969 phydev->supported = SUPPORTED_1000baseT_Full;
2970 phydev->advertising = ADVERTISED_1000baseT_Full;
2971 } else {
2972 phydev->supported = SUPPORTED_100baseT_Full;
2973 phydev->advertising = ADVERTISED_100baseT_Full;
2974 }
2975
2976 if (priv->chip->config_at_probe) {
2977 priv->phy = phydev;
2978
2979 ret = ar8xxx_start(priv);
2980 if (ret)
2981 goto err_unregister_switch;
2982 }
2983 } else {
2984 if (ar8xxx_has_gige(priv)) {
2985 phydev->supported |= SUPPORTED_1000baseT_Full;
2986 phydev->advertising |= ADVERTISED_1000baseT_Full;
2987 }
2988 }
2989
2990 phydev->priv = priv;
2991
2992 list_add(&priv->list, &ar8xxx_dev_list);
2993
2994 mutex_unlock(&ar8xxx_dev_list_lock);
2995
2996 return 0;
2997
2998 err_unregister_switch:
2999 if (--priv->use_count)
3000 goto unlock;
3001
3002 unregister_switch(&priv->dev);
3003
3004 free_priv:
3005 ar8xxx_free(priv);
3006 unlock:
3007 mutex_unlock(&ar8xxx_dev_list_lock);
3008 return ret;
3009 }
3010
3011 static void
3012 ar8xxx_phy_detach(struct phy_device *phydev)
3013 {
3014 struct net_device *dev = phydev->attached_dev;
3015
3016 if (!dev)
3017 return;
3018
3019 dev->phy_ptr = NULL;
3020 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
3021 dev->eth_mangle_rx = NULL;
3022 dev->eth_mangle_tx = NULL;
3023 }
3024
3025 static void
3026 ar8xxx_phy_remove(struct phy_device *phydev)
3027 {
3028 struct ar8xxx_priv *priv = phydev->priv;
3029
3030 if (WARN_ON(!priv))
3031 return;
3032
3033 phydev->priv = NULL;
3034 if (--priv->use_count > 0)
3035 return;
3036
3037 mutex_lock(&ar8xxx_dev_list_lock);
3038 list_del(&priv->list);
3039 mutex_unlock(&ar8xxx_dev_list_lock);
3040
3041 unregister_switch(&priv->dev);
3042 ar8xxx_mib_stop(priv);
3043 ar8xxx_free(priv);
3044 }
3045
3046 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3047 static int
3048 ar8xxx_phy_soft_reset(struct phy_device *phydev)
3049 {
3050 /* we don't need an extra reset */
3051 return 0;
3052 }
3053 #endif
3054
3055 static struct phy_driver ar8xxx_phy_driver = {
3056 .phy_id = 0x004d0000,
3057 .name = "Atheros AR8216/AR8236/AR8316",
3058 .phy_id_mask = 0xffff0000,
3059 .features = PHY_BASIC_FEATURES,
3060 .probe = ar8xxx_phy_probe,
3061 .remove = ar8xxx_phy_remove,
3062 .detach = ar8xxx_phy_detach,
3063 .config_init = ar8xxx_phy_config_init,
3064 .config_aneg = ar8xxx_phy_config_aneg,
3065 .read_status = ar8xxx_phy_read_status,
3066 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3067 .soft_reset = ar8xxx_phy_soft_reset,
3068 #endif
3069 .driver = { .owner = THIS_MODULE },
3070 };
3071
3072 int __init
3073 ar8xxx_init(void)
3074 {
3075 return phy_driver_register(&ar8xxx_phy_driver);
3076 }
3077
3078 void __exit
3079 ar8xxx_exit(void)
3080 {
3081 phy_driver_unregister(&ar8xxx_phy_driver);
3082 }
3083
3084 module_init(ar8xxx_init);
3085 module_exit(ar8xxx_exit);
3086 MODULE_LICENSE("GPL");
3087
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