projects / openwrt / staging / jow.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
kernel: rewrite the phy packet hook, put it in the network stack to avoid having...
[openwrt/staging/jow.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include "ar8216.h"
36
37 /* size of the vlan table */
38 #define AR8X16_MAX_VLANS 128
39 #define AR8X16_PROBE_RETRIES 10
40 #define AR8X16_MAX_PORTS 8
41
42 struct ar8216_priv;
43
44 #define AR8XXX_CAP_GIGE BIT(0)
45
46 struct ar8xxx_chip {
47 unsigned long caps;
48
49 int (*hw_init)(struct ar8216_priv *priv);
50 void (*init_globals)(struct ar8216_priv *priv);
51 void (*init_port)(struct ar8216_priv *priv, int port);
52 void (*setup_port)(struct ar8216_priv *priv, int port, u32 egress,
53 u32 ingress, u32 members, u32 pvid);
54 u32 (*read_port_status)(struct ar8216_priv *priv, int port);
55 int (*atu_flush)(struct ar8216_priv *priv);
56 void (*vtu_flush)(struct ar8216_priv *priv);
57 void (*vtu_load_vlan)(struct ar8216_priv *priv, u32 vid, u32 port_mask);
58 };
59
60 struct ar8216_priv {
61 struct switch_dev dev;
62 struct phy_device *phy;
63 u32 (*read)(struct ar8216_priv *priv, int reg);
64 void (*write)(struct ar8216_priv *priv, int reg, u32 val);
65 const struct net_device_ops *ndo_old;
66 struct net_device_ops ndo;
67 struct mutex reg_mutex;
68 int chip_type;
69 const struct ar8xxx_chip *chip;
70 bool initialized;
71 bool port4_phy;
72 char buf[80];
73
74 bool init;
75 bool mii_lo_first;
76
77 /* all fields below are cleared on reset */
78 bool vlan;
79 u16 vlan_id[AR8X16_MAX_VLANS];
80 u8 vlan_table[AR8X16_MAX_VLANS];
81 u8 vlan_tagged;
82 u16 pvid[AR8X16_MAX_PORTS];
83 };
84
85 #define to_ar8216(_dev) container_of(_dev, struct ar8216_priv, dev)
86
87 static inline bool ar8xxx_has_gige(struct ar8216_priv *priv)
88 {
89 return priv->chip->caps & AR8XXX_CAP_GIGE;
90 }
91
92 static inline void
93 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
94 {
95 regaddr >>= 1;
96 *r1 = regaddr & 0x1e;
97
98 regaddr >>= 5;
99 *r2 = regaddr & 0x7;
100
101 regaddr >>= 3;
102 *page = regaddr & 0x1ff;
103 }
104
105 static u32
106 ar8216_mii_read(struct ar8216_priv *priv, int reg)
107 {
108 struct phy_device *phy = priv->phy;
109 struct mii_bus *bus = phy->bus;
110 u16 r1, r2, page;
111 u16 lo, hi;
112
113 split_addr((u32) reg, &r1, &r2, &page);
114
115 mutex_lock(&bus->mdio_lock);
116
117 bus->write(bus, 0x18, 0, page);
118 usleep_range(1000, 2000); /* wait for the page switch to propagate */
119 lo = bus->read(bus, 0x10 | r2, r1);
120 hi = bus->read(bus, 0x10 | r2, r1 + 1);
121
122 mutex_unlock(&bus->mdio_lock);
123
124 return (hi << 16) | lo;
125 }
126
127 static void
128 ar8216_mii_write(struct ar8216_priv *priv, int reg, u32 val)
129 {
130 struct phy_device *phy = priv->phy;
131 struct mii_bus *bus = phy->bus;
132 u16 r1, r2, r3;
133 u16 lo, hi;
134
135 split_addr((u32) reg, &r1, &r2, &r3);
136 lo = val & 0xffff;
137 hi = (u16) (val >> 16);
138
139 mutex_lock(&bus->mdio_lock);
140
141 bus->write(bus, 0x18, 0, r3);
142 usleep_range(1000, 2000); /* wait for the page switch to propagate */
143 if (priv->mii_lo_first) {
144 bus->write(bus, 0x10 | r2, r1, lo);
145 bus->write(bus, 0x10 | r2, r1 + 1, hi);
146 } else {
147 bus->write(bus, 0x10 | r2, r1 + 1, hi);
148 bus->write(bus, 0x10 | r2, r1, lo);
149 }
150
151 mutex_unlock(&bus->mdio_lock);
152 }
153
154 static void
155 ar8216_phy_dbg_write(struct ar8216_priv *priv, int phy_addr,
156 u16 dbg_addr, u16 dbg_data)
157 {
158 struct mii_bus *bus = priv->phy->bus;
159
160 mutex_lock(&bus->mdio_lock);
161 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
162 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
163 mutex_unlock(&bus->mdio_lock);
164 }
165
166 static u32
167 ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
168 {
169 u32 v;
170
171 lockdep_assert_held(&priv->reg_mutex);
172
173 v = priv->read(priv, reg);
174 v &= ~mask;
175 v |= val;
176 priv->write(priv, reg, v);
177
178 return v;
179 }
180
181 static void
182 ar8216_read_port_link(struct ar8216_priv *priv, int port,
183 struct switch_port_link *link)
184 {
185 u32 status;
186 u32 speed;
187
188 memset(link, '\0', sizeof(*link));
189
190 status = priv->chip->read_port_status(priv, port);
191
192 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
193 if (link->aneg) {
194 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
195 if (!link->link)
196 return;
197 } else {
198 link->link = true;
199 }
200
201 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
202 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
203 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
204
205 speed = (status & AR8216_PORT_STATUS_SPEED) >>
206 AR8216_PORT_STATUS_SPEED_S;
207
208 switch (speed) {
209 case AR8216_PORT_SPEED_10M:
210 link->speed = SWITCH_PORT_SPEED_10;
211 break;
212 case AR8216_PORT_SPEED_100M:
213 link->speed = SWITCH_PORT_SPEED_100;
214 break;
215 case AR8216_PORT_SPEED_1000M:
216 link->speed = SWITCH_PORT_SPEED_1000;
217 break;
218 default:
219 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
220 break;
221 }
222 }
223
224 static struct sk_buff *
225 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
226 {
227 struct ar8216_priv *priv = dev->phy_ptr;
228 unsigned char *buf;
229
230 if (unlikely(!priv))
231 goto error;
232
233 if (!priv->vlan)
234 goto send;
235
236 if (unlikely(skb_headroom(skb) < 2)) {
237 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
238 goto error;
239 }
240
241 buf = skb_push(skb, 2);
242 buf[0] = 0x10;
243 buf[1] = 0x80;
244
245 send:
246 return skb;
247
248 error:
249 dev_kfree_skb_any(skb);
250 return NULL;
251 }
252
253 static void
254 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
255 {
256 struct ar8216_priv *priv;
257 unsigned char *buf;
258 int port, vlan;
259
260 priv = dev->phy_ptr;
261 if (!priv)
262 return;
263
264 /* don't strip the header if vlan mode is disabled */
265 if (!priv->vlan)
266 return;
267
268 /* strip header, get vlan id */
269 buf = skb->data;
270 skb_pull(skb, 2);
271
272 /* check for vlan header presence */
273 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
274 return;
275
276 port = buf[0] & 0xf;
277
278 /* no need to fix up packets coming from a tagged source */
279 if (priv->vlan_tagged & (1 << port))
280 return;
281
282 /* lookup port vid from local table, the switch passes an invalid vlan id */
283 vlan = priv->vlan_id[priv->pvid[port]];
284
285 buf[14 + 2] &= 0xf0;
286 buf[14 + 2] |= vlan >> 8;
287 buf[15 + 2] = vlan & 0xff;
288 }
289
290 static int
291 ar8216_wait_bit(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
292 {
293 int timeout = 20;
294 u32 t = 0;
295
296 while (1) {
297 t = priv->read(priv, reg);
298 if ((t & mask) == val)
299 return 0;
300
301 if (timeout-- <= 0)
302 break;
303
304 udelay(10);
305 }
306
307 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
308 (unsigned int) reg, t, mask, val);
309 return -ETIMEDOUT;
310 }
311
312 static void
313 ar8216_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
314 {
315 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
316 return;
317 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
318 val &= AR8216_VTUDATA_MEMBER;
319 val |= AR8216_VTUDATA_VALID;
320 priv->write(priv, AR8216_REG_VTU_DATA, val);
321 }
322 op |= AR8216_VTU_ACTIVE;
323 priv->write(priv, AR8216_REG_VTU, op);
324 }
325
326 static void
327 ar8216_vtu_flush(struct ar8216_priv *priv)
328 {
329 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
330 }
331
332 static void
333 ar8216_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
334 {
335 u32 op;
336
337 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
338 ar8216_vtu_op(priv, op, port_mask);
339 }
340
341 static int
342 ar8216_atu_flush(struct ar8216_priv *priv)
343 {
344 int ret;
345
346 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
347 if (!ret)
348 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
349
350 return ret;
351 }
352
353 static u32
354 ar8216_read_port_status(struct ar8216_priv *priv, int port)
355 {
356 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
357 }
358
359 static void
360 ar8216_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
361 u32 members, u32 pvid)
362 {
363 u32 header;
364
365 if (priv->vlan && port == AR8216_PORT_CPU && priv->chip_type == AR8216)
366 header = AR8216_PORT_CTRL_HEADER;
367 else
368 header = 0;
369
370 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
371 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
372 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
373 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
374 AR8216_PORT_CTRL_LEARN | header |
375 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
376 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
377
378 ar8216_rmw(priv, AR8216_REG_PORT_VLAN(port),
379 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
380 AR8216_PORT_VLAN_DEFAULT_ID,
381 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
382 (ingress << AR8216_PORT_VLAN_MODE_S) |
383 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
384 }
385
386 static int
387 ar8216_hw_init(struct ar8216_priv *priv)
388 {
389 return 0;
390 }
391
392 static void
393 ar8216_init_globals(struct ar8216_priv *priv)
394 {
395 /* standard atheros magic */
396 priv->write(priv, 0x38, 0xc000050e);
397
398 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
399 AR8216_GCTRL_MTU, 1518 + 8 + 2);
400 }
401
402 static void
403 ar8216_init_port(struct ar8216_priv *priv, int port)
404 {
405 /* Enable port learning and tx */
406 priv->write(priv, AR8216_REG_PORT_CTRL(port),
407 AR8216_PORT_CTRL_LEARN |
408 (4 << AR8216_PORT_CTRL_STATE_S));
409
410 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
411
412 if (port == AR8216_PORT_CPU) {
413 priv->write(priv, AR8216_REG_PORT_STATUS(port),
414 AR8216_PORT_STATUS_LINK_UP |
415 (ar8xxx_has_gige(priv) ?
416 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
417 AR8216_PORT_STATUS_TXMAC |
418 AR8216_PORT_STATUS_RXMAC |
419 ((priv->chip_type == AR8316) ? AR8216_PORT_STATUS_RXFLOW : 0) |
420 ((priv->chip_type == AR8316) ? AR8216_PORT_STATUS_TXFLOW : 0) |
421 AR8216_PORT_STATUS_DUPLEX);
422 } else {
423 priv->write(priv, AR8216_REG_PORT_STATUS(port),
424 AR8216_PORT_STATUS_LINK_AUTO);
425 }
426 }
427
428 static const struct ar8xxx_chip ar8216_chip = {
429 .hw_init = ar8216_hw_init,
430 .init_globals = ar8216_init_globals,
431 .init_port = ar8216_init_port,
432 .setup_port = ar8216_setup_port,
433 .read_port_status = ar8216_read_port_status,
434 .atu_flush = ar8216_atu_flush,
435 .vtu_flush = ar8216_vtu_flush,
436 .vtu_load_vlan = ar8216_vtu_load_vlan,
437 };
438
439 static void
440 ar8236_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
441 u32 members, u32 pvid)
442 {
443 ar8216_rmw(priv, AR8216_REG_PORT_CTRL(port),
444 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
445 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
446 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
447 AR8216_PORT_CTRL_LEARN |
448 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
449 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
450
451 ar8216_rmw(priv, AR8236_REG_PORT_VLAN(port),
452 AR8236_PORT_VLAN_DEFAULT_ID,
453 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
454
455 ar8216_rmw(priv, AR8236_REG_PORT_VLAN2(port),
456 AR8236_PORT_VLAN2_VLAN_MODE |
457 AR8236_PORT_VLAN2_MEMBER,
458 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
459 (members << AR8236_PORT_VLAN2_MEMBER_S));
460 }
461
462 static int
463 ar8236_hw_init(struct ar8216_priv *priv)
464 {
465 int i;
466 struct mii_bus *bus;
467
468 if (priv->initialized)
469 return 0;
470
471 /* Initialize the PHYs */
472 bus = priv->phy->bus;
473 for (i = 0; i < 5; i++) {
474 mdiobus_write(bus, i, MII_ADVERTISE,
475 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
476 ADVERTISE_PAUSE_ASYM);
477 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
478 }
479 msleep(1000);
480
481 priv->initialized = true;
482 return 0;
483 }
484
485 static void
486 ar8236_init_globals(struct ar8216_priv *priv)
487 {
488 /* enable jumbo frames */
489 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
490 AR8316_GCTRL_MTU, 9018 + 8 + 2);
491 }
492
493 static const struct ar8xxx_chip ar8236_chip = {
494 .hw_init = ar8236_hw_init,
495 .init_globals = ar8236_init_globals,
496 .init_port = ar8216_init_port,
497 .setup_port = ar8236_setup_port,
498 .read_port_status = ar8216_read_port_status,
499 .atu_flush = ar8216_atu_flush,
500 .vtu_flush = ar8216_vtu_flush,
501 .vtu_load_vlan = ar8216_vtu_load_vlan,
502 };
503
504 static int
505 ar8316_hw_init(struct ar8216_priv *priv)
506 {
507 int i;
508 u32 val, newval;
509 struct mii_bus *bus;
510
511 val = priv->read(priv, 0x8);
512
513 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
514 if (priv->port4_phy) {
515 /* value taken from Ubiquiti RouterStation Pro */
516 newval = 0x81461bea;
517 printk(KERN_INFO "ar8316: Using port 4 as PHY\n");
518 } else {
519 newval = 0x01261be2;
520 printk(KERN_INFO "ar8316: Using port 4 as switch port\n");
521 }
522 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
523 /* value taken from AVM Fritz!Box 7390 sources */
524 newval = 0x010e5b71;
525 } else {
526 /* no known value for phy interface */
527 printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
528 priv->phy->interface);
529 return -EINVAL;
530 }
531
532 if (val == newval)
533 goto out;
534
535 priv->write(priv, 0x8, newval);
536
537 /* Initialize the ports */
538 bus = priv->phy->bus;
539 for (i = 0; i < 5; i++) {
540 if ((i == 4) && priv->port4_phy &&
541 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
542 /* work around for phy4 rgmii mode */
543 ar8216_phy_dbg_write(priv, i, 0x12, 0x480c);
544 /* rx delay */
545 ar8216_phy_dbg_write(priv, i, 0x0, 0x824e);
546 /* tx delay */
547 ar8216_phy_dbg_write(priv, i, 0x5, 0x3d47);
548 msleep(1000);
549 }
550
551 /* initialize the port itself */
552 mdiobus_write(bus, i, MII_ADVERTISE,
553 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
554 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
555 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
556 msleep(1000);
557 }
558
559 out:
560 priv->initialized = true;
561 return 0;
562 }
563
564 static void
565 ar8316_init_globals(struct ar8216_priv *priv)
566 {
567 /* standard atheros magic */
568 priv->write(priv, 0x38, 0xc000050e);
569
570 /* enable cpu port to receive multicast and broadcast frames */
571 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
572
573 /* enable jumbo frames */
574 ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
575 AR8316_GCTRL_MTU, 9018 + 8 + 2);
576 }
577
578 static const struct ar8xxx_chip ar8316_chip = {
579 .caps = AR8XXX_CAP_GIGE,
580 .hw_init = ar8316_hw_init,
581 .init_globals = ar8316_init_globals,
582 .init_port = ar8216_init_port,
583 .setup_port = ar8216_setup_port,
584 .read_port_status = ar8216_read_port_status,
585 .atu_flush = ar8216_atu_flush,
586 .vtu_flush = ar8216_vtu_flush,
587 .vtu_load_vlan = ar8216_vtu_load_vlan,
588 };
589
590 static u32
591 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
592 {
593 u32 t;
594
595 if (!cfg)
596 return 0;
597
598 t = 0;
599 switch (cfg->mode) {
600 case AR8327_PAD_NC:
601 break;
602
603 case AR8327_PAD_MAC2MAC_MII:
604 t = AR8327_PAD_MAC_MII_EN;
605 if (cfg->rxclk_sel)
606 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
607 if (cfg->txclk_sel)
608 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
609 break;
610
611 case AR8327_PAD_MAC2MAC_GMII:
612 t = AR8327_PAD_MAC_GMII_EN;
613 if (cfg->rxclk_sel)
614 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
615 if (cfg->txclk_sel)
616 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
617 break;
618
619 case AR8327_PAD_MAC_SGMII:
620 t = AR8327_PAD_SGMII_EN;
621 break;
622
623 case AR8327_PAD_MAC2PHY_MII:
624 t = AR8327_PAD_PHY_MII_EN;
625 if (cfg->rxclk_sel)
626 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
627 if (cfg->txclk_sel)
628 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
629 break;
630
631 case AR8327_PAD_MAC2PHY_GMII:
632 t = AR8327_PAD_PHY_GMII_EN;
633 if (cfg->pipe_rxclk_sel)
634 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
635 if (cfg->rxclk_sel)
636 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
637 if (cfg->txclk_sel)
638 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
639 break;
640
641 case AR8327_PAD_MAC_RGMII:
642 t = AR8327_PAD_RGMII_EN;
643 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
644 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
645 if (cfg->rxclk_delay_en)
646 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
647 if (cfg->txclk_delay_en)
648 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
649 break;
650
651 case AR8327_PAD_PHY_GMII:
652 t = AR8327_PAD_PHYX_GMII_EN;
653 break;
654
655 case AR8327_PAD_PHY_RGMII:
656 t = AR8327_PAD_PHYX_RGMII_EN;
657 break;
658
659 case AR8327_PAD_PHY_MII:
660 t = AR8327_PAD_PHYX_MII_EN;
661 break;
662 }
663
664 return t;
665 }
666
667 static int
668 ar8327_hw_init(struct ar8216_priv *priv)
669 {
670 struct ar8327_platform_data *pdata;
671 u32 t;
672 int i;
673
674 pdata = priv->phy->dev.platform_data;
675 if (!pdata)
676 return -EINVAL;
677
678 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
679 priv->write(priv, AR8327_REG_PAD0_MODE, t);
680 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
681 priv->write(priv, AR8327_REG_PAD5_MODE, t);
682 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
683 priv->write(priv, AR8327_REG_PAD6_MODE, t);
684
685 priv->write(priv, AR8327_REG_POWER_ON_STRIP, 0x40000000);
686
687 /* fixup PHYs */
688 for (i = 0; i < AR8327_NUM_PHYS; i++) {
689 /* For 100M waveform */
690 ar8216_phy_dbg_write(priv, i, 0, 0x02ea);
691
692 /* Turn on Gigabit clock */
693 ar8216_phy_dbg_write(priv, i, 0x3d, 0x68a0);
694 }
695
696 return 0;
697 }
698
699 static void
700 ar8327_init_globals(struct ar8216_priv *priv)
701 {
702 u32 t;
703
704 /* enable CPU port and disable mirror port */
705 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
706 AR8327_FWD_CTRL0_MIRROR_PORT;
707 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
708
709 /* forward multicast and broadcast frames to CPU */
710 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
711 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
712 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
713 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
714
715 /* setup MTU */
716 ar8216_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
717 AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
718 }
719
720 static void
721 ar8327_init_cpuport(struct ar8216_priv *priv)
722 {
723 struct ar8327_platform_data *pdata;
724 struct ar8327_port_cfg *cfg;
725 u32 t;
726
727 pdata = priv->phy->dev.platform_data;
728 if (!pdata)
729 return;
730
731 cfg = &pdata->cpuport_cfg;
732 if (!cfg->force_link) {
733 priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU),
734 AR8216_PORT_STATUS_LINK_AUTO);
735 return;
736 }
737
738 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
739 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
740 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
741 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
742 switch (cfg->speed) {
743 case AR8327_PORT_SPEED_10:
744 t |= AR8216_PORT_SPEED_10M;
745 break;
746 case AR8327_PORT_SPEED_100:
747 t |= AR8216_PORT_SPEED_100M;
748 break;
749 case AR8327_PORT_SPEED_1000:
750 t |= AR8216_PORT_SPEED_1000M;
751 break;
752 }
753
754 priv->write(priv, AR8327_REG_PORT_STATUS(AR8216_PORT_CPU), t);
755 }
756
757 static void
758 ar8327_init_port(struct ar8216_priv *priv, int port)
759 {
760 u32 t;
761
762 if (port == AR8216_PORT_CPU) {
763 ar8327_init_cpuport(priv);
764 } else {
765 t = AR8216_PORT_STATUS_LINK_AUTO;
766 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
767 }
768
769 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
770
771 priv->write(priv, AR8327_REG_PORT_VLAN0(port), 0);
772
773 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
774 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
775
776 t = AR8327_PORT_LOOKUP_LEARN;
777 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
778 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
779 }
780
781 static u32
782 ar8327_read_port_status(struct ar8216_priv *priv, int port)
783 {
784 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
785 }
786
787 static int
788 ar8327_atu_flush(struct ar8216_priv *priv)
789 {
790 int ret;
791
792 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
793 AR8327_ATU_FUNC_BUSY, 0);
794 if (!ret)
795 priv->write(priv, AR8327_REG_ATU_FUNC,
796 AR8327_ATU_FUNC_OP_FLUSH);
797
798 return ret;
799 }
800
801 static void
802 ar8327_vtu_op(struct ar8216_priv *priv, u32 op, u32 val)
803 {
804 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
805 AR8327_VTU_FUNC1_BUSY, 0))
806 return;
807
808 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
809 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
810
811 op |= AR8327_VTU_FUNC1_BUSY;
812 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
813 }
814
815 static void
816 ar8327_vtu_flush(struct ar8216_priv *priv)
817 {
818 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
819 }
820
821 static void
822 ar8327_vtu_load_vlan(struct ar8216_priv *priv, u32 vid, u32 port_mask)
823 {
824 u32 op;
825 u32 val;
826 int i;
827
828 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
829 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
830 for (i = 0; i < AR8327_NUM_PORTS; i++) {
831 u32 mode;
832
833 if ((port_mask & BIT(i)) == 0)
834 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
835 else if (priv->vlan == 0)
836 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
837 else if (priv->vlan_tagged & BIT(i))
838 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
839 else
840 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
841
842 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
843 }
844 ar8327_vtu_op(priv, op, val);
845 }
846
847 static void
848 ar8327_setup_port(struct ar8216_priv *priv, int port, u32 egress, u32 ingress,
849 u32 members, u32 pvid)
850 {
851 u32 t;
852 u32 mode;
853
854 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
855 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
856 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
857
858 mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
859 switch (egress) {
860 case AR8216_OUT_KEEP:
861 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
862 break;
863 case AR8216_OUT_STRIP_VLAN:
864 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
865 break;
866 case AR8216_OUT_ADD_VLAN:
867 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
868 break;
869 }
870
871 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
872 t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
873 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
874
875 t = members;
876 t |= AR8327_PORT_LOOKUP_LEARN;
877 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
878 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
879 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
880 }
881
882 static const struct ar8xxx_chip ar8327_chip = {
883 .caps = AR8XXX_CAP_GIGE,
884 .hw_init = ar8327_hw_init,
885 .init_globals = ar8327_init_globals,
886 .init_port = ar8327_init_port,
887 .setup_port = ar8327_setup_port,
888 .read_port_status = ar8327_read_port_status,
889 .atu_flush = ar8327_atu_flush,
890 .vtu_flush = ar8327_vtu_flush,
891 .vtu_load_vlan = ar8327_vtu_load_vlan,
892 };
893
894 static int
895 ar8216_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
896 struct switch_val *val)
897 {
898 struct ar8216_priv *priv = to_ar8216(dev);
899 priv->vlan = !!val->value.i;
900 return 0;
901 }
902
903 static int
904 ar8216_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
905 struct switch_val *val)
906 {
907 struct ar8216_priv *priv = to_ar8216(dev);
908 val->value.i = priv->vlan;
909 return 0;
910 }
911
912
913 static int
914 ar8216_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
915 {
916 struct ar8216_priv *priv = to_ar8216(dev);
917
918 /* make sure no invalid PVIDs get set */
919
920 if (vlan >= dev->vlans)
921 return -EINVAL;
922
923 priv->pvid[port] = vlan;
924 return 0;
925 }
926
927 static int
928 ar8216_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
929 {
930 struct ar8216_priv *priv = to_ar8216(dev);
931 *vlan = priv->pvid[port];
932 return 0;
933 }
934
935 static int
936 ar8216_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
937 struct switch_val *val)
938 {
939 struct ar8216_priv *priv = to_ar8216(dev);
940 priv->vlan_id[val->port_vlan] = val->value.i;
941 return 0;
942 }
943
944 static int
945 ar8216_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
946 struct switch_val *val)
947 {
948 struct ar8216_priv *priv = to_ar8216(dev);
949 val->value.i = priv->vlan_id[val->port_vlan];
950 return 0;
951 }
952
953 static int
954 ar8216_sw_get_port_link(struct switch_dev *dev, int port,
955 struct switch_port_link *link)
956 {
957 struct ar8216_priv *priv = to_ar8216(dev);
958
959 ar8216_read_port_link(priv, port, link);
960 return 0;
961 }
962
963 static int
964 ar8216_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
965 {
966 struct ar8216_priv *priv = to_ar8216(dev);
967 u8 ports = priv->vlan_table[val->port_vlan];
968 int i;
969
970 val->len = 0;
971 for (i = 0; i < dev->ports; i++) {
972 struct switch_port *p;
973
974 if (!(ports & (1 << i)))
975 continue;
976
977 p = &val->value.ports[val->len++];
978 p->id = i;
979 if (priv->vlan_tagged & (1 << i))
980 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
981 else
982 p->flags = 0;
983 }
984 return 0;
985 }
986
987 static int
988 ar8216_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
989 {
990 struct ar8216_priv *priv = to_ar8216(dev);
991 u8 *vt = &priv->vlan_table[val->port_vlan];
992 int i, j;
993
994 *vt = 0;
995 for (i = 0; i < val->len; i++) {
996 struct switch_port *p = &val->value.ports[i];
997
998 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
999 priv->vlan_tagged |= (1 << p->id);
1000 } else {
1001 priv->vlan_tagged &= ~(1 << p->id);
1002 priv->pvid[p->id] = val->port_vlan;
1003
1004 /* make sure that an untagged port does not
1005 * appear in other vlans */
1006 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1007 if (j == val->port_vlan)
1008 continue;
1009 priv->vlan_table[j] &= ~(1 << p->id);
1010 }
1011 }
1012
1013 *vt |= 1 << p->id;
1014 }
1015 return 0;
1016 }
1017
1018 static int
1019 ar8216_sw_hw_apply(struct switch_dev *dev)
1020 {
1021 struct ar8216_priv *priv = to_ar8216(dev);
1022 u8 portmask[AR8X16_MAX_PORTS];
1023 int i, j;
1024
1025 mutex_lock(&priv->reg_mutex);
1026 /* flush all vlan translation unit entries */
1027 priv->chip->vtu_flush(priv);
1028
1029 memset(portmask, 0, sizeof(portmask));
1030 if (!priv->init) {
1031 /* calculate the port destination masks and load vlans
1032 * into the vlan translation unit */
1033 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1034 u8 vp = priv->vlan_table[j];
1035
1036 if (!vp)
1037 continue;
1038
1039 for (i = 0; i < dev->ports; i++) {
1040 u8 mask = (1 << i);
1041 if (vp & mask)
1042 portmask[i] |= vp & ~mask;
1043 }
1044
1045 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1046 priv->vlan_table[j]);
1047 }
1048 } else {
1049 /* vlan disabled:
1050 * isolate all ports, but connect them to the cpu port */
1051 for (i = 0; i < dev->ports; i++) {
1052 if (i == AR8216_PORT_CPU)
1053 continue;
1054
1055 portmask[i] = 1 << AR8216_PORT_CPU;
1056 portmask[AR8216_PORT_CPU] |= (1 << i);
1057 }
1058 }
1059
1060 /* update the port destination mask registers and tag settings */
1061 for (i = 0; i < dev->ports; i++) {
1062 int egress, ingress;
1063 int pvid;
1064
1065 if (priv->vlan) {
1066 pvid = priv->vlan_id[priv->pvid[i]];
1067 if (priv->vlan_tagged & (1 << i))
1068 egress = AR8216_OUT_ADD_VLAN;
1069 else
1070 egress = AR8216_OUT_STRIP_VLAN;
1071 ingress = AR8216_IN_SECURE;
1072 } else {
1073 pvid = i;
1074 egress = AR8216_OUT_KEEP;
1075 ingress = AR8216_IN_PORT_ONLY;
1076 }
1077
1078 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1079 pvid);
1080 }
1081 mutex_unlock(&priv->reg_mutex);
1082 return 0;
1083 }
1084
1085 static int
1086 ar8216_sw_reset_switch(struct switch_dev *dev)
1087 {
1088 struct ar8216_priv *priv = to_ar8216(dev);
1089 int i;
1090
1091 mutex_lock(&priv->reg_mutex);
1092 memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
1093 offsetof(struct ar8216_priv, vlan));
1094
1095 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1096 priv->vlan_id[i] = i;
1097
1098 /* Configure all ports */
1099 for (i = 0; i < dev->ports; i++)
1100 priv->chip->init_port(priv, i);
1101
1102 priv->chip->init_globals(priv);
1103 mutex_unlock(&priv->reg_mutex);
1104
1105 return ar8216_sw_hw_apply(dev);
1106 }
1107
1108 static struct switch_attr ar8216_globals[] = {
1109 {
1110 .type = SWITCH_TYPE_INT,
1111 .name = "enable_vlan",
1112 .description = "Enable VLAN mode",
1113 .set = ar8216_sw_set_vlan,
1114 .get = ar8216_sw_get_vlan,
1115 .max = 1
1116 },
1117 };
1118
1119 static struct switch_attr ar8216_port[] = {
1120 };
1121
1122 static struct switch_attr ar8216_vlan[] = {
1123 {
1124 .type = SWITCH_TYPE_INT,
1125 .name = "vid",
1126 .description = "VLAN ID (0-4094)",
1127 .set = ar8216_sw_set_vid,
1128 .get = ar8216_sw_get_vid,
1129 .max = 4094,
1130 },
1131 };
1132
1133 static const struct switch_dev_ops ar8216_sw_ops = {
1134 .attr_global = {
1135 .attr = ar8216_globals,
1136 .n_attr = ARRAY_SIZE(ar8216_globals),
1137 },
1138 .attr_port = {
1139 .attr = ar8216_port,
1140 .n_attr = ARRAY_SIZE(ar8216_port),
1141 },
1142 .attr_vlan = {
1143 .attr = ar8216_vlan,
1144 .n_attr = ARRAY_SIZE(ar8216_vlan),
1145 },
1146 .get_port_pvid = ar8216_sw_get_pvid,
1147 .set_port_pvid = ar8216_sw_set_pvid,
1148 .get_vlan_ports = ar8216_sw_get_ports,
1149 .set_vlan_ports = ar8216_sw_set_ports,
1150 .apply_config = ar8216_sw_hw_apply,
1151 .reset_switch = ar8216_sw_reset_switch,
1152 .get_port_link = ar8216_sw_get_port_link,
1153 };
1154
1155 static int
1156 ar8216_id_chip(struct ar8216_priv *priv)
1157 {
1158 u32 val;
1159 u16 id;
1160 int i;
1161
1162 priv->chip_type = UNKNOWN;
1163
1164 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1165 if (val == ~0)
1166 return -ENODEV;
1167
1168 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1169 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1170 u16 t;
1171
1172 val = ar8216_mii_read(priv, AR8216_REG_CTRL);
1173 if (val == ~0)
1174 return -ENODEV;
1175
1176 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1177 if (t != id)
1178 return -ENODEV;
1179 }
1180
1181 switch (id) {
1182 case 0x0101:
1183 priv->chip_type = AR8216;
1184 priv->chip = &ar8216_chip;
1185 break;
1186 case 0x0301:
1187 priv->chip_type = AR8236;
1188 priv->chip = &ar8236_chip;
1189 break;
1190 case 0x1000:
1191 case 0x1001:
1192 priv->chip_type = AR8316;
1193 priv->chip = &ar8316_chip;
1194 break;
1195 case 0x1202:
1196 priv->chip_type = AR8327;
1197 priv->mii_lo_first = true;
1198 priv->chip = &ar8327_chip;
1199 break;
1200 default:
1201 printk(KERN_DEBUG
1202 "ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
1203 (int)(id >> AR8216_CTRL_VERSION_S),
1204 (int)(id & AR8216_CTRL_REVISION),
1205 mdiobus_read(priv->phy->bus, priv->phy->addr, 2),
1206 mdiobus_read(priv->phy->bus, priv->phy->addr, 3));
1207
1208 return -ENODEV;
1209 }
1210
1211 return 0;
1212 }
1213
1214 static int
1215 ar8216_config_init(struct phy_device *pdev)
1216 {
1217 struct ar8216_priv *priv = pdev->priv;
1218 struct net_device *dev = pdev->attached_dev;
1219 struct switch_dev *swdev;
1220 int ret;
1221
1222 if (!priv) {
1223 priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
1224 if (priv == NULL)
1225 return -ENOMEM;
1226 }
1227
1228 priv->phy = pdev;
1229
1230 ret = ar8216_id_chip(priv);
1231 if (ret)
1232 goto err_free_priv;
1233
1234 if (pdev->addr != 0) {
1235 if (ar8xxx_has_gige(priv)) {
1236 pdev->supported |= SUPPORTED_1000baseT_Full;
1237 pdev->advertising |= ADVERTISED_1000baseT_Full;
1238 }
1239
1240 if (priv->chip_type == AR8316) {
1241 /* check if we're attaching to the switch twice */
1242 pdev = pdev->bus->phy_map[0];
1243 if (!pdev) {
1244 kfree(priv);
1245 return 0;
1246 }
1247
1248 /* switch device has not been initialized, reuse priv */
1249 if (!pdev->priv) {
1250 priv->port4_phy = true;
1251 pdev->priv = priv;
1252 return 0;
1253 }
1254
1255 kfree(priv);
1256
1257 /* switch device has been initialized, reinit */
1258 priv = pdev->priv;
1259 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1260 priv->initialized = false;
1261 priv->port4_phy = true;
1262 ar8316_hw_init(priv);
1263 return 0;
1264 }
1265
1266 kfree(priv);
1267 return 0;
1268 }
1269
1270 printk(KERN_INFO "%s: AR%d switch driver attached.\n",
1271 pdev->attached_dev->name, priv->chip_type);
1272
1273 if (ar8xxx_has_gige(priv))
1274 pdev->supported = SUPPORTED_1000baseT_Full;
1275 else
1276 pdev->supported = SUPPORTED_100baseT_Full;
1277 pdev->advertising = pdev->supported;
1278
1279 mutex_init(&priv->reg_mutex);
1280 priv->read = ar8216_mii_read;
1281 priv->write = ar8216_mii_write;
1282
1283 pdev->priv = priv;
1284
1285 swdev = &priv->dev;
1286 swdev->cpu_port = AR8216_PORT_CPU;
1287 swdev->ops = &ar8216_sw_ops;
1288 swdev->ports = AR8216_NUM_PORTS;
1289
1290 if (priv->chip_type == AR8316) {
1291 swdev->name = "Atheros AR8316";
1292 swdev->vlans = AR8X16_MAX_VLANS;
1293
1294 if (priv->port4_phy) {
1295 /* port 5 connected to the other mac, therefore unusable */
1296 swdev->ports = (AR8216_NUM_PORTS - 1);
1297 }
1298 } else if (priv->chip_type == AR8236) {
1299 swdev->name = "Atheros AR8236";
1300 swdev->vlans = AR8216_NUM_VLANS;
1301 swdev->ports = AR8216_NUM_PORTS;
1302 } else if (priv->chip_type == AR8327) {
1303 swdev->name = "Atheros AR8327";
1304 swdev->vlans = AR8X16_MAX_VLANS;
1305 swdev->ports = AR8327_NUM_PORTS;
1306 } else {
1307 swdev->name = "Atheros AR8216";
1308 swdev->vlans = AR8216_NUM_VLANS;
1309 }
1310
1311 ret = register_switch(&priv->dev, pdev->attached_dev);
1312 if (ret)
1313 goto err_free_priv;
1314
1315 priv->init = true;
1316
1317 ret = priv->chip->hw_init(priv);
1318 if (ret)
1319 goto err_free_priv;
1320
1321 ret = ar8216_sw_reset_switch(&priv->dev);
1322 if (ret)
1323 goto err_free_priv;
1324
1325 dev->phy_ptr = priv;
1326
1327 /* VID fixup only needed on ar8216 */
1328 if (pdev->addr == 0 && priv->chip_type == AR8216) {
1329 dev->priv_flags |= IFF_NO_IP_ALIGN;
1330 dev->eth_mangle_rx = ar8216_mangle_rx;
1331 dev->eth_mangle_tx = ar8216_mangle_tx;
1332 }
1333
1334 priv->init = false;
1335
1336 return 0;
1337
1338 err_free_priv:
1339 kfree(priv);
1340 return ret;
1341 }
1342
1343 static int
1344 ar8216_read_status(struct phy_device *phydev)
1345 {
1346 struct ar8216_priv *priv = phydev->priv;
1347 struct switch_port_link link;
1348 int ret;
1349
1350 if (phydev->addr != 0)
1351 return genphy_read_status(phydev);
1352
1353 ar8216_read_port_link(priv, phydev->addr, &link);
1354 phydev->link = !!link.link;
1355 if (!phydev->link)
1356 return 0;
1357
1358 switch (link.speed) {
1359 case SWITCH_PORT_SPEED_10:
1360 phydev->speed = SPEED_10;
1361 break;
1362 case SWITCH_PORT_SPEED_100:
1363 phydev->speed = SPEED_100;
1364 break;
1365 case SWITCH_PORT_SPEED_1000:
1366 phydev->speed = SPEED_1000;
1367 break;
1368 default:
1369 phydev->speed = 0;
1370 }
1371 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1372
1373 /* flush the address translation unit */
1374 mutex_lock(&priv->reg_mutex);
1375 ret = priv->chip->atu_flush(priv);
1376 mutex_unlock(&priv->reg_mutex);
1377
1378 phydev->state = PHY_RUNNING;
1379 netif_carrier_on(phydev->attached_dev);
1380 phydev->adjust_link(phydev->attached_dev);
1381
1382 return ret;
1383 }
1384
1385 static int
1386 ar8216_config_aneg(struct phy_device *phydev)
1387 {
1388 if (phydev->addr == 0)
1389 return 0;
1390
1391 return genphy_config_aneg(phydev);
1392 }
1393
1394 static int
1395 ar8216_probe(struct phy_device *pdev)
1396 {
1397 struct ar8216_priv priv;
1398
1399 priv.phy = pdev;
1400 return ar8216_id_chip(&priv);
1401 }
1402
1403 static void
1404 ar8216_remove(struct phy_device *pdev)
1405 {
1406 struct ar8216_priv *priv = pdev->priv;
1407 struct net_device *dev = pdev->attached_dev;
1408
1409 if (!priv)
1410 return;
1411
1412 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
1413 dev->eth_mangle_rx = NULL;
1414 dev->eth_mangle_tx = NULL;
1415
1416 if (pdev->addr == 0)
1417 unregister_switch(&priv->dev);
1418 kfree(priv);
1419 }
1420
1421 static struct phy_driver ar8216_driver = {
1422 .phy_id = 0x004d0000,
1423 .name = "Atheros AR8216/AR8236/AR8316",
1424 .phy_id_mask = 0xffff0000,
1425 .features = PHY_BASIC_FEATURES,
1426 .probe = ar8216_probe,
1427 .remove = ar8216_remove,
1428 .config_init = &ar8216_config_init,
1429 .config_aneg = &ar8216_config_aneg,
1430 .read_status = &ar8216_read_status,
1431 .driver = { .owner = THIS_MODULE },
1432 };
1433
1434 int __init
1435 ar8216_init(void)
1436 {
1437 return phy_driver_register(&ar8216_driver);
1438 }
1439
1440 void __exit
1441 ar8216_exit(void)
1442 {
1443 phy_driver_unregister(&ar8216_driver);
1444 }
1445
1446 module_init(ar8216_init);
1447 module_exit(ar8216_exit);
1448 MODULE_LICENSE("GPL");
1449
Staging tree of Jo-Philipp Wich