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generic: 6.6: refresh backport patches
[openwrt/openwrt.git] / target / linux / generic / backport-6.6 / 716-v6.9-07-net-phy-qcom-add-support-for-QCA807x-PHY-Family.patch
1 From d1cb613efbd3cd7d0c000167816beb3f248f5eb8 Mon Sep 17 00:00:00 2001
2 From: Robert Marko <robert.marko@sartura.hr>
3 Date: Tue, 6 Feb 2024 18:31:10 +0100
4 Subject: [PATCH 07/10] net: phy: qcom: add support for QCA807x PHY Family
5
6 This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s.
7
8 They are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te,
9 100BASE-TX and 1000BASE-T PHY-s.
10
11 They feature 2 SerDes, one for PSGMII or QSGMII connection with
12 MAC, while second one is SGMII for connection to MAC or fiber.
13
14 Both models have a combo port that supports 1000BASE-X and
15 100BASE-FX fiber.
16
17 PHY package can be configured in 3 mode following this table:
18
19 First Serdes mode Second Serdes mode
20 Option 1 PSGMII for copper Disabled
21 ports 0-4
22 Option 2 PSGMII for copper 1000BASE-X / 100BASE-FX
23 ports 0-4
24 Option 3 QSGMII for copper SGMII for
25 ports 0-3 copper port 4
26
27 Each PHY inside of QCA807x series has 4 digitally controlled
28 output only pins that natively drive LED-s.
29 But some vendors used these to driver generic LED-s controlled
30 by userspace, so lets enable registering each PHY as GPIO
31 controller and add driver for it.
32
33 These are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x
34 boards.
35
36 Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
37 Signed-off-by: Robert Marko <robert.marko@sartura.hr>
38 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
39 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
40 Signed-off-by: David S. Miller <davem@davemloft.net>
41 ---
42 drivers/net/phy/qcom/Kconfig | 8 +
43 drivers/net/phy/qcom/Makefile | 1 +
44 drivers/net/phy/qcom/qca807x.c | 597 +++++++++++++++++++++++++++++++++
45 3 files changed, 606 insertions(+)
46 create mode 100644 drivers/net/phy/qcom/qca807x.c
47
48 --- a/drivers/net/phy/qcom/Kconfig
49 +++ b/drivers/net/phy/qcom/Kconfig
50 @@ -20,3 +20,11 @@ config QCA808X_PHY
51 select QCOM_NET_PHYLIB
52 help
53 Currently supports the QCA8081 model
54 +
55 +config QCA807X_PHY
56 + tristate "Qualcomm QCA807x PHYs"
57 + select QCOM_NET_PHYLIB
58 + depends on OF_MDIO
59 + help
60 + Currently supports the Qualcomm QCA8072, QCA8075 and the PSGMII
61 + control PHY.
62 --- a/drivers/net/phy/qcom/Makefile
63 +++ b/drivers/net/phy/qcom/Makefile
64 @@ -3,3 +3,4 @@ obj-$(CONFIG_QCOM_NET_PHYLIB) += qcom-ph
65 obj-$(CONFIG_AT803X_PHY) += at803x.o
66 obj-$(CONFIG_QCA83XX_PHY) += qca83xx.o
67 obj-$(CONFIG_QCA808X_PHY) += qca808x.o
68 +obj-$(CONFIG_QCA807X_PHY) += qca807x.o
69 --- /dev/null
70 +++ b/drivers/net/phy/qcom/qca807x.c
71 @@ -0,0 +1,597 @@
72 +// SPDX-License-Identifier: GPL-2.0-or-later
73 +/*
74 + * Copyright (c) 2023 Sartura Ltd.
75 + *
76 + * Author: Robert Marko <robert.marko@sartura.hr>
77 + * Christian Marangi <ansuelsmth@gmail.com>
78 + *
79 + * Qualcomm QCA8072 and QCA8075 PHY driver
80 + */
81 +
82 +#include <linux/module.h>
83 +#include <linux/of.h>
84 +#include <linux/phy.h>
85 +#include <linux/bitfield.h>
86 +#include <linux/gpio/driver.h>
87 +#include <linux/sfp.h>
88 +
89 +#include "qcom.h"
90 +
91 +#define QCA807X_CHIP_CONFIGURATION 0x1f
92 +#define QCA807X_BT_BX_REG_SEL BIT(15)
93 +#define QCA807X_BT_BX_REG_SEL_FIBER 0
94 +#define QCA807X_BT_BX_REG_SEL_COPPER 1
95 +#define QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK GENMASK(3, 0)
96 +#define QCA807X_CHIP_CONFIGURATION_MODE_QSGMII_SGMII 4
97 +#define QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_FIBER 3
98 +#define QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_ALL_COPPER 0
99 +
100 +#define QCA807X_MEDIA_SELECT_STATUS 0x1a
101 +#define QCA807X_MEDIA_DETECTED_COPPER BIT(5)
102 +#define QCA807X_MEDIA_DETECTED_1000_BASE_X BIT(4)
103 +#define QCA807X_MEDIA_DETECTED_100_BASE_FX BIT(3)
104 +
105 +#define QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION 0x807e
106 +#define QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION_EN BIT(0)
107 +
108 +#define QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH 0x801a
109 +#define QCA807X_CONTROL_DAC_MASK GENMASK(2, 0)
110 +/* List of tweaks enabled by this bit:
111 + * - With both FULL amplitude and FULL bias current: bias current
112 + * is set to half.
113 + * - With only DSP amplitude: bias current is set to half and
114 + * is set to 1/4 with cable < 10m.
115 + * - With DSP bias current (included both DSP amplitude and
116 + * DSP bias current): bias current is half the detected current
117 + * with cable < 10m.
118 + */
119 +#define QCA807X_CONTROL_DAC_BIAS_CURRENT_TWEAK BIT(2)
120 +#define QCA807X_CONTROL_DAC_DSP_BIAS_CURRENT BIT(1)
121 +#define QCA807X_CONTROL_DAC_DSP_AMPLITUDE BIT(0)
122 +
123 +#define QCA807X_MMD7_LED_100N_1 0x8074
124 +#define QCA807X_MMD7_LED_100N_2 0x8075
125 +#define QCA807X_MMD7_LED_1000N_1 0x8076
126 +#define QCA807X_MMD7_LED_1000N_2 0x8077
127 +
128 +#define QCA807X_MMD7_LED_CTRL(x) (0x8074 + ((x) * 2))
129 +#define QCA807X_MMD7_LED_FORCE_CTRL(x) (0x8075 + ((x) * 2))
130 +
131 +#define QCA807X_GPIO_FORCE_EN BIT(15)
132 +#define QCA807X_GPIO_FORCE_MODE_MASK GENMASK(14, 13)
133 +
134 +#define QCA807X_FUNCTION_CONTROL 0x10
135 +#define QCA807X_FC_MDI_CROSSOVER_MODE_MASK GENMASK(6, 5)
136 +#define QCA807X_FC_MDI_CROSSOVER_AUTO 3
137 +#define QCA807X_FC_MDI_CROSSOVER_MANUAL_MDIX 1
138 +#define QCA807X_FC_MDI_CROSSOVER_MANUAL_MDI 0
139 +
140 +/* PQSGMII Analog PHY specific */
141 +#define PQSGMII_CTRL_REG 0x0
142 +#define PQSGMII_ANALOG_SW_RESET BIT(6)
143 +#define PQSGMII_DRIVE_CONTROL_1 0xb
144 +#define PQSGMII_TX_DRIVER_MASK GENMASK(7, 4)
145 +#define PQSGMII_TX_DRIVER_140MV 0x0
146 +#define PQSGMII_TX_DRIVER_160MV 0x1
147 +#define PQSGMII_TX_DRIVER_180MV 0x2
148 +#define PQSGMII_TX_DRIVER_200MV 0x3
149 +#define PQSGMII_TX_DRIVER_220MV 0x4
150 +#define PQSGMII_TX_DRIVER_240MV 0x5
151 +#define PQSGMII_TX_DRIVER_260MV 0x6
152 +#define PQSGMII_TX_DRIVER_280MV 0x7
153 +#define PQSGMII_TX_DRIVER_300MV 0x8
154 +#define PQSGMII_TX_DRIVER_320MV 0x9
155 +#define PQSGMII_TX_DRIVER_400MV 0xa
156 +#define PQSGMII_TX_DRIVER_500MV 0xb
157 +#define PQSGMII_TX_DRIVER_600MV 0xc
158 +#define PQSGMII_MODE_CTRL 0x6d
159 +#define PQSGMII_MODE_CTRL_AZ_WORKAROUND_MASK BIT(0)
160 +#define PQSGMII_MMD3_SERDES_CONTROL 0x805a
161 +
162 +#define PHY_ID_QCA8072 0x004dd0b2
163 +#define PHY_ID_QCA8075 0x004dd0b1
164 +
165 +#define QCA807X_COMBO_ADDR_OFFSET 4
166 +#define QCA807X_PQSGMII_ADDR_OFFSET 5
167 +#define SERDES_RESET_SLEEP 100
168 +
169 +enum qca807x_global_phy {
170 + QCA807X_COMBO_ADDR = 4,
171 + QCA807X_PQSGMII_ADDR = 5,
172 +};
173 +
174 +struct qca807x_shared_priv {
175 + unsigned int package_mode;
176 + u32 tx_drive_strength;
177 +};
178 +
179 +struct qca807x_gpio_priv {
180 + struct phy_device *phy;
181 +};
182 +
183 +struct qca807x_priv {
184 + bool dac_full_amplitude;
185 + bool dac_full_bias_current;
186 + bool dac_disable_bias_current_tweak;
187 +};
188 +
189 +static int qca807x_cable_test_start(struct phy_device *phydev)
190 +{
191 + /* we do all the (time consuming) work later */
192 + return 0;
193 +}
194 +
195 +#ifdef CONFIG_GPIOLIB
196 +static int qca807x_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
197 +{
198 + return GPIO_LINE_DIRECTION_OUT;
199 +}
200 +
201 +static int qca807x_gpio_get(struct gpio_chip *gc, unsigned int offset)
202 +{
203 + struct qca807x_gpio_priv *priv = gpiochip_get_data(gc);
204 + u16 reg;
205 + int val;
206 +
207 + reg = QCA807X_MMD7_LED_FORCE_CTRL(offset);
208 + val = phy_read_mmd(priv->phy, MDIO_MMD_AN, reg);
209 +
210 + return FIELD_GET(QCA807X_GPIO_FORCE_MODE_MASK, val);
211 +}
212 +
213 +static void qca807x_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
214 +{
215 + struct qca807x_gpio_priv *priv = gpiochip_get_data(gc);
216 + u16 reg;
217 + int val;
218 +
219 + reg = QCA807X_MMD7_LED_FORCE_CTRL(offset);
220 +
221 + val = phy_read_mmd(priv->phy, MDIO_MMD_AN, reg);
222 + val &= ~QCA807X_GPIO_FORCE_MODE_MASK;
223 + val |= QCA807X_GPIO_FORCE_EN;
224 + val |= FIELD_PREP(QCA807X_GPIO_FORCE_MODE_MASK, value);
225 +
226 + phy_write_mmd(priv->phy, MDIO_MMD_AN, reg, val);
227 +}
228 +
229 +static int qca807x_gpio_dir_out(struct gpio_chip *gc, unsigned int offset, int value)
230 +{
231 + qca807x_gpio_set(gc, offset, value);
232 +
233 + return 0;
234 +}
235 +
236 +static int qca807x_gpio(struct phy_device *phydev)
237 +{
238 + struct device *dev = &phydev->mdio.dev;
239 + struct qca807x_gpio_priv *priv;
240 + struct gpio_chip *gc;
241 +
242 + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
243 + if (!priv)
244 + return -ENOMEM;
245 +
246 + priv->phy = phydev;
247 +
248 + gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
249 + if (!gc)
250 + return -ENOMEM;
251 +
252 + gc->label = dev_name(dev);
253 + gc->base = -1;
254 + gc->ngpio = 2;
255 + gc->parent = dev;
256 + gc->owner = THIS_MODULE;
257 + gc->can_sleep = true;
258 + gc->get_direction = qca807x_gpio_get_direction;
259 + gc->direction_output = qca807x_gpio_dir_out;
260 + gc->get = qca807x_gpio_get;
261 + gc->set = qca807x_gpio_set;
262 +
263 + return devm_gpiochip_add_data(dev, gc, priv);
264 +}
265 +#endif
266 +
267 +static int qca807x_read_fiber_status(struct phy_device *phydev)
268 +{
269 + bool changed;
270 + int ss, err;
271 +
272 + err = genphy_c37_read_status(phydev, &changed);
273 + if (err || !changed)
274 + return err;
275 +
276 + /* Read the QCA807x PHY-Specific Status register fiber page,
277 + * which indicates the speed and duplex that the PHY is actually
278 + * using, irrespective of whether we are in autoneg mode or not.
279 + */
280 + ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
281 + if (ss < 0)
282 + return ss;
283 +
284 + phydev->speed = SPEED_UNKNOWN;
285 + phydev->duplex = DUPLEX_UNKNOWN;
286 + if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
287 + switch (FIELD_GET(AT803X_SS_SPEED_MASK, ss)) {
288 + case AT803X_SS_SPEED_100:
289 + phydev->speed = SPEED_100;
290 + break;
291 + case AT803X_SS_SPEED_1000:
292 + phydev->speed = SPEED_1000;
293 + break;
294 + }
295 +
296 + if (ss & AT803X_SS_DUPLEX)
297 + phydev->duplex = DUPLEX_FULL;
298 + else
299 + phydev->duplex = DUPLEX_HALF;
300 + }
301 +
302 + return 0;
303 +}
304 +
305 +static int qca807x_read_status(struct phy_device *phydev)
306 +{
307 + if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) {
308 + switch (phydev->port) {
309 + case PORT_FIBRE:
310 + return qca807x_read_fiber_status(phydev);
311 + case PORT_TP:
312 + return at803x_read_status(phydev);
313 + default:
314 + return -EINVAL;
315 + }
316 + }
317 +
318 + return at803x_read_status(phydev);
319 +}
320 +
321 +static int qca807x_phy_package_probe_once(struct phy_device *phydev)
322 +{
323 + struct phy_package_shared *shared = phydev->shared;
324 + struct qca807x_shared_priv *priv = shared->priv;
325 + unsigned int tx_drive_strength;
326 + const char *package_mode_name;
327 +
328 + /* Default to 600mw if not defined */
329 + if (of_property_read_u32(shared->np, "qcom,tx-drive-strength-milliwatt",
330 + &tx_drive_strength))
331 + tx_drive_strength = 600;
332 +
333 + switch (tx_drive_strength) {
334 + case 140:
335 + priv->tx_drive_strength = PQSGMII_TX_DRIVER_140MV;
336 + break;
337 + case 160:
338 + priv->tx_drive_strength = PQSGMII_TX_DRIVER_160MV;
339 + break;
340 + case 180:
341 + priv->tx_drive_strength = PQSGMII_TX_DRIVER_180MV;
342 + break;
343 + case 200:
344 + priv->tx_drive_strength = PQSGMII_TX_DRIVER_200MV;
345 + break;
346 + case 220:
347 + priv->tx_drive_strength = PQSGMII_TX_DRIVER_220MV;
348 + break;
349 + case 240:
350 + priv->tx_drive_strength = PQSGMII_TX_DRIVER_240MV;
351 + break;
352 + case 260:
353 + priv->tx_drive_strength = PQSGMII_TX_DRIVER_260MV;
354 + break;
355 + case 280:
356 + priv->tx_drive_strength = PQSGMII_TX_DRIVER_280MV;
357 + break;
358 + case 300:
359 + priv->tx_drive_strength = PQSGMII_TX_DRIVER_300MV;
360 + break;
361 + case 320:
362 + priv->tx_drive_strength = PQSGMII_TX_DRIVER_320MV;
363 + break;
364 + case 400:
365 + priv->tx_drive_strength = PQSGMII_TX_DRIVER_400MV;
366 + break;
367 + case 500:
368 + priv->tx_drive_strength = PQSGMII_TX_DRIVER_500MV;
369 + break;
370 + case 600:
371 + priv->tx_drive_strength = PQSGMII_TX_DRIVER_600MV;
372 + break;
373 + default:
374 + return -EINVAL;
375 + }
376 +
377 + priv->package_mode = PHY_INTERFACE_MODE_NA;
378 + if (!of_property_read_string(shared->np, "qcom,package-mode",
379 + &package_mode_name)) {
380 + if (!strcasecmp(package_mode_name,
381 + phy_modes(PHY_INTERFACE_MODE_PSGMII)))
382 + priv->package_mode = PHY_INTERFACE_MODE_PSGMII;
383 + else if (!strcasecmp(package_mode_name,
384 + phy_modes(PHY_INTERFACE_MODE_QSGMII)))
385 + priv->package_mode = PHY_INTERFACE_MODE_QSGMII;
386 + else
387 + return -EINVAL;
388 + }
389 +
390 + return 0;
391 +}
392 +
393 +static int qca807x_phy_package_config_init_once(struct phy_device *phydev)
394 +{
395 + struct phy_package_shared *shared = phydev->shared;
396 + struct qca807x_shared_priv *priv = shared->priv;
397 + int val, ret;
398 +
399 + phy_lock_mdio_bus(phydev);
400 +
401 + /* Set correct PHY package mode */
402 + val = __phy_package_read(phydev, QCA807X_COMBO_ADDR,
403 + QCA807X_CHIP_CONFIGURATION);
404 + val &= ~QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK;
405 + /* package_mode can be QSGMII or PSGMII and we validate
406 + * this in probe_once.
407 + * With package_mode to NA, we default to PSGMII.
408 + */
409 + switch (priv->package_mode) {
410 + case PHY_INTERFACE_MODE_QSGMII:
411 + val |= QCA807X_CHIP_CONFIGURATION_MODE_QSGMII_SGMII;
412 + break;
413 + case PHY_INTERFACE_MODE_PSGMII:
414 + default:
415 + val |= QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_ALL_COPPER;
416 + }
417 + ret = __phy_package_write(phydev, QCA807X_COMBO_ADDR,
418 + QCA807X_CHIP_CONFIGURATION, val);
419 + if (ret)
420 + goto exit;
421 +
422 + /* After mode change Serdes reset is required */
423 + val = __phy_package_read(phydev, QCA807X_PQSGMII_ADDR,
424 + PQSGMII_CTRL_REG);
425 + val &= ~PQSGMII_ANALOG_SW_RESET;
426 + ret = __phy_package_write(phydev, QCA807X_PQSGMII_ADDR,
427 + PQSGMII_CTRL_REG, val);
428 + if (ret)
429 + goto exit;
430 +
431 + msleep(SERDES_RESET_SLEEP);
432 +
433 + val = __phy_package_read(phydev, QCA807X_PQSGMII_ADDR,
434 + PQSGMII_CTRL_REG);
435 + val |= PQSGMII_ANALOG_SW_RESET;
436 + ret = __phy_package_write(phydev, QCA807X_PQSGMII_ADDR,
437 + PQSGMII_CTRL_REG, val);
438 + if (ret)
439 + goto exit;
440 +
441 + /* Workaround to enable AZ transmitting ability */
442 + val = __phy_package_read_mmd(phydev, QCA807X_PQSGMII_ADDR,
443 + MDIO_MMD_PMAPMD, PQSGMII_MODE_CTRL);
444 + val &= ~PQSGMII_MODE_CTRL_AZ_WORKAROUND_MASK;
445 + ret = __phy_package_write_mmd(phydev, QCA807X_PQSGMII_ADDR,
446 + MDIO_MMD_PMAPMD, PQSGMII_MODE_CTRL, val);
447 + if (ret)
448 + goto exit;
449 +
450 + /* Set PQSGMII TX AMP strength */
451 + val = __phy_package_read(phydev, QCA807X_PQSGMII_ADDR,
452 + PQSGMII_DRIVE_CONTROL_1);
453 + val &= ~PQSGMII_TX_DRIVER_MASK;
454 + val |= FIELD_PREP(PQSGMII_TX_DRIVER_MASK, priv->tx_drive_strength);
455 + ret = __phy_package_write(phydev, QCA807X_PQSGMII_ADDR,
456 + PQSGMII_DRIVE_CONTROL_1, val);
457 + if (ret)
458 + goto exit;
459 +
460 + /* Prevent PSGMII going into hibernation via PSGMII self test */
461 + val = __phy_package_read_mmd(phydev, QCA807X_COMBO_ADDR,
462 + MDIO_MMD_PCS, PQSGMII_MMD3_SERDES_CONTROL);
463 + val &= ~BIT(1);
464 + ret = __phy_package_write_mmd(phydev, QCA807X_COMBO_ADDR,
465 + MDIO_MMD_PCS, PQSGMII_MMD3_SERDES_CONTROL, val);
466 +
467 +exit:
468 + phy_unlock_mdio_bus(phydev);
469 +
470 + return ret;
471 +}
472 +
473 +static int qca807x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
474 +{
475 + struct phy_device *phydev = upstream;
476 + __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };
477 + phy_interface_t iface;
478 + int ret;
479 + DECLARE_PHY_INTERFACE_MASK(interfaces);
480 +
481 + sfp_parse_support(phydev->sfp_bus, id, support, interfaces);
482 + iface = sfp_select_interface(phydev->sfp_bus, support);
483 +
484 + dev_info(&phydev->mdio.dev, "%s SFP module inserted\n", phy_modes(iface));
485 +
486 + switch (iface) {
487 + case PHY_INTERFACE_MODE_1000BASEX:
488 + case PHY_INTERFACE_MODE_100BASEX:
489 + /* Set PHY mode to PSGMII combo (1/4 copper + combo ports) mode */
490 + ret = phy_modify(phydev,
491 + QCA807X_CHIP_CONFIGURATION,
492 + QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK,
493 + QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_FIBER);
494 + /* Enable fiber mode autodection (1000Base-X or 100Base-FX) */
495 + ret = phy_set_bits_mmd(phydev,
496 + MDIO_MMD_AN,
497 + QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION,
498 + QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION_EN);
499 + /* Select fiber page */
500 + ret = phy_clear_bits(phydev,
501 + QCA807X_CHIP_CONFIGURATION,
502 + QCA807X_BT_BX_REG_SEL);
503 +
504 + phydev->port = PORT_FIBRE;
505 + break;
506 + default:
507 + dev_err(&phydev->mdio.dev, "Incompatible SFP module inserted\n");
508 + return -EINVAL;
509 + }
510 +
511 + return ret;
512 +}
513 +
514 +static void qca807x_sfp_remove(void *upstream)
515 +{
516 + struct phy_device *phydev = upstream;
517 +
518 + /* Select copper page */
519 + phy_set_bits(phydev,
520 + QCA807X_CHIP_CONFIGURATION,
521 + QCA807X_BT_BX_REG_SEL);
522 +
523 + phydev->port = PORT_TP;
524 +}
525 +
526 +static const struct sfp_upstream_ops qca807x_sfp_ops = {
527 + .attach = phy_sfp_attach,
528 + .detach = phy_sfp_detach,
529 + .module_insert = qca807x_sfp_insert,
530 + .module_remove = qca807x_sfp_remove,
531 +};
532 +
533 +static int qca807x_probe(struct phy_device *phydev)
534 +{
535 + struct device_node *node = phydev->mdio.dev.of_node;
536 + struct qca807x_shared_priv *shared_priv;
537 + struct device *dev = &phydev->mdio.dev;
538 + struct phy_package_shared *shared;
539 + struct qca807x_priv *priv;
540 + int ret;
541 +
542 + ret = devm_of_phy_package_join(dev, phydev, sizeof(*shared_priv));
543 + if (ret)
544 + return ret;
545 +
546 + if (phy_package_probe_once(phydev)) {
547 + ret = qca807x_phy_package_probe_once(phydev);
548 + if (ret)
549 + return ret;
550 + }
551 +
552 + shared = phydev->shared;
553 + shared_priv = shared->priv;
554 +
555 + /* Make sure PHY follow PHY package mode if enforced */
556 + if (shared_priv->package_mode != PHY_INTERFACE_MODE_NA &&
557 + phydev->interface != shared_priv->package_mode)
558 + return -EINVAL;
559 +
560 + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
561 + if (!priv)
562 + return -ENOMEM;
563 +
564 + priv->dac_full_amplitude = of_property_read_bool(node, "qcom,dac-full-amplitude");
565 + priv->dac_full_bias_current = of_property_read_bool(node, "qcom,dac-full-bias-current");
566 + priv->dac_disable_bias_current_tweak = of_property_read_bool(node,
567 + "qcom,dac-disable-bias-current-tweak");
568 +
569 + if (IS_ENABLED(CONFIG_GPIOLIB)) {
570 + /* Do not register a GPIO controller unless flagged for it */
571 + if (of_property_read_bool(node, "gpio-controller")) {
572 + ret = qca807x_gpio(phydev);
573 + if (ret)
574 + return ret;
575 + }
576 + }
577 +
578 + /* Attach SFP bus on combo port*/
579 + if (phy_read(phydev, QCA807X_CHIP_CONFIGURATION)) {
580 + ret = phy_sfp_probe(phydev, &qca807x_sfp_ops);
581 + if (ret)
582 + return ret;
583 + linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);
584 + linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->advertising);
585 + }
586 +
587 + phydev->priv = priv;
588 +
589 + return 0;
590 +}
591 +
592 +static int qca807x_config_init(struct phy_device *phydev)
593 +{
594 + struct qca807x_priv *priv = phydev->priv;
595 + u16 control_dac;
596 + int ret;
597 +
598 + if (phy_package_init_once(phydev)) {
599 + ret = qca807x_phy_package_config_init_once(phydev);
600 + if (ret)
601 + return ret;
602 + }
603 +
604 + control_dac = phy_read_mmd(phydev, MDIO_MMD_AN,
605 + QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH);
606 + control_dac &= ~QCA807X_CONTROL_DAC_MASK;
607 + if (!priv->dac_full_amplitude)
608 + control_dac |= QCA807X_CONTROL_DAC_DSP_AMPLITUDE;
609 + if (!priv->dac_full_amplitude)
610 + control_dac |= QCA807X_CONTROL_DAC_DSP_BIAS_CURRENT;
611 + if (!priv->dac_disable_bias_current_tweak)
612 + control_dac |= QCA807X_CONTROL_DAC_BIAS_CURRENT_TWEAK;
613 + return phy_write_mmd(phydev, MDIO_MMD_AN,
614 + QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH,
615 + control_dac);
616 +}
617 +
618 +static struct phy_driver qca807x_drivers[] = {
619 + {
620 + PHY_ID_MATCH_EXACT(PHY_ID_QCA8072),
621 + .name = "Qualcomm QCA8072",
622 + .flags = PHY_POLL_CABLE_TEST,
623 + /* PHY_GBIT_FEATURES */
624 + .probe = qca807x_probe,
625 + .config_init = qca807x_config_init,
626 + .read_status = qca807x_read_status,
627 + .config_intr = at803x_config_intr,
628 + .handle_interrupt = at803x_handle_interrupt,
629 + .soft_reset = genphy_soft_reset,
630 + .get_tunable = at803x_get_tunable,
631 + .set_tunable = at803x_set_tunable,
632 + .resume = genphy_resume,
633 + .suspend = genphy_suspend,
634 + .cable_test_start = qca807x_cable_test_start,
635 + .cable_test_get_status = qca808x_cable_test_get_status,
636 + },
637 + {
638 + PHY_ID_MATCH_EXACT(PHY_ID_QCA8075),
639 + .name = "Qualcomm QCA8075",
640 + .flags = PHY_POLL_CABLE_TEST,
641 + /* PHY_GBIT_FEATURES */
642 + .probe = qca807x_probe,
643 + .config_init = qca807x_config_init,
644 + .read_status = qca807x_read_status,
645 + .config_intr = at803x_config_intr,
646 + .handle_interrupt = at803x_handle_interrupt,
647 + .soft_reset = genphy_soft_reset,
648 + .get_tunable = at803x_get_tunable,
649 + .set_tunable = at803x_set_tunable,
650 + .resume = genphy_resume,
651 + .suspend = genphy_suspend,
652 + .cable_test_start = qca807x_cable_test_start,
653 + .cable_test_get_status = qca808x_cable_test_get_status,
654 + },
655 +};
656 +module_phy_driver(qca807x_drivers);
657 +
658 +static struct mdio_device_id __maybe_unused qca807x_tbl[] = {
659 + { PHY_ID_MATCH_EXACT(PHY_ID_QCA8072) },
660 + { PHY_ID_MATCH_EXACT(PHY_ID_QCA8075) },
661 + { }
662 +};
663 +
664 +MODULE_AUTHOR("Robert Marko <robert.marko@sartura.hr>");
665 +MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
666 +MODULE_DESCRIPTION("Qualcomm QCA807x PHY driver");
667 +MODULE_DEVICE_TABLE(mdio, qca807x_tbl);
668 +MODULE_LICENSE("GPL");
OpenWrt Source Repository