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generic: 6.6: refresh backport patches
[openwrt/openwrt.git] / target / linux / generic / backport-6.6 / 702-01-v6.7-net-phy-aquantia-move-to-separate-directory.patch
1 From d2213db3f49bce8e7a87c8de05b9a091f78f654e Mon Sep 17 00:00:00 2001
2 From: Christian Marangi <ansuelsmth@gmail.com>
3 Date: Tue, 14 Nov 2023 15:08:41 +0100
4 Subject: [PATCH 1/3] net: phy: aquantia: move to separate directory
5
6 Move aquantia PHY driver to separate driectory in preparation for
7 firmware loading support to keep things tidy.
8
9 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
10 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
11 Signed-off-by: David S. Miller <davem@davemloft.net>
12 ---
13 drivers/net/phy/Kconfig | 5 +----
14 drivers/net/phy/Makefile | 6 +-----
15 drivers/net/phy/aquantia/Kconfig | 5 +++++
16 drivers/net/phy/aquantia/Makefile | 6 ++++++
17 drivers/net/phy/{ => aquantia}/aquantia.h | 0
18 drivers/net/phy/{ => aquantia}/aquantia_hwmon.c | 0
19 drivers/net/phy/{ => aquantia}/aquantia_main.c | 0
20 7 files changed, 13 insertions(+), 9 deletions(-)
21 create mode 100644 drivers/net/phy/aquantia/Kconfig
22 create mode 100644 drivers/net/phy/aquantia/Makefile
23 rename drivers/net/phy/{ => aquantia}/aquantia.h (100%)
24 rename drivers/net/phy/{ => aquantia}/aquantia_hwmon.c (100%)
25 rename drivers/net/phy/{ => aquantia}/aquantia_main.c (100%)
26
27 --- a/drivers/net/phy/Kconfig
28 +++ b/drivers/net/phy/Kconfig
29 @@ -96,10 +96,7 @@ config ADIN1100_PHY
30 Currently supports the:
31 - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
32
33 -config AQUANTIA_PHY
34 - tristate "Aquantia PHYs"
35 - help
36 - Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405
37 +source "drivers/net/phy/aquantia/Kconfig"
38
39 config AX88796B_PHY
40 tristate "Asix PHYs"
41 --- a/drivers/net/phy/Makefile
42 +++ b/drivers/net/phy/Makefile
43 @@ -35,11 +35,7 @@ obj-y += $(sfp-obj-y) $(sfp-obj-m)
44 obj-$(CONFIG_ADIN_PHY) += adin.o
45 obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
46 obj-$(CONFIG_AMD_PHY) += amd.o
47 -aquantia-objs += aquantia_main.o
48 -ifdef CONFIG_HWMON
49 -aquantia-objs += aquantia_hwmon.o
50 -endif
51 -obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o
52 +obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
53 obj-$(CONFIG_AT803X_PHY) += at803x.o
54 obj-$(CONFIG_AX88796B_PHY) += ax88796b.o
55 obj-$(CONFIG_BCM54140_PHY) += bcm54140.o
56 --- /dev/null
57 +++ b/drivers/net/phy/aquantia/Kconfig
58 @@ -0,0 +1,5 @@
59 +# SPDX-License-Identifier: GPL-2.0-only
60 +config AQUANTIA_PHY
61 + tristate "Aquantia PHYs"
62 + help
63 + Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405
64 --- /dev/null
65 +++ b/drivers/net/phy/aquantia/Makefile
66 @@ -0,0 +1,6 @@
67 +# SPDX-License-Identifier: GPL-2.0
68 +aquantia-objs += aquantia_main.o
69 +ifdef CONFIG_HWMON
70 +aquantia-objs += aquantia_hwmon.o
71 +endif
72 +obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o
73 --- a/drivers/net/phy/aquantia.h
74 +++ /dev/null
75 @@ -1,16 +0,0 @@
76 -/* SPDX-License-Identifier: GPL-2.0 */
77 -/* HWMON driver for Aquantia PHY
78 - *
79 - * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
80 - * Author: Andrew Lunn <andrew@lunn.ch>
81 - * Author: Heiner Kallweit <hkallweit1@gmail.com>
82 - */
83 -
84 -#include <linux/device.h>
85 -#include <linux/phy.h>
86 -
87 -#if IS_REACHABLE(CONFIG_HWMON)
88 -int aqr_hwmon_probe(struct phy_device *phydev);
89 -#else
90 -static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; }
91 -#endif
92 --- /dev/null
93 +++ b/drivers/net/phy/aquantia/aquantia.h
94 @@ -0,0 +1,16 @@
95 +/* SPDX-License-Identifier: GPL-2.0 */
96 +/* HWMON driver for Aquantia PHY
97 + *
98 + * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
99 + * Author: Andrew Lunn <andrew@lunn.ch>
100 + * Author: Heiner Kallweit <hkallweit1@gmail.com>
101 + */
102 +
103 +#include <linux/device.h>
104 +#include <linux/phy.h>
105 +
106 +#if IS_REACHABLE(CONFIG_HWMON)
107 +int aqr_hwmon_probe(struct phy_device *phydev);
108 +#else
109 +static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; }
110 +#endif
111 --- /dev/null
112 +++ b/drivers/net/phy/aquantia/aquantia_hwmon.c
113 @@ -0,0 +1,250 @@
114 +// SPDX-License-Identifier: GPL-2.0
115 +/* HWMON driver for Aquantia PHY
116 + *
117 + * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
118 + * Author: Andrew Lunn <andrew@lunn.ch>
119 + * Author: Heiner Kallweit <hkallweit1@gmail.com>
120 + */
121 +
122 +#include <linux/phy.h>
123 +#include <linux/device.h>
124 +#include <linux/ctype.h>
125 +#include <linux/hwmon.h>
126 +
127 +#include "aquantia.h"
128 +
129 +/* Vendor specific 1, MDIO_MMD_VEND2 */
130 +#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
131 +#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
132 +#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
133 +#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
134 +#define VEND1_THERMAL_STAT1 0xc820
135 +#define VEND1_THERMAL_STAT2 0xc821
136 +#define VEND1_THERMAL_STAT2_VALID BIT(0)
137 +#define VEND1_GENERAL_STAT1 0xc830
138 +#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
139 +#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
140 +#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
141 +#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
142 +
143 +#if IS_REACHABLE(CONFIG_HWMON)
144 +
145 +static umode_t aqr_hwmon_is_visible(const void *data,
146 + enum hwmon_sensor_types type,
147 + u32 attr, int channel)
148 +{
149 + if (type != hwmon_temp)
150 + return 0;
151 +
152 + switch (attr) {
153 + case hwmon_temp_input:
154 + case hwmon_temp_min_alarm:
155 + case hwmon_temp_max_alarm:
156 + case hwmon_temp_lcrit_alarm:
157 + case hwmon_temp_crit_alarm:
158 + return 0444;
159 + case hwmon_temp_min:
160 + case hwmon_temp_max:
161 + case hwmon_temp_lcrit:
162 + case hwmon_temp_crit:
163 + return 0644;
164 + default:
165 + return 0;
166 + }
167 +}
168 +
169 +static int aqr_hwmon_get(struct phy_device *phydev, int reg, long *value)
170 +{
171 + int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
172 +
173 + if (temp < 0)
174 + return temp;
175 +
176 + /* 16 bit value is 2's complement with LSB = 1/256th degree Celsius */
177 + *value = (s16)temp * 1000 / 256;
178 +
179 + return 0;
180 +}
181 +
182 +static int aqr_hwmon_set(struct phy_device *phydev, int reg, long value)
183 +{
184 + int temp;
185 +
186 + if (value >= 128000 || value < -128000)
187 + return -ERANGE;
188 +
189 + temp = value * 256 / 1000;
190 +
191 + /* temp is in s16 range and we're interested in lower 16 bits only */
192 + return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp);
193 +}
194 +
195 +static int aqr_hwmon_test_bit(struct phy_device *phydev, int reg, int bit)
196 +{
197 + int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
198 +
199 + if (val < 0)
200 + return val;
201 +
202 + return !!(val & bit);
203 +}
204 +
205 +static int aqr_hwmon_status1(struct phy_device *phydev, int bit, long *value)
206 +{
207 + int val = aqr_hwmon_test_bit(phydev, VEND1_GENERAL_STAT1, bit);
208 +
209 + if (val < 0)
210 + return val;
211 +
212 + *value = val;
213 +
214 + return 0;
215 +}
216 +
217 +static int aqr_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
218 + u32 attr, int channel, long *value)
219 +{
220 + struct phy_device *phydev = dev_get_drvdata(dev);
221 + int reg;
222 +
223 + if (type != hwmon_temp)
224 + return -EOPNOTSUPP;
225 +
226 + switch (attr) {
227 + case hwmon_temp_input:
228 + reg = aqr_hwmon_test_bit(phydev, VEND1_THERMAL_STAT2,
229 + VEND1_THERMAL_STAT2_VALID);
230 + if (reg < 0)
231 + return reg;
232 + if (!reg)
233 + return -EBUSY;
234 +
235 + return aqr_hwmon_get(phydev, VEND1_THERMAL_STAT1, value);
236 +
237 + case hwmon_temp_lcrit:
238 + return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
239 + value);
240 + case hwmon_temp_min:
241 + return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
242 + value);
243 + case hwmon_temp_max:
244 + return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
245 + value);
246 + case hwmon_temp_crit:
247 + return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
248 + value);
249 + case hwmon_temp_lcrit_alarm:
250 + return aqr_hwmon_status1(phydev,
251 + VEND1_GENERAL_STAT1_LOW_TEMP_FAIL,
252 + value);
253 + case hwmon_temp_min_alarm:
254 + return aqr_hwmon_status1(phydev,
255 + VEND1_GENERAL_STAT1_LOW_TEMP_WARN,
256 + value);
257 + case hwmon_temp_max_alarm:
258 + return aqr_hwmon_status1(phydev,
259 + VEND1_GENERAL_STAT1_HIGH_TEMP_WARN,
260 + value);
261 + case hwmon_temp_crit_alarm:
262 + return aqr_hwmon_status1(phydev,
263 + VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL,
264 + value);
265 + default:
266 + return -EOPNOTSUPP;
267 + }
268 +}
269 +
270 +static int aqr_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
271 + u32 attr, int channel, long value)
272 +{
273 + struct phy_device *phydev = dev_get_drvdata(dev);
274 +
275 + if (type != hwmon_temp)
276 + return -EOPNOTSUPP;
277 +
278 + switch (attr) {
279 + case hwmon_temp_lcrit:
280 + return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
281 + value);
282 + case hwmon_temp_min:
283 + return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
284 + value);
285 + case hwmon_temp_max:
286 + return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
287 + value);
288 + case hwmon_temp_crit:
289 + return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
290 + value);
291 + default:
292 + return -EOPNOTSUPP;
293 + }
294 +}
295 +
296 +static const struct hwmon_ops aqr_hwmon_ops = {
297 + .is_visible = aqr_hwmon_is_visible,
298 + .read = aqr_hwmon_read,
299 + .write = aqr_hwmon_write,
300 +};
301 +
302 +static u32 aqr_hwmon_chip_config[] = {
303 + HWMON_C_REGISTER_TZ,
304 + 0,
305 +};
306 +
307 +static const struct hwmon_channel_info aqr_hwmon_chip = {
308 + .type = hwmon_chip,
309 + .config = aqr_hwmon_chip_config,
310 +};
311 +
312 +static u32 aqr_hwmon_temp_config[] = {
313 + HWMON_T_INPUT |
314 + HWMON_T_MAX | HWMON_T_MIN |
315 + HWMON_T_MAX_ALARM | HWMON_T_MIN_ALARM |
316 + HWMON_T_CRIT | HWMON_T_LCRIT |
317 + HWMON_T_CRIT_ALARM | HWMON_T_LCRIT_ALARM,
318 + 0,
319 +};
320 +
321 +static const struct hwmon_channel_info aqr_hwmon_temp = {
322 + .type = hwmon_temp,
323 + .config = aqr_hwmon_temp_config,
324 +};
325 +
326 +static const struct hwmon_channel_info * const aqr_hwmon_info[] = {
327 + &aqr_hwmon_chip,
328 + &aqr_hwmon_temp,
329 + NULL,
330 +};
331 +
332 +static const struct hwmon_chip_info aqr_hwmon_chip_info = {
333 + .ops = &aqr_hwmon_ops,
334 + .info = aqr_hwmon_info,
335 +};
336 +
337 +int aqr_hwmon_probe(struct phy_device *phydev)
338 +{
339 + struct device *dev = &phydev->mdio.dev;
340 + struct device *hwmon_dev;
341 + char *hwmon_name;
342 + int i, j;
343 +
344 + hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
345 + if (!hwmon_name)
346 + return -ENOMEM;
347 +
348 + for (i = j = 0; hwmon_name[i]; i++) {
349 + if (isalnum(hwmon_name[i])) {
350 + if (i != j)
351 + hwmon_name[j] = hwmon_name[i];
352 + j++;
353 + }
354 + }
355 + hwmon_name[j] = '\0';
356 +
357 + hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
358 + phydev, &aqr_hwmon_chip_info, NULL);
359 +
360 + return PTR_ERR_OR_ZERO(hwmon_dev);
361 +}
362 +
363 +#endif
364 --- /dev/null
365 +++ b/drivers/net/phy/aquantia/aquantia_main.c
366 @@ -0,0 +1,882 @@
367 +// SPDX-License-Identifier: GPL-2.0
368 +/*
369 + * Driver for Aquantia PHY
370 + *
371 + * Author: Shaohui Xie <Shaohui.Xie@freescale.com>
372 + *
373 + * Copyright 2015 Freescale Semiconductor, Inc.
374 + */
375 +
376 +#include <linux/kernel.h>
377 +#include <linux/module.h>
378 +#include <linux/delay.h>
379 +#include <linux/bitfield.h>
380 +#include <linux/phy.h>
381 +
382 +#include "aquantia.h"
383 +
384 +#define PHY_ID_AQ1202 0x03a1b445
385 +#define PHY_ID_AQ2104 0x03a1b460
386 +#define PHY_ID_AQR105 0x03a1b4a2
387 +#define PHY_ID_AQR106 0x03a1b4d0
388 +#define PHY_ID_AQR107 0x03a1b4e0
389 +#define PHY_ID_AQCS109 0x03a1b5c2
390 +#define PHY_ID_AQR405 0x03a1b4b0
391 +#define PHY_ID_AQR112 0x03a1b662
392 +#define PHY_ID_AQR412 0x03a1b712
393 +#define PHY_ID_AQR113C 0x31c31c12
394 +
395 +#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
396 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
397 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
398 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1
399 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2
400 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3
401 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4
402 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
403 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7
404 +#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
405 +
406 +#define MDIO_AN_VEND_PROV 0xc400
407 +#define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
408 +#define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
409 +#define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11)
410 +#define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10)
411 +#define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4)
412 +#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)
413 +#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
414 +
415 +#define MDIO_AN_TX_VEND_STATUS1 0xc800
416 +#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)
417 +#define MDIO_AN_TX_VEND_STATUS1_10BASET 0
418 +#define MDIO_AN_TX_VEND_STATUS1_100BASETX 1
419 +#define MDIO_AN_TX_VEND_STATUS1_1000BASET 2
420 +#define MDIO_AN_TX_VEND_STATUS1_10GBASET 3
421 +#define MDIO_AN_TX_VEND_STATUS1_2500BASET 4
422 +#define MDIO_AN_TX_VEND_STATUS1_5000BASET 5
423 +#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0)
424 +
425 +#define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00
426 +#define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1)
427 +
428 +#define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01
429 +#define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0)
430 +
431 +#define MDIO_AN_TX_VEND_INT_MASK2 0xd401
432 +#define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
433 +
434 +#define MDIO_AN_RX_LP_STAT1 0xe820
435 +#define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15)
436 +#define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14)
437 +#define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13)
438 +#define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12)
439 +#define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2)
440 +
441 +#define MDIO_AN_RX_LP_STAT4 0xe823
442 +#define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8)
443 +#define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0)
444 +
445 +#define MDIO_AN_RX_VEND_STAT3 0xe832
446 +#define MDIO_AN_RX_VEND_STAT3_AFR BIT(0)
447 +
448 +/* MDIO_MMD_C22EXT */
449 +#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
450 +#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
451 +#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
452 +#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
453 +#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
454 +#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
455 +#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
456 +#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
457 +#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
458 +#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
459 +
460 +/* Vendor specific 1, MDIO_MMD_VEND1 */
461 +#define VEND1_GLOBAL_FW_ID 0x0020
462 +#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
463 +#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
464 +
465 +#define VEND1_GLOBAL_GEN_STAT2 0xc831
466 +#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
467 +
468 +/* The following registers all have similar layouts; first the registers... */
469 +#define VEND1_GLOBAL_CFG_10M 0x0310
470 +#define VEND1_GLOBAL_CFG_100M 0x031b
471 +#define VEND1_GLOBAL_CFG_1G 0x031c
472 +#define VEND1_GLOBAL_CFG_2_5G 0x031d
473 +#define VEND1_GLOBAL_CFG_5G 0x031e
474 +#define VEND1_GLOBAL_CFG_10G 0x031f
475 +/* ...and now the fields */
476 +#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
477 +#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
478 +#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
479 +#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
480 +
481 +#define VEND1_GLOBAL_RSVD_STAT1 0xc885
482 +#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
483 +#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
484 +
485 +#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
486 +#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
487 +#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
488 +
489 +#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
490 +#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
491 +
492 +#define VEND1_GLOBAL_INT_STD_MASK 0xff00
493 +#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
494 +#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
495 +#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
496 +#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
497 +#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
498 +#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
499 +#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
500 +#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
501 +#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
502 +#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
503 +#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
504 +
505 +#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
506 +#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
507 +#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
508 +#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
509 +#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
510 +#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
511 +#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
512 +#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
513 +#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
514 +
515 +/* Sleep and timeout for checking if the Processor-Intensive
516 + * MDIO operation is finished
517 + */
518 +#define AQR107_OP_IN_PROG_SLEEP 1000
519 +#define AQR107_OP_IN_PROG_TIMEOUT 100000
520 +
521 +struct aqr107_hw_stat {
522 + const char *name;
523 + int reg;
524 + int size;
525 +};
526 +
527 +#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
528 +static const struct aqr107_hw_stat aqr107_hw_stats[] = {
529 + SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
530 + SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
531 + SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8),
532 + SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26),
533 + SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26),
534 + SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8),
535 + SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8),
536 + SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
537 + SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
538 + SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
539 +};
540 +#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
541 +
542 +struct aqr107_priv {
543 + u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
544 +};
545 +
546 +static int aqr107_get_sset_count(struct phy_device *phydev)
547 +{
548 + return AQR107_SGMII_STAT_SZ;
549 +}
550 +
551 +static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
552 +{
553 + int i;
554 +
555 + for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)
556 + strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name,
557 + ETH_GSTRING_LEN);
558 +}
559 +
560 +static u64 aqr107_get_stat(struct phy_device *phydev, int index)
561 +{
562 + const struct aqr107_hw_stat *stat = aqr107_hw_stats + index;
563 + int len_l = min(stat->size, 16);
564 + int len_h = stat->size - len_l;
565 + u64 ret;
566 + int val;
567 +
568 + val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
569 + if (val < 0)
570 + return U64_MAX;
571 +
572 + ret = val & GENMASK(len_l - 1, 0);
573 + if (len_h) {
574 + val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
575 + if (val < 0)
576 + return U64_MAX;
577 +
578 + ret += (val & GENMASK(len_h - 1, 0)) << 16;
579 + }
580 +
581 + return ret;
582 +}
583 +
584 +static void aqr107_get_stats(struct phy_device *phydev,
585 + struct ethtool_stats *stats, u64 *data)
586 +{
587 + struct aqr107_priv *priv = phydev->priv;
588 + u64 val;
589 + int i;
590 +
591 + for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {
592 + val = aqr107_get_stat(phydev, i);
593 + if (val == U64_MAX)
594 + phydev_err(phydev, "Reading HW Statistics failed for %s\n",
595 + aqr107_hw_stats[i].name);
596 + else
597 + priv->sgmii_stats[i] += val;
598 +
599 + data[i] = priv->sgmii_stats[i];
600 + }
601 +}
602 +
603 +static int aqr_config_aneg(struct phy_device *phydev)
604 +{
605 + bool changed = false;
606 + u16 reg;
607 + int ret;
608 +
609 + if (phydev->autoneg == AUTONEG_DISABLE)
610 + return genphy_c45_pma_setup_forced(phydev);
611 +
612 + ret = genphy_c45_an_config_aneg(phydev);
613 + if (ret < 0)
614 + return ret;
615 + if (ret > 0)
616 + changed = true;
617 +
618 + /* Clause 45 has no standardized support for 1000BaseT, therefore
619 + * use vendor registers for this mode.
620 + */
621 + reg = 0;
622 + if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
623 + phydev->advertising))
624 + reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
625 +
626 + if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
627 + phydev->advertising))
628 + reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
629 +
630 + /* Handle the case when the 2.5G and 5G speeds are not advertised */
631 + if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
632 + phydev->advertising))
633 + reg |= MDIO_AN_VEND_PROV_2500BASET_FULL;
634 +
635 + if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
636 + phydev->advertising))
637 + reg |= MDIO_AN_VEND_PROV_5000BASET_FULL;
638 +
639 + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
640 + MDIO_AN_VEND_PROV_1000BASET_HALF |
641 + MDIO_AN_VEND_PROV_1000BASET_FULL |
642 + MDIO_AN_VEND_PROV_2500BASET_FULL |
643 + MDIO_AN_VEND_PROV_5000BASET_FULL, reg);
644 + if (ret < 0)
645 + return ret;
646 + if (ret > 0)
647 + changed = true;
648 +
649 + return genphy_c45_check_and_restart_aneg(phydev, changed);
650 +}
651 +
652 +static int aqr_config_intr(struct phy_device *phydev)
653 +{
654 + bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
655 + int err;
656 +
657 + if (en) {
658 + /* Clear any pending interrupts before enabling them */
659 + err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
660 + if (err < 0)
661 + return err;
662 + }
663 +
664 + err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
665 + en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);
666 + if (err < 0)
667 + return err;
668 +
669 + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
670 + en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);
671 + if (err < 0)
672 + return err;
673 +
674 + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
675 + en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
676 + VEND1_GLOBAL_INT_VEND_MASK_AN : 0);
677 + if (err < 0)
678 + return err;
679 +
680 + if (!en) {
681 + /* Clear any pending interrupts after we have disabled them */
682 + err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
683 + if (err < 0)
684 + return err;
685 + }
686 +
687 + return 0;
688 +}
689 +
690 +static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev)
691 +{
692 + int irq_status;
693 +
694 + irq_status = phy_read_mmd(phydev, MDIO_MMD_AN,
695 + MDIO_AN_TX_VEND_INT_STATUS2);
696 + if (irq_status < 0) {
697 + phy_error(phydev);
698 + return IRQ_NONE;
699 + }
700 +
701 + if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK))
702 + return IRQ_NONE;
703 +
704 + phy_trigger_machine(phydev);
705 +
706 + return IRQ_HANDLED;
707 +}
708 +
709 +static int aqr_read_status(struct phy_device *phydev)
710 +{
711 + int val;
712 +
713 + if (phydev->autoneg == AUTONEG_ENABLE) {
714 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
715 + if (val < 0)
716 + return val;
717 +
718 + linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
719 + phydev->lp_advertising,
720 + val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
721 + linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
722 + phydev->lp_advertising,
723 + val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
724 + }
725 +
726 + return genphy_c45_read_status(phydev);
727 +}
728 +
729 +static int aqr107_read_rate(struct phy_device *phydev)
730 +{
731 + u32 config_reg;
732 + int val;
733 +
734 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
735 + if (val < 0)
736 + return val;
737 +
738 + if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
739 + phydev->duplex = DUPLEX_FULL;
740 + else
741 + phydev->duplex = DUPLEX_HALF;
742 +
743 + switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
744 + case MDIO_AN_TX_VEND_STATUS1_10BASET:
745 + phydev->speed = SPEED_10;
746 + config_reg = VEND1_GLOBAL_CFG_10M;
747 + break;
748 + case MDIO_AN_TX_VEND_STATUS1_100BASETX:
749 + phydev->speed = SPEED_100;
750 + config_reg = VEND1_GLOBAL_CFG_100M;
751 + break;
752 + case MDIO_AN_TX_VEND_STATUS1_1000BASET:
753 + phydev->speed = SPEED_1000;
754 + config_reg = VEND1_GLOBAL_CFG_1G;
755 + break;
756 + case MDIO_AN_TX_VEND_STATUS1_2500BASET:
757 + phydev->speed = SPEED_2500;
758 + config_reg = VEND1_GLOBAL_CFG_2_5G;
759 + break;
760 + case MDIO_AN_TX_VEND_STATUS1_5000BASET:
761 + phydev->speed = SPEED_5000;
762 + config_reg = VEND1_GLOBAL_CFG_5G;
763 + break;
764 + case MDIO_AN_TX_VEND_STATUS1_10GBASET:
765 + phydev->speed = SPEED_10000;
766 + config_reg = VEND1_GLOBAL_CFG_10G;
767 + break;
768 + default:
769 + phydev->speed = SPEED_UNKNOWN;
770 + return 0;
771 + }
772 +
773 + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);
774 + if (val < 0)
775 + return val;
776 +
777 + if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) ==
778 + VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)
779 + phydev->rate_matching = RATE_MATCH_PAUSE;
780 + else
781 + phydev->rate_matching = RATE_MATCH_NONE;
782 +
783 + return 0;
784 +}
785 +
786 +static int aqr107_read_status(struct phy_device *phydev)
787 +{
788 + int val, ret;
789 +
790 + ret = aqr_read_status(phydev);
791 + if (ret)
792 + return ret;
793 +
794 + if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
795 + return 0;
796 +
797 + val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
798 + if (val < 0)
799 + return val;
800 +
801 + switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
802 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
803 + phydev->interface = PHY_INTERFACE_MODE_10GKR;
804 + break;
805 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX:
806 + phydev->interface = PHY_INTERFACE_MODE_1000BASEKX;
807 + break;
808 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
809 + phydev->interface = PHY_INTERFACE_MODE_10GBASER;
810 + break;
811 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
812 + phydev->interface = PHY_INTERFACE_MODE_USXGMII;
813 + break;
814 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI:
815 + phydev->interface = PHY_INTERFACE_MODE_XAUI;
816 + break;
817 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
818 + phydev->interface = PHY_INTERFACE_MODE_SGMII;
819 + break;
820 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI:
821 + phydev->interface = PHY_INTERFACE_MODE_RXAUI;
822 + break;
823 + case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
824 + phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
825 + break;
826 + default:
827 + phydev->interface = PHY_INTERFACE_MODE_NA;
828 + break;
829 + }
830 +
831 + /* Read possibly downshifted rate from vendor register */
832 + return aqr107_read_rate(phydev);
833 +}
834 +
835 +static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
836 +{
837 + int val, cnt, enable;
838 +
839 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
840 + if (val < 0)
841 + return val;
842 +
843 + enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
844 + cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
845 +
846 + *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
847 +
848 + return 0;
849 +}
850 +
851 +static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
852 +{
853 + int val = 0;
854 +
855 + if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
856 + return -E2BIG;
857 +
858 + if (cnt != DOWNSHIFT_DEV_DISABLE) {
859 + val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
860 + val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
861 + }
862 +
863 + return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
864 + MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
865 + MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
866 +}
867 +
868 +static int aqr107_get_tunable(struct phy_device *phydev,
869 + struct ethtool_tunable *tuna, void *data)
870 +{
871 + switch (tuna->id) {
872 + case ETHTOOL_PHY_DOWNSHIFT:
873 + return aqr107_get_downshift(phydev, data);
874 + default:
875 + return -EOPNOTSUPP;
876 + }
877 +}
878 +
879 +static int aqr107_set_tunable(struct phy_device *phydev,
880 + struct ethtool_tunable *tuna, const void *data)
881 +{
882 + switch (tuna->id) {
883 + case ETHTOOL_PHY_DOWNSHIFT:
884 + return aqr107_set_downshift(phydev, *(const u8 *)data);
885 + default:
886 + return -EOPNOTSUPP;
887 + }
888 +}
889 +
890 +/* If we configure settings whilst firmware is still initializing the chip,
891 + * then these settings may be overwritten. Therefore make sure chip
892 + * initialization has completed. Use presence of the firmware ID as
893 + * indicator for initialization having completed.
894 + * The chip also provides a "reset completed" bit, but it's cleared after
895 + * read. Therefore function would time out if called again.
896 + */
897 +static int aqr107_wait_reset_complete(struct phy_device *phydev)
898 +{
899 + int val;
900 +
901 + return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
902 + VEND1_GLOBAL_FW_ID, val, val != 0,
903 + 20000, 2000000, false);
904 +}
905 +
906 +static void aqr107_chip_info(struct phy_device *phydev)
907 +{
908 + u8 fw_major, fw_minor, build_id, prov_id;
909 + int val;
910 +
911 + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
912 + if (val < 0)
913 + return;
914 +
915 + fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val);
916 + fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val);
917 +
918 + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
919 + if (val < 0)
920 + return;
921 +
922 + build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
923 + prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
924 +
925 + phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
926 + fw_major, fw_minor, build_id, prov_id);
927 +}
928 +
929 +static int aqr107_config_init(struct phy_device *phydev)
930 +{
931 + int ret;
932 +
933 + /* Check that the PHY interface type is compatible */
934 + if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
935 + phydev->interface != PHY_INTERFACE_MODE_1000BASEKX &&
936 + phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
937 + phydev->interface != PHY_INTERFACE_MODE_XGMII &&
938 + phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
939 + phydev->interface != PHY_INTERFACE_MODE_10GKR &&
940 + phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
941 + phydev->interface != PHY_INTERFACE_MODE_XAUI &&
942 + phydev->interface != PHY_INTERFACE_MODE_RXAUI)
943 + return -ENODEV;
944 +
945 + WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
946 + "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
947 +
948 + ret = aqr107_wait_reset_complete(phydev);
949 + if (!ret)
950 + aqr107_chip_info(phydev);
951 +
952 + return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
953 +}
954 +
955 +static int aqcs109_config_init(struct phy_device *phydev)
956 +{
957 + int ret;
958 +
959 + /* Check that the PHY interface type is compatible */
960 + if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
961 + phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
962 + return -ENODEV;
963 +
964 + ret = aqr107_wait_reset_complete(phydev);
965 + if (!ret)
966 + aqr107_chip_info(phydev);
967 +
968 + /* AQCS109 belongs to a chip family partially supporting 10G and 5G.
969 + * PMA speed ability bits are the same for all members of the family,
970 + * AQCS109 however supports speeds up to 2.5G only.
971 + */
972 + phy_set_max_speed(phydev, SPEED_2500);
973 +
974 + return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
975 +}
976 +
977 +static void aqr107_link_change_notify(struct phy_device *phydev)
978 +{
979 + u8 fw_major, fw_minor;
980 + bool downshift, short_reach, afr;
981 + int mode, val;
982 +
983 + if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
984 + return;
985 +
986 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
987 + /* call failed or link partner is no Aquantia PHY */
988 + if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
989 + return;
990 +
991 + short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
992 + downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
993 +
994 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
995 + if (val < 0)
996 + return;
997 +
998 + fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
999 + fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
1000 +
1001 + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
1002 + if (val < 0)
1003 + return;
1004 +
1005 + afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
1006 +
1007 + phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
1008 + fw_major, fw_minor,
1009 + short_reach ? ", short reach mode" : "",
1010 + downshift ? ", fast-retrain downshift advertised" : "",
1011 + afr ? ", fast reframe advertised" : "");
1012 +
1013 + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
1014 + if (val < 0)
1015 + return;
1016 +
1017 + mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
1018 + if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
1019 + phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
1020 +}
1021 +
1022 +static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
1023 +{
1024 + int val, err;
1025 +
1026 + /* The datasheet notes to wait at least 1ms after issuing a
1027 + * processor intensive operation before checking.
1028 + * We cannot use the 'sleep_before_read' parameter of read_poll_timeout
1029 + * because that just determines the maximum time slept, not the minimum.
1030 + */
1031 + usleep_range(1000, 5000);
1032 +
1033 + err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
1034 + VEND1_GLOBAL_GEN_STAT2, val,
1035 + !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG),
1036 + AQR107_OP_IN_PROG_SLEEP,
1037 + AQR107_OP_IN_PROG_TIMEOUT, false);
1038 + if (err) {
1039 + phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");
1040 + return err;
1041 + }
1042 +
1043 + return 0;
1044 +}
1045 +
1046 +static int aqr107_get_rate_matching(struct phy_device *phydev,
1047 + phy_interface_t iface)
1048 +{
1049 + if (iface == PHY_INTERFACE_MODE_10GBASER ||
1050 + iface == PHY_INTERFACE_MODE_2500BASEX ||
1051 + iface == PHY_INTERFACE_MODE_NA)
1052 + return RATE_MATCH_PAUSE;
1053 + return RATE_MATCH_NONE;
1054 +}
1055 +
1056 +static int aqr107_suspend(struct phy_device *phydev)
1057 +{
1058 + int err;
1059 +
1060 + err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
1061 + MDIO_CTRL1_LPOWER);
1062 + if (err)
1063 + return err;
1064 +
1065 + return aqr107_wait_processor_intensive_op(phydev);
1066 +}
1067 +
1068 +static int aqr107_resume(struct phy_device *phydev)
1069 +{
1070 + int err;
1071 +
1072 + err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
1073 + MDIO_CTRL1_LPOWER);
1074 + if (err)
1075 + return err;
1076 +
1077 + return aqr107_wait_processor_intensive_op(phydev);
1078 +}
1079 +
1080 +static int aqr107_probe(struct phy_device *phydev)
1081 +{
1082 + phydev->priv = devm_kzalloc(&phydev->mdio.dev,
1083 + sizeof(struct aqr107_priv), GFP_KERNEL);
1084 + if (!phydev->priv)
1085 + return -ENOMEM;
1086 +
1087 + return aqr_hwmon_probe(phydev);
1088 +}
1089 +
1090 +static struct phy_driver aqr_driver[] = {
1091 +{
1092 + PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
1093 + .name = "Aquantia AQ1202",
1094 + .config_aneg = aqr_config_aneg,
1095 + .config_intr = aqr_config_intr,
1096 + .handle_interrupt = aqr_handle_interrupt,
1097 + .read_status = aqr_read_status,
1098 +},
1099 +{
1100 + PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
1101 + .name = "Aquantia AQ2104",
1102 + .config_aneg = aqr_config_aneg,
1103 + .config_intr = aqr_config_intr,
1104 + .handle_interrupt = aqr_handle_interrupt,
1105 + .read_status = aqr_read_status,
1106 +},
1107 +{
1108 + PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
1109 + .name = "Aquantia AQR105",
1110 + .config_aneg = aqr_config_aneg,
1111 + .config_intr = aqr_config_intr,
1112 + .handle_interrupt = aqr_handle_interrupt,
1113 + .read_status = aqr_read_status,
1114 + .suspend = aqr107_suspend,
1115 + .resume = aqr107_resume,
1116 +},
1117 +{
1118 + PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
1119 + .name = "Aquantia AQR106",
1120 + .config_aneg = aqr_config_aneg,
1121 + .config_intr = aqr_config_intr,
1122 + .handle_interrupt = aqr_handle_interrupt,
1123 + .read_status = aqr_read_status,
1124 +},
1125 +{
1126 + PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
1127 + .name = "Aquantia AQR107",
1128 + .probe = aqr107_probe,
1129 + .get_rate_matching = aqr107_get_rate_matching,
1130 + .config_init = aqr107_config_init,
1131 + .config_aneg = aqr_config_aneg,
1132 + .config_intr = aqr_config_intr,
1133 + .handle_interrupt = aqr_handle_interrupt,
1134 + .read_status = aqr107_read_status,
1135 + .get_tunable = aqr107_get_tunable,
1136 + .set_tunable = aqr107_set_tunable,
1137 + .suspend = aqr107_suspend,
1138 + .resume = aqr107_resume,
1139 + .get_sset_count = aqr107_get_sset_count,
1140 + .get_strings = aqr107_get_strings,
1141 + .get_stats = aqr107_get_stats,
1142 + .link_change_notify = aqr107_link_change_notify,
1143 +},
1144 +{
1145 + PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
1146 + .name = "Aquantia AQCS109",
1147 + .probe = aqr107_probe,
1148 + .get_rate_matching = aqr107_get_rate_matching,
1149 + .config_init = aqcs109_config_init,
1150 + .config_aneg = aqr_config_aneg,
1151 + .config_intr = aqr_config_intr,
1152 + .handle_interrupt = aqr_handle_interrupt,
1153 + .read_status = aqr107_read_status,
1154 + .get_tunable = aqr107_get_tunable,
1155 + .set_tunable = aqr107_set_tunable,
1156 + .suspend = aqr107_suspend,
1157 + .resume = aqr107_resume,
1158 + .get_sset_count = aqr107_get_sset_count,
1159 + .get_strings = aqr107_get_strings,
1160 + .get_stats = aqr107_get_stats,
1161 + .link_change_notify = aqr107_link_change_notify,
1162 +},
1163 +{
1164 + PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
1165 + .name = "Aquantia AQR405",
1166 + .config_aneg = aqr_config_aneg,
1167 + .config_intr = aqr_config_intr,
1168 + .handle_interrupt = aqr_handle_interrupt,
1169 + .read_status = aqr_read_status,
1170 +},
1171 +{
1172 + PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
1173 + .name = "Aquantia AQR112",
1174 + .probe = aqr107_probe,
1175 + .config_aneg = aqr_config_aneg,
1176 + .config_intr = aqr_config_intr,
1177 + .handle_interrupt = aqr_handle_interrupt,
1178 + .get_tunable = aqr107_get_tunable,
1179 + .set_tunable = aqr107_set_tunable,
1180 + .suspend = aqr107_suspend,
1181 + .resume = aqr107_resume,
1182 + .read_status = aqr107_read_status,
1183 + .get_rate_matching = aqr107_get_rate_matching,
1184 + .get_sset_count = aqr107_get_sset_count,
1185 + .get_strings = aqr107_get_strings,
1186 + .get_stats = aqr107_get_stats,
1187 + .link_change_notify = aqr107_link_change_notify,
1188 +},
1189 +{
1190 + PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
1191 + .name = "Aquantia AQR412",
1192 + .probe = aqr107_probe,
1193 + .config_aneg = aqr_config_aneg,
1194 + .config_intr = aqr_config_intr,
1195 + .handle_interrupt = aqr_handle_interrupt,
1196 + .get_tunable = aqr107_get_tunable,
1197 + .set_tunable = aqr107_set_tunable,
1198 + .suspend = aqr107_suspend,
1199 + .resume = aqr107_resume,
1200 + .read_status = aqr107_read_status,
1201 + .get_rate_matching = aqr107_get_rate_matching,
1202 + .get_sset_count = aqr107_get_sset_count,
1203 + .get_strings = aqr107_get_strings,
1204 + .get_stats = aqr107_get_stats,
1205 + .link_change_notify = aqr107_link_change_notify,
1206 +},
1207 +{
1208 + PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
1209 + .name = "Aquantia AQR113C",
1210 + .probe = aqr107_probe,
1211 + .get_rate_matching = aqr107_get_rate_matching,
1212 + .config_init = aqr107_config_init,
1213 + .config_aneg = aqr_config_aneg,
1214 + .config_intr = aqr_config_intr,
1215 + .handle_interrupt = aqr_handle_interrupt,
1216 + .read_status = aqr107_read_status,
1217 + .get_tunable = aqr107_get_tunable,
1218 + .set_tunable = aqr107_set_tunable,
1219 + .suspend = aqr107_suspend,
1220 + .resume = aqr107_resume,
1221 + .get_sset_count = aqr107_get_sset_count,
1222 + .get_strings = aqr107_get_strings,
1223 + .get_stats = aqr107_get_stats,
1224 + .link_change_notify = aqr107_link_change_notify,
1225 +},
1226 +};
1227 +
1228 +module_phy_driver(aqr_driver);
1229 +
1230 +static struct mdio_device_id __maybe_unused aqr_tbl[] = {
1231 + { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
1232 + { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
1233 + { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
1234 + { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
1235 + { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
1236 + { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
1237 + { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
1238 + { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
1239 + { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
1240 + { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
1241 + { }
1242 +};
1243 +
1244 +MODULE_DEVICE_TABLE(mdio, aqr_tbl);
1245 +
1246 +MODULE_DESCRIPTION("Aquantia PHY driver");
1247 +MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
1248 +MODULE_LICENSE("GPL v2");
1249 --- a/drivers/net/phy/aquantia_hwmon.c
1250 +++ /dev/null
1251 @@ -1,250 +0,0 @@
1252 -// SPDX-License-Identifier: GPL-2.0
1253 -/* HWMON driver for Aquantia PHY
1254 - *
1255 - * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
1256 - * Author: Andrew Lunn <andrew@lunn.ch>
1257 - * Author: Heiner Kallweit <hkallweit1@gmail.com>
1258 - */
1259 -
1260 -#include <linux/phy.h>
1261 -#include <linux/device.h>
1262 -#include <linux/ctype.h>
1263 -#include <linux/hwmon.h>
1264 -
1265 -#include "aquantia.h"
1266 -
1267 -/* Vendor specific 1, MDIO_MMD_VEND2 */
1268 -#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL 0xc421
1269 -#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
1270 -#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
1271 -#define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
1272 -#define VEND1_THERMAL_STAT1 0xc820
1273 -#define VEND1_THERMAL_STAT2 0xc821
1274 -#define VEND1_THERMAL_STAT2_VALID BIT(0)
1275 -#define VEND1_GENERAL_STAT1 0xc830
1276 -#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL BIT(14)
1277 -#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL BIT(13)
1278 -#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN BIT(12)
1279 -#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN BIT(11)
1280 -
1281 -#if IS_REACHABLE(CONFIG_HWMON)
1282 -
1283 -static umode_t aqr_hwmon_is_visible(const void *data,
1284 - enum hwmon_sensor_types type,
1285 - u32 attr, int channel)
1286 -{
1287 - if (type != hwmon_temp)
1288 - return 0;
1289 -
1290 - switch (attr) {
1291 - case hwmon_temp_input:
1292 - case hwmon_temp_min_alarm:
1293 - case hwmon_temp_max_alarm:
1294 - case hwmon_temp_lcrit_alarm:
1295 - case hwmon_temp_crit_alarm:
1296 - return 0444;
1297 - case hwmon_temp_min:
1298 - case hwmon_temp_max:
1299 - case hwmon_temp_lcrit:
1300 - case hwmon_temp_crit:
1301 - return 0644;
1302 - default:
1303 - return 0;
1304 - }
1305 -}
1306 -
1307 -static int aqr_hwmon_get(struct phy_device *phydev, int reg, long *value)
1308 -{
1309 - int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
1310 -
1311 - if (temp < 0)
1312 - return temp;
1313 -
1314 - /* 16 bit value is 2's complement with LSB = 1/256th degree Celsius */
1315 - *value = (s16)temp * 1000 / 256;
1316 -
1317 - return 0;
1318 -}
1319 -
1320 -static int aqr_hwmon_set(struct phy_device *phydev, int reg, long value)
1321 -{
1322 - int temp;
1323 -
1324 - if (value >= 128000 || value < -128000)
1325 - return -ERANGE;
1326 -
1327 - temp = value * 256 / 1000;
1328 -
1329 - /* temp is in s16 range and we're interested in lower 16 bits only */
1330 - return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp);
1331 -}
1332 -
1333 -static int aqr_hwmon_test_bit(struct phy_device *phydev, int reg, int bit)
1334 -{
1335 - int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
1336 -
1337 - if (val < 0)
1338 - return val;
1339 -
1340 - return !!(val & bit);
1341 -}
1342 -
1343 -static int aqr_hwmon_status1(struct phy_device *phydev, int bit, long *value)
1344 -{
1345 - int val = aqr_hwmon_test_bit(phydev, VEND1_GENERAL_STAT1, bit);
1346 -
1347 - if (val < 0)
1348 - return val;
1349 -
1350 - *value = val;
1351 -
1352 - return 0;
1353 -}
1354 -
1355 -static int aqr_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
1356 - u32 attr, int channel, long *value)
1357 -{
1358 - struct phy_device *phydev = dev_get_drvdata(dev);
1359 - int reg;
1360 -
1361 - if (type != hwmon_temp)
1362 - return -EOPNOTSUPP;
1363 -
1364 - switch (attr) {
1365 - case hwmon_temp_input:
1366 - reg = aqr_hwmon_test_bit(phydev, VEND1_THERMAL_STAT2,
1367 - VEND1_THERMAL_STAT2_VALID);
1368 - if (reg < 0)
1369 - return reg;
1370 - if (!reg)
1371 - return -EBUSY;
1372 -
1373 - return aqr_hwmon_get(phydev, VEND1_THERMAL_STAT1, value);
1374 -
1375 - case hwmon_temp_lcrit:
1376 - return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
1377 - value);
1378 - case hwmon_temp_min:
1379 - return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
1380 - value);
1381 - case hwmon_temp_max:
1382 - return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
1383 - value);
1384 - case hwmon_temp_crit:
1385 - return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
1386 - value);
1387 - case hwmon_temp_lcrit_alarm:
1388 - return aqr_hwmon_status1(phydev,
1389 - VEND1_GENERAL_STAT1_LOW_TEMP_FAIL,
1390 - value);
1391 - case hwmon_temp_min_alarm:
1392 - return aqr_hwmon_status1(phydev,
1393 - VEND1_GENERAL_STAT1_LOW_TEMP_WARN,
1394 - value);
1395 - case hwmon_temp_max_alarm:
1396 - return aqr_hwmon_status1(phydev,
1397 - VEND1_GENERAL_STAT1_HIGH_TEMP_WARN,
1398 - value);
1399 - case hwmon_temp_crit_alarm:
1400 - return aqr_hwmon_status1(phydev,
1401 - VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL,
1402 - value);
1403 - default:
1404 - return -EOPNOTSUPP;
1405 - }
1406 -}
1407 -
1408 -static int aqr_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
1409 - u32 attr, int channel, long value)
1410 -{
1411 - struct phy_device *phydev = dev_get_drvdata(dev);
1412 -
1413 - if (type != hwmon_temp)
1414 - return -EOPNOTSUPP;
1415 -
1416 - switch (attr) {
1417 - case hwmon_temp_lcrit:
1418 - return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
1419 - value);
1420 - case hwmon_temp_min:
1421 - return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
1422 - value);
1423 - case hwmon_temp_max:
1424 - return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
1425 - value);
1426 - case hwmon_temp_crit:
1427 - return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
1428 - value);
1429 - default:
1430 - return -EOPNOTSUPP;
1431 - }
1432 -}
1433 -
1434 -static const struct hwmon_ops aqr_hwmon_ops = {
1435 - .is_visible = aqr_hwmon_is_visible,
1436 - .read = aqr_hwmon_read,
1437 - .write = aqr_hwmon_write,
1438 -};
1439 -
1440 -static u32 aqr_hwmon_chip_config[] = {
1441 - HWMON_C_REGISTER_TZ,
1442 - 0,
1443 -};
1444 -
1445 -static const struct hwmon_channel_info aqr_hwmon_chip = {
1446 - .type = hwmon_chip,
1447 - .config = aqr_hwmon_chip_config,
1448 -};
1449 -
1450 -static u32 aqr_hwmon_temp_config[] = {
1451 - HWMON_T_INPUT |
1452 - HWMON_T_MAX | HWMON_T_MIN |
1453 - HWMON_T_MAX_ALARM | HWMON_T_MIN_ALARM |
1454 - HWMON_T_CRIT | HWMON_T_LCRIT |
1455 - HWMON_T_CRIT_ALARM | HWMON_T_LCRIT_ALARM,
1456 - 0,
1457 -};
1458 -
1459 -static const struct hwmon_channel_info aqr_hwmon_temp = {
1460 - .type = hwmon_temp,
1461 - .config = aqr_hwmon_temp_config,
1462 -};
1463 -
1464 -static const struct hwmon_channel_info * const aqr_hwmon_info[] = {
1465 - &aqr_hwmon_chip,
1466 - &aqr_hwmon_temp,
1467 - NULL,
1468 -};
1469 -
1470 -static const struct hwmon_chip_info aqr_hwmon_chip_info = {
1471 - .ops = &aqr_hwmon_ops,
1472 - .info = aqr_hwmon_info,
1473 -};
1474 -
1475 -int aqr_hwmon_probe(struct phy_device *phydev)
1476 -{
1477 - struct device *dev = &phydev->mdio.dev;
1478 - struct device *hwmon_dev;
1479 - char *hwmon_name;
1480 - int i, j;
1481 -
1482 - hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
1483 - if (!hwmon_name)
1484 - return -ENOMEM;
1485 -
1486 - for (i = j = 0; hwmon_name[i]; i++) {
1487 - if (isalnum(hwmon_name[i])) {
1488 - if (i != j)
1489 - hwmon_name[j] = hwmon_name[i];
1490 - j++;
1491 - }
1492 - }
1493 - hwmon_name[j] = '\0';
1494 -
1495 - hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
1496 - phydev, &aqr_hwmon_chip_info, NULL);
1497 -
1498 - return PTR_ERR_OR_ZERO(hwmon_dev);
1499 -}
1500 -
1501 -#endif
1502 --- a/drivers/net/phy/aquantia_main.c
1503 +++ /dev/null
1504 @@ -1,882 +0,0 @@
1505 -// SPDX-License-Identifier: GPL-2.0
1506 -/*
1507 - * Driver for Aquantia PHY
1508 - *
1509 - * Author: Shaohui Xie <Shaohui.Xie@freescale.com>
1510 - *
1511 - * Copyright 2015 Freescale Semiconductor, Inc.
1512 - */
1513 -
1514 -#include <linux/kernel.h>
1515 -#include <linux/module.h>
1516 -#include <linux/delay.h>
1517 -#include <linux/bitfield.h>
1518 -#include <linux/phy.h>
1519 -
1520 -#include "aquantia.h"
1521 -
1522 -#define PHY_ID_AQ1202 0x03a1b445
1523 -#define PHY_ID_AQ2104 0x03a1b460
1524 -#define PHY_ID_AQR105 0x03a1b4a2
1525 -#define PHY_ID_AQR106 0x03a1b4d0
1526 -#define PHY_ID_AQR107 0x03a1b4e0
1527 -#define PHY_ID_AQCS109 0x03a1b5c2
1528 -#define PHY_ID_AQR405 0x03a1b4b0
1529 -#define PHY_ID_AQR112 0x03a1b662
1530 -#define PHY_ID_AQR412 0x03a1b712
1531 -#define PHY_ID_AQR113C 0x31c31c12
1532 -
1533 -#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
1534 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
1535 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
1536 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1
1537 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2
1538 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3
1539 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4
1540 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
1541 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7
1542 -#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
1543 -
1544 -#define MDIO_AN_VEND_PROV 0xc400
1545 -#define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
1546 -#define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
1547 -#define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11)
1548 -#define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10)
1549 -#define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4)
1550 -#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)
1551 -#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
1552 -
1553 -#define MDIO_AN_TX_VEND_STATUS1 0xc800
1554 -#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)
1555 -#define MDIO_AN_TX_VEND_STATUS1_10BASET 0
1556 -#define MDIO_AN_TX_VEND_STATUS1_100BASETX 1
1557 -#define MDIO_AN_TX_VEND_STATUS1_1000BASET 2
1558 -#define MDIO_AN_TX_VEND_STATUS1_10GBASET 3
1559 -#define MDIO_AN_TX_VEND_STATUS1_2500BASET 4
1560 -#define MDIO_AN_TX_VEND_STATUS1_5000BASET 5
1561 -#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0)
1562 -
1563 -#define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00
1564 -#define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1)
1565 -
1566 -#define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01
1567 -#define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0)
1568 -
1569 -#define MDIO_AN_TX_VEND_INT_MASK2 0xd401
1570 -#define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
1571 -
1572 -#define MDIO_AN_RX_LP_STAT1 0xe820
1573 -#define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15)
1574 -#define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14)
1575 -#define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13)
1576 -#define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12)
1577 -#define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2)
1578 -
1579 -#define MDIO_AN_RX_LP_STAT4 0xe823
1580 -#define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8)
1581 -#define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0)
1582 -
1583 -#define MDIO_AN_RX_VEND_STAT3 0xe832
1584 -#define MDIO_AN_RX_VEND_STAT3_AFR BIT(0)
1585 -
1586 -/* MDIO_MMD_C22EXT */
1587 -#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
1588 -#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
1589 -#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
1590 -#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
1591 -#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
1592 -#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
1593 -#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
1594 -#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
1595 -#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
1596 -#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
1597 -
1598 -/* Vendor specific 1, MDIO_MMD_VEND1 */
1599 -#define VEND1_GLOBAL_FW_ID 0x0020
1600 -#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
1601 -#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
1602 -
1603 -#define VEND1_GLOBAL_GEN_STAT2 0xc831
1604 -#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
1605 -
1606 -/* The following registers all have similar layouts; first the registers... */
1607 -#define VEND1_GLOBAL_CFG_10M 0x0310
1608 -#define VEND1_GLOBAL_CFG_100M 0x031b
1609 -#define VEND1_GLOBAL_CFG_1G 0x031c
1610 -#define VEND1_GLOBAL_CFG_2_5G 0x031d
1611 -#define VEND1_GLOBAL_CFG_5G 0x031e
1612 -#define VEND1_GLOBAL_CFG_10G 0x031f
1613 -/* ...and now the fields */
1614 -#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
1615 -#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
1616 -#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
1617 -#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
1618 -
1619 -#define VEND1_GLOBAL_RSVD_STAT1 0xc885
1620 -#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
1621 -#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
1622 -
1623 -#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
1624 -#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
1625 -#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
1626 -
1627 -#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
1628 -#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
1629 -
1630 -#define VEND1_GLOBAL_INT_STD_MASK 0xff00
1631 -#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
1632 -#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
1633 -#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
1634 -#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
1635 -#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
1636 -#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
1637 -#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
1638 -#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
1639 -#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
1640 -#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
1641 -#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
1642 -
1643 -#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
1644 -#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
1645 -#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
1646 -#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
1647 -#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
1648 -#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
1649 -#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
1650 -#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
1651 -#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
1652 -
1653 -/* Sleep and timeout for checking if the Processor-Intensive
1654 - * MDIO operation is finished
1655 - */
1656 -#define AQR107_OP_IN_PROG_SLEEP 1000
1657 -#define AQR107_OP_IN_PROG_TIMEOUT 100000
1658 -
1659 -struct aqr107_hw_stat {
1660 - const char *name;
1661 - int reg;
1662 - int size;
1663 -};
1664 -
1665 -#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
1666 -static const struct aqr107_hw_stat aqr107_hw_stats[] = {
1667 - SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
1668 - SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
1669 - SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8),
1670 - SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26),
1671 - SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26),
1672 - SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8),
1673 - SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8),
1674 - SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
1675 - SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
1676 - SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
1677 -};
1678 -#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
1679 -
1680 -struct aqr107_priv {
1681 - u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
1682 -};
1683 -
1684 -static int aqr107_get_sset_count(struct phy_device *phydev)
1685 -{
1686 - return AQR107_SGMII_STAT_SZ;
1687 -}
1688 -
1689 -static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
1690 -{
1691 - int i;
1692 -
1693 - for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)
1694 - strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name,
1695 - ETH_GSTRING_LEN);
1696 -}
1697 -
1698 -static u64 aqr107_get_stat(struct phy_device *phydev, int index)
1699 -{
1700 - const struct aqr107_hw_stat *stat = aqr107_hw_stats + index;
1701 - int len_l = min(stat->size, 16);
1702 - int len_h = stat->size - len_l;
1703 - u64 ret;
1704 - int val;
1705 -
1706 - val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
1707 - if (val < 0)
1708 - return U64_MAX;
1709 -
1710 - ret = val & GENMASK(len_l - 1, 0);
1711 - if (len_h) {
1712 - val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
1713 - if (val < 0)
1714 - return U64_MAX;
1715 -
1716 - ret += (val & GENMASK(len_h - 1, 0)) << 16;
1717 - }
1718 -
1719 - return ret;
1720 -}
1721 -
1722 -static void aqr107_get_stats(struct phy_device *phydev,
1723 - struct ethtool_stats *stats, u64 *data)
1724 -{
1725 - struct aqr107_priv *priv = phydev->priv;
1726 - u64 val;
1727 - int i;
1728 -
1729 - for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {
1730 - val = aqr107_get_stat(phydev, i);
1731 - if (val == U64_MAX)
1732 - phydev_err(phydev, "Reading HW Statistics failed for %s\n",
1733 - aqr107_hw_stats[i].name);
1734 - else
1735 - priv->sgmii_stats[i] += val;
1736 -
1737 - data[i] = priv->sgmii_stats[i];
1738 - }
1739 -}
1740 -
1741 -static int aqr_config_aneg(struct phy_device *phydev)
1742 -{
1743 - bool changed = false;
1744 - u16 reg;
1745 - int ret;
1746 -
1747 - if (phydev->autoneg == AUTONEG_DISABLE)
1748 - return genphy_c45_pma_setup_forced(phydev);
1749 -
1750 - ret = genphy_c45_an_config_aneg(phydev);
1751 - if (ret < 0)
1752 - return ret;
1753 - if (ret > 0)
1754 - changed = true;
1755 -
1756 - /* Clause 45 has no standardized support for 1000BaseT, therefore
1757 - * use vendor registers for this mode.
1758 - */
1759 - reg = 0;
1760 - if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1761 - phydev->advertising))
1762 - reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
1763 -
1764 - if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1765 - phydev->advertising))
1766 - reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
1767 -
1768 - /* Handle the case when the 2.5G and 5G speeds are not advertised */
1769 - if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
1770 - phydev->advertising))
1771 - reg |= MDIO_AN_VEND_PROV_2500BASET_FULL;
1772 -
1773 - if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
1774 - phydev->advertising))
1775 - reg |= MDIO_AN_VEND_PROV_5000BASET_FULL;
1776 -
1777 - ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
1778 - MDIO_AN_VEND_PROV_1000BASET_HALF |
1779 - MDIO_AN_VEND_PROV_1000BASET_FULL |
1780 - MDIO_AN_VEND_PROV_2500BASET_FULL |
1781 - MDIO_AN_VEND_PROV_5000BASET_FULL, reg);
1782 - if (ret < 0)
1783 - return ret;
1784 - if (ret > 0)
1785 - changed = true;
1786 -
1787 - return genphy_c45_check_and_restart_aneg(phydev, changed);
1788 -}
1789 -
1790 -static int aqr_config_intr(struct phy_device *phydev)
1791 -{
1792 - bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
1793 - int err;
1794 -
1795 - if (en) {
1796 - /* Clear any pending interrupts before enabling them */
1797 - err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
1798 - if (err < 0)
1799 - return err;
1800 - }
1801 -
1802 - err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
1803 - en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);
1804 - if (err < 0)
1805 - return err;
1806 -
1807 - err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
1808 - en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);
1809 - if (err < 0)
1810 - return err;
1811 -
1812 - err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
1813 - en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
1814 - VEND1_GLOBAL_INT_VEND_MASK_AN : 0);
1815 - if (err < 0)
1816 - return err;
1817 -
1818 - if (!en) {
1819 - /* Clear any pending interrupts after we have disabled them */
1820 - err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
1821 - if (err < 0)
1822 - return err;
1823 - }
1824 -
1825 - return 0;
1826 -}
1827 -
1828 -static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev)
1829 -{
1830 - int irq_status;
1831 -
1832 - irq_status = phy_read_mmd(phydev, MDIO_MMD_AN,
1833 - MDIO_AN_TX_VEND_INT_STATUS2);
1834 - if (irq_status < 0) {
1835 - phy_error(phydev);
1836 - return IRQ_NONE;
1837 - }
1838 -
1839 - if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK))
1840 - return IRQ_NONE;
1841 -
1842 - phy_trigger_machine(phydev);
1843 -
1844 - return IRQ_HANDLED;
1845 -}
1846 -
1847 -static int aqr_read_status(struct phy_device *phydev)
1848 -{
1849 - int val;
1850 -
1851 - if (phydev->autoneg == AUTONEG_ENABLE) {
1852 - val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
1853 - if (val < 0)
1854 - return val;
1855 -
1856 - linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1857 - phydev->lp_advertising,
1858 - val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
1859 - linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1860 - phydev->lp_advertising,
1861 - val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
1862 - }
1863 -
1864 - return genphy_c45_read_status(phydev);
1865 -}
1866 -
1867 -static int aqr107_read_rate(struct phy_device *phydev)
1868 -{
1869 - u32 config_reg;
1870 - int val;
1871 -
1872 - val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
1873 - if (val < 0)
1874 - return val;
1875 -
1876 - if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
1877 - phydev->duplex = DUPLEX_FULL;
1878 - else
1879 - phydev->duplex = DUPLEX_HALF;
1880 -
1881 - switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
1882 - case MDIO_AN_TX_VEND_STATUS1_10BASET:
1883 - phydev->speed = SPEED_10;
1884 - config_reg = VEND1_GLOBAL_CFG_10M;
1885 - break;
1886 - case MDIO_AN_TX_VEND_STATUS1_100BASETX:
1887 - phydev->speed = SPEED_100;
1888 - config_reg = VEND1_GLOBAL_CFG_100M;
1889 - break;
1890 - case MDIO_AN_TX_VEND_STATUS1_1000BASET:
1891 - phydev->speed = SPEED_1000;
1892 - config_reg = VEND1_GLOBAL_CFG_1G;
1893 - break;
1894 - case MDIO_AN_TX_VEND_STATUS1_2500BASET:
1895 - phydev->speed = SPEED_2500;
1896 - config_reg = VEND1_GLOBAL_CFG_2_5G;
1897 - break;
1898 - case MDIO_AN_TX_VEND_STATUS1_5000BASET:
1899 - phydev->speed = SPEED_5000;
1900 - config_reg = VEND1_GLOBAL_CFG_5G;
1901 - break;
1902 - case MDIO_AN_TX_VEND_STATUS1_10GBASET:
1903 - phydev->speed = SPEED_10000;
1904 - config_reg = VEND1_GLOBAL_CFG_10G;
1905 - break;
1906 - default:
1907 - phydev->speed = SPEED_UNKNOWN;
1908 - return 0;
1909 - }
1910 -
1911 - val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);
1912 - if (val < 0)
1913 - return val;
1914 -
1915 - if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) ==
1916 - VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)
1917 - phydev->rate_matching = RATE_MATCH_PAUSE;
1918 - else
1919 - phydev->rate_matching = RATE_MATCH_NONE;
1920 -
1921 - return 0;
1922 -}
1923 -
1924 -static int aqr107_read_status(struct phy_device *phydev)
1925 -{
1926 - int val, ret;
1927 -
1928 - ret = aqr_read_status(phydev);
1929 - if (ret)
1930 - return ret;
1931 -
1932 - if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
1933 - return 0;
1934 -
1935 - val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
1936 - if (val < 0)
1937 - return val;
1938 -
1939 - switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
1940 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
1941 - phydev->interface = PHY_INTERFACE_MODE_10GKR;
1942 - break;
1943 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX:
1944 - phydev->interface = PHY_INTERFACE_MODE_1000BASEKX;
1945 - break;
1946 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
1947 - phydev->interface = PHY_INTERFACE_MODE_10GBASER;
1948 - break;
1949 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
1950 - phydev->interface = PHY_INTERFACE_MODE_USXGMII;
1951 - break;
1952 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI:
1953 - phydev->interface = PHY_INTERFACE_MODE_XAUI;
1954 - break;
1955 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
1956 - phydev->interface = PHY_INTERFACE_MODE_SGMII;
1957 - break;
1958 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI:
1959 - phydev->interface = PHY_INTERFACE_MODE_RXAUI;
1960 - break;
1961 - case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
1962 - phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
1963 - break;
1964 - default:
1965 - phydev->interface = PHY_INTERFACE_MODE_NA;
1966 - break;
1967 - }
1968 -
1969 - /* Read possibly downshifted rate from vendor register */
1970 - return aqr107_read_rate(phydev);
1971 -}
1972 -
1973 -static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
1974 -{
1975 - int val, cnt, enable;
1976 -
1977 - val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
1978 - if (val < 0)
1979 - return val;
1980 -
1981 - enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
1982 - cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
1983 -
1984 - *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
1985 -
1986 - return 0;
1987 -}
1988 -
1989 -static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
1990 -{
1991 - int val = 0;
1992 -
1993 - if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
1994 - return -E2BIG;
1995 -
1996 - if (cnt != DOWNSHIFT_DEV_DISABLE) {
1997 - val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
1998 - val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
1999 - }
2000 -
2001 - return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
2002 - MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
2003 - MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
2004 -}
2005 -
2006 -static int aqr107_get_tunable(struct phy_device *phydev,
2007 - struct ethtool_tunable *tuna, void *data)
2008 -{
2009 - switch (tuna->id) {
2010 - case ETHTOOL_PHY_DOWNSHIFT:
2011 - return aqr107_get_downshift(phydev, data);
2012 - default:
2013 - return -EOPNOTSUPP;
2014 - }
2015 -}
2016 -
2017 -static int aqr107_set_tunable(struct phy_device *phydev,
2018 - struct ethtool_tunable *tuna, const void *data)
2019 -{
2020 - switch (tuna->id) {
2021 - case ETHTOOL_PHY_DOWNSHIFT:
2022 - return aqr107_set_downshift(phydev, *(const u8 *)data);
2023 - default:
2024 - return -EOPNOTSUPP;
2025 - }
2026 -}
2027 -
2028 -/* If we configure settings whilst firmware is still initializing the chip,
2029 - * then these settings may be overwritten. Therefore make sure chip
2030 - * initialization has completed. Use presence of the firmware ID as
2031 - * indicator for initialization having completed.
2032 - * The chip also provides a "reset completed" bit, but it's cleared after
2033 - * read. Therefore function would time out if called again.
2034 - */
2035 -static int aqr107_wait_reset_complete(struct phy_device *phydev)
2036 -{
2037 - int val;
2038 -
2039 - return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
2040 - VEND1_GLOBAL_FW_ID, val, val != 0,
2041 - 20000, 2000000, false);
2042 -}
2043 -
2044 -static void aqr107_chip_info(struct phy_device *phydev)
2045 -{
2046 - u8 fw_major, fw_minor, build_id, prov_id;
2047 - int val;
2048 -
2049 - val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
2050 - if (val < 0)
2051 - return;
2052 -
2053 - fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val);
2054 - fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val);
2055 -
2056 - val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
2057 - if (val < 0)
2058 - return;
2059 -
2060 - build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
2061 - prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
2062 -
2063 - phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
2064 - fw_major, fw_minor, build_id, prov_id);
2065 -}
2066 -
2067 -static int aqr107_config_init(struct phy_device *phydev)
2068 -{
2069 - int ret;
2070 -
2071 - /* Check that the PHY interface type is compatible */
2072 - if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
2073 - phydev->interface != PHY_INTERFACE_MODE_1000BASEKX &&
2074 - phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
2075 - phydev->interface != PHY_INTERFACE_MODE_XGMII &&
2076 - phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
2077 - phydev->interface != PHY_INTERFACE_MODE_10GKR &&
2078 - phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
2079 - phydev->interface != PHY_INTERFACE_MODE_XAUI &&
2080 - phydev->interface != PHY_INTERFACE_MODE_RXAUI)
2081 - return -ENODEV;
2082 -
2083 - WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
2084 - "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
2085 -
2086 - ret = aqr107_wait_reset_complete(phydev);
2087 - if (!ret)
2088 - aqr107_chip_info(phydev);
2089 -
2090 - return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
2091 -}
2092 -
2093 -static int aqcs109_config_init(struct phy_device *phydev)
2094 -{
2095 - int ret;
2096 -
2097 - /* Check that the PHY interface type is compatible */
2098 - if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
2099 - phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
2100 - return -ENODEV;
2101 -
2102 - ret = aqr107_wait_reset_complete(phydev);
2103 - if (!ret)
2104 - aqr107_chip_info(phydev);
2105 -
2106 - /* AQCS109 belongs to a chip family partially supporting 10G and 5G.
2107 - * PMA speed ability bits are the same for all members of the family,
2108 - * AQCS109 however supports speeds up to 2.5G only.
2109 - */
2110 - phy_set_max_speed(phydev, SPEED_2500);
2111 -
2112 - return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
2113 -}
2114 -
2115 -static void aqr107_link_change_notify(struct phy_device *phydev)
2116 -{
2117 - u8 fw_major, fw_minor;
2118 - bool downshift, short_reach, afr;
2119 - int mode, val;
2120 -
2121 - if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
2122 - return;
2123 -
2124 - val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
2125 - /* call failed or link partner is no Aquantia PHY */
2126 - if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
2127 - return;
2128 -
2129 - short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
2130 - downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
2131 -
2132 - val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
2133 - if (val < 0)
2134 - return;
2135 -
2136 - fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
2137 - fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
2138 -
2139 - val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
2140 - if (val < 0)
2141 - return;
2142 -
2143 - afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
2144 -
2145 - phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
2146 - fw_major, fw_minor,
2147 - short_reach ? ", short reach mode" : "",
2148 - downshift ? ", fast-retrain downshift advertised" : "",
2149 - afr ? ", fast reframe advertised" : "");
2150 -
2151 - val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
2152 - if (val < 0)
2153 - return;
2154 -
2155 - mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
2156 - if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
2157 - phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
2158 -}
2159 -
2160 -static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
2161 -{
2162 - int val, err;
2163 -
2164 - /* The datasheet notes to wait at least 1ms after issuing a
2165 - * processor intensive operation before checking.
2166 - * We cannot use the 'sleep_before_read' parameter of read_poll_timeout
2167 - * because that just determines the maximum time slept, not the minimum.
2168 - */
2169 - usleep_range(1000, 5000);
2170 -
2171 - err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
2172 - VEND1_GLOBAL_GEN_STAT2, val,
2173 - !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG),
2174 - AQR107_OP_IN_PROG_SLEEP,
2175 - AQR107_OP_IN_PROG_TIMEOUT, false);
2176 - if (err) {
2177 - phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");
2178 - return err;
2179 - }
2180 -
2181 - return 0;
2182 -}
2183 -
2184 -static int aqr107_get_rate_matching(struct phy_device *phydev,
2185 - phy_interface_t iface)
2186 -{
2187 - if (iface == PHY_INTERFACE_MODE_10GBASER ||
2188 - iface == PHY_INTERFACE_MODE_2500BASEX ||
2189 - iface == PHY_INTERFACE_MODE_NA)
2190 - return RATE_MATCH_PAUSE;
2191 - return RATE_MATCH_NONE;
2192 -}
2193 -
2194 -static int aqr107_suspend(struct phy_device *phydev)
2195 -{
2196 - int err;
2197 -
2198 - err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
2199 - MDIO_CTRL1_LPOWER);
2200 - if (err)
2201 - return err;
2202 -
2203 - return aqr107_wait_processor_intensive_op(phydev);
2204 -}
2205 -
2206 -static int aqr107_resume(struct phy_device *phydev)
2207 -{
2208 - int err;
2209 -
2210 - err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
2211 - MDIO_CTRL1_LPOWER);
2212 - if (err)
2213 - return err;
2214 -
2215 - return aqr107_wait_processor_intensive_op(phydev);
2216 -}
2217 -
2218 -static int aqr107_probe(struct phy_device *phydev)
2219 -{
2220 - phydev->priv = devm_kzalloc(&phydev->mdio.dev,
2221 - sizeof(struct aqr107_priv), GFP_KERNEL);
2222 - if (!phydev->priv)
2223 - return -ENOMEM;
2224 -
2225 - return aqr_hwmon_probe(phydev);
2226 -}
2227 -
2228 -static struct phy_driver aqr_driver[] = {
2229 -{
2230 - PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
2231 - .name = "Aquantia AQ1202",
2232 - .config_aneg = aqr_config_aneg,
2233 - .config_intr = aqr_config_intr,
2234 - .handle_interrupt = aqr_handle_interrupt,
2235 - .read_status = aqr_read_status,
2236 -},
2237 -{
2238 - PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
2239 - .name = "Aquantia AQ2104",
2240 - .config_aneg = aqr_config_aneg,
2241 - .config_intr = aqr_config_intr,
2242 - .handle_interrupt = aqr_handle_interrupt,
2243 - .read_status = aqr_read_status,
2244 -},
2245 -{
2246 - PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
2247 - .name = "Aquantia AQR105",
2248 - .config_aneg = aqr_config_aneg,
2249 - .config_intr = aqr_config_intr,
2250 - .handle_interrupt = aqr_handle_interrupt,
2251 - .read_status = aqr_read_status,
2252 - .suspend = aqr107_suspend,
2253 - .resume = aqr107_resume,
2254 -},
2255 -{
2256 - PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
2257 - .name = "Aquantia AQR106",
2258 - .config_aneg = aqr_config_aneg,
2259 - .config_intr = aqr_config_intr,
2260 - .handle_interrupt = aqr_handle_interrupt,
2261 - .read_status = aqr_read_status,
2262 -},
2263 -{
2264 - PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
2265 - .name = "Aquantia AQR107",
2266 - .probe = aqr107_probe,
2267 - .get_rate_matching = aqr107_get_rate_matching,
2268 - .config_init = aqr107_config_init,
2269 - .config_aneg = aqr_config_aneg,
2270 - .config_intr = aqr_config_intr,
2271 - .handle_interrupt = aqr_handle_interrupt,
2272 - .read_status = aqr107_read_status,
2273 - .get_tunable = aqr107_get_tunable,
2274 - .set_tunable = aqr107_set_tunable,
2275 - .suspend = aqr107_suspend,
2276 - .resume = aqr107_resume,
2277 - .get_sset_count = aqr107_get_sset_count,
2278 - .get_strings = aqr107_get_strings,
2279 - .get_stats = aqr107_get_stats,
2280 - .link_change_notify = aqr107_link_change_notify,
2281 -},
2282 -{
2283 - PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
2284 - .name = "Aquantia AQCS109",
2285 - .probe = aqr107_probe,
2286 - .get_rate_matching = aqr107_get_rate_matching,
2287 - .config_init = aqcs109_config_init,
2288 - .config_aneg = aqr_config_aneg,
2289 - .config_intr = aqr_config_intr,
2290 - .handle_interrupt = aqr_handle_interrupt,
2291 - .read_status = aqr107_read_status,
2292 - .get_tunable = aqr107_get_tunable,
2293 - .set_tunable = aqr107_set_tunable,
2294 - .suspend = aqr107_suspend,
2295 - .resume = aqr107_resume,
2296 - .get_sset_count = aqr107_get_sset_count,
2297 - .get_strings = aqr107_get_strings,
2298 - .get_stats = aqr107_get_stats,
2299 - .link_change_notify = aqr107_link_change_notify,
2300 -},
2301 -{
2302 - PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
2303 - .name = "Aquantia AQR405",
2304 - .config_aneg = aqr_config_aneg,
2305 - .config_intr = aqr_config_intr,
2306 - .handle_interrupt = aqr_handle_interrupt,
2307 - .read_status = aqr_read_status,
2308 -},
2309 -{
2310 - PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
2311 - .name = "Aquantia AQR112",
2312 - .probe = aqr107_probe,
2313 - .config_aneg = aqr_config_aneg,
2314 - .config_intr = aqr_config_intr,
2315 - .handle_interrupt = aqr_handle_interrupt,
2316 - .get_tunable = aqr107_get_tunable,
2317 - .set_tunable = aqr107_set_tunable,
2318 - .suspend = aqr107_suspend,
2319 - .resume = aqr107_resume,
2320 - .read_status = aqr107_read_status,
2321 - .get_rate_matching = aqr107_get_rate_matching,
2322 - .get_sset_count = aqr107_get_sset_count,
2323 - .get_strings = aqr107_get_strings,
2324 - .get_stats = aqr107_get_stats,
2325 - .link_change_notify = aqr107_link_change_notify,
2326 -},
2327 -{
2328 - PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
2329 - .name = "Aquantia AQR412",
2330 - .probe = aqr107_probe,
2331 - .config_aneg = aqr_config_aneg,
2332 - .config_intr = aqr_config_intr,
2333 - .handle_interrupt = aqr_handle_interrupt,
2334 - .get_tunable = aqr107_get_tunable,
2335 - .set_tunable = aqr107_set_tunable,
2336 - .suspend = aqr107_suspend,
2337 - .resume = aqr107_resume,
2338 - .read_status = aqr107_read_status,
2339 - .get_rate_matching = aqr107_get_rate_matching,
2340 - .get_sset_count = aqr107_get_sset_count,
2341 - .get_strings = aqr107_get_strings,
2342 - .get_stats = aqr107_get_stats,
2343 - .link_change_notify = aqr107_link_change_notify,
2344 -},
2345 -{
2346 - PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
2347 - .name = "Aquantia AQR113C",
2348 - .probe = aqr107_probe,
2349 - .get_rate_matching = aqr107_get_rate_matching,
2350 - .config_init = aqr107_config_init,
2351 - .config_aneg = aqr_config_aneg,
2352 - .config_intr = aqr_config_intr,
2353 - .handle_interrupt = aqr_handle_interrupt,
2354 - .read_status = aqr107_read_status,
2355 - .get_tunable = aqr107_get_tunable,
2356 - .set_tunable = aqr107_set_tunable,
2357 - .suspend = aqr107_suspend,
2358 - .resume = aqr107_resume,
2359 - .get_sset_count = aqr107_get_sset_count,
2360 - .get_strings = aqr107_get_strings,
2361 - .get_stats = aqr107_get_stats,
2362 - .link_change_notify = aqr107_link_change_notify,
2363 -},
2364 -};
2365 -
2366 -module_phy_driver(aqr_driver);
2367 -
2368 -static struct mdio_device_id __maybe_unused aqr_tbl[] = {
2369 - { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
2370 - { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
2371 - { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
2372 - { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
2373 - { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
2374 - { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
2375 - { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
2376 - { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
2377 - { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
2378 - { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
2379 - { }
2380 -};
2381 -
2382 -MODULE_DEVICE_TABLE(mdio, aqr_tbl);
2383 -
2384 -MODULE_DESCRIPTION("Aquantia PHY driver");
2385 -MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
2386 -MODULE_LICENSE("GPL v2");
OpenWrt Source Repository