generic: Support Altima AMI101L PHY
[openwrt/openwrt.git] / target / linux / generic / backport-6.1 / 733-v6.4-24-net-ethernet-mediatek-fix-ppe-flow-accounting-for-v1.patch
1 From 88a0fd5927b7c2c7aecd6dc747d898eb38043d2b Mon Sep 17 00:00:00 2001
2 From: Felix Fietkau <nbd@nbd.name>
3 Date: Thu, 20 Apr 2023 22:06:42 +0100
4 Subject: [PATCH 093/250] net: mtk_eth_soc: mediatek: fix ppe flow accounting
5 for v1 hardware
6
7 Older chips (like MT7622) use a different bit in ib2 to enable hardware
8 counter support. Add macros for both and select the appropriate bit.
9
10 Fixes: 3fbe4d8c0e53 ("net: ethernet: mtk_eth_soc: ppe: add support for flow accounting")
11 Signed-off-by: Felix Fietkau <nbd@nbd.name>
12 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
13 Signed-off-by: David S. Miller <davem@davemloft.net>
14 ---
15 drivers/net/ethernet/mediatek/mtk_ppe.c | 10 ++++++++--
16 drivers/net/ethernet/mediatek/mtk_ppe.h | 3 ++-
17 2 files changed, 10 insertions(+), 3 deletions(-)
18
19 --- a/drivers/net/ethernet/mediatek/mtk_ppe.c
20 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
21 @@ -599,6 +599,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
22 struct mtk_eth *eth = ppe->eth;
23 u16 timestamp = mtk_eth_timestamp(eth);
24 struct mtk_foe_entry *hwe;
25 + u32 val;
26
27 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
28 entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP_V2;
29 @@ -615,8 +616,13 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
30 wmb();
31 hwe->ib1 = entry->ib1;
32
33 - if (ppe->accounting)
34 - *mtk_foe_entry_ib2(eth, hwe) |= MTK_FOE_IB2_MIB_CNT;
35 + if (ppe->accounting) {
36 + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
37 + val = MTK_FOE_IB2_MIB_CNT_V2;
38 + else
39 + val = MTK_FOE_IB2_MIB_CNT;
40 + *mtk_foe_entry_ib2(eth, hwe) |= val;
41 + }
42
43 dma_wmb();
44
45 --- a/drivers/net/ethernet/mediatek/mtk_ppe.h
46 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
47 @@ -55,9 +55,10 @@ enum {
48 #define MTK_FOE_IB2_PSE_QOS BIT(4)
49 #define MTK_FOE_IB2_DEST_PORT GENMASK(7, 5)
50 #define MTK_FOE_IB2_MULTICAST BIT(8)
51 +#define MTK_FOE_IB2_MIB_CNT BIT(10)
52
53 #define MTK_FOE_IB2_WDMA_QID2 GENMASK(13, 12)
54 -#define MTK_FOE_IB2_MIB_CNT BIT(15)
55 +#define MTK_FOE_IB2_MIB_CNT_V2 BIT(15)
56 #define MTK_FOE_IB2_WDMA_DEVIDX BIT(16)
57 #define MTK_FOE_IB2_WDMA_WINFO BIT(17)
58