target/linux/generic/backport-6.1/733-v6.3-15-net-ethernet-mtk_eth_soc-reset-PCS-state.patch

   1 From 611e2dabb4b3243d176739fd6a5a34d007fa3f86 Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Tue, 14 Mar 2023 00:34:26 +0000
   4 Subject: [PATCH 1/2] net: ethernet: mtk_eth_soc: reset PCS state
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
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   8
   9 Reset the internal PCS state machine when changing interface mode.
  10 This prevents confusing the state machine when changing interface
  11 modes, e.g. from SGMII to 2500Base-X or vice-versa.
  12
  13 Fixes: 7e538372694b ("net: ethernet: mediatek: Re-add support SGMII")
  14 Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
  15 Tested-by: Bjørn Mork <bjorn@mork.no>
  16 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  17 Signed-off-by: David S. Miller <davem@davemloft.net>
  18 ---
  19  drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++++
  20  drivers/net/ethernet/mediatek/mtk_sgmii.c   | 4 ++++
  21  2 files changed, 8 insertions(+)
  22
  23 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  24 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  25 @@ -542,6 +542,10 @@
  26  #define SGMII_SEND_AN_ERROR_EN         BIT(11)
  27  #define SGMII_IF_MODE_MASK             GENMASK(5, 1)
  28
  29 +/* Register to reset SGMII design */
  30 +#define SGMII_RESERVED_0       0x34
  31 +#define SGMII_SW_RESET         BIT(0)
  32 +
  33  /* Register to set SGMII speed, ANA RG_ Control Signals III*/
  34  #define SGMSYS_ANA_RG_CS3      0x2028
  35  #define RG_PHY_SPEED_MASK      (BIT(2) | BIT(3))
  36 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
  37 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
  38 @@ -88,6 +88,10 @@ static int mtk_pcs_config(struct phylink
  39                 regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
  40                                    SGMII_PHYA_PWD, SGMII_PHYA_PWD);
  41
  42 +               /* Reset SGMII PCS state */
  43 +               regmap_update_bits(mpcs->regmap, SGMII_RESERVED_0,
  44 +                                  SGMII_SW_RESET, SGMII_SW_RESET);
  45 +
  46                 if (interface == PHY_INTERFACE_MODE_2500BASEX)
  47                         rgc3 = RG_PHY_SPEED_3_125G;
  48                 else