target/linux/generic/backport-6.1/733-v6.2-08-net-mtk_eth_soc-move-interface-speed-selection.patch

   1 From f752c0df13dfeb721c11d3debb79f08cf437344f Mon Sep 17 00:00:00 2001
   2 From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
   3 Date: Thu, 27 Oct 2022 14:11:13 +0100
   4 Subject: [PATCH 07/10] net: mtk_eth_soc: move interface speed selection
   5
   6 Move the selection of the underlying interface speed to the pcs_config
   7 function, so we always program the interface speed.
   8
   9 Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
  10 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  11 ---
  12  drivers/net/ethernet/mediatek/mtk_sgmii.c | 18 ++++++++++--------
  13  1 file changed, 10 insertions(+), 8 deletions(-)
  14
  15 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
  16 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
  17 @@ -53,14 +53,6 @@ static void mtk_pcs_setup_mode_an(struct
  18  static void mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs,
  19                                      phy_interface_t interface)
  20  {
  21 -       unsigned int rgc3;
  22 -
  23 -       if (interface == PHY_INTERFACE_MODE_2500BASEX)
  24 -               rgc3 = RG_PHY_SPEED_3_125G;
  25 -
  26 -       regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
  27 -                          RG_PHY_SPEED_3_125G, rgc3);
  28 -
  29         /* Disable SGMII AN */
  30         regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
  31                            SGMII_AN_ENABLE, 0);
  32 @@ -77,6 +69,16 @@ static int mtk_pcs_config(struct phylink
  33                           bool permit_pause_to_mac)
  34  {
  35         struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
  36 +       unsigned int rgc3;
  37 +
  38 +       if (interface == PHY_INTERFACE_MODE_2500BASEX)
  39 +               rgc3 = RG_PHY_SPEED_3_125G;
  40 +       else
  41 +               rgc3 = 0;
  42 +
  43 +       /* Configure the underlying interface speed */
  44 +       regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
  45 +                          RG_PHY_SPEED_3_125G, rgc3);
  46
  47         /* Setup SGMIISYS with the determined property */
  48         if (interface != PHY_INTERFACE_MODE_SGMII)