target/linux/generic/backport-6.1/733-v6.2-02-net-mtk_eth_soc-add-definitions-for-PCS.patch

   1 From b6a709cb51f7bdc55c01cec886098a9753ce8c28 Mon Sep 17 00:00:00 2001
   2 From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
   3 Date: Thu, 27 Oct 2022 14:10:42 +0100
   4 Subject: [PATCH 01/10] net: mtk_eth_soc: add definitions for PCS
   5
   6 As a result of help from Frank Wunderlich to investigate and test, we
   7 know a bit more about the PCS on the Mediatek platforms. Update the
   8 definitions from this investigation.
   9
  10 This PCS appears similar, but not identical to the Lynx PCS.
  11
  12 Although not included in this patch, but for future reference, the PHY
  13 ID registers at offset 4 read as 0x4d544950 'MTIP'.
  14
  15 Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
  16 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  17 ---
  18  drivers/net/ethernet/mediatek/mtk_eth_soc.h | 13 ++++++++++---
  19  1 file changed, 10 insertions(+), 3 deletions(-)
  20
  21 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  22 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  23 @@ -504,8 +504,10 @@
  24  #define ETHSYS_DMA_AG_MAP_PPE  BIT(2)
  25
  26  /* SGMII subsystem config registers */
  27 -/* Register to auto-negotiation restart */
  28 +/* BMCR (low 16) BMSR (high 16) */
  29  #define SGMSYS_PCS_CONTROL_1   0x0
  30 +#define SGMII_BMCR             GENMASK(15, 0)
  31 +#define SGMII_BMSR             GENMASK(31, 16)
  32  #define SGMII_AN_RESTART       BIT(9)
  33  #define SGMII_ISOLATE          BIT(10)
  34  #define SGMII_AN_ENABLE                BIT(12)
  35 @@ -515,13 +517,18 @@
  36  #define SGMII_PCS_FAULT                BIT(23)
  37  #define SGMII_AN_EXPANSION_CLR BIT(30)
  38
  39 +#define SGMSYS_PCS_ADVERTISE   0x8
  40 +#define SGMII_ADVERTISE                GENMASK(15, 0)
  41 +#define SGMII_LPA              GENMASK(31, 16)
  42 +
  43  /* Register to programmable link timer, the unit in 2 * 8ns */
  44  #define SGMSYS_PCS_LINK_TIMER  0x18
  45 -#define SGMII_LINK_TIMER_DEFAULT       (0x186a0 & GENMASK(19, 0))
  46 +#define SGMII_LINK_TIMER_MASK  GENMASK(19, 0)
  47 +#define SGMII_LINK_TIMER_DEFAULT       (0x186a0 & SGMII_LINK_TIMER_MASK)
  48
  49  /* Register to control remote fault */
  50  #define SGMSYS_SGMII_MODE              0x20
  51 -#define SGMII_IF_MODE_BIT0             BIT(0)
  52 +#define SGMII_IF_MODE_SGMII            BIT(0)
  53  #define SGMII_SPEED_DUPLEX_AN          BIT(1)
  54  #define SGMII_SPEED_MASK               GENMASK(3, 2)
  55  #define SGMII_SPEED_10                 FIELD_PREP(SGMII_SPEED_MASK, 0)