target/linux/generic/backport-6.1/710-v6.8-net-phy-at803x-better-align-function-varibles-to-ope.patch

   1 From 7961ef1fa10ec35ad6923fb5751877116e4b035b Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Tue, 19 Dec 2023 21:21:24 +0100
   4 Subject: [PATCH] net: phy: at803x: better align function varibles to open
   5  parenthesis
   6
   7 Better align function variables to open parenthesis as suggested by
   8 checkpatch script for qca808x function to make code cleaner.
   9
  10 For cable_test_get_status function some additional rework was needed to
  11 handle too long functions.
  12
  13 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  14 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  15 Signed-off-by: David S. Miller <davem@davemloft.net>
  16 ---
  17  drivers/net/phy/at803x.c | 67 ++++++++++++++++++++++------------------
  18  1 file changed, 37 insertions(+), 30 deletions(-)
  19
  20 --- a/drivers/net/phy/at803x.c
  21 +++ b/drivers/net/phy/at803x.c
  22 @@ -1781,27 +1781,27 @@ static int qca808x_phy_fast_retrain_conf
  23                 return ret;
  24
  25         phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
  26 -                       QCA808X_TOP_OPTION1_DATA);
  27 +                     QCA808X_TOP_OPTION1_DATA);
  28         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
  29 -                       QCA808X_MSE_THRESHOLD_20DB_VALUE);
  30 +                     QCA808X_MSE_THRESHOLD_20DB_VALUE);
  31         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
  32 -                       QCA808X_MSE_THRESHOLD_17DB_VALUE);
  33 +                     QCA808X_MSE_THRESHOLD_17DB_VALUE);
  34         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
  35 -                       QCA808X_MSE_THRESHOLD_27DB_VALUE);
  36 +                     QCA808X_MSE_THRESHOLD_27DB_VALUE);
  37         phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
  38 -                       QCA808X_MSE_THRESHOLD_28DB_VALUE);
  39 +                     QCA808X_MSE_THRESHOLD_28DB_VALUE);
  40         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
  41 -                       QCA808X_MMD3_DEBUG_1_VALUE);
  42 +                     QCA808X_MMD3_DEBUG_1_VALUE);
  43         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
  44 -                       QCA808X_MMD3_DEBUG_4_VALUE);
  45 +                     QCA808X_MMD3_DEBUG_4_VALUE);
  46         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
  47 -                       QCA808X_MMD3_DEBUG_5_VALUE);
  48 +                     QCA808X_MMD3_DEBUG_5_VALUE);
  49         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
  50 -                       QCA808X_MMD3_DEBUG_3_VALUE);
  51 +                     QCA808X_MMD3_DEBUG_3_VALUE);
  52         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
  53 -                       QCA808X_MMD3_DEBUG_6_VALUE);
  54 +                     QCA808X_MMD3_DEBUG_6_VALUE);
  55         phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
  56 -                       QCA808X_MMD3_DEBUG_2_VALUE);
  57 +                     QCA808X_MMD3_DEBUG_2_VALUE);
  58
  59         return 0;
  60  }
  61 @@ -1838,13 +1838,14 @@ static int qca808x_config_init(struct ph
  62
  63         /* Active adc&vga on 802.3az for the link 1000M and 100M */
  64         ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
  65 -                       QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
  66 +                            QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
  67         if (ret)
  68                 return ret;
  69
  70         /* Adjust the threshold on 802.3az for the link 1000M */
  71         ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
  72 -                       QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, QCA808X_MMD3_AZ_TRAINING_VAL);
  73 +                           QCA808X_PHY_MMD3_AZ_TRAINING_CTRL,
  74 +                           QCA808X_MMD3_AZ_TRAINING_VAL);
  75         if (ret)
  76                 return ret;
  77
  78 @@ -1870,7 +1871,8 @@ static int qca808x_config_init(struct ph
  79
  80         /* Configure adc threshold as 100mv for the link 10M */
  81         return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
  82 -                       QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV);
  83 +                                    QCA808X_ADC_THRESHOLD_MASK,
  84 +                                    QCA808X_ADC_THRESHOLD_100MV);
  85  }
  86
  87  static int qca808x_read_status(struct phy_device *phydev)
  88 @@ -1883,7 +1885,7 @@ static int qca808x_read_status(struct ph
  89                 return ret;
  90
  91         linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
  92 -                       ret & MDIO_AN_10GBT_STAT_LP2_5G);
  93 +                        ret & MDIO_AN_10GBT_STAT_LP2_5G);
  94
  95         ret = genphy_read_status(phydev);
  96         if (ret)
  97 @@ -1913,7 +1915,7 @@ static int qca808x_read_status(struct ph
  98                  */
  99                 if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
 100                         if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
 101 -                                       qca808x_is_prefer_master(phydev)) {
 102 +                           qca808x_is_prefer_master(phydev)) {
 103                                 qca808x_phy_ms_seed_enable(phydev, false);
 104                         } else {
 105                                 qca808x_phy_ms_seed_enable(phydev, true);
 106 @@ -2070,18 +2072,22 @@ static int qca808x_cable_test_get_status
 107         ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
 108                                 qca808x_cable_test_result_trans(pair_d));
 109
 110 -       if (qca808x_cdt_fault_length_valid(pair_a))
 111 -               ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A,
 112 -                               qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A));
 113 -       if (qca808x_cdt_fault_length_valid(pair_b))
 114 -               ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B,
 115 -                               qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B));
 116 -       if (qca808x_cdt_fault_length_valid(pair_c))
 117 -               ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C,
 118 -                               qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C));
 119 -       if (qca808x_cdt_fault_length_valid(pair_d))
 120 -               ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D,
 121 -                               qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D));
 122 +       if (qca808x_cdt_fault_length_valid(pair_a)) {
 123 +               val = qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A);
 124 +               ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
 125 +       }
 126 +       if (qca808x_cdt_fault_length_valid(pair_b)) {
 127 +               val = qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B);
 128 +               ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
 129 +       }
 130 +       if (qca808x_cdt_fault_length_valid(pair_c)) {
 131 +               val = qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C);
 132 +               ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
 133 +       }
 134 +       if (qca808x_cdt_fault_length_valid(pair_d)) {
 135 +               val = qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D);
 136 +               ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
 137 +       }
 138
 139         *finished = true;
 140
 141 @@ -2148,8 +2154,9 @@ static void qca808x_link_change_notify(s
 142          * the interface device address is always phy address added by 1.
 143          */
 144         mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
 145 -                       MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
 146 -                       QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
 147 +                                  MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
 148 +                                  QCA8081_PHY_FIFO_RSTN,
 149 +                                  phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
 150  }
 151
 152  static struct phy_driver at803x_driver[] = {