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[openwrt/openwrt.git] / target / linux / generic / backport-5.15 / 770-v6.0-net-dsa-qca8k-move-driver-to-qca-dir.patch
1 From 4bbaf764e1e1786eb937fdb62172f656f512e116 Mon Sep 17 00:00:00 2001
2 From: Christian Marangi <ansuelsmth@gmail.com>
3 Date: Wed, 13 Jul 2022 22:53:50 +0200
4 Subject: [PATCH 1/1] net: dsa: qca8k: move driver to qca dir
5
6 Move qca8k driver to qca dir in preparation for code split and
7 introduction of ipq4019 switch based on qca8k.
8
9 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
10 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
11 Signed-off-by: David S. Miller <davem@davemloft.net>
12 ---
13 drivers/net/dsa/Kconfig | 8 --------
14 drivers/net/dsa/Makefile | 1 -
15 drivers/net/dsa/qca/Kconfig | 8 ++++++++
16 drivers/net/dsa/qca/Makefile | 1 +
17 drivers/net/dsa/{ => qca}/qca8k.c | 0
18 drivers/net/dsa/{ => qca}/qca8k.h | 0
19 6 files changed, 9 insertions(+), 9 deletions(-)
20 rename drivers/net/dsa/{ => qca}/qca8k.c (100%)
21 rename drivers/net/dsa/{ => qca}/qca8k.h (100%)
22
23 --- a/drivers/net/dsa/Kconfig
24 +++ b/drivers/net/dsa/Kconfig
25 @@ -60,14 +60,6 @@ source "drivers/net/dsa/sja1105/Kconfig"
26
27 source "drivers/net/dsa/xrs700x/Kconfig"
28
29 -config NET_DSA_QCA8K
30 - tristate "Qualcomm Atheros QCA8K Ethernet switch family support"
31 - select NET_DSA_TAG_QCA
32 - select REGMAP
33 - help
34 - This enables support for the Qualcomm Atheros QCA8K Ethernet
35 - switch chips.
36 -
37 config NET_DSA_REALTEK_SMI
38 tristate "Realtek SMI Ethernet switch family support"
39 select NET_DSA_TAG_RTL4_A
40 --- a/drivers/net/dsa/Makefile
41 +++ b/drivers/net/dsa/Makefile
42 @@ -8,7 +8,6 @@ endif
43 obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o
44 obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o
45 obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
46 -obj-$(CONFIG_NET_DSA_QCA8K) += qca8k.o
47 obj-$(CONFIG_NET_DSA_REALTEK_SMI) += realtek-smi.o
48 realtek-smi-objs := realtek-smi-core.o rtl8366.o rtl8366rb.o
49 obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303-core.o
50 --- a/drivers/net/dsa/qca/Kconfig
51 +++ b/drivers/net/dsa/qca/Kconfig
52 @@ -7,3 +7,11 @@ config NET_DSA_AR9331
53 help
54 This enables support for the Qualcomm Atheros AR9331 built-in Ethernet
55 switch.
56 +
57 +config NET_DSA_QCA8K
58 + tristate "Qualcomm Atheros QCA8K Ethernet switch family support"
59 + select NET_DSA_TAG_QCA
60 + select REGMAP
61 + help
62 + This enables support for the Qualcomm Atheros QCA8K Ethernet
63 + switch chips.
64 --- a/drivers/net/dsa/qca/Makefile
65 +++ b/drivers/net/dsa/qca/Makefile
66 @@ -1,2 +1,3 @@
67 # SPDX-License-Identifier: GPL-2.0-only
68 obj-$(CONFIG_NET_DSA_AR9331) += ar9331.o
69 +obj-$(CONFIG_NET_DSA_QCA8K) += qca8k.o
70 --- /dev/null
71 +++ b/drivers/net/dsa/qca/qca8k.c
72 @@ -0,0 +1,3243 @@
73 +// SPDX-License-Identifier: GPL-2.0
74 +/*
75 + * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
76 + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
77 + * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
78 + * Copyright (c) 2016 John Crispin <john@phrozen.org>
79 + */
80 +
81 +#include <linux/module.h>
82 +#include <linux/phy.h>
83 +#include <linux/netdevice.h>
84 +#include <linux/bitfield.h>
85 +#include <linux/regmap.h>
86 +#include <net/dsa.h>
87 +#include <linux/of_net.h>
88 +#include <linux/of_mdio.h>
89 +#include <linux/of_platform.h>
90 +#include <linux/if_bridge.h>
91 +#include <linux/mdio.h>
92 +#include <linux/phylink.h>
93 +#include <linux/gpio/consumer.h>
94 +#include <linux/etherdevice.h>
95 +#include <linux/dsa/tag_qca.h>
96 +
97 +#include "qca8k.h"
98 +
99 +#define MIB_DESC(_s, _o, _n) \
100 + { \
101 + .size = (_s), \
102 + .offset = (_o), \
103 + .name = (_n), \
104 + }
105 +
106 +static const struct qca8k_mib_desc ar8327_mib[] = {
107 + MIB_DESC(1, 0x00, "RxBroad"),
108 + MIB_DESC(1, 0x04, "RxPause"),
109 + MIB_DESC(1, 0x08, "RxMulti"),
110 + MIB_DESC(1, 0x0c, "RxFcsErr"),
111 + MIB_DESC(1, 0x10, "RxAlignErr"),
112 + MIB_DESC(1, 0x14, "RxRunt"),
113 + MIB_DESC(1, 0x18, "RxFragment"),
114 + MIB_DESC(1, 0x1c, "Rx64Byte"),
115 + MIB_DESC(1, 0x20, "Rx128Byte"),
116 + MIB_DESC(1, 0x24, "Rx256Byte"),
117 + MIB_DESC(1, 0x28, "Rx512Byte"),
118 + MIB_DESC(1, 0x2c, "Rx1024Byte"),
119 + MIB_DESC(1, 0x30, "Rx1518Byte"),
120 + MIB_DESC(1, 0x34, "RxMaxByte"),
121 + MIB_DESC(1, 0x38, "RxTooLong"),
122 + MIB_DESC(2, 0x3c, "RxGoodByte"),
123 + MIB_DESC(2, 0x44, "RxBadByte"),
124 + MIB_DESC(1, 0x4c, "RxOverFlow"),
125 + MIB_DESC(1, 0x50, "Filtered"),
126 + MIB_DESC(1, 0x54, "TxBroad"),
127 + MIB_DESC(1, 0x58, "TxPause"),
128 + MIB_DESC(1, 0x5c, "TxMulti"),
129 + MIB_DESC(1, 0x60, "TxUnderRun"),
130 + MIB_DESC(1, 0x64, "Tx64Byte"),
131 + MIB_DESC(1, 0x68, "Tx128Byte"),
132 + MIB_DESC(1, 0x6c, "Tx256Byte"),
133 + MIB_DESC(1, 0x70, "Tx512Byte"),
134 + MIB_DESC(1, 0x74, "Tx1024Byte"),
135 + MIB_DESC(1, 0x78, "Tx1518Byte"),
136 + MIB_DESC(1, 0x7c, "TxMaxByte"),
137 + MIB_DESC(1, 0x80, "TxOverSize"),
138 + MIB_DESC(2, 0x84, "TxByte"),
139 + MIB_DESC(1, 0x8c, "TxCollision"),
140 + MIB_DESC(1, 0x90, "TxAbortCol"),
141 + MIB_DESC(1, 0x94, "TxMultiCol"),
142 + MIB_DESC(1, 0x98, "TxSingleCol"),
143 + MIB_DESC(1, 0x9c, "TxExcDefer"),
144 + MIB_DESC(1, 0xa0, "TxDefer"),
145 + MIB_DESC(1, 0xa4, "TxLateCol"),
146 + MIB_DESC(1, 0xa8, "RXUnicast"),
147 + MIB_DESC(1, 0xac, "TXUnicast"),
148 +};
149 +
150 +static void
151 +qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
152 +{
153 + regaddr >>= 1;
154 + *r1 = regaddr & 0x1e;
155 +
156 + regaddr >>= 5;
157 + *r2 = regaddr & 0x7;
158 +
159 + regaddr >>= 3;
160 + *page = regaddr & 0x3ff;
161 +}
162 +
163 +static int
164 +qca8k_set_lo(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 lo)
165 +{
166 + u16 *cached_lo = &priv->mdio_cache.lo;
167 + struct mii_bus *bus = priv->bus;
168 + int ret;
169 +
170 + if (lo == *cached_lo)
171 + return 0;
172 +
173 + ret = bus->write(bus, phy_id, regnum, lo);
174 + if (ret < 0)
175 + dev_err_ratelimited(&bus->dev,
176 + "failed to write qca8k 32bit lo register\n");
177 +
178 + *cached_lo = lo;
179 + return 0;
180 +}
181 +
182 +static int
183 +qca8k_set_hi(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 hi)
184 +{
185 + u16 *cached_hi = &priv->mdio_cache.hi;
186 + struct mii_bus *bus = priv->bus;
187 + int ret;
188 +
189 + if (hi == *cached_hi)
190 + return 0;
191 +
192 + ret = bus->write(bus, phy_id, regnum, hi);
193 + if (ret < 0)
194 + dev_err_ratelimited(&bus->dev,
195 + "failed to write qca8k 32bit hi register\n");
196 +
197 + *cached_hi = hi;
198 + return 0;
199 +}
200 +
201 +static int
202 +qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
203 +{
204 + int ret;
205 +
206 + ret = bus->read(bus, phy_id, regnum);
207 + if (ret >= 0) {
208 + *val = ret;
209 + ret = bus->read(bus, phy_id, regnum + 1);
210 + *val |= ret << 16;
211 + }
212 +
213 + if (ret < 0) {
214 + dev_err_ratelimited(&bus->dev,
215 + "failed to read qca8k 32bit register\n");
216 + *val = 0;
217 + return ret;
218 + }
219 +
220 + return 0;
221 +}
222 +
223 +static void
224 +qca8k_mii_write32(struct qca8k_priv *priv, int phy_id, u32 regnum, u32 val)
225 +{
226 + u16 lo, hi;
227 + int ret;
228 +
229 + lo = val & 0xffff;
230 + hi = (u16)(val >> 16);
231 +
232 + ret = qca8k_set_lo(priv, phy_id, regnum, lo);
233 + if (ret >= 0)
234 + ret = qca8k_set_hi(priv, phy_id, regnum + 1, hi);
235 +}
236 +
237 +static int
238 +qca8k_set_page(struct qca8k_priv *priv, u16 page)
239 +{
240 + u16 *cached_page = &priv->mdio_cache.page;
241 + struct mii_bus *bus = priv->bus;
242 + int ret;
243 +
244 + if (page == *cached_page)
245 + return 0;
246 +
247 + ret = bus->write(bus, 0x18, 0, page);
248 + if (ret < 0) {
249 + dev_err_ratelimited(&bus->dev,
250 + "failed to set qca8k page\n");
251 + return ret;
252 + }
253 +
254 + *cached_page = page;
255 + usleep_range(1000, 2000);
256 + return 0;
257 +}
258 +
259 +static int
260 +qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
261 +{
262 + return regmap_read(priv->regmap, reg, val);
263 +}
264 +
265 +static int
266 +qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
267 +{
268 + return regmap_write(priv->regmap, reg, val);
269 +}
270 +
271 +static int
272 +qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
273 +{
274 + return regmap_update_bits(priv->regmap, reg, mask, write_val);
275 +}
276 +
277 +static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff *skb)
278 +{
279 + struct qca8k_mgmt_eth_data *mgmt_eth_data;
280 + struct qca8k_priv *priv = ds->priv;
281 + struct qca_mgmt_ethhdr *mgmt_ethhdr;
282 + u8 len, cmd;
283 +
284 + mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb_mac_header(skb);
285 + mgmt_eth_data = &priv->mgmt_eth_data;
286 +
287 + cmd = FIELD_GET(QCA_HDR_MGMT_CMD, mgmt_ethhdr->command);
288 + len = FIELD_GET(QCA_HDR_MGMT_LENGTH, mgmt_ethhdr->command);
289 +
290 + /* Make sure the seq match the requested packet */
291 + if (mgmt_ethhdr->seq == mgmt_eth_data->seq)
292 + mgmt_eth_data->ack = true;
293 +
294 + if (cmd == MDIO_READ) {
295 + mgmt_eth_data->data[0] = mgmt_ethhdr->mdio_data;
296 +
297 + /* Get the rest of the 12 byte of data.
298 + * The read/write function will extract the requested data.
299 + */
300 + if (len > QCA_HDR_MGMT_DATA1_LEN)
301 + memcpy(mgmt_eth_data->data + 1, skb->data,
302 + QCA_HDR_MGMT_DATA2_LEN);
303 + }
304 +
305 + complete(&mgmt_eth_data->rw_done);
306 +}
307 +
308 +static struct sk_buff *qca8k_alloc_mdio_header(enum mdio_cmd cmd, u32 reg, u32 *val,
309 + int priority, unsigned int len)
310 +{
311 + struct qca_mgmt_ethhdr *mgmt_ethhdr;
312 + unsigned int real_len;
313 + struct sk_buff *skb;
314 + u32 *data2;
315 + u16 hdr;
316 +
317 + skb = dev_alloc_skb(QCA_HDR_MGMT_PKT_LEN);
318 + if (!skb)
319 + return NULL;
320 +
321 + /* Max value for len reg is 15 (0xf) but the switch actually return 16 byte
322 + * Actually for some reason the steps are:
323 + * 0: nothing
324 + * 1-4: first 4 byte
325 + * 5-6: first 12 byte
326 + * 7-15: all 16 byte
327 + */
328 + if (len == 16)
329 + real_len = 15;
330 + else
331 + real_len = len;
332 +
333 + skb_reset_mac_header(skb);
334 + skb_set_network_header(skb, skb->len);
335 +
336 + mgmt_ethhdr = skb_push(skb, QCA_HDR_MGMT_HEADER_LEN + QCA_HDR_LEN);
337 +
338 + hdr = FIELD_PREP(QCA_HDR_XMIT_VERSION, QCA_HDR_VERSION);
339 + hdr |= FIELD_PREP(QCA_HDR_XMIT_PRIORITY, priority);
340 + hdr |= QCA_HDR_XMIT_FROM_CPU;
341 + hdr |= FIELD_PREP(QCA_HDR_XMIT_DP_BIT, BIT(0));
342 + hdr |= FIELD_PREP(QCA_HDR_XMIT_CONTROL, QCA_HDR_XMIT_TYPE_RW_REG);
343 +
344 + mgmt_ethhdr->command = FIELD_PREP(QCA_HDR_MGMT_ADDR, reg);
345 + mgmt_ethhdr->command |= FIELD_PREP(QCA_HDR_MGMT_LENGTH, real_len);
346 + mgmt_ethhdr->command |= FIELD_PREP(QCA_HDR_MGMT_CMD, cmd);
347 + mgmt_ethhdr->command |= FIELD_PREP(QCA_HDR_MGMT_CHECK_CODE,
348 + QCA_HDR_MGMT_CHECK_CODE_VAL);
349 +
350 + if (cmd == MDIO_WRITE)
351 + mgmt_ethhdr->mdio_data = *val;
352 +
353 + mgmt_ethhdr->hdr = htons(hdr);
354 +
355 + data2 = skb_put_zero(skb, QCA_HDR_MGMT_DATA2_LEN + QCA_HDR_MGMT_PADDING_LEN);
356 + if (cmd == MDIO_WRITE && len > QCA_HDR_MGMT_DATA1_LEN)
357 + memcpy(data2, val + 1, len - QCA_HDR_MGMT_DATA1_LEN);
358 +
359 + return skb;
360 +}
361 +
362 +static void qca8k_mdio_header_fill_seq_num(struct sk_buff *skb, u32 seq_num)
363 +{
364 + struct qca_mgmt_ethhdr *mgmt_ethhdr;
365 +
366 + mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb->data;
367 + mgmt_ethhdr->seq = FIELD_PREP(QCA_HDR_MGMT_SEQ_NUM, seq_num);
368 +}
369 +
370 +static int qca8k_read_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
371 +{
372 + struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data;
373 + struct sk_buff *skb;
374 + bool ack;
375 + int ret;
376 +
377 + skb = qca8k_alloc_mdio_header(MDIO_READ, reg, NULL,
378 + QCA8K_ETHERNET_MDIO_PRIORITY, len);
379 + if (!skb)
380 + return -ENOMEM;
381 +
382 + mutex_lock(&mgmt_eth_data->mutex);
383 +
384 + /* Check mgmt_master if is operational */
385 + if (!priv->mgmt_master) {
386 + kfree_skb(skb);
387 + mutex_unlock(&mgmt_eth_data->mutex);
388 + return -EINVAL;
389 + }
390 +
391 + skb->dev = priv->mgmt_master;
392 +
393 + reinit_completion(&mgmt_eth_data->rw_done);
394 +
395 + /* Increment seq_num and set it in the mdio pkt */
396 + mgmt_eth_data->seq++;
397 + qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
398 + mgmt_eth_data->ack = false;
399 +
400 + dev_queue_xmit(skb);
401 +
402 + ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
403 + msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT));
404 +
405 + *val = mgmt_eth_data->data[0];
406 + if (len > QCA_HDR_MGMT_DATA1_LEN)
407 + memcpy(val + 1, mgmt_eth_data->data + 1, len - QCA_HDR_MGMT_DATA1_LEN);
408 +
409 + ack = mgmt_eth_data->ack;
410 +
411 + mutex_unlock(&mgmt_eth_data->mutex);
412 +
413 + if (ret <= 0)
414 + return -ETIMEDOUT;
415 +
416 + if (!ack)
417 + return -EINVAL;
418 +
419 + return 0;
420 +}
421 +
422 +static int qca8k_write_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
423 +{
424 + struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data;
425 + struct sk_buff *skb;
426 + bool ack;
427 + int ret;
428 +
429 + skb = qca8k_alloc_mdio_header(MDIO_WRITE, reg, val,
430 + QCA8K_ETHERNET_MDIO_PRIORITY, len);
431 + if (!skb)
432 + return -ENOMEM;
433 +
434 + mutex_lock(&mgmt_eth_data->mutex);
435 +
436 + /* Check mgmt_master if is operational */
437 + if (!priv->mgmt_master) {
438 + kfree_skb(skb);
439 + mutex_unlock(&mgmt_eth_data->mutex);
440 + return -EINVAL;
441 + }
442 +
443 + skb->dev = priv->mgmt_master;
444 +
445 + reinit_completion(&mgmt_eth_data->rw_done);
446 +
447 + /* Increment seq_num and set it in the mdio pkt */
448 + mgmt_eth_data->seq++;
449 + qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
450 + mgmt_eth_data->ack = false;
451 +
452 + dev_queue_xmit(skb);
453 +
454 + ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
455 + msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT));
456 +
457 + ack = mgmt_eth_data->ack;
458 +
459 + mutex_unlock(&mgmt_eth_data->mutex);
460 +
461 + if (ret <= 0)
462 + return -ETIMEDOUT;
463 +
464 + if (!ack)
465 + return -EINVAL;
466 +
467 + return 0;
468 +}
469 +
470 +static int
471 +qca8k_regmap_update_bits_eth(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
472 +{
473 + u32 val = 0;
474 + int ret;
475 +
476 + ret = qca8k_read_eth(priv, reg, &val, sizeof(val));
477 + if (ret)
478 + return ret;
479 +
480 + val &= ~mask;
481 + val |= write_val;
482 +
483 + return qca8k_write_eth(priv, reg, &val, sizeof(val));
484 +}
485 +
486 +static int
487 +qca8k_bulk_read(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
488 +{
489 + int i, count = len / sizeof(u32), ret;
490 +
491 + if (priv->mgmt_master && !qca8k_read_eth(priv, reg, val, len))
492 + return 0;
493 +
494 + for (i = 0; i < count; i++) {
495 + ret = regmap_read(priv->regmap, reg + (i * 4), val + i);
496 + if (ret < 0)
497 + return ret;
498 + }
499 +
500 + return 0;
501 +}
502 +
503 +static int
504 +qca8k_bulk_write(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
505 +{
506 + int i, count = len / sizeof(u32), ret;
507 + u32 tmp;
508 +
509 + if (priv->mgmt_master && !qca8k_write_eth(priv, reg, val, len))
510 + return 0;
511 +
512 + for (i = 0; i < count; i++) {
513 + tmp = val[i];
514 +
515 + ret = regmap_write(priv->regmap, reg + (i * 4), tmp);
516 + if (ret < 0)
517 + return ret;
518 + }
519 +
520 + return 0;
521 +}
522 +
523 +static int
524 +qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
525 +{
526 + struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
527 + struct mii_bus *bus = priv->bus;
528 + u16 r1, r2, page;
529 + int ret;
530 +
531 + if (!qca8k_read_eth(priv, reg, val, sizeof(*val)))
532 + return 0;
533 +
534 + qca8k_split_addr(reg, &r1, &r2, &page);
535 +
536 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
537 +
538 + ret = qca8k_set_page(priv, page);
539 + if (ret < 0)
540 + goto exit;
541 +
542 + ret = qca8k_mii_read32(bus, 0x10 | r2, r1, val);
543 +
544 +exit:
545 + mutex_unlock(&bus->mdio_lock);
546 + return ret;
547 +}
548 +
549 +static int
550 +qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
551 +{
552 + struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
553 + struct mii_bus *bus = priv->bus;
554 + u16 r1, r2, page;
555 + int ret;
556 +
557 + if (!qca8k_write_eth(priv, reg, &val, sizeof(val)))
558 + return 0;
559 +
560 + qca8k_split_addr(reg, &r1, &r2, &page);
561 +
562 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
563 +
564 + ret = qca8k_set_page(priv, page);
565 + if (ret < 0)
566 + goto exit;
567 +
568 + qca8k_mii_write32(priv, 0x10 | r2, r1, val);
569 +
570 +exit:
571 + mutex_unlock(&bus->mdio_lock);
572 + return ret;
573 +}
574 +
575 +static int
576 +qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_val)
577 +{
578 + struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
579 + struct mii_bus *bus = priv->bus;
580 + u16 r1, r2, page;
581 + u32 val;
582 + int ret;
583 +
584 + if (!qca8k_regmap_update_bits_eth(priv, reg, mask, write_val))
585 + return 0;
586 +
587 + qca8k_split_addr(reg, &r1, &r2, &page);
588 +
589 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
590 +
591 + ret = qca8k_set_page(priv, page);
592 + if (ret < 0)
593 + goto exit;
594 +
595 + ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
596 + if (ret < 0)
597 + goto exit;
598 +
599 + val &= ~mask;
600 + val |= write_val;
601 + qca8k_mii_write32(priv, 0x10 | r2, r1, val);
602 +
603 +exit:
604 + mutex_unlock(&bus->mdio_lock);
605 +
606 + return ret;
607 +}
608 +
609 +static const struct regmap_range qca8k_readable_ranges[] = {
610 + regmap_reg_range(0x0000, 0x00e4), /* Global control */
611 + regmap_reg_range(0x0100, 0x0168), /* EEE control */
612 + regmap_reg_range(0x0200, 0x0270), /* Parser control */
613 + regmap_reg_range(0x0400, 0x0454), /* ACL */
614 + regmap_reg_range(0x0600, 0x0718), /* Lookup */
615 + regmap_reg_range(0x0800, 0x0b70), /* QM */
616 + regmap_reg_range(0x0c00, 0x0c80), /* PKT */
617 + regmap_reg_range(0x0e00, 0x0e98), /* L3 */
618 + regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
619 + regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
620 + regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
621 + regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
622 + regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
623 + regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
624 + regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
625 +
626 +};
627 +
628 +static const struct regmap_access_table qca8k_readable_table = {
629 + .yes_ranges = qca8k_readable_ranges,
630 + .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
631 +};
632 +
633 +static struct regmap_config qca8k_regmap_config = {
634 + .reg_bits = 16,
635 + .val_bits = 32,
636 + .reg_stride = 4,
637 + .max_register = 0x16ac, /* end MIB - Port6 range */
638 + .reg_read = qca8k_regmap_read,
639 + .reg_write = qca8k_regmap_write,
640 + .reg_update_bits = qca8k_regmap_update_bits,
641 + .rd_table = &qca8k_readable_table,
642 + .disable_locking = true, /* Locking is handled by qca8k read/write */
643 + .cache_type = REGCACHE_NONE, /* Explicitly disable CACHE */
644 +};
645 +
646 +static int
647 +qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
648 +{
649 + u32 val;
650 +
651 + return regmap_read_poll_timeout(priv->regmap, reg, val, !(val & mask), 0,
652 + QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC);
653 +}
654 +
655 +static int
656 +qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
657 +{
658 + u32 reg[3];
659 + int ret;
660 +
661 + /* load the ARL table into an array */
662 + ret = qca8k_bulk_read(priv, QCA8K_REG_ATU_DATA0, reg, sizeof(reg));
663 + if (ret)
664 + return ret;
665 +
666 + /* vid - 83:72 */
667 + fdb->vid = FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]);
668 + /* aging - 67:64 */
669 + fdb->aging = FIELD_GET(QCA8K_ATU_STATUS_MASK, reg[2]);
670 + /* portmask - 54:48 */
671 + fdb->port_mask = FIELD_GET(QCA8K_ATU_PORT_MASK, reg[1]);
672 + /* mac - 47:0 */
673 + fdb->mac[0] = FIELD_GET(QCA8K_ATU_ADDR0_MASK, reg[1]);
674 + fdb->mac[1] = FIELD_GET(QCA8K_ATU_ADDR1_MASK, reg[1]);
675 + fdb->mac[2] = FIELD_GET(QCA8K_ATU_ADDR2_MASK, reg[0]);
676 + fdb->mac[3] = FIELD_GET(QCA8K_ATU_ADDR3_MASK, reg[0]);
677 + fdb->mac[4] = FIELD_GET(QCA8K_ATU_ADDR4_MASK, reg[0]);
678 + fdb->mac[5] = FIELD_GET(QCA8K_ATU_ADDR5_MASK, reg[0]);
679 +
680 + return 0;
681 +}
682 +
683 +static void
684 +qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
685 + u8 aging)
686 +{
687 + u32 reg[3] = { 0 };
688 +
689 + /* vid - 83:72 */
690 + reg[2] = FIELD_PREP(QCA8K_ATU_VID_MASK, vid);
691 + /* aging - 67:64 */
692 + reg[2] |= FIELD_PREP(QCA8K_ATU_STATUS_MASK, aging);
693 + /* portmask - 54:48 */
694 + reg[1] = FIELD_PREP(QCA8K_ATU_PORT_MASK, port_mask);
695 + /* mac - 47:0 */
696 + reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR0_MASK, mac[0]);
697 + reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR1_MASK, mac[1]);
698 + reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR2_MASK, mac[2]);
699 + reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR3_MASK, mac[3]);
700 + reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR4_MASK, mac[4]);
701 + reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]);
702 +
703 + /* load the array into the ARL table */
704 + qca8k_bulk_write(priv, QCA8K_REG_ATU_DATA0, reg, sizeof(reg));
705 +}
706 +
707 +static int
708 +qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
709 +{
710 + u32 reg;
711 + int ret;
712 +
713 + /* Set the command and FDB index */
714 + reg = QCA8K_ATU_FUNC_BUSY;
715 + reg |= cmd;
716 + if (port >= 0) {
717 + reg |= QCA8K_ATU_FUNC_PORT_EN;
718 + reg |= FIELD_PREP(QCA8K_ATU_FUNC_PORT_MASK, port);
719 + }
720 +
721 + /* Write the function register triggering the table access */
722 + ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
723 + if (ret)
724 + return ret;
725 +
726 + /* wait for completion */
727 + ret = qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY);
728 + if (ret)
729 + return ret;
730 +
731 + /* Check for table full violation when adding an entry */
732 + if (cmd == QCA8K_FDB_LOAD) {
733 + ret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, &reg);
734 + if (ret < 0)
735 + return ret;
736 + if (reg & QCA8K_ATU_FUNC_FULL)
737 + return -1;
738 + }
739 +
740 + return 0;
741 +}
742 +
743 +static int
744 +qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
745 +{
746 + int ret;
747 +
748 + qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
749 + ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
750 + if (ret < 0)
751 + return ret;
752 +
753 + return qca8k_fdb_read(priv, fdb);
754 +}
755 +
756 +static int
757 +qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
758 + u16 vid, u8 aging)
759 +{
760 + int ret;
761 +
762 + mutex_lock(&priv->reg_mutex);
763 + qca8k_fdb_write(priv, vid, port_mask, mac, aging);
764 + ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
765 + mutex_unlock(&priv->reg_mutex);
766 +
767 + return ret;
768 +}
769 +
770 +static int
771 +qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
772 +{
773 + int ret;
774 +
775 + mutex_lock(&priv->reg_mutex);
776 + qca8k_fdb_write(priv, vid, port_mask, mac, 0);
777 + ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
778 + mutex_unlock(&priv->reg_mutex);
779 +
780 + return ret;
781 +}
782 +
783 +static void
784 +qca8k_fdb_flush(struct qca8k_priv *priv)
785 +{
786 + mutex_lock(&priv->reg_mutex);
787 + qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
788 + mutex_unlock(&priv->reg_mutex);
789 +}
790 +
791 +static int
792 +qca8k_fdb_search_and_insert(struct qca8k_priv *priv, u8 port_mask,
793 + const u8 *mac, u16 vid)
794 +{
795 + struct qca8k_fdb fdb = { 0 };
796 + int ret;
797 +
798 + mutex_lock(&priv->reg_mutex);
799 +
800 + qca8k_fdb_write(priv, vid, 0, mac, 0);
801 + ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1);
802 + if (ret < 0)
803 + goto exit;
804 +
805 + ret = qca8k_fdb_read(priv, &fdb);
806 + if (ret < 0)
807 + goto exit;
808 +
809 + /* Rule exist. Delete first */
810 + if (!fdb.aging) {
811 + ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
812 + if (ret)
813 + goto exit;
814 + }
815 +
816 + /* Add port to fdb portmask */
817 + fdb.port_mask |= port_mask;
818 +
819 + qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging);
820 + ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
821 +
822 +exit:
823 + mutex_unlock(&priv->reg_mutex);
824 + return ret;
825 +}
826 +
827 +static int
828 +qca8k_fdb_search_and_del(struct qca8k_priv *priv, u8 port_mask,
829 + const u8 *mac, u16 vid)
830 +{
831 + struct qca8k_fdb fdb = { 0 };
832 + int ret;
833 +
834 + mutex_lock(&priv->reg_mutex);
835 +
836 + qca8k_fdb_write(priv, vid, 0, mac, 0);
837 + ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1);
838 + if (ret < 0)
839 + goto exit;
840 +
841 + /* Rule doesn't exist. Why delete? */
842 + if (!fdb.aging) {
843 + ret = -EINVAL;
844 + goto exit;
845 + }
846 +
847 + ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
848 + if (ret)
849 + goto exit;
850 +
851 + /* Only port in the rule is this port. Don't re insert */
852 + if (fdb.port_mask == port_mask)
853 + goto exit;
854 +
855 + /* Remove port from port mask */
856 + fdb.port_mask &= ~port_mask;
857 +
858 + qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging);
859 + ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
860 +
861 +exit:
862 + mutex_unlock(&priv->reg_mutex);
863 + return ret;
864 +}
865 +
866 +static int
867 +qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)
868 +{
869 + u32 reg;
870 + int ret;
871 +
872 + /* Set the command and VLAN index */
873 + reg = QCA8K_VTU_FUNC1_BUSY;
874 + reg |= cmd;
875 + reg |= FIELD_PREP(QCA8K_VTU_FUNC1_VID_MASK, vid);
876 +
877 + /* Write the function register triggering the table access */
878 + ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
879 + if (ret)
880 + return ret;
881 +
882 + /* wait for completion */
883 + ret = qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY);
884 + if (ret)
885 + return ret;
886 +
887 + /* Check for table full violation when adding an entry */
888 + if (cmd == QCA8K_VLAN_LOAD) {
889 + ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, &reg);
890 + if (ret < 0)
891 + return ret;
892 + if (reg & QCA8K_VTU_FUNC1_FULL)
893 + return -ENOMEM;
894 + }
895 +
896 + return 0;
897 +}
898 +
899 +static int
900 +qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged)
901 +{
902 + u32 reg;
903 + int ret;
904 +
905 + /*
906 + We do the right thing with VLAN 0 and treat it as untagged while
907 + preserving the tag on egress.
908 + */
909 + if (vid == 0)
910 + return 0;
911 +
912 + mutex_lock(&priv->reg_mutex);
913 + ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
914 + if (ret < 0)
915 + goto out;
916 +
917 + ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
918 + if (ret < 0)
919 + goto out;
920 + reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;
921 + reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);
922 + if (untagged)
923 + reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(port);
924 + else
925 + reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(port);
926 +
927 + ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
928 + if (ret)
929 + goto out;
930 + ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
931 +
932 +out:
933 + mutex_unlock(&priv->reg_mutex);
934 +
935 + return ret;
936 +}
937 +
938 +static int
939 +qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid)
940 +{
941 + u32 reg, mask;
942 + int ret, i;
943 + bool del;
944 +
945 + mutex_lock(&priv->reg_mutex);
946 + ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
947 + if (ret < 0)
948 + goto out;
949 +
950 + ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
951 + if (ret < 0)
952 + goto out;
953 + reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);
954 + reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(port);
955 +
956 + /* Check if we're the last member to be removed */
957 + del = true;
958 + for (i = 0; i < QCA8K_NUM_PORTS; i++) {
959 + mask = QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i);
960 +
961 + if ((reg & mask) != mask) {
962 + del = false;
963 + break;
964 + }
965 + }
966 +
967 + if (del) {
968 + ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid);
969 + } else {
970 + ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
971 + if (ret)
972 + goto out;
973 + ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
974 + }
975 +
976 +out:
977 + mutex_unlock(&priv->reg_mutex);
978 +
979 + return ret;
980 +}
981 +
982 +static int
983 +qca8k_mib_init(struct qca8k_priv *priv)
984 +{
985 + int ret;
986 +
987 + mutex_lock(&priv->reg_mutex);
988 + ret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB,
989 + QCA8K_MIB_FUNC | QCA8K_MIB_BUSY,
990 + FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_FLUSH) |
991 + QCA8K_MIB_BUSY);
992 + if (ret)
993 + goto exit;
994 +
995 + ret = qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
996 + if (ret)
997 + goto exit;
998 +
999 + ret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
1000 + if (ret)
1001 + goto exit;
1002 +
1003 + ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
1004 +
1005 +exit:
1006 + mutex_unlock(&priv->reg_mutex);
1007 + return ret;
1008 +}
1009 +
1010 +static void
1011 +qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
1012 +{
1013 + u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
1014 +
1015 + /* Port 0 and 6 have no internal PHY */
1016 + if (port > 0 && port < 6)
1017 + mask |= QCA8K_PORT_STATUS_LINK_AUTO;
1018 +
1019 + if (enable)
1020 + regmap_set_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);
1021 + else
1022 + regmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);
1023 +}
1024 +
1025 +static int
1026 +qca8k_phy_eth_busy_wait(struct qca8k_mgmt_eth_data *mgmt_eth_data,
1027 + struct sk_buff *read_skb, u32 *val)
1028 +{
1029 + struct sk_buff *skb = skb_copy(read_skb, GFP_KERNEL);
1030 + bool ack;
1031 + int ret;
1032 +
1033 + reinit_completion(&mgmt_eth_data->rw_done);
1034 +
1035 + /* Increment seq_num and set it in the copy pkt */
1036 + mgmt_eth_data->seq++;
1037 + qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
1038 + mgmt_eth_data->ack = false;
1039 +
1040 + dev_queue_xmit(skb);
1041 +
1042 + ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
1043 + QCA8K_ETHERNET_TIMEOUT);
1044 +
1045 + ack = mgmt_eth_data->ack;
1046 +
1047 + if (ret <= 0)
1048 + return -ETIMEDOUT;
1049 +
1050 + if (!ack)
1051 + return -EINVAL;
1052 +
1053 + *val = mgmt_eth_data->data[0];
1054 +
1055 + return 0;
1056 +}
1057 +
1058 +static int
1059 +qca8k_phy_eth_command(struct qca8k_priv *priv, bool read, int phy,
1060 + int regnum, u16 data)
1061 +{
1062 + struct sk_buff *write_skb, *clear_skb, *read_skb;
1063 + struct qca8k_mgmt_eth_data *mgmt_eth_data;
1064 + u32 write_val, clear_val = 0, val;
1065 + struct net_device *mgmt_master;
1066 + int ret, ret1;
1067 + bool ack;
1068 +
1069 + if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
1070 + return -EINVAL;
1071 +
1072 + mgmt_eth_data = &priv->mgmt_eth_data;
1073 +
1074 + write_val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
1075 + QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
1076 + QCA8K_MDIO_MASTER_REG_ADDR(regnum);
1077 +
1078 + if (read) {
1079 + write_val |= QCA8K_MDIO_MASTER_READ;
1080 + } else {
1081 + write_val |= QCA8K_MDIO_MASTER_WRITE;
1082 + write_val |= QCA8K_MDIO_MASTER_DATA(data);
1083 + }
1084 +
1085 + /* Prealloc all the needed skb before the lock */
1086 + write_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, &write_val,
1087 + QCA8K_ETHERNET_PHY_PRIORITY, sizeof(write_val));
1088 + if (!write_skb)
1089 + return -ENOMEM;
1090 +
1091 + clear_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, &clear_val,
1092 + QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val));
1093 + if (!clear_skb) {
1094 + ret = -ENOMEM;
1095 + goto err_clear_skb;
1096 + }
1097 +
1098 + read_skb = qca8k_alloc_mdio_header(MDIO_READ, QCA8K_MDIO_MASTER_CTRL, &clear_val,
1099 + QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val));
1100 + if (!read_skb) {
1101 + ret = -ENOMEM;
1102 + goto err_read_skb;
1103 + }
1104 +
1105 + /* Actually start the request:
1106 + * 1. Send mdio master packet
1107 + * 2. Busy Wait for mdio master command
1108 + * 3. Get the data if we are reading
1109 + * 4. Reset the mdio master (even with error)
1110 + */
1111 + mutex_lock(&mgmt_eth_data->mutex);
1112 +
1113 + /* Check if mgmt_master is operational */
1114 + mgmt_master = priv->mgmt_master;
1115 + if (!mgmt_master) {
1116 + mutex_unlock(&mgmt_eth_data->mutex);
1117 + ret = -EINVAL;
1118 + goto err_mgmt_master;
1119 + }
1120 +
1121 + read_skb->dev = mgmt_master;
1122 + clear_skb->dev = mgmt_master;
1123 + write_skb->dev = mgmt_master;
1124 +
1125 + reinit_completion(&mgmt_eth_data->rw_done);
1126 +
1127 + /* Increment seq_num and set it in the write pkt */
1128 + mgmt_eth_data->seq++;
1129 + qca8k_mdio_header_fill_seq_num(write_skb, mgmt_eth_data->seq);
1130 + mgmt_eth_data->ack = false;
1131 +
1132 + dev_queue_xmit(write_skb);
1133 +
1134 + ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
1135 + QCA8K_ETHERNET_TIMEOUT);
1136 +
1137 + ack = mgmt_eth_data->ack;
1138 +
1139 + if (ret <= 0) {
1140 + ret = -ETIMEDOUT;
1141 + kfree_skb(read_skb);
1142 + goto exit;
1143 + }
1144 +
1145 + if (!ack) {
1146 + ret = -EINVAL;
1147 + kfree_skb(read_skb);
1148 + goto exit;
1149 + }
1150 +
1151 + ret = read_poll_timeout(qca8k_phy_eth_busy_wait, ret1,
1152 + !(val & QCA8K_MDIO_MASTER_BUSY), 0,
1153 + QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
1154 + mgmt_eth_data, read_skb, &val);
1155 +
1156 + if (ret < 0 && ret1 < 0) {
1157 + ret = ret1;
1158 + goto exit;
1159 + }
1160 +
1161 + if (read) {
1162 + reinit_completion(&mgmt_eth_data->rw_done);
1163 +
1164 + /* Increment seq_num and set it in the read pkt */
1165 + mgmt_eth_data->seq++;
1166 + qca8k_mdio_header_fill_seq_num(read_skb, mgmt_eth_data->seq);
1167 + mgmt_eth_data->ack = false;
1168 +
1169 + dev_queue_xmit(read_skb);
1170 +
1171 + ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
1172 + QCA8K_ETHERNET_TIMEOUT);
1173 +
1174 + ack = mgmt_eth_data->ack;
1175 +
1176 + if (ret <= 0) {
1177 + ret = -ETIMEDOUT;
1178 + goto exit;
1179 + }
1180 +
1181 + if (!ack) {
1182 + ret = -EINVAL;
1183 + goto exit;
1184 + }
1185 +
1186 + ret = mgmt_eth_data->data[0] & QCA8K_MDIO_MASTER_DATA_MASK;
1187 + } else {
1188 + kfree_skb(read_skb);
1189 + }
1190 +exit:
1191 + reinit_completion(&mgmt_eth_data->rw_done);
1192 +
1193 + /* Increment seq_num and set it in the clear pkt */
1194 + mgmt_eth_data->seq++;
1195 + qca8k_mdio_header_fill_seq_num(clear_skb, mgmt_eth_data->seq);
1196 + mgmt_eth_data->ack = false;
1197 +
1198 + dev_queue_xmit(clear_skb);
1199 +
1200 + wait_for_completion_timeout(&mgmt_eth_data->rw_done,
1201 + QCA8K_ETHERNET_TIMEOUT);
1202 +
1203 + mutex_unlock(&mgmt_eth_data->mutex);
1204 +
1205 + return ret;
1206 +
1207 + /* Error handling before lock */
1208 +err_mgmt_master:
1209 + kfree_skb(read_skb);
1210 +err_read_skb:
1211 + kfree_skb(clear_skb);
1212 +err_clear_skb:
1213 + kfree_skb(write_skb);
1214 +
1215 + return ret;
1216 +}
1217 +
1218 +static u32
1219 +qca8k_port_to_phy(int port)
1220 +{
1221 + /* From Andrew Lunn:
1222 + * Port 0 has no internal phy.
1223 + * Port 1 has an internal PHY at MDIO address 0.
1224 + * Port 2 has an internal PHY at MDIO address 1.
1225 + * ...
1226 + * Port 5 has an internal PHY at MDIO address 4.
1227 + * Port 6 has no internal PHY.
1228 + */
1229 +
1230 + return port - 1;
1231 +}
1232 +
1233 +static int
1234 +qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)
1235 +{
1236 + u16 r1, r2, page;
1237 + u32 val;
1238 + int ret, ret1;
1239 +
1240 + qca8k_split_addr(reg, &r1, &r2, &page);
1241 +
1242 + ret = read_poll_timeout(qca8k_mii_read32, ret1, !(val & mask), 0,
1243 + QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
1244 + bus, 0x10 | r2, r1, &val);
1245 +
1246 + /* Check if qca8k_read has failed for a different reason
1247 + * before returnting -ETIMEDOUT
1248 + */
1249 + if (ret < 0 && ret1 < 0)
1250 + return ret1;
1251 +
1252 + return ret;
1253 +}
1254 +
1255 +static int
1256 +qca8k_mdio_write(struct qca8k_priv *priv, int phy, int regnum, u16 data)
1257 +{
1258 + struct mii_bus *bus = priv->bus;
1259 + u16 r1, r2, page;
1260 + u32 val;
1261 + int ret;
1262 +
1263 + if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
1264 + return -EINVAL;
1265 +
1266 + val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
1267 + QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
1268 + QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
1269 + QCA8K_MDIO_MASTER_DATA(data);
1270 +
1271 + qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
1272 +
1273 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
1274 +
1275 + ret = qca8k_set_page(priv, page);
1276 + if (ret)
1277 + goto exit;
1278 +
1279 + qca8k_mii_write32(priv, 0x10 | r2, r1, val);
1280 +
1281 + ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
1282 + QCA8K_MDIO_MASTER_BUSY);
1283 +
1284 +exit:
1285 + /* even if the busy_wait timeouts try to clear the MASTER_EN */
1286 + qca8k_mii_write32(priv, 0x10 | r2, r1, 0);
1287 +
1288 + mutex_unlock(&bus->mdio_lock);
1289 +
1290 + return ret;
1291 +}
1292 +
1293 +static int
1294 +qca8k_mdio_read(struct qca8k_priv *priv, int phy, int regnum)
1295 +{
1296 + struct mii_bus *bus = priv->bus;
1297 + u16 r1, r2, page;
1298 + u32 val;
1299 + int ret;
1300 +
1301 + if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
1302 + return -EINVAL;
1303 +
1304 + val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
1305 + QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
1306 + QCA8K_MDIO_MASTER_REG_ADDR(regnum);
1307 +
1308 + qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
1309 +
1310 + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
1311 +
1312 + ret = qca8k_set_page(priv, page);
1313 + if (ret)
1314 + goto exit;
1315 +
1316 + qca8k_mii_write32(priv, 0x10 | r2, r1, val);
1317 +
1318 + ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
1319 + QCA8K_MDIO_MASTER_BUSY);
1320 + if (ret)
1321 + goto exit;
1322 +
1323 + ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
1324 +
1325 +exit:
1326 + /* even if the busy_wait timeouts try to clear the MASTER_EN */
1327 + qca8k_mii_write32(priv, 0x10 | r2, r1, 0);
1328 +
1329 + mutex_unlock(&bus->mdio_lock);
1330 +
1331 + if (ret >= 0)
1332 + ret = val & QCA8K_MDIO_MASTER_DATA_MASK;
1333 +
1334 + return ret;
1335 +}
1336 +
1337 +static int
1338 +qca8k_internal_mdio_write(struct mii_bus *slave_bus, int phy, int regnum, u16 data)
1339 +{
1340 + struct qca8k_priv *priv = slave_bus->priv;
1341 + int ret;
1342 +
1343 + /* Use mdio Ethernet when available, fallback to legacy one on error */
1344 + ret = qca8k_phy_eth_command(priv, false, phy, regnum, data);
1345 + if (!ret)
1346 + return 0;
1347 +
1348 + return qca8k_mdio_write(priv, phy, regnum, data);
1349 +}
1350 +
1351 +static int
1352 +qca8k_internal_mdio_read(struct mii_bus *slave_bus, int phy, int regnum)
1353 +{
1354 + struct qca8k_priv *priv = slave_bus->priv;
1355 + int ret;
1356 +
1357 + /* Use mdio Ethernet when available, fallback to legacy one on error */
1358 + ret = qca8k_phy_eth_command(priv, true, phy, regnum, 0);
1359 + if (ret >= 0)
1360 + return ret;
1361 +
1362 + ret = qca8k_mdio_read(priv, phy, regnum);
1363 +
1364 + if (ret < 0)
1365 + return 0xffff;
1366 +
1367 + return ret;
1368 +}
1369 +
1370 +static int
1371 +qca8k_legacy_mdio_write(struct mii_bus *slave_bus, int port, int regnum, u16 data)
1372 +{
1373 + port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
1374 +
1375 + return qca8k_internal_mdio_write(slave_bus, port, regnum, data);
1376 +}
1377 +
1378 +static int
1379 +qca8k_legacy_mdio_read(struct mii_bus *slave_bus, int port, int regnum)
1380 +{
1381 + port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
1382 +
1383 + return qca8k_internal_mdio_read(slave_bus, port, regnum);
1384 +}
1385 +
1386 +static int
1387 +qca8k_mdio_register(struct qca8k_priv *priv)
1388 +{
1389 + struct dsa_switch *ds = priv->ds;
1390 + struct device_node *mdio;
1391 + struct mii_bus *bus;
1392 +
1393 + bus = devm_mdiobus_alloc(ds->dev);
1394 + if (!bus)
1395 + return -ENOMEM;
1396 +
1397 + bus->priv = (void *)priv;
1398 + snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d.%d",
1399 + ds->dst->index, ds->index);
1400 + bus->parent = ds->dev;
1401 + bus->phy_mask = ~ds->phys_mii_mask;
1402 + ds->slave_mii_bus = bus;
1403 +
1404 + /* Check if the devicetree declare the port:phy mapping */
1405 + mdio = of_get_child_by_name(priv->dev->of_node, "mdio");
1406 + if (of_device_is_available(mdio)) {
1407 + bus->name = "qca8k slave mii";
1408 + bus->read = qca8k_internal_mdio_read;
1409 + bus->write = qca8k_internal_mdio_write;
1410 + return devm_of_mdiobus_register(priv->dev, bus, mdio);
1411 + }
1412 +
1413 + /* If a mapping can't be found the legacy mapping is used,
1414 + * using the qca8k_port_to_phy function
1415 + */
1416 + bus->name = "qca8k-legacy slave mii";
1417 + bus->read = qca8k_legacy_mdio_read;
1418 + bus->write = qca8k_legacy_mdio_write;
1419 + return devm_mdiobus_register(priv->dev, bus);
1420 +}
1421 +
1422 +static int
1423 +qca8k_setup_mdio_bus(struct qca8k_priv *priv)
1424 +{
1425 + u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg;
1426 + struct device_node *ports, *port;
1427 + phy_interface_t mode;
1428 + int err;
1429 +
1430 + ports = of_get_child_by_name(priv->dev->of_node, "ports");
1431 + if (!ports)
1432 + ports = of_get_child_by_name(priv->dev->of_node, "ethernet-ports");
1433 +
1434 + if (!ports)
1435 + return -EINVAL;
1436 +
1437 + for_each_available_child_of_node(ports, port) {
1438 + err = of_property_read_u32(port, "reg", &reg);
1439 + if (err) {
1440 + of_node_put(port);
1441 + of_node_put(ports);
1442 + return err;
1443 + }
1444 +
1445 + if (!dsa_is_user_port(priv->ds, reg))
1446 + continue;
1447 +
1448 + of_get_phy_mode(port, &mode);
1449 +
1450 + if (of_property_read_bool(port, "phy-handle") &&
1451 + mode != PHY_INTERFACE_MODE_INTERNAL)
1452 + external_mdio_mask |= BIT(reg);
1453 + else
1454 + internal_mdio_mask |= BIT(reg);
1455 + }
1456 +
1457 + of_node_put(ports);
1458 + if (!external_mdio_mask && !internal_mdio_mask) {
1459 + dev_err(priv->dev, "no PHYs are defined.\n");
1460 + return -EINVAL;
1461 + }
1462 +
1463 + /* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through
1464 + * the MDIO_MASTER register also _disconnects_ the external MDC
1465 + * passthrough to the internal PHYs. It's not possible to use both
1466 + * configurations at the same time!
1467 + *
1468 + * Because this came up during the review process:
1469 + * If the external mdio-bus driver is capable magically disabling
1470 + * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's
1471 + * accessors for the time being, it would be possible to pull this
1472 + * off.
1473 + */
1474 + if (!!external_mdio_mask && !!internal_mdio_mask) {
1475 + dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n");
1476 + return -EINVAL;
1477 + }
1478 +
1479 + if (external_mdio_mask) {
1480 + /* Make sure to disable the internal mdio bus in cases
1481 + * a dt-overlay and driver reload changed the configuration
1482 + */
1483 +
1484 + return regmap_clear_bits(priv->regmap, QCA8K_MDIO_MASTER_CTRL,
1485 + QCA8K_MDIO_MASTER_EN);
1486 + }
1487 +
1488 + return qca8k_mdio_register(priv);
1489 +}
1490 +
1491 +static int
1492 +qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
1493 +{
1494 + u32 mask = 0;
1495 + int ret = 0;
1496 +
1497 + /* SoC specific settings for ipq8064.
1498 + * If more device require this consider adding
1499 + * a dedicated binding.
1500 + */
1501 + if (of_machine_is_compatible("qcom,ipq8064"))
1502 + mask |= QCA8K_MAC_PWR_RGMII0_1_8V;
1503 +
1504 + /* SoC specific settings for ipq8065 */
1505 + if (of_machine_is_compatible("qcom,ipq8065"))
1506 + mask |= QCA8K_MAC_PWR_RGMII1_1_8V;
1507 +
1508 + if (mask) {
1509 + ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL,
1510 + QCA8K_MAC_PWR_RGMII0_1_8V |
1511 + QCA8K_MAC_PWR_RGMII1_1_8V,
1512 + mask);
1513 + }
1514 +
1515 + return ret;
1516 +}
1517 +
1518 +static int qca8k_find_cpu_port(struct dsa_switch *ds)
1519 +{
1520 + struct qca8k_priv *priv = ds->priv;
1521 +
1522 + /* Find the connected cpu port. Valid port are 0 or 6 */
1523 + if (dsa_is_cpu_port(ds, 0))
1524 + return 0;
1525 +
1526 + dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6");
1527 +
1528 + if (dsa_is_cpu_port(ds, 6))
1529 + return 6;
1530 +
1531 + return -EINVAL;
1532 +}
1533 +
1534 +static int
1535 +qca8k_setup_of_pws_reg(struct qca8k_priv *priv)
1536 +{
1537 + struct device_node *node = priv->dev->of_node;
1538 + const struct qca8k_match_data *data;
1539 + u32 val = 0;
1540 + int ret;
1541 +
1542 + /* QCA8327 require to set to the correct mode.
1543 + * His bigger brother QCA8328 have the 172 pin layout.
1544 + * Should be applied by default but we set this just to make sure.
1545 + */
1546 + if (priv->switch_id == QCA8K_ID_QCA8327) {
1547 + data = of_device_get_match_data(priv->dev);
1548 +
1549 + /* Set the correct package of 148 pin for QCA8327 */
1550 + if (data->reduced_package)
1551 + val |= QCA8327_PWS_PACKAGE148_EN;
1552 +
1553 + ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN,
1554 + val);
1555 + if (ret)
1556 + return ret;
1557 + }
1558 +
1559 + if (of_property_read_bool(node, "qca,ignore-power-on-sel"))
1560 + val |= QCA8K_PWS_POWER_ON_SEL;
1561 +
1562 + if (of_property_read_bool(node, "qca,led-open-drain")) {
1563 + if (!(val & QCA8K_PWS_POWER_ON_SEL)) {
1564 + dev_err(priv->dev, "qca,led-open-drain require qca,ignore-power-on-sel to be set.");
1565 + return -EINVAL;
1566 + }
1567 +
1568 + val |= QCA8K_PWS_LED_OPEN_EN_CSR;
1569 + }
1570 +
1571 + return qca8k_rmw(priv, QCA8K_REG_PWS,
1572 + QCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL,
1573 + val);
1574 +}
1575 +
1576 +static int
1577 +qca8k_parse_port_config(struct qca8k_priv *priv)
1578 +{
1579 + int port, cpu_port_index = -1, ret;
1580 + struct device_node *port_dn;
1581 + phy_interface_t mode;
1582 + struct dsa_port *dp;
1583 + u32 delay;
1584 +
1585 + /* We have 2 CPU port. Check them */
1586 + for (port = 0; port < QCA8K_NUM_PORTS; port++) {
1587 + /* Skip every other port */
1588 + if (port != 0 && port != 6)
1589 + continue;
1590 +
1591 + dp = dsa_to_port(priv->ds, port);
1592 + port_dn = dp->dn;
1593 + cpu_port_index++;
1594 +
1595 + if (!of_device_is_available(port_dn))
1596 + continue;
1597 +
1598 + ret = of_get_phy_mode(port_dn, &mode);
1599 + if (ret)
1600 + continue;
1601 +
1602 + switch (mode) {
1603 + case PHY_INTERFACE_MODE_RGMII:
1604 + case PHY_INTERFACE_MODE_RGMII_ID:
1605 + case PHY_INTERFACE_MODE_RGMII_TXID:
1606 + case PHY_INTERFACE_MODE_RGMII_RXID:
1607 + case PHY_INTERFACE_MODE_SGMII:
1608 + delay = 0;
1609 +
1610 + if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay))
1611 + /* Switch regs accept value in ns, convert ps to ns */
1612 + delay = delay / 1000;
1613 + else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
1614 + mode == PHY_INTERFACE_MODE_RGMII_TXID)
1615 + delay = 1;
1616 +
1617 + if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, delay)) {
1618 + dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
1619 + delay = 3;
1620 + }
1621 +
1622 + priv->ports_config.rgmii_tx_delay[cpu_port_index] = delay;
1623 +
1624 + delay = 0;
1625 +
1626 + if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay))
1627 + /* Switch regs accept value in ns, convert ps to ns */
1628 + delay = delay / 1000;
1629 + else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
1630 + mode == PHY_INTERFACE_MODE_RGMII_RXID)
1631 + delay = 2;
1632 +
1633 + if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, delay)) {
1634 + dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
1635 + delay = 3;
1636 + }
1637 +
1638 + priv->ports_config.rgmii_rx_delay[cpu_port_index] = delay;
1639 +
1640 + /* Skip sgmii parsing for rgmii* mode */
1641 + if (mode == PHY_INTERFACE_MODE_RGMII ||
1642 + mode == PHY_INTERFACE_MODE_RGMII_ID ||
1643 + mode == PHY_INTERFACE_MODE_RGMII_TXID ||
1644 + mode == PHY_INTERFACE_MODE_RGMII_RXID)
1645 + break;
1646 +
1647 + if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge"))
1648 + priv->ports_config.sgmii_tx_clk_falling_edge = true;
1649 +
1650 + if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
1651 + priv->ports_config.sgmii_rx_clk_falling_edge = true;
1652 +
1653 + if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) {
1654 + priv->ports_config.sgmii_enable_pll = true;
1655 +
1656 + if (priv->switch_id == QCA8K_ID_QCA8327) {
1657 + dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling");
1658 + priv->ports_config.sgmii_enable_pll = false;
1659 + }
1660 +
1661 + if (priv->switch_revision < 2)
1662 + dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more.");
1663 + }
1664 +
1665 + break;
1666 + default:
1667 + continue;
1668 + }
1669 + }
1670 +
1671 + return 0;
1672 +}
1673 +
1674 +static int
1675 +qca8k_setup(struct dsa_switch *ds)
1676 +{
1677 + struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
1678 + int cpu_port, ret, i;
1679 + u32 mask;
1680 +
1681 + cpu_port = qca8k_find_cpu_port(ds);
1682 + if (cpu_port < 0) {
1683 + dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6");
1684 + return cpu_port;
1685 + }
1686 +
1687 + /* Parse CPU port config to be later used in phy_link mac_config */
1688 + ret = qca8k_parse_port_config(priv);
1689 + if (ret)
1690 + return ret;
1691 +
1692 + ret = qca8k_setup_mdio_bus(priv);
1693 + if (ret)
1694 + return ret;
1695 +
1696 + ret = qca8k_setup_of_pws_reg(priv);
1697 + if (ret)
1698 + return ret;
1699 +
1700 + ret = qca8k_setup_mac_pwr_sel(priv);
1701 + if (ret)
1702 + return ret;
1703 +
1704 + /* Make sure MAC06 is disabled */
1705 + ret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT0_PAD_CTRL,
1706 + QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);
1707 + if (ret) {
1708 + dev_err(priv->dev, "failed disabling MAC06 exchange");
1709 + return ret;
1710 + }
1711 +
1712 + /* Enable CPU Port */
1713 + ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
1714 + QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
1715 + if (ret) {
1716 + dev_err(priv->dev, "failed enabling CPU port");
1717 + return ret;
1718 + }
1719 +
1720 + /* Enable MIB counters */
1721 + ret = qca8k_mib_init(priv);
1722 + if (ret)
1723 + dev_warn(priv->dev, "mib init failed");
1724 +
1725 + /* Initial setup of all ports */
1726 + for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1727 + /* Disable forwarding by default on all ports */
1728 + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1729 + QCA8K_PORT_LOOKUP_MEMBER, 0);
1730 + if (ret)
1731 + return ret;
1732 +
1733 + /* Enable QCA header mode on all cpu ports */
1734 + if (dsa_is_cpu_port(ds, i)) {
1735 + ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i),
1736 + FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |
1737 + FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));
1738 + if (ret) {
1739 + dev_err(priv->dev, "failed enabling QCA header mode");
1740 + return ret;
1741 + }
1742 + }
1743 +
1744 + /* Disable MAC by default on all user ports */
1745 + if (dsa_is_user_port(ds, i))
1746 + qca8k_port_set_status(priv, i, 0);
1747 + }
1748 +
1749 + /* Forward all unknown frames to CPU port for Linux processing
1750 + * Notice that in multi-cpu config only one port should be set
1751 + * for igmp, unknown, multicast and broadcast packet
1752 + */
1753 + ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
1754 + FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) |
1755 + FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) |
1756 + FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) |
1757 + FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port)));
1758 + if (ret)
1759 + return ret;
1760 +
1761 + /* Setup connection between CPU port & user ports
1762 + * Configure specific switch configuration for ports
1763 + */
1764 + for (i = 0; i < QCA8K_NUM_PORTS; i++) {
1765 + /* CPU port gets connected to all user ports of the switch */
1766 + if (dsa_is_cpu_port(ds, i)) {
1767 + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1768 + QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
1769 + if (ret)
1770 + return ret;
1771 + }
1772 +
1773 + /* Individual user ports get connected to CPU port only */
1774 + if (dsa_is_user_port(ds, i)) {
1775 + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
1776 + QCA8K_PORT_LOOKUP_MEMBER,
1777 + BIT(cpu_port));
1778 + if (ret)
1779 + return ret;
1780 +
1781 + /* Enable ARP Auto-learning by default */
1782 + ret = regmap_set_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(i),
1783 + QCA8K_PORT_LOOKUP_LEARN);
1784 + if (ret)
1785 + return ret;
1786 +
1787 + /* For port based vlans to work we need to set the
1788 + * default egress vid
1789 + */
1790 + ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
1791 + QCA8K_EGREES_VLAN_PORT_MASK(i),
1792 + QCA8K_EGREES_VLAN_PORT(i, QCA8K_PORT_VID_DEF));
1793 + if (ret)
1794 + return ret;
1795 +
1796 + ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
1797 + QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
1798 + QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
1799 + if (ret)
1800 + return ret;
1801 + }
1802 +
1803 + /* The port 5 of the qca8337 have some problem in flood condition. The
1804 + * original legacy driver had some specific buffer and priority settings
1805 + * for the different port suggested by the QCA switch team. Add this
1806 + * missing settings to improve switch stability under load condition.
1807 + * This problem is limited to qca8337 and other qca8k switch are not affected.
1808 + */
1809 + if (priv->switch_id == QCA8K_ID_QCA8337) {
1810 + switch (i) {
1811 + /* The 2 CPU port and port 5 requires some different
1812 + * priority than any other ports.
1813 + */
1814 + case 0:
1815 + case 5:
1816 + case 6:
1817 + mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1818 + QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1819 + QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |
1820 + QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |
1821 + QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |
1822 + QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |
1823 + QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
1824 + break;
1825 + default:
1826 + mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
1827 + QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
1828 + QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |
1829 + QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |
1830 + QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
1831 + }
1832 + qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask);
1833 +
1834 + mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |
1835 + QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1836 + QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1837 + QCA8K_PORT_HOL_CTRL1_WRED_EN;
1838 + qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),
1839 + QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |
1840 + QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
1841 + QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
1842 + QCA8K_PORT_HOL_CTRL1_WRED_EN,
1843 + mask);
1844 + }
1845 + }
1846 +
1847 + /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */
1848 + if (priv->switch_id == QCA8K_ID_QCA8327) {
1849 + mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |
1850 + QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);
1851 + qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,
1852 + QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK |
1853 + QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK,
1854 + mask);
1855 + }
1856 +
1857 + /* Setup our port MTUs to match power on defaults */
1858 + ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
1859 + if (ret)
1860 + dev_warn(priv->dev, "failed setting MTU settings");
1861 +
1862 + /* Flush the FDB table */
1863 + qca8k_fdb_flush(priv);
1864 +
1865 + /* We don't have interrupts for link changes, so we need to poll */
1866 + ds->pcs_poll = true;
1867 +
1868 + /* Set min a max ageing value supported */
1869 + ds->ageing_time_min = 7000;
1870 + ds->ageing_time_max = 458745000;
1871 +
1872 + /* Set max number of LAGs supported */
1873 + ds->num_lag_ids = QCA8K_NUM_LAGS;
1874 +
1875 + return 0;
1876 +}
1877 +
1878 +static void
1879 +qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_index,
1880 + u32 reg)
1881 +{
1882 + u32 delay, val = 0;
1883 + int ret;
1884 +
1885 + /* Delay can be declared in 3 different way.
1886 + * Mode to rgmii and internal-delay standard binding defined
1887 + * rgmii-id or rgmii-tx/rx phy mode set.
1888 + * The parse logic set a delay different than 0 only when one
1889 + * of the 3 different way is used. In all other case delay is
1890 + * not enabled. With ID or TX/RXID delay is enabled and set
1891 + * to the default and recommended value.
1892 + */
1893 + if (priv->ports_config.rgmii_tx_delay[cpu_port_index]) {
1894 + delay = priv->ports_config.rgmii_tx_delay[cpu_port_index];
1895 +
1896 + val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
1897 + QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
1898 + }
1899 +
1900 + if (priv->ports_config.rgmii_rx_delay[cpu_port_index]) {
1901 + delay = priv->ports_config.rgmii_rx_delay[cpu_port_index];
1902 +
1903 + val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
1904 + QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
1905 + }
1906 +
1907 + /* Set RGMII delay based on the selected values */
1908 + ret = qca8k_rmw(priv, reg,
1909 + QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK |
1910 + QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK |
1911 + QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
1912 + QCA8K_PORT_PAD_RGMII_RX_DELAY_EN,
1913 + val);
1914 + if (ret)
1915 + dev_err(priv->dev, "Failed to set internal delay for CPU port%d",
1916 + cpu_port_index == QCA8K_CPU_PORT0 ? 0 : 6);
1917 +}
1918 +
1919 +static void
1920 +qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
1921 + const struct phylink_link_state *state)
1922 +{
1923 + struct qca8k_priv *priv = ds->priv;
1924 + int cpu_port_index, ret;
1925 + u32 reg, val;
1926 +
1927 + switch (port) {
1928 + case 0: /* 1st CPU port */
1929 + if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1930 + state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1931 + state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1932 + state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1933 + state->interface != PHY_INTERFACE_MODE_SGMII)
1934 + return;
1935 +
1936 + reg = QCA8K_REG_PORT0_PAD_CTRL;
1937 + cpu_port_index = QCA8K_CPU_PORT0;
1938 + break;
1939 + case 1:
1940 + case 2:
1941 + case 3:
1942 + case 4:
1943 + case 5:
1944 + /* Internal PHY, nothing to do */
1945 + return;
1946 + case 6: /* 2nd CPU port / external PHY */
1947 + if (state->interface != PHY_INTERFACE_MODE_RGMII &&
1948 + state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
1949 + state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
1950 + state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
1951 + state->interface != PHY_INTERFACE_MODE_SGMII &&
1952 + state->interface != PHY_INTERFACE_MODE_1000BASEX)
1953 + return;
1954 +
1955 + reg = QCA8K_REG_PORT6_PAD_CTRL;
1956 + cpu_port_index = QCA8K_CPU_PORT6;
1957 + break;
1958 + default:
1959 + dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
1960 + return;
1961 + }
1962 +
1963 + if (port != 6 && phylink_autoneg_inband(mode)) {
1964 + dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
1965 + __func__);
1966 + return;
1967 + }
1968 +
1969 + switch (state->interface) {
1970 + case PHY_INTERFACE_MODE_RGMII:
1971 + case PHY_INTERFACE_MODE_RGMII_ID:
1972 + case PHY_INTERFACE_MODE_RGMII_TXID:
1973 + case PHY_INTERFACE_MODE_RGMII_RXID:
1974 + qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
1975 +
1976 + /* Configure rgmii delay */
1977 + qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
1978 +
1979 + /* QCA8337 requires to set rgmii rx delay for all ports.
1980 + * This is enabled through PORT5_PAD_CTRL for all ports,
1981 + * rather than individual port registers.
1982 + */
1983 + if (priv->switch_id == QCA8K_ID_QCA8337)
1984 + qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
1985 + QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
1986 + break;
1987 + case PHY_INTERFACE_MODE_SGMII:
1988 + case PHY_INTERFACE_MODE_1000BASEX:
1989 + /* Enable SGMII on the port */
1990 + qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
1991 +
1992 + /* Enable/disable SerDes auto-negotiation as necessary */
1993 + ret = qca8k_read(priv, QCA8K_REG_PWS, &val);
1994 + if (ret)
1995 + return;
1996 + if (phylink_autoneg_inband(mode))
1997 + val &= ~QCA8K_PWS_SERDES_AEN_DIS;
1998 + else
1999 + val |= QCA8K_PWS_SERDES_AEN_DIS;
2000 + qca8k_write(priv, QCA8K_REG_PWS, val);
2001 +
2002 + /* Configure the SGMII parameters */
2003 + ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
2004 + if (ret)
2005 + return;
2006 +
2007 + val |= QCA8K_SGMII_EN_SD;
2008 +
2009 + if (priv->ports_config.sgmii_enable_pll)
2010 + val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
2011 + QCA8K_SGMII_EN_TX;
2012 +
2013 + if (dsa_is_cpu_port(ds, port)) {
2014 + /* CPU port, we're talking to the CPU MAC, be a PHY */
2015 + val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
2016 + val |= QCA8K_SGMII_MODE_CTRL_PHY;
2017 + } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
2018 + val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
2019 + val |= QCA8K_SGMII_MODE_CTRL_MAC;
2020 + } else if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
2021 + val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
2022 + val |= QCA8K_SGMII_MODE_CTRL_BASEX;
2023 + }
2024 +
2025 + qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
2026 +
2027 + /* From original code is reported port instability as SGMII also
2028 + * require delay set. Apply advised values here or take them from DT.
2029 + */
2030 + if (state->interface == PHY_INTERFACE_MODE_SGMII)
2031 + qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
2032 +
2033 + /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
2034 + * falling edge is set writing in the PORT0 PAD reg
2035 + */
2036 + if (priv->switch_id == QCA8K_ID_QCA8327 ||
2037 + priv->switch_id == QCA8K_ID_QCA8337)
2038 + reg = QCA8K_REG_PORT0_PAD_CTRL;
2039 +
2040 + val = 0;
2041 +
2042 + /* SGMII Clock phase configuration */
2043 + if (priv->ports_config.sgmii_rx_clk_falling_edge)
2044 + val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
2045 +
2046 + if (priv->ports_config.sgmii_tx_clk_falling_edge)
2047 + val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
2048 +
2049 + if (val)
2050 + ret = qca8k_rmw(priv, reg,
2051 + QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
2052 + QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
2053 + val);
2054 +
2055 + break;
2056 + default:
2057 + dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
2058 + phy_modes(state->interface), port);
2059 + return;
2060 + }
2061 +}
2062 +
2063 +static void
2064 +qca8k_phylink_validate(struct dsa_switch *ds, int port,
2065 + unsigned long *supported,
2066 + struct phylink_link_state *state)
2067 +{
2068 + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
2069 +
2070 + switch (port) {
2071 + case 0: /* 1st CPU port */
2072 + if (state->interface != PHY_INTERFACE_MODE_NA &&
2073 + state->interface != PHY_INTERFACE_MODE_RGMII &&
2074 + state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
2075 + state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
2076 + state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
2077 + state->interface != PHY_INTERFACE_MODE_SGMII)
2078 + goto unsupported;
2079 + break;
2080 + case 1:
2081 + case 2:
2082 + case 3:
2083 + case 4:
2084 + case 5:
2085 + /* Internal PHY */
2086 + if (state->interface != PHY_INTERFACE_MODE_NA &&
2087 + state->interface != PHY_INTERFACE_MODE_GMII &&
2088 + state->interface != PHY_INTERFACE_MODE_INTERNAL)
2089 + goto unsupported;
2090 + break;
2091 + case 6: /* 2nd CPU port / external PHY */
2092 + if (state->interface != PHY_INTERFACE_MODE_NA &&
2093 + state->interface != PHY_INTERFACE_MODE_RGMII &&
2094 + state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
2095 + state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
2096 + state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
2097 + state->interface != PHY_INTERFACE_MODE_SGMII &&
2098 + state->interface != PHY_INTERFACE_MODE_1000BASEX)
2099 + goto unsupported;
2100 + break;
2101 + default:
2102 +unsupported:
2103 + linkmode_zero(supported);
2104 + return;
2105 + }
2106 +
2107 + phylink_set_port_modes(mask);
2108 + phylink_set(mask, Autoneg);
2109 +
2110 + phylink_set(mask, 1000baseT_Full);
2111 + phylink_set(mask, 10baseT_Half);
2112 + phylink_set(mask, 10baseT_Full);
2113 + phylink_set(mask, 100baseT_Half);
2114 + phylink_set(mask, 100baseT_Full);
2115 +
2116 + if (state->interface == PHY_INTERFACE_MODE_1000BASEX)
2117 + phylink_set(mask, 1000baseX_Full);
2118 +
2119 + phylink_set(mask, Pause);
2120 + phylink_set(mask, Asym_Pause);
2121 +
2122 + linkmode_and(supported, supported, mask);
2123 + linkmode_and(state->advertising, state->advertising, mask);
2124 +}
2125 +
2126 +static int
2127 +qca8k_phylink_mac_link_state(struct dsa_switch *ds, int port,
2128 + struct phylink_link_state *state)
2129 +{
2130 + struct qca8k_priv *priv = ds->priv;
2131 + u32 reg;
2132 + int ret;
2133 +
2134 + ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), &reg);
2135 + if (ret < 0)
2136 + return ret;
2137 +
2138 + state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
2139 + state->an_complete = state->link;
2140 + state->an_enabled = !!(reg & QCA8K_PORT_STATUS_LINK_AUTO);
2141 + state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
2142 + DUPLEX_HALF;
2143 +
2144 + switch (reg & QCA8K_PORT_STATUS_SPEED) {
2145 + case QCA8K_PORT_STATUS_SPEED_10:
2146 + state->speed = SPEED_10;
2147 + break;
2148 + case QCA8K_PORT_STATUS_SPEED_100:
2149 + state->speed = SPEED_100;
2150 + break;
2151 + case QCA8K_PORT_STATUS_SPEED_1000:
2152 + state->speed = SPEED_1000;
2153 + break;
2154 + default:
2155 + state->speed = SPEED_UNKNOWN;
2156 + break;
2157 + }
2158 +
2159 + state->pause = MLO_PAUSE_NONE;
2160 + if (reg & QCA8K_PORT_STATUS_RXFLOW)
2161 + state->pause |= MLO_PAUSE_RX;
2162 + if (reg & QCA8K_PORT_STATUS_TXFLOW)
2163 + state->pause |= MLO_PAUSE_TX;
2164 +
2165 + return 1;
2166 +}
2167 +
2168 +static void
2169 +qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
2170 + phy_interface_t interface)
2171 +{
2172 + struct qca8k_priv *priv = ds->priv;
2173 +
2174 + qca8k_port_set_status(priv, port, 0);
2175 +}
2176 +
2177 +static void
2178 +qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
2179 + phy_interface_t interface, struct phy_device *phydev,
2180 + int speed, int duplex, bool tx_pause, bool rx_pause)
2181 +{
2182 + struct qca8k_priv *priv = ds->priv;
2183 + u32 reg;
2184 +
2185 + if (phylink_autoneg_inband(mode)) {
2186 + reg = QCA8K_PORT_STATUS_LINK_AUTO;
2187 + } else {
2188 + switch (speed) {
2189 + case SPEED_10:
2190 + reg = QCA8K_PORT_STATUS_SPEED_10;
2191 + break;
2192 + case SPEED_100:
2193 + reg = QCA8K_PORT_STATUS_SPEED_100;
2194 + break;
2195 + case SPEED_1000:
2196 + reg = QCA8K_PORT_STATUS_SPEED_1000;
2197 + break;
2198 + default:
2199 + reg = QCA8K_PORT_STATUS_LINK_AUTO;
2200 + break;
2201 + }
2202 +
2203 + if (duplex == DUPLEX_FULL)
2204 + reg |= QCA8K_PORT_STATUS_DUPLEX;
2205 +
2206 + if (rx_pause || dsa_is_cpu_port(ds, port))
2207 + reg |= QCA8K_PORT_STATUS_RXFLOW;
2208 +
2209 + if (tx_pause || dsa_is_cpu_port(ds, port))
2210 + reg |= QCA8K_PORT_STATUS_TXFLOW;
2211 + }
2212 +
2213 + reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
2214 +
2215 + qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
2216 +}
2217 +
2218 +static void
2219 +qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)
2220 +{
2221 + const struct qca8k_match_data *match_data;
2222 + struct qca8k_priv *priv = ds->priv;
2223 + int i;
2224 +
2225 + if (stringset != ETH_SS_STATS)
2226 + return;
2227 +
2228 + match_data = of_device_get_match_data(priv->dev);
2229 +
2230 + for (i = 0; i < match_data->mib_count; i++)
2231 + strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
2232 + ETH_GSTRING_LEN);
2233 +}
2234 +
2235 +static void qca8k_mib_autocast_handler(struct dsa_switch *ds, struct sk_buff *skb)
2236 +{
2237 + const struct qca8k_match_data *match_data;
2238 + struct qca8k_mib_eth_data *mib_eth_data;
2239 + struct qca8k_priv *priv = ds->priv;
2240 + const struct qca8k_mib_desc *mib;
2241 + struct mib_ethhdr *mib_ethhdr;
2242 + int i, mib_len, offset = 0;
2243 + u64 *data;
2244 + u8 port;
2245 +
2246 + mib_ethhdr = (struct mib_ethhdr *)skb_mac_header(skb);
2247 + mib_eth_data = &priv->mib_eth_data;
2248 +
2249 + /* The switch autocast every port. Ignore other packet and
2250 + * parse only the requested one.
2251 + */
2252 + port = FIELD_GET(QCA_HDR_RECV_SOURCE_PORT, ntohs(mib_ethhdr->hdr));
2253 + if (port != mib_eth_data->req_port)
2254 + goto exit;
2255 +
2256 + match_data = device_get_match_data(priv->dev);
2257 + data = mib_eth_data->data;
2258 +
2259 + for (i = 0; i < match_data->mib_count; i++) {
2260 + mib = &ar8327_mib[i];
2261 +
2262 + /* First 3 mib are present in the skb head */
2263 + if (i < 3) {
2264 + data[i] = mib_ethhdr->data[i];
2265 + continue;
2266 + }
2267 +
2268 + mib_len = sizeof(uint32_t);
2269 +
2270 + /* Some mib are 64 bit wide */
2271 + if (mib->size == 2)
2272 + mib_len = sizeof(uint64_t);
2273 +
2274 + /* Copy the mib value from packet to the */
2275 + memcpy(data + i, skb->data + offset, mib_len);
2276 +
2277 + /* Set the offset for the next mib */
2278 + offset += mib_len;
2279 + }
2280 +
2281 +exit:
2282 + /* Complete on receiving all the mib packet */
2283 + if (refcount_dec_and_test(&mib_eth_data->port_parsed))
2284 + complete(&mib_eth_data->rw_done);
2285 +}
2286 +
2287 +static int
2288 +qca8k_get_ethtool_stats_eth(struct dsa_switch *ds, int port, u64 *data)
2289 +{
2290 + struct dsa_port *dp = dsa_to_port(ds, port);
2291 + struct qca8k_mib_eth_data *mib_eth_data;
2292 + struct qca8k_priv *priv = ds->priv;
2293 + int ret;
2294 +
2295 + mib_eth_data = &priv->mib_eth_data;
2296 +
2297 + mutex_lock(&mib_eth_data->mutex);
2298 +
2299 + reinit_completion(&mib_eth_data->rw_done);
2300 +
2301 + mib_eth_data->req_port = dp->index;
2302 + mib_eth_data->data = data;
2303 + refcount_set(&mib_eth_data->port_parsed, QCA8K_NUM_PORTS);
2304 +
2305 + mutex_lock(&priv->reg_mutex);
2306 +
2307 + /* Send mib autocast request */
2308 + ret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB,
2309 + QCA8K_MIB_FUNC | QCA8K_MIB_BUSY,
2310 + FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_CAST) |
2311 + QCA8K_MIB_BUSY);
2312 +
2313 + mutex_unlock(&priv->reg_mutex);
2314 +
2315 + if (ret)
2316 + goto exit;
2317 +
2318 + ret = wait_for_completion_timeout(&mib_eth_data->rw_done, QCA8K_ETHERNET_TIMEOUT);
2319 +
2320 +exit:
2321 + mutex_unlock(&mib_eth_data->mutex);
2322 +
2323 + return ret;
2324 +}
2325 +
2326 +static void
2327 +qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
2328 + uint64_t *data)
2329 +{
2330 + struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
2331 + const struct qca8k_match_data *match_data;
2332 + const struct qca8k_mib_desc *mib;
2333 + u32 reg, i, val;
2334 + u32 hi = 0;
2335 + int ret;
2336 +
2337 + if (priv->mgmt_master &&
2338 + qca8k_get_ethtool_stats_eth(ds, port, data) > 0)
2339 + return;
2340 +
2341 + match_data = of_device_get_match_data(priv->dev);
2342 +
2343 + for (i = 0; i < match_data->mib_count; i++) {
2344 + mib = &ar8327_mib[i];
2345 + reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
2346 +
2347 + ret = qca8k_read(priv, reg, &val);
2348 + if (ret < 0)
2349 + continue;
2350 +
2351 + if (mib->size == 2) {
2352 + ret = qca8k_read(priv, reg + 4, &hi);
2353 + if (ret < 0)
2354 + continue;
2355 + }
2356 +
2357 + data[i] = val;
2358 + if (mib->size == 2)
2359 + data[i] |= (u64)hi << 32;
2360 + }
2361 +}
2362 +
2363 +static int
2364 +qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
2365 +{
2366 + const struct qca8k_match_data *match_data;
2367 + struct qca8k_priv *priv = ds->priv;
2368 +
2369 + if (sset != ETH_SS_STATS)
2370 + return 0;
2371 +
2372 + match_data = of_device_get_match_data(priv->dev);
2373 +
2374 + return match_data->mib_count;
2375 +}
2376 +
2377 +static int
2378 +qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
2379 +{
2380 + struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
2381 + u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
2382 + u32 reg;
2383 + int ret;
2384 +
2385 + mutex_lock(&priv->reg_mutex);
2386 + ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, &reg);
2387 + if (ret < 0)
2388 + goto exit;
2389 +
2390 + if (eee->eee_enabled)
2391 + reg |= lpi_en;
2392 + else
2393 + reg &= ~lpi_en;
2394 + ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
2395 +
2396 +exit:
2397 + mutex_unlock(&priv->reg_mutex);
2398 + return ret;
2399 +}
2400 +
2401 +static int
2402 +qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
2403 +{
2404 + /* Nothing to do on the port's MAC */
2405 + return 0;
2406 +}
2407 +
2408 +static void
2409 +qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
2410 +{
2411 + struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
2412 + u32 stp_state;
2413 +
2414 + switch (state) {
2415 + case BR_STATE_DISABLED:
2416 + stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
2417 + break;
2418 + case BR_STATE_BLOCKING:
2419 + stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
2420 + break;
2421 + case BR_STATE_LISTENING:
2422 + stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
2423 + break;
2424 + case BR_STATE_LEARNING:
2425 + stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
2426 + break;
2427 + case BR_STATE_FORWARDING:
2428 + default:
2429 + stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
2430 + break;
2431 + }
2432 +
2433 + qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
2434 + QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
2435 +}
2436 +
2437 +static int
2438 +qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
2439 +{
2440 + struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
2441 + int port_mask, cpu_port;
2442 + int i, ret;
2443 +
2444 + cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
2445 + port_mask = BIT(cpu_port);
2446 +
2447 + for (i = 0; i < QCA8K_NUM_PORTS; i++) {
2448 + if (dsa_is_cpu_port(ds, i))
2449 + continue;
2450 + if (dsa_to_port(ds, i)->bridge_dev != br)
2451 + continue;
2452 + /* Add this port to the portvlan mask of the other ports
2453 + * in the bridge
2454 + */
2455 + ret = regmap_set_bits(priv->regmap,
2456 + QCA8K_PORT_LOOKUP_CTRL(i),
2457 + BIT(port));
2458 + if (ret)
2459 + return ret;
2460 + if (i != port)
2461 + port_mask |= BIT(i);
2462 + }
2463 +
2464 + /* Add all other ports to this ports portvlan mask */
2465 + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
2466 + QCA8K_PORT_LOOKUP_MEMBER, port_mask);
2467 +
2468 + return ret;
2469 +}
2470 +
2471 +static void
2472 +qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
2473 +{
2474 + struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
2475 + int cpu_port, i;
2476 +
2477 + cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
2478 +
2479 + for (i = 0; i < QCA8K_NUM_PORTS; i++) {
2480 + if (dsa_is_cpu_port(ds, i))
2481 + continue;
2482 + if (dsa_to_port(ds, i)->bridge_dev != br)
2483 + continue;
2484 + /* Remove this port to the portvlan mask of the other ports
2485 + * in the bridge
2486 + */
2487 + regmap_clear_bits(priv->regmap,
2488 + QCA8K_PORT_LOOKUP_CTRL(i),
2489 + BIT(port));
2490 + }
2491 +
2492 + /* Set the cpu port to be the only one in the portvlan mask of
2493 + * this port
2494 + */
2495 + qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
2496 + QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port));
2497 +}
2498 +
2499 +static void
2500 +qca8k_port_fast_age(struct dsa_switch *ds, int port)
2501 +{
2502 + struct qca8k_priv *priv = ds->priv;
2503 +
2504 + mutex_lock(&priv->reg_mutex);
2505 + qca8k_fdb_access(priv, QCA8K_FDB_FLUSH_PORT, port);
2506 + mutex_unlock(&priv->reg_mutex);
2507 +}
2508 +
2509 +static int
2510 +qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
2511 +{
2512 + struct qca8k_priv *priv = ds->priv;
2513 + unsigned int secs = msecs / 1000;
2514 + u32 val;
2515 +
2516 + /* AGE_TIME reg is set in 7s step */
2517 + val = secs / 7;
2518 +
2519 + /* Handle case with 0 as val to NOT disable
2520 + * learning
2521 + */
2522 + if (!val)
2523 + val = 1;
2524 +
2525 + return regmap_update_bits(priv->regmap, QCA8K_REG_ATU_CTRL, QCA8K_ATU_AGE_TIME_MASK,
2526 + QCA8K_ATU_AGE_TIME(val));
2527 +}
2528 +
2529 +static int
2530 +qca8k_port_enable(struct dsa_switch *ds, int port,
2531 + struct phy_device *phy)
2532 +{
2533 + struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
2534 +
2535 + qca8k_port_set_status(priv, port, 1);
2536 + priv->port_enabled_map |= BIT(port);
2537 +
2538 + if (dsa_is_user_port(ds, port))
2539 + phy_support_asym_pause(phy);
2540 +
2541 + return 0;
2542 +}
2543 +
2544 +static void
2545 +qca8k_port_disable(struct dsa_switch *ds, int port)
2546 +{
2547 + struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
2548 +
2549 + qca8k_port_set_status(priv, port, 0);
2550 + priv->port_enabled_map &= ~BIT(port);
2551 +}
2552 +
2553 +static int
2554 +qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2555 +{
2556 + struct qca8k_priv *priv = ds->priv;
2557 + int ret;
2558 +
2559 + /* We have only have a general MTU setting.
2560 + * DSA always set the CPU port's MTU to the largest MTU of the slave
2561 + * ports.
2562 + * Setting MTU just for the CPU port is sufficient to correctly set a
2563 + * value for every port.
2564 + */
2565 + if (!dsa_is_cpu_port(ds, port))
2566 + return 0;
2567 +
2568 + /* To change the MAX_FRAME_SIZE the cpu ports must be off or
2569 + * the switch panics.
2570 + * Turn off both cpu ports before applying the new value to prevent
2571 + * this.
2572 + */
2573 + if (priv->port_enabled_map & BIT(0))
2574 + qca8k_port_set_status(priv, 0, 0);
2575 +
2576 + if (priv->port_enabled_map & BIT(6))
2577 + qca8k_port_set_status(priv, 6, 0);
2578 +
2579 + /* Include L2 header / FCS length */
2580 + ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, new_mtu + ETH_HLEN + ETH_FCS_LEN);
2581 +
2582 + if (priv->port_enabled_map & BIT(0))
2583 + qca8k_port_set_status(priv, 0, 1);
2584 +
2585 + if (priv->port_enabled_map & BIT(6))
2586 + qca8k_port_set_status(priv, 6, 1);
2587 +
2588 + return ret;
2589 +}
2590 +
2591 +static int
2592 +qca8k_port_max_mtu(struct dsa_switch *ds, int port)
2593 +{
2594 + return QCA8K_MAX_MTU;
2595 +}
2596 +
2597 +static int
2598 +qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
2599 + u16 port_mask, u16 vid)
2600 +{
2601 + /* Set the vid to the port vlan id if no vid is set */
2602 + if (!vid)
2603 + vid = QCA8K_PORT_VID_DEF;
2604 +
2605 + return qca8k_fdb_add(priv, addr, port_mask, vid,
2606 + QCA8K_ATU_STATUS_STATIC);
2607 +}
2608 +
2609 +static int
2610 +qca8k_port_fdb_add(struct dsa_switch *ds, int port,
2611 + const unsigned char *addr, u16 vid)
2612 +{
2613 + struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
2614 + u16 port_mask = BIT(port);
2615 +
2616 + return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
2617 +}
2618 +
2619 +static int
2620 +qca8k_port_fdb_del(struct dsa_switch *ds, int port,
2621 + const unsigned char *addr, u16 vid)
2622 +{
2623 + struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
2624 + u16 port_mask = BIT(port);
2625 +
2626 + if (!vid)
2627 + vid = QCA8K_PORT_VID_DEF;
2628 +
2629 + return qca8k_fdb_del(priv, addr, port_mask, vid);
2630 +}
2631 +
2632 +static int
2633 +qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
2634 + dsa_fdb_dump_cb_t *cb, void *data)
2635 +{
2636 + struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
2637 + struct qca8k_fdb _fdb = { 0 };
2638 + int cnt = QCA8K_NUM_FDB_RECORDS;
2639 + bool is_static;
2640 + int ret = 0;
2641 +
2642 + mutex_lock(&priv->reg_mutex);
2643 + while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
2644 + if (!_fdb.aging)
2645 + break;
2646 + is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
2647 + ret = cb(_fdb.mac, _fdb.vid, is_static, data);
2648 + if (ret)
2649 + break;
2650 + }
2651 + mutex_unlock(&priv->reg_mutex);
2652 +
2653 + return 0;
2654 +}
2655 +
2656 +static int
2657 +qca8k_port_mdb_add(struct dsa_switch *ds, int port,
2658 + const struct switchdev_obj_port_mdb *mdb)
2659 +{
2660 + struct qca8k_priv *priv = ds->priv;
2661 + const u8 *addr = mdb->addr;
2662 + u16 vid = mdb->vid;
2663 +
2664 + return qca8k_fdb_search_and_insert(priv, BIT(port), addr, vid);
2665 +}
2666 +
2667 +static int
2668 +qca8k_port_mdb_del(struct dsa_switch *ds, int port,
2669 + const struct switchdev_obj_port_mdb *mdb)
2670 +{
2671 + struct qca8k_priv *priv = ds->priv;
2672 + const u8 *addr = mdb->addr;
2673 + u16 vid = mdb->vid;
2674 +
2675 + return qca8k_fdb_search_and_del(priv, BIT(port), addr, vid);
2676 +}
2677 +
2678 +static int
2679 +qca8k_port_mirror_add(struct dsa_switch *ds, int port,
2680 + struct dsa_mall_mirror_tc_entry *mirror,
2681 + bool ingress)
2682 +{
2683 + struct qca8k_priv *priv = ds->priv;
2684 + int monitor_port, ret;
2685 + u32 reg, val;
2686 +
2687 + /* Check for existent entry */
2688 + if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
2689 + return -EEXIST;
2690 +
2691 + ret = regmap_read(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, &val);
2692 + if (ret)
2693 + return ret;
2694 +
2695 + /* QCA83xx can have only one port set to mirror mode.
2696 + * Check that the correct port is requested and return error otherwise.
2697 + * When no mirror port is set, the values is set to 0xF
2698 + */
2699 + monitor_port = FIELD_GET(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
2700 + if (monitor_port != 0xF && monitor_port != mirror->to_local_port)
2701 + return -EEXIST;
2702 +
2703 + /* Set the monitor port */
2704 + val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM,
2705 + mirror->to_local_port);
2706 + ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
2707 + QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
2708 + if (ret)
2709 + return ret;
2710 +
2711 + if (ingress) {
2712 + reg = QCA8K_PORT_LOOKUP_CTRL(port);
2713 + val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN;
2714 + } else {
2715 + reg = QCA8K_REG_PORT_HOL_CTRL1(port);
2716 + val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN;
2717 + }
2718 +
2719 + ret = regmap_update_bits(priv->regmap, reg, val, val);
2720 + if (ret)
2721 + return ret;
2722 +
2723 + /* Track mirror port for tx and rx to decide when the
2724 + * mirror port has to be disabled.
2725 + */
2726 + if (ingress)
2727 + priv->mirror_rx |= BIT(port);
2728 + else
2729 + priv->mirror_tx |= BIT(port);
2730 +
2731 + return 0;
2732 +}
2733 +
2734 +static void
2735 +qca8k_port_mirror_del(struct dsa_switch *ds, int port,
2736 + struct dsa_mall_mirror_tc_entry *mirror)
2737 +{
2738 + struct qca8k_priv *priv = ds->priv;
2739 + u32 reg, val;
2740 + int ret;
2741 +
2742 + if (mirror->ingress) {
2743 + reg = QCA8K_PORT_LOOKUP_CTRL(port);
2744 + val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN;
2745 + } else {
2746 + reg = QCA8K_REG_PORT_HOL_CTRL1(port);
2747 + val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN;
2748 + }
2749 +
2750 + ret = regmap_clear_bits(priv->regmap, reg, val);
2751 + if (ret)
2752 + goto err;
2753 +
2754 + if (mirror->ingress)
2755 + priv->mirror_rx &= ~BIT(port);
2756 + else
2757 + priv->mirror_tx &= ~BIT(port);
2758 +
2759 + /* No port set to send packet to mirror port. Disable mirror port */
2760 + if (!priv->mirror_rx && !priv->mirror_tx) {
2761 + val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, 0xF);
2762 + ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
2763 + QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
2764 + if (ret)
2765 + goto err;
2766 + }
2767 +err:
2768 + dev_err(priv->dev, "Failed to del mirror port from %d", port);
2769 +}
2770 +
2771 +static int
2772 +qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
2773 + struct netlink_ext_ack *extack)
2774 +{
2775 + struct qca8k_priv *priv = ds->priv;
2776 + int ret;
2777 +
2778 + if (vlan_filtering) {
2779 + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
2780 + QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,
2781 + QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);
2782 + } else {
2783 + ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
2784 + QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,
2785 + QCA8K_PORT_LOOKUP_VLAN_MODE_NONE);
2786 + }
2787 +
2788 + return ret;
2789 +}
2790 +
2791 +static int
2792 +qca8k_port_vlan_add(struct dsa_switch *ds, int port,
2793 + const struct switchdev_obj_port_vlan *vlan,
2794 + struct netlink_ext_ack *extack)
2795 +{
2796 + bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2797 + bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2798 + struct qca8k_priv *priv = ds->priv;
2799 + int ret;
2800 +
2801 + ret = qca8k_vlan_add(priv, port, vlan->vid, untagged);
2802 + if (ret) {
2803 + dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret);
2804 + return ret;
2805 + }
2806 +
2807 + if (pvid) {
2808 + ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
2809 + QCA8K_EGREES_VLAN_PORT_MASK(port),
2810 + QCA8K_EGREES_VLAN_PORT(port, vlan->vid));
2811 + if (ret)
2812 + return ret;
2813 +
2814 + ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
2815 + QCA8K_PORT_VLAN_CVID(vlan->vid) |
2816 + QCA8K_PORT_VLAN_SVID(vlan->vid));
2817 + }
2818 +
2819 + return ret;
2820 +}
2821 +
2822 +static int
2823 +qca8k_port_vlan_del(struct dsa_switch *ds, int port,
2824 + const struct switchdev_obj_port_vlan *vlan)
2825 +{
2826 + struct qca8k_priv *priv = ds->priv;
2827 + int ret;
2828 +
2829 + ret = qca8k_vlan_del(priv, port, vlan->vid);
2830 + if (ret)
2831 + dev_err(priv->dev, "Failed to delete VLAN from port %d (%d)", port, ret);
2832 +
2833 + return ret;
2834 +}
2835 +
2836 +static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port)
2837 +{
2838 + struct qca8k_priv *priv = ds->priv;
2839 +
2840 + /* Communicate to the phy internal driver the switch revision.
2841 + * Based on the switch revision different values needs to be
2842 + * set to the dbg and mmd reg on the phy.
2843 + * The first 2 bit are used to communicate the switch revision
2844 + * to the phy driver.
2845 + */
2846 + if (port > 0 && port < 6)
2847 + return priv->switch_revision;
2848 +
2849 + return 0;
2850 +}
2851 +
2852 +static enum dsa_tag_protocol
2853 +qca8k_get_tag_protocol(struct dsa_switch *ds, int port,
2854 + enum dsa_tag_protocol mp)
2855 +{
2856 + return DSA_TAG_PROTO_QCA;
2857 +}
2858 +
2859 +static bool
2860 +qca8k_lag_can_offload(struct dsa_switch *ds,
2861 + struct net_device *lag,
2862 + struct netdev_lag_upper_info *info)
2863 +{
2864 + struct dsa_port *dp;
2865 + int id, members = 0;
2866 +
2867 + id = dsa_lag_id(ds->dst, lag);
2868 + if (id < 0 || id >= ds->num_lag_ids)
2869 + return false;
2870 +
2871 + dsa_lag_foreach_port(dp, ds->dst, lag)
2872 + /* Includes the port joining the LAG */
2873 + members++;
2874 +
2875 + if (members > QCA8K_NUM_PORTS_FOR_LAG)
2876 + return false;
2877 +
2878 + if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
2879 + return false;
2880 +
2881 + if (info->hash_type != NETDEV_LAG_HASH_L2 &&
2882 + info->hash_type != NETDEV_LAG_HASH_L23)
2883 + return false;
2884 +
2885 + return true;
2886 +}
2887 +
2888 +static int
2889 +qca8k_lag_setup_hash(struct dsa_switch *ds,
2890 + struct net_device *lag,
2891 + struct netdev_lag_upper_info *info)
2892 +{
2893 + struct qca8k_priv *priv = ds->priv;
2894 + bool unique_lag = true;
2895 + u32 hash = 0;
2896 + int i, id;
2897 +
2898 + id = dsa_lag_id(ds->dst, lag);
2899 +
2900 + switch (info->hash_type) {
2901 + case NETDEV_LAG_HASH_L23:
2902 + hash |= QCA8K_TRUNK_HASH_SIP_EN;
2903 + hash |= QCA8K_TRUNK_HASH_DIP_EN;
2904 + fallthrough;
2905 + case NETDEV_LAG_HASH_L2:
2906 + hash |= QCA8K_TRUNK_HASH_SA_EN;
2907 + hash |= QCA8K_TRUNK_HASH_DA_EN;
2908 + break;
2909 + default: /* We should NEVER reach this */
2910 + return -EOPNOTSUPP;
2911 + }
2912 +
2913 + /* Check if we are the unique configured LAG */
2914 + dsa_lags_foreach_id(i, ds->dst)
2915 + if (i != id && dsa_lag_dev(ds->dst, i)) {
2916 + unique_lag = false;
2917 + break;
2918 + }
2919 +
2920 + /* Hash Mode is global. Make sure the same Hash Mode
2921 + * is set to all the 4 possible lag.
2922 + * If we are the unique LAG we can set whatever hash
2923 + * mode we want.
2924 + * To change hash mode it's needed to remove all LAG
2925 + * and change the mode with the latest.
2926 + */
2927 + if (unique_lag) {
2928 + priv->lag_hash_mode = hash;
2929 + } else if (priv->lag_hash_mode != hash) {
2930 + netdev_err(lag, "Error: Mismateched Hash Mode across different lag is not supported\n");
2931 + return -EOPNOTSUPP;
2932 + }
2933 +
2934 + return regmap_update_bits(priv->regmap, QCA8K_TRUNK_HASH_EN_CTRL,
2935 + QCA8K_TRUNK_HASH_MASK, hash);
2936 +}
2937 +
2938 +static int
2939 +qca8k_lag_refresh_portmap(struct dsa_switch *ds, int port,
2940 + struct net_device *lag, bool delete)
2941 +{
2942 + struct qca8k_priv *priv = ds->priv;
2943 + int ret, id, i;
2944 + u32 val;
2945 +
2946 + id = dsa_lag_id(ds->dst, lag);
2947 +
2948 + /* Read current port member */
2949 + ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0, &val);
2950 + if (ret)
2951 + return ret;
2952 +
2953 + /* Shift val to the correct trunk */
2954 + val >>= QCA8K_REG_GOL_TRUNK_SHIFT(id);
2955 + val &= QCA8K_REG_GOL_TRUNK_MEMBER_MASK;
2956 + if (delete)
2957 + val &= ~BIT(port);
2958 + else
2959 + val |= BIT(port);
2960 +
2961 + /* Update port member. With empty portmap disable trunk */
2962 + ret = regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0,
2963 + QCA8K_REG_GOL_TRUNK_MEMBER(id) |
2964 + QCA8K_REG_GOL_TRUNK_EN(id),
2965 + !val << QCA8K_REG_GOL_TRUNK_SHIFT(id) |
2966 + val << QCA8K_REG_GOL_TRUNK_SHIFT(id));
2967 +
2968 + /* Search empty member if adding or port on deleting */
2969 + for (i = 0; i < QCA8K_NUM_PORTS_FOR_LAG; i++) {
2970 + ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id), &val);
2971 + if (ret)
2972 + return ret;
2973 +
2974 + val >>= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i);
2975 + val &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK;
2976 +
2977 + if (delete) {
2978 + /* If port flagged to be disabled assume this member is
2979 + * empty
2980 + */
2981 + if (val != QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK)
2982 + continue;
2983 +
2984 + val &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK;
2985 + if (val != port)
2986 + continue;
2987 + } else {
2988 + /* If port flagged to be enabled assume this member is
2989 + * already set
2990 + */
2991 + if (val == QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK)
2992 + continue;
2993 + }
2994 +
2995 + /* We have found the member to add/remove */
2996 + break;
2997 + }
2998 +
2999 + /* Set port in the correct port mask or disable port if in delete mode */
3000 + return regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id),
3001 + QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(id, i) |
3002 + QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(id, i),
3003 + !delete << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i) |
3004 + port << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i));
3005 +}
3006 +
3007 +static int
3008 +qca8k_port_lag_join(struct dsa_switch *ds, int port,
3009 + struct net_device *lag,
3010 + struct netdev_lag_upper_info *info)
3011 +{
3012 + int ret;
3013 +
3014 + if (!qca8k_lag_can_offload(ds, lag, info))
3015 + return -EOPNOTSUPP;
3016 +
3017 + ret = qca8k_lag_setup_hash(ds, lag, info);
3018 + if (ret)
3019 + return ret;
3020 +
3021 + return qca8k_lag_refresh_portmap(ds, port, lag, false);
3022 +}
3023 +
3024 +static int
3025 +qca8k_port_lag_leave(struct dsa_switch *ds, int port,
3026 + struct net_device *lag)
3027 +{
3028 + return qca8k_lag_refresh_portmap(ds, port, lag, true);
3029 +}
3030 +
3031 +static void
3032 +qca8k_master_change(struct dsa_switch *ds, const struct net_device *master,
3033 + bool operational)
3034 +{
3035 + struct dsa_port *dp = master->dsa_ptr;
3036 + struct qca8k_priv *priv = ds->priv;
3037 +
3038 + /* Ethernet MIB/MDIO is only supported for CPU port 0 */
3039 + if (dp->index != 0)
3040 + return;
3041 +
3042 + mutex_lock(&priv->mgmt_eth_data.mutex);
3043 + mutex_lock(&priv->mib_eth_data.mutex);
3044 +
3045 + priv->mgmt_master = operational ? (struct net_device *)master : NULL;
3046 +
3047 + mutex_unlock(&priv->mib_eth_data.mutex);
3048 + mutex_unlock(&priv->mgmt_eth_data.mutex);
3049 +}
3050 +
3051 +static int qca8k_connect_tag_protocol(struct dsa_switch *ds,
3052 + enum dsa_tag_protocol proto)
3053 +{
3054 + struct qca_tagger_data *tagger_data;
3055 +
3056 + switch (proto) {
3057 + case DSA_TAG_PROTO_QCA:
3058 + tagger_data = ds->tagger_data;
3059 +
3060 + tagger_data->rw_reg_ack_handler = qca8k_rw_reg_ack_handler;
3061 + tagger_data->mib_autocast_handler = qca8k_mib_autocast_handler;
3062 +
3063 + break;
3064 + default:
3065 + return -EOPNOTSUPP;
3066 + }
3067 +
3068 + return 0;
3069 +}
3070 +
3071 +static const struct dsa_switch_ops qca8k_switch_ops = {
3072 + .get_tag_protocol = qca8k_get_tag_protocol,
3073 + .setup = qca8k_setup,
3074 + .get_strings = qca8k_get_strings,
3075 + .get_ethtool_stats = qca8k_get_ethtool_stats,
3076 + .get_sset_count = qca8k_get_sset_count,
3077 + .set_ageing_time = qca8k_set_ageing_time,
3078 + .get_mac_eee = qca8k_get_mac_eee,
3079 + .set_mac_eee = qca8k_set_mac_eee,
3080 + .port_enable = qca8k_port_enable,
3081 + .port_disable = qca8k_port_disable,
3082 + .port_change_mtu = qca8k_port_change_mtu,
3083 + .port_max_mtu = qca8k_port_max_mtu,
3084 + .port_stp_state_set = qca8k_port_stp_state_set,
3085 + .port_bridge_join = qca8k_port_bridge_join,
3086 + .port_bridge_leave = qca8k_port_bridge_leave,
3087 + .port_fast_age = qca8k_port_fast_age,
3088 + .port_fdb_add = qca8k_port_fdb_add,
3089 + .port_fdb_del = qca8k_port_fdb_del,
3090 + .port_fdb_dump = qca8k_port_fdb_dump,
3091 + .port_mdb_add = qca8k_port_mdb_add,
3092 + .port_mdb_del = qca8k_port_mdb_del,
3093 + .port_mirror_add = qca8k_port_mirror_add,
3094 + .port_mirror_del = qca8k_port_mirror_del,
3095 + .port_vlan_filtering = qca8k_port_vlan_filtering,
3096 + .port_vlan_add = qca8k_port_vlan_add,
3097 + .port_vlan_del = qca8k_port_vlan_del,
3098 + .phylink_validate = qca8k_phylink_validate,
3099 + .phylink_mac_link_state = qca8k_phylink_mac_link_state,
3100 + .phylink_mac_config = qca8k_phylink_mac_config,
3101 + .phylink_mac_link_down = qca8k_phylink_mac_link_down,
3102 + .phylink_mac_link_up = qca8k_phylink_mac_link_up,
3103 + .get_phy_flags = qca8k_get_phy_flags,
3104 + .port_lag_join = qca8k_port_lag_join,
3105 + .port_lag_leave = qca8k_port_lag_leave,
3106 + .master_state_change = qca8k_master_change,
3107 + .connect_tag_protocol = qca8k_connect_tag_protocol,
3108 +};
3109 +
3110 +static int qca8k_read_switch_id(struct qca8k_priv *priv)
3111 +{
3112 + const struct qca8k_match_data *data;
3113 + u32 val;
3114 + u8 id;
3115 + int ret;
3116 +
3117 + /* get the switches ID from the compatible */
3118 + data = of_device_get_match_data(priv->dev);
3119 + if (!data)
3120 + return -ENODEV;
3121 +
3122 + ret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, &val);
3123 + if (ret < 0)
3124 + return -ENODEV;
3125 +
3126 + id = QCA8K_MASK_CTRL_DEVICE_ID(val);
3127 + if (id != data->id) {
3128 + dev_err(priv->dev, "Switch id detected %x but expected %x", id, data->id);
3129 + return -ENODEV;
3130 + }
3131 +
3132 + priv->switch_id = id;
3133 +
3134 + /* Save revision to communicate to the internal PHY driver */
3135 + priv->switch_revision = QCA8K_MASK_CTRL_REV_ID(val);
3136 +
3137 + return 0;
3138 +}
3139 +
3140 +static int
3141 +qca8k_sw_probe(struct mdio_device *mdiodev)
3142 +{
3143 + struct qca8k_priv *priv;
3144 + int ret;
3145 +
3146 + /* allocate the private data struct so that we can probe the switches
3147 + * ID register
3148 + */
3149 + priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
3150 + if (!priv)
3151 + return -ENOMEM;
3152 +
3153 + priv->bus = mdiodev->bus;
3154 + priv->dev = &mdiodev->dev;
3155 +
3156 + priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset",
3157 + GPIOD_ASIS);
3158 + if (IS_ERR(priv->reset_gpio))
3159 + return PTR_ERR(priv->reset_gpio);
3160 +
3161 + if (priv->reset_gpio) {
3162 + gpiod_set_value_cansleep(priv->reset_gpio, 1);
3163 + /* The active low duration must be greater than 10 ms
3164 + * and checkpatch.pl wants 20 ms.
3165 + */
3166 + msleep(20);
3167 + gpiod_set_value_cansleep(priv->reset_gpio, 0);
3168 + }
3169 +
3170 + /* Start by setting up the register mapping */
3171 + priv->regmap = devm_regmap_init(&mdiodev->dev, NULL, priv,
3172 + &qca8k_regmap_config);
3173 + if (IS_ERR(priv->regmap)) {
3174 + dev_err(priv->dev, "regmap initialization failed");
3175 + return PTR_ERR(priv->regmap);
3176 + }
3177 +
3178 + priv->mdio_cache.page = 0xffff;
3179 + priv->mdio_cache.lo = 0xffff;
3180 + priv->mdio_cache.hi = 0xffff;
3181 +
3182 + /* Check the detected switch id */
3183 + ret = qca8k_read_switch_id(priv);
3184 + if (ret)
3185 + return ret;
3186 +
3187 + priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
3188 + if (!priv->ds)
3189 + return -ENOMEM;
3190 +
3191 + mutex_init(&priv->mgmt_eth_data.mutex);
3192 + init_completion(&priv->mgmt_eth_data.rw_done);
3193 +
3194 + mutex_init(&priv->mib_eth_data.mutex);
3195 + init_completion(&priv->mib_eth_data.rw_done);
3196 +
3197 + priv->ds->dev = &mdiodev->dev;
3198 + priv->ds->num_ports = QCA8K_NUM_PORTS;
3199 + priv->ds->priv = priv;
3200 + priv->ds->ops = &qca8k_switch_ops;
3201 + mutex_init(&priv->reg_mutex);
3202 + dev_set_drvdata(&mdiodev->dev, priv);
3203 +
3204 + return dsa_register_switch(priv->ds);
3205 +}
3206 +
3207 +static void
3208 +qca8k_sw_remove(struct mdio_device *mdiodev)
3209 +{
3210 + struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
3211 + int i;
3212 +
3213 + if (!priv)
3214 + return;
3215 +
3216 + for (i = 0; i < QCA8K_NUM_PORTS; i++)
3217 + qca8k_port_set_status(priv, i, 0);
3218 +
3219 + dsa_unregister_switch(priv->ds);
3220 +
3221 + dev_set_drvdata(&mdiodev->dev, NULL);
3222 +}
3223 +
3224 +static void qca8k_sw_shutdown(struct mdio_device *mdiodev)
3225 +{
3226 + struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
3227 +
3228 + if (!priv)
3229 + return;
3230 +
3231 + dsa_switch_shutdown(priv->ds);
3232 +
3233 + dev_set_drvdata(&mdiodev->dev, NULL);
3234 +}
3235 +
3236 +#ifdef CONFIG_PM_SLEEP
3237 +static void
3238 +qca8k_set_pm(struct qca8k_priv *priv, int enable)
3239 +{
3240 + int port;
3241 +
3242 + for (port = 0; port < QCA8K_NUM_PORTS; port++) {
3243 + /* Do not enable on resume if the port was
3244 + * disabled before.
3245 + */
3246 + if (!(priv->port_enabled_map & BIT(port)))
3247 + continue;
3248 +
3249 + qca8k_port_set_status(priv, port, enable);
3250 + }
3251 +}
3252 +
3253 +static int qca8k_suspend(struct device *dev)
3254 +{
3255 + struct qca8k_priv *priv = dev_get_drvdata(dev);
3256 +
3257 + qca8k_set_pm(priv, 0);
3258 +
3259 + return dsa_switch_suspend(priv->ds);
3260 +}
3261 +
3262 +static int qca8k_resume(struct device *dev)
3263 +{
3264 + struct qca8k_priv *priv = dev_get_drvdata(dev);
3265 +
3266 + qca8k_set_pm(priv, 1);
3267 +
3268 + return dsa_switch_resume(priv->ds);
3269 +}
3270 +#endif /* CONFIG_PM_SLEEP */
3271 +
3272 +static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
3273 + qca8k_suspend, qca8k_resume);
3274 +
3275 +static const struct qca8k_match_data qca8327 = {
3276 + .id = QCA8K_ID_QCA8327,
3277 + .reduced_package = true,
3278 + .mib_count = QCA8K_QCA832X_MIB_COUNT,
3279 +};
3280 +
3281 +static const struct qca8k_match_data qca8328 = {
3282 + .id = QCA8K_ID_QCA8327,
3283 + .mib_count = QCA8K_QCA832X_MIB_COUNT,
3284 +};
3285 +
3286 +static const struct qca8k_match_data qca833x = {
3287 + .id = QCA8K_ID_QCA8337,
3288 + .mib_count = QCA8K_QCA833X_MIB_COUNT,
3289 +};
3290 +
3291 +static const struct of_device_id qca8k_of_match[] = {
3292 + { .compatible = "qca,qca8327", .data = &qca8327 },
3293 + { .compatible = "qca,qca8328", .data = &qca8328 },
3294 + { .compatible = "qca,qca8334", .data = &qca833x },
3295 + { .compatible = "qca,qca8337", .data = &qca833x },
3296 + { /* sentinel */ },
3297 +};
3298 +
3299 +static struct mdio_driver qca8kmdio_driver = {
3300 + .probe = qca8k_sw_probe,
3301 + .remove = qca8k_sw_remove,
3302 + .shutdown = qca8k_sw_shutdown,
3303 + .mdiodrv.driver = {
3304 + .name = "qca8k",
3305 + .of_match_table = qca8k_of_match,
3306 + .pm = &qca8k_pm_ops,
3307 + },
3308 +};
3309 +
3310 +mdio_module_driver(qca8kmdio_driver);
3311 +
3312 +MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
3313 +MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
3314 +MODULE_LICENSE("GPL v2");
3315 +MODULE_ALIAS("platform:qca8k");
3316 --- /dev/null
3317 +++ b/drivers/net/dsa/qca/qca8k.h
3318 @@ -0,0 +1,411 @@
3319 +/* SPDX-License-Identifier: GPL-2.0-only */
3320 +/*
3321 + * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
3322 + * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
3323 + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3324 + */
3325 +
3326 +#ifndef __QCA8K_H
3327 +#define __QCA8K_H
3328 +
3329 +#include <linux/delay.h>
3330 +#include <linux/regmap.h>
3331 +#include <linux/gpio.h>
3332 +#include <linux/dsa/tag_qca.h>
3333 +
3334 +#define QCA8K_ETHERNET_MDIO_PRIORITY 7
3335 +#define QCA8K_ETHERNET_PHY_PRIORITY 6
3336 +#define QCA8K_ETHERNET_TIMEOUT 100
3337 +
3338 +#define QCA8K_NUM_PORTS 7
3339 +#define QCA8K_NUM_CPU_PORTS 2
3340 +#define QCA8K_MAX_MTU 9000
3341 +#define QCA8K_NUM_LAGS 4
3342 +#define QCA8K_NUM_PORTS_FOR_LAG 4
3343 +
3344 +#define PHY_ID_QCA8327 0x004dd034
3345 +#define QCA8K_ID_QCA8327 0x12
3346 +#define PHY_ID_QCA8337 0x004dd036
3347 +#define QCA8K_ID_QCA8337 0x13
3348 +
3349 +#define QCA8K_QCA832X_MIB_COUNT 39
3350 +#define QCA8K_QCA833X_MIB_COUNT 41
3351 +
3352 +#define QCA8K_BUSY_WAIT_TIMEOUT 2000
3353 +
3354 +#define QCA8K_NUM_FDB_RECORDS 2048
3355 +
3356 +#define QCA8K_PORT_VID_DEF 1
3357 +
3358 +/* Global control registers */
3359 +#define QCA8K_REG_MASK_CTRL 0x000
3360 +#define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0)
3361 +#define QCA8K_MASK_CTRL_REV_ID(x) FIELD_GET(QCA8K_MASK_CTRL_REV_ID_MASK, x)
3362 +#define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8)
3363 +#define QCA8K_MASK_CTRL_DEVICE_ID(x) FIELD_GET(QCA8K_MASK_CTRL_DEVICE_ID_MASK, x)
3364 +#define QCA8K_REG_PORT0_PAD_CTRL 0x004
3365 +#define QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN BIT(31)
3366 +#define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE BIT(19)
3367 +#define QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE BIT(18)
3368 +#define QCA8K_REG_PORT5_PAD_CTRL 0x008
3369 +#define QCA8K_REG_PORT6_PAD_CTRL 0x00c
3370 +#define QCA8K_PORT_PAD_RGMII_EN BIT(26)
3371 +#define QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK GENMASK(23, 22)
3372 +#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) FIELD_PREP(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, x)
3373 +#define QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK GENMASK(21, 20)
3374 +#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) FIELD_PREP(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, x)
3375 +#define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25)
3376 +#define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
3377 +#define QCA8K_PORT_PAD_SGMII_EN BIT(7)
3378 +#define QCA8K_REG_PWS 0x010
3379 +#define QCA8K_PWS_POWER_ON_SEL BIT(31)
3380 +/* This reg is only valid for QCA832x and toggle the package
3381 + * type from 176 pin (by default) to 148 pin used on QCA8327
3382 + */
3383 +#define QCA8327_PWS_PACKAGE148_EN BIT(30)
3384 +#define QCA8K_PWS_LED_OPEN_EN_CSR BIT(24)
3385 +#define QCA8K_PWS_SERDES_AEN_DIS BIT(7)
3386 +#define QCA8K_REG_MODULE_EN 0x030
3387 +#define QCA8K_MODULE_EN_MIB BIT(0)
3388 +#define QCA8K_REG_MIB 0x034
3389 +#define QCA8K_MIB_FUNC GENMASK(26, 24)
3390 +#define QCA8K_MIB_CPU_KEEP BIT(20)
3391 +#define QCA8K_MIB_BUSY BIT(17)
3392 +#define QCA8K_MDIO_MASTER_CTRL 0x3c
3393 +#define QCA8K_MDIO_MASTER_BUSY BIT(31)
3394 +#define QCA8K_MDIO_MASTER_EN BIT(30)
3395 +#define QCA8K_MDIO_MASTER_READ BIT(27)
3396 +#define QCA8K_MDIO_MASTER_WRITE 0
3397 +#define QCA8K_MDIO_MASTER_SUP_PRE BIT(26)
3398 +#define QCA8K_MDIO_MASTER_PHY_ADDR_MASK GENMASK(25, 21)
3399 +#define QCA8K_MDIO_MASTER_PHY_ADDR(x) FIELD_PREP(QCA8K_MDIO_MASTER_PHY_ADDR_MASK, x)
3400 +#define QCA8K_MDIO_MASTER_REG_ADDR_MASK GENMASK(20, 16)
3401 +#define QCA8K_MDIO_MASTER_REG_ADDR(x) FIELD_PREP(QCA8K_MDIO_MASTER_REG_ADDR_MASK, x)
3402 +#define QCA8K_MDIO_MASTER_DATA_MASK GENMASK(15, 0)
3403 +#define QCA8K_MDIO_MASTER_DATA(x) FIELD_PREP(QCA8K_MDIO_MASTER_DATA_MASK, x)
3404 +#define QCA8K_MDIO_MASTER_MAX_PORTS 5
3405 +#define QCA8K_MDIO_MASTER_MAX_REG 32
3406 +#define QCA8K_GOL_MAC_ADDR0 0x60
3407 +#define QCA8K_GOL_MAC_ADDR1 0x64
3408 +#define QCA8K_MAX_FRAME_SIZE 0x78
3409 +#define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
3410 +#define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0)
3411 +#define QCA8K_PORT_STATUS_SPEED_10 0
3412 +#define QCA8K_PORT_STATUS_SPEED_100 0x1
3413 +#define QCA8K_PORT_STATUS_SPEED_1000 0x2
3414 +#define QCA8K_PORT_STATUS_TXMAC BIT(2)
3415 +#define QCA8K_PORT_STATUS_RXMAC BIT(3)
3416 +#define QCA8K_PORT_STATUS_TXFLOW BIT(4)
3417 +#define QCA8K_PORT_STATUS_RXFLOW BIT(5)
3418 +#define QCA8K_PORT_STATUS_DUPLEX BIT(6)
3419 +#define QCA8K_PORT_STATUS_LINK_UP BIT(8)
3420 +#define QCA8K_PORT_STATUS_LINK_AUTO BIT(9)
3421 +#define QCA8K_PORT_STATUS_LINK_PAUSE BIT(10)
3422 +#define QCA8K_PORT_STATUS_FLOW_AUTO BIT(12)
3423 +#define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4))
3424 +#define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2)
3425 +#define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)
3426 +#define QCA8K_PORT_HDR_CTRL_ALL 2
3427 +#define QCA8K_PORT_HDR_CTRL_MGMT 1
3428 +#define QCA8K_PORT_HDR_CTRL_NONE 0
3429 +#define QCA8K_REG_SGMII_CTRL 0x0e0
3430 +#define QCA8K_SGMII_EN_PLL BIT(1)
3431 +#define QCA8K_SGMII_EN_RX BIT(2)
3432 +#define QCA8K_SGMII_EN_TX BIT(3)
3433 +#define QCA8K_SGMII_EN_SD BIT(4)
3434 +#define QCA8K_SGMII_CLK125M_DELAY BIT(7)
3435 +#define QCA8K_SGMII_MODE_CTRL_MASK GENMASK(23, 22)
3436 +#define QCA8K_SGMII_MODE_CTRL(x) FIELD_PREP(QCA8K_SGMII_MODE_CTRL_MASK, x)
3437 +#define QCA8K_SGMII_MODE_CTRL_BASEX QCA8K_SGMII_MODE_CTRL(0x0)
3438 +#define QCA8K_SGMII_MODE_CTRL_PHY QCA8K_SGMII_MODE_CTRL(0x1)
3439 +#define QCA8K_SGMII_MODE_CTRL_MAC QCA8K_SGMII_MODE_CTRL(0x2)
3440 +
3441 +/* MAC_PWR_SEL registers */
3442 +#define QCA8K_REG_MAC_PWR_SEL 0x0e4
3443 +#define QCA8K_MAC_PWR_RGMII1_1_8V BIT(18)
3444 +#define QCA8K_MAC_PWR_RGMII0_1_8V BIT(19)
3445 +
3446 +/* EEE control registers */
3447 +#define QCA8K_REG_EEE_CTRL 0x100
3448 +#define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2)
3449 +
3450 +/* TRUNK_HASH_EN registers */
3451 +#define QCA8K_TRUNK_HASH_EN_CTRL 0x270
3452 +#define QCA8K_TRUNK_HASH_SIP_EN BIT(3)
3453 +#define QCA8K_TRUNK_HASH_DIP_EN BIT(2)
3454 +#define QCA8K_TRUNK_HASH_SA_EN BIT(1)
3455 +#define QCA8K_TRUNK_HASH_DA_EN BIT(0)
3456 +#define QCA8K_TRUNK_HASH_MASK GENMASK(3, 0)
3457 +
3458 +/* ACL registers */
3459 +#define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8))
3460 +#define QCA8K_PORT_VLAN_CVID_MASK GENMASK(27, 16)
3461 +#define QCA8K_PORT_VLAN_CVID(x) FIELD_PREP(QCA8K_PORT_VLAN_CVID_MASK, x)
3462 +#define QCA8K_PORT_VLAN_SVID_MASK GENMASK(11, 0)
3463 +#define QCA8K_PORT_VLAN_SVID(x) FIELD_PREP(QCA8K_PORT_VLAN_SVID_MASK, x)
3464 +#define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8))
3465 +#define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470
3466 +#define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474
3467 +
3468 +/* Lookup registers */
3469 +#define QCA8K_REG_ATU_DATA0 0x600
3470 +#define QCA8K_ATU_ADDR2_MASK GENMASK(31, 24)
3471 +#define QCA8K_ATU_ADDR3_MASK GENMASK(23, 16)
3472 +#define QCA8K_ATU_ADDR4_MASK GENMASK(15, 8)
3473 +#define QCA8K_ATU_ADDR5_MASK GENMASK(7, 0)
3474 +#define QCA8K_REG_ATU_DATA1 0x604
3475 +#define QCA8K_ATU_PORT_MASK GENMASK(22, 16)
3476 +#define QCA8K_ATU_ADDR0_MASK GENMASK(15, 8)
3477 +#define QCA8K_ATU_ADDR1_MASK GENMASK(7, 0)
3478 +#define QCA8K_REG_ATU_DATA2 0x608
3479 +#define QCA8K_ATU_VID_MASK GENMASK(19, 8)
3480 +#define QCA8K_ATU_STATUS_MASK GENMASK(3, 0)
3481 +#define QCA8K_ATU_STATUS_STATIC 0xf
3482 +#define QCA8K_REG_ATU_FUNC 0x60c
3483 +#define QCA8K_ATU_FUNC_BUSY BIT(31)
3484 +#define QCA8K_ATU_FUNC_PORT_EN BIT(14)
3485 +#define QCA8K_ATU_FUNC_MULTI_EN BIT(13)
3486 +#define QCA8K_ATU_FUNC_FULL BIT(12)
3487 +#define QCA8K_ATU_FUNC_PORT_MASK GENMASK(11, 8)
3488 +#define QCA8K_REG_VTU_FUNC0 0x610
3489 +#define QCA8K_VTU_FUNC0_VALID BIT(20)
3490 +#define QCA8K_VTU_FUNC0_IVL_EN BIT(19)
3491 +/* QCA8K_VTU_FUNC0_EG_MODE_MASK GENMASK(17, 4)
3492 + * It does contain VLAN_MODE for each port [5:4] for port0,
3493 + * [7:6] for port1 ... [17:16] for port6. Use virtual port
3494 + * define to handle this.
3495 + */
3496 +#define QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i) (4 + (_i) * 2)
3497 +#define QCA8K_VTU_FUNC0_EG_MODE_MASK GENMASK(1, 0)
3498 +#define QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(_i) (GENMASK(1, 0) << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
3499 +#define QCA8K_VTU_FUNC0_EG_MODE_UNMOD FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x0)
3500 +#define QCA8K_VTU_FUNC0_EG_MODE_PORT_UNMOD(_i) (QCA8K_VTU_FUNC0_EG_MODE_UNMOD << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
3501 +#define QCA8K_VTU_FUNC0_EG_MODE_UNTAG FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x1)
3502 +#define QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(_i) (QCA8K_VTU_FUNC0_EG_MODE_UNTAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
3503 +#define QCA8K_VTU_FUNC0_EG_MODE_TAG FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x2)
3504 +#define QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(_i) (QCA8K_VTU_FUNC0_EG_MODE_TAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
3505 +#define QCA8K_VTU_FUNC0_EG_MODE_NOT FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x3)
3506 +#define QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(_i) (QCA8K_VTU_FUNC0_EG_MODE_NOT << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
3507 +#define QCA8K_REG_VTU_FUNC1 0x614
3508 +#define QCA8K_VTU_FUNC1_BUSY BIT(31)
3509 +#define QCA8K_VTU_FUNC1_VID_MASK GENMASK(27, 16)
3510 +#define QCA8K_VTU_FUNC1_FULL BIT(4)
3511 +#define QCA8K_REG_ATU_CTRL 0x618
3512 +#define QCA8K_ATU_AGE_TIME_MASK GENMASK(15, 0)
3513 +#define QCA8K_ATU_AGE_TIME(x) FIELD_PREP(QCA8K_ATU_AGE_TIME_MASK, (x))
3514 +#define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
3515 +#define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
3516 +#define QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM GENMASK(7, 4)
3517 +#define QCA8K_REG_GLOBAL_FW_CTRL1 0x624
3518 +#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK GENMASK(30, 24)
3519 +#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK GENMASK(22, 16)
3520 +#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK GENMASK(14, 8)
3521 +#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK GENMASK(6, 0)
3522 +#define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc)
3523 +#define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0)
3524 +#define QCA8K_PORT_LOOKUP_VLAN_MODE_MASK GENMASK(9, 8)
3525 +#define QCA8K_PORT_LOOKUP_VLAN_MODE(x) FIELD_PREP(QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, x)
3526 +#define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE QCA8K_PORT_LOOKUP_VLAN_MODE(0x0)
3527 +#define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK QCA8K_PORT_LOOKUP_VLAN_MODE(0x1)
3528 +#define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK QCA8K_PORT_LOOKUP_VLAN_MODE(0x2)
3529 +#define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE QCA8K_PORT_LOOKUP_VLAN_MODE(0x3)
3530 +#define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16)
3531 +#define QCA8K_PORT_LOOKUP_STATE(x) FIELD_PREP(QCA8K_PORT_LOOKUP_STATE_MASK, x)
3532 +#define QCA8K_PORT_LOOKUP_STATE_DISABLED QCA8K_PORT_LOOKUP_STATE(0x0)
3533 +#define QCA8K_PORT_LOOKUP_STATE_BLOCKING QCA8K_PORT_LOOKUP_STATE(0x1)
3534 +#define QCA8K_PORT_LOOKUP_STATE_LISTENING QCA8K_PORT_LOOKUP_STATE(0x2)
3535 +#define QCA8K_PORT_LOOKUP_STATE_LEARNING QCA8K_PORT_LOOKUP_STATE(0x3)
3536 +#define QCA8K_PORT_LOOKUP_STATE_FORWARD QCA8K_PORT_LOOKUP_STATE(0x4)
3537 +#define QCA8K_PORT_LOOKUP_LEARN BIT(20)
3538 +#define QCA8K_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
3539 +
3540 +#define QCA8K_REG_GOL_TRUNK_CTRL0 0x700
3541 +/* 4 max trunk first
3542 + * first 6 bit for member bitmap
3543 + * 7th bit is to enable trunk port
3544 + */
3545 +#define QCA8K_REG_GOL_TRUNK_SHIFT(_i) ((_i) * 8)
3546 +#define QCA8K_REG_GOL_TRUNK_EN_MASK BIT(7)
3547 +#define QCA8K_REG_GOL_TRUNK_EN(_i) (QCA8K_REG_GOL_TRUNK_EN_MASK << QCA8K_REG_GOL_TRUNK_SHIFT(_i))
3548 +#define QCA8K_REG_GOL_TRUNK_MEMBER_MASK GENMASK(6, 0)
3549 +#define QCA8K_REG_GOL_TRUNK_MEMBER(_i) (QCA8K_REG_GOL_TRUNK_MEMBER_MASK << QCA8K_REG_GOL_TRUNK_SHIFT(_i))
3550 +/* 0x704 for TRUNK 0-1 --- 0x708 for TRUNK 2-3 */
3551 +#define QCA8K_REG_GOL_TRUNK_CTRL(_i) (0x704 + (((_i) / 2) * 4))
3552 +#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK GENMASK(3, 0)
3553 +#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK BIT(3)
3554 +#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK GENMASK(2, 0)
3555 +#define QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i) (((_i) / 2) * 16)
3556 +#define QCA8K_REG_GOL_MEM_ID_SHIFT(_i) ((_i) * 4)
3557 +/* Complex shift: FIRST shift for port THEN shift for trunk */
3558 +#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j) (QCA8K_REG_GOL_MEM_ID_SHIFT(_j) + QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i))
3559 +#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(_i, _j) (QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j))
3560 +#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(_i, _j) (QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j))
3561 +
3562 +#define QCA8K_REG_GLOBAL_FC_THRESH 0x800
3563 +#define QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK GENMASK(24, 16)
3564 +#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK, x)
3565 +#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK GENMASK(8, 0)
3566 +#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK, x)
3567 +
3568 +#define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8)
3569 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK GENMASK(3, 0)
3570 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK, x)
3571 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK GENMASK(7, 4)
3572 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK, x)
3573 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK GENMASK(11, 8)
3574 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK, x)
3575 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK GENMASK(15, 12)
3576 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK, x)
3577 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK GENMASK(19, 16)
3578 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK, x)
3579 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK GENMASK(23, 20)
3580 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK, x)
3581 +#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK GENMASK(29, 24)
3582 +#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK, x)
3583 +
3584 +#define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
3585 +#define QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK GENMASK(3, 0)
3586 +#define QCA8K_PORT_HOL_CTRL1_ING(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK, x)
3587 +#define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6)
3588 +#define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7)
3589 +#define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8)
3590 +#define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
3591 +
3592 +/* Pkt edit registers */
3593 +#define QCA8K_EGREES_VLAN_PORT_SHIFT(_i) (16 * ((_i) % 2))
3594 +#define QCA8K_EGREES_VLAN_PORT_MASK(_i) (GENMASK(11, 0) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
3595 +#define QCA8K_EGREES_VLAN_PORT(_i, x) ((x) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
3596 +#define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2)))
3597 +
3598 +/* L3 registers */
3599 +#define QCA8K_HROUTER_CONTROL 0xe00
3600 +#define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M GENMASK(17, 16)
3601 +#define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S 16
3602 +#define QCA8K_HROUTER_CONTROL_ARP_AGE_MODE 1
3603 +#define QCA8K_HROUTER_PBASED_CONTROL1 0xe08
3604 +#define QCA8K_HROUTER_PBASED_CONTROL2 0xe0c
3605 +#define QCA8K_HNAT_CONTROL 0xe38
3606 +
3607 +/* MIB registers */
3608 +#define QCA8K_PORT_MIB_COUNTER(_i) (0x1000 + (_i) * 0x100)
3609 +
3610 +/* QCA specific MII registers */
3611 +#define MII_ATH_MMD_ADDR 0x0d
3612 +#define MII_ATH_MMD_DATA 0x0e
3613 +
3614 +enum {
3615 + QCA8K_PORT_SPEED_10M = 0,
3616 + QCA8K_PORT_SPEED_100M = 1,
3617 + QCA8K_PORT_SPEED_1000M = 2,
3618 + QCA8K_PORT_SPEED_ERR = 3,
3619 +};
3620 +
3621 +enum qca8k_fdb_cmd {
3622 + QCA8K_FDB_FLUSH = 1,
3623 + QCA8K_FDB_LOAD = 2,
3624 + QCA8K_FDB_PURGE = 3,
3625 + QCA8K_FDB_FLUSH_PORT = 5,
3626 + QCA8K_FDB_NEXT = 6,
3627 + QCA8K_FDB_SEARCH = 7,
3628 +};
3629 +
3630 +enum qca8k_vlan_cmd {
3631 + QCA8K_VLAN_FLUSH = 1,
3632 + QCA8K_VLAN_LOAD = 2,
3633 + QCA8K_VLAN_PURGE = 3,
3634 + QCA8K_VLAN_REMOVE_PORT = 4,
3635 + QCA8K_VLAN_NEXT = 5,
3636 + QCA8K_VLAN_READ = 6,
3637 +};
3638 +
3639 +enum qca8k_mid_cmd {
3640 + QCA8K_MIB_FLUSH = 1,
3641 + QCA8K_MIB_FLUSH_PORT = 2,
3642 + QCA8K_MIB_CAST = 3,
3643 +};
3644 +
3645 +struct qca8k_match_data {
3646 + u8 id;
3647 + bool reduced_package;
3648 + u8 mib_count;
3649 +};
3650 +
3651 +enum {
3652 + QCA8K_CPU_PORT0,
3653 + QCA8K_CPU_PORT6,
3654 +};
3655 +
3656 +struct qca8k_mgmt_eth_data {
3657 + struct completion rw_done;
3658 + struct mutex mutex; /* Enforce one mdio read/write at time */
3659 + bool ack;
3660 + u32 seq;
3661 + u32 data[4];
3662 +};
3663 +
3664 +struct qca8k_mib_eth_data {
3665 + struct completion rw_done;
3666 + struct mutex mutex; /* Process one command at time */
3667 + refcount_t port_parsed; /* Counter to track parsed port */
3668 + u8 req_port;
3669 + u64 *data; /* pointer to ethtool data */
3670 +};
3671 +
3672 +struct qca8k_ports_config {
3673 + bool sgmii_rx_clk_falling_edge;
3674 + bool sgmii_tx_clk_falling_edge;
3675 + bool sgmii_enable_pll;
3676 + u8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
3677 + u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
3678 +};
3679 +
3680 +struct qca8k_mdio_cache {
3681 +/* The 32bit switch registers are accessed indirectly. To achieve this we need
3682 + * to set the page of the register. Track the last page that was set to reduce
3683 + * mdio writes
3684 + */
3685 + u16 page;
3686 +/* lo and hi can also be cached and from Documentation we can skip one
3687 + * extra mdio write if lo or hi is didn't change.
3688 + */
3689 + u16 lo;
3690 + u16 hi;
3691 +};
3692 +
3693 +struct qca8k_priv {
3694 + u8 switch_id;
3695 + u8 switch_revision;
3696 + u8 mirror_rx;
3697 + u8 mirror_tx;
3698 + u8 lag_hash_mode;
3699 + /* Each bit correspond to a port. This switch can support a max of 7 port.
3700 + * Bit 1: port enabled. Bit 0: port disabled.
3701 + */
3702 + u8 port_enabled_map;
3703 + struct qca8k_ports_config ports_config;
3704 + struct regmap *regmap;
3705 + struct mii_bus *bus;
3706 + struct dsa_switch *ds;
3707 + struct mutex reg_mutex;
3708 + struct device *dev;
3709 + struct gpio_desc *reset_gpio;
3710 + struct net_device *mgmt_master; /* Track if mdio/mib Ethernet is available */
3711 + struct qca8k_mgmt_eth_data mgmt_eth_data;
3712 + struct qca8k_mib_eth_data mib_eth_data;
3713 + struct qca8k_mdio_cache mdio_cache;
3714 +};
3715 +
3716 +struct qca8k_mib_desc {
3717 + unsigned int size;
3718 + unsigned int offset;
3719 + const char *name;
3720 +};
3721 +
3722 +struct qca8k_fdb {
3723 + u16 vid;
3724 + u8 port_mask;
3725 + u8 aging;
3726 + u8 mac[6];
3727 +};
3728 +
3729 +#endif /* __QCA8K_H */
3730 --- a/drivers/net/dsa/qca8k.c
3731 +++ /dev/null
3732 @@ -1,3243 +0,0 @@
3733 -// SPDX-License-Identifier: GPL-2.0
3734 -/*
3735 - * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
3736 - * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
3737 - * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
3738 - * Copyright (c) 2016 John Crispin <john@phrozen.org>
3739 - */
3740 -
3741 -#include <linux/module.h>
3742 -#include <linux/phy.h>
3743 -#include <linux/netdevice.h>
3744 -#include <linux/bitfield.h>
3745 -#include <linux/regmap.h>
3746 -#include <net/dsa.h>
3747 -#include <linux/of_net.h>
3748 -#include <linux/of_mdio.h>
3749 -#include <linux/of_platform.h>
3750 -#include <linux/if_bridge.h>
3751 -#include <linux/mdio.h>
3752 -#include <linux/phylink.h>
3753 -#include <linux/gpio/consumer.h>
3754 -#include <linux/etherdevice.h>
3755 -#include <linux/dsa/tag_qca.h>
3756 -
3757 -#include "qca8k.h"
3758 -
3759 -#define MIB_DESC(_s, _o, _n) \
3760 - { \
3761 - .size = (_s), \
3762 - .offset = (_o), \
3763 - .name = (_n), \
3764 - }
3765 -
3766 -static const struct qca8k_mib_desc ar8327_mib[] = {
3767 - MIB_DESC(1, 0x00, "RxBroad"),
3768 - MIB_DESC(1, 0x04, "RxPause"),
3769 - MIB_DESC(1, 0x08, "RxMulti"),
3770 - MIB_DESC(1, 0x0c, "RxFcsErr"),
3771 - MIB_DESC(1, 0x10, "RxAlignErr"),
3772 - MIB_DESC(1, 0x14, "RxRunt"),
3773 - MIB_DESC(1, 0x18, "RxFragment"),
3774 - MIB_DESC(1, 0x1c, "Rx64Byte"),
3775 - MIB_DESC(1, 0x20, "Rx128Byte"),
3776 - MIB_DESC(1, 0x24, "Rx256Byte"),
3777 - MIB_DESC(1, 0x28, "Rx512Byte"),
3778 - MIB_DESC(1, 0x2c, "Rx1024Byte"),
3779 - MIB_DESC(1, 0x30, "Rx1518Byte"),
3780 - MIB_DESC(1, 0x34, "RxMaxByte"),
3781 - MIB_DESC(1, 0x38, "RxTooLong"),
3782 - MIB_DESC(2, 0x3c, "RxGoodByte"),
3783 - MIB_DESC(2, 0x44, "RxBadByte"),
3784 - MIB_DESC(1, 0x4c, "RxOverFlow"),
3785 - MIB_DESC(1, 0x50, "Filtered"),
3786 - MIB_DESC(1, 0x54, "TxBroad"),
3787 - MIB_DESC(1, 0x58, "TxPause"),
3788 - MIB_DESC(1, 0x5c, "TxMulti"),
3789 - MIB_DESC(1, 0x60, "TxUnderRun"),
3790 - MIB_DESC(1, 0x64, "Tx64Byte"),
3791 - MIB_DESC(1, 0x68, "Tx128Byte"),
3792 - MIB_DESC(1, 0x6c, "Tx256Byte"),
3793 - MIB_DESC(1, 0x70, "Tx512Byte"),
3794 - MIB_DESC(1, 0x74, "Tx1024Byte"),
3795 - MIB_DESC(1, 0x78, "Tx1518Byte"),
3796 - MIB_DESC(1, 0x7c, "TxMaxByte"),
3797 - MIB_DESC(1, 0x80, "TxOverSize"),
3798 - MIB_DESC(2, 0x84, "TxByte"),
3799 - MIB_DESC(1, 0x8c, "TxCollision"),
3800 - MIB_DESC(1, 0x90, "TxAbortCol"),
3801 - MIB_DESC(1, 0x94, "TxMultiCol"),
3802 - MIB_DESC(1, 0x98, "TxSingleCol"),
3803 - MIB_DESC(1, 0x9c, "TxExcDefer"),
3804 - MIB_DESC(1, 0xa0, "TxDefer"),
3805 - MIB_DESC(1, 0xa4, "TxLateCol"),
3806 - MIB_DESC(1, 0xa8, "RXUnicast"),
3807 - MIB_DESC(1, 0xac, "TXUnicast"),
3808 -};
3809 -
3810 -static void
3811 -qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
3812 -{
3813 - regaddr >>= 1;
3814 - *r1 = regaddr & 0x1e;
3815 -
3816 - regaddr >>= 5;
3817 - *r2 = regaddr & 0x7;
3818 -
3819 - regaddr >>= 3;
3820 - *page = regaddr & 0x3ff;
3821 -}
3822 -
3823 -static int
3824 -qca8k_set_lo(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 lo)
3825 -{
3826 - u16 *cached_lo = &priv->mdio_cache.lo;
3827 - struct mii_bus *bus = priv->bus;
3828 - int ret;
3829 -
3830 - if (lo == *cached_lo)
3831 - return 0;
3832 -
3833 - ret = bus->write(bus, phy_id, regnum, lo);
3834 - if (ret < 0)
3835 - dev_err_ratelimited(&bus->dev,
3836 - "failed to write qca8k 32bit lo register\n");
3837 -
3838 - *cached_lo = lo;
3839 - return 0;
3840 -}
3841 -
3842 -static int
3843 -qca8k_set_hi(struct qca8k_priv *priv, int phy_id, u32 regnum, u16 hi)
3844 -{
3845 - u16 *cached_hi = &priv->mdio_cache.hi;
3846 - struct mii_bus *bus = priv->bus;
3847 - int ret;
3848 -
3849 - if (hi == *cached_hi)
3850 - return 0;
3851 -
3852 - ret = bus->write(bus, phy_id, regnum, hi);
3853 - if (ret < 0)
3854 - dev_err_ratelimited(&bus->dev,
3855 - "failed to write qca8k 32bit hi register\n");
3856 -
3857 - *cached_hi = hi;
3858 - return 0;
3859 -}
3860 -
3861 -static int
3862 -qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val)
3863 -{
3864 - int ret;
3865 -
3866 - ret = bus->read(bus, phy_id, regnum);
3867 - if (ret >= 0) {
3868 - *val = ret;
3869 - ret = bus->read(bus, phy_id, regnum + 1);
3870 - *val |= ret << 16;
3871 - }
3872 -
3873 - if (ret < 0) {
3874 - dev_err_ratelimited(&bus->dev,
3875 - "failed to read qca8k 32bit register\n");
3876 - *val = 0;
3877 - return ret;
3878 - }
3879 -
3880 - return 0;
3881 -}
3882 -
3883 -static void
3884 -qca8k_mii_write32(struct qca8k_priv *priv, int phy_id, u32 regnum, u32 val)
3885 -{
3886 - u16 lo, hi;
3887 - int ret;
3888 -
3889 - lo = val & 0xffff;
3890 - hi = (u16)(val >> 16);
3891 -
3892 - ret = qca8k_set_lo(priv, phy_id, regnum, lo);
3893 - if (ret >= 0)
3894 - ret = qca8k_set_hi(priv, phy_id, regnum + 1, hi);
3895 -}
3896 -
3897 -static int
3898 -qca8k_set_page(struct qca8k_priv *priv, u16 page)
3899 -{
3900 - u16 *cached_page = &priv->mdio_cache.page;
3901 - struct mii_bus *bus = priv->bus;
3902 - int ret;
3903 -
3904 - if (page == *cached_page)
3905 - return 0;
3906 -
3907 - ret = bus->write(bus, 0x18, 0, page);
3908 - if (ret < 0) {
3909 - dev_err_ratelimited(&bus->dev,
3910 - "failed to set qca8k page\n");
3911 - return ret;
3912 - }
3913 -
3914 - *cached_page = page;
3915 - usleep_range(1000, 2000);
3916 - return 0;
3917 -}
3918 -
3919 -static int
3920 -qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
3921 -{
3922 - return regmap_read(priv->regmap, reg, val);
3923 -}
3924 -
3925 -static int
3926 -qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
3927 -{
3928 - return regmap_write(priv->regmap, reg, val);
3929 -}
3930 -
3931 -static int
3932 -qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
3933 -{
3934 - return regmap_update_bits(priv->regmap, reg, mask, write_val);
3935 -}
3936 -
3937 -static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff *skb)
3938 -{
3939 - struct qca8k_mgmt_eth_data *mgmt_eth_data;
3940 - struct qca8k_priv *priv = ds->priv;
3941 - struct qca_mgmt_ethhdr *mgmt_ethhdr;
3942 - u8 len, cmd;
3943 -
3944 - mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb_mac_header(skb);
3945 - mgmt_eth_data = &priv->mgmt_eth_data;
3946 -
3947 - cmd = FIELD_GET(QCA_HDR_MGMT_CMD, mgmt_ethhdr->command);
3948 - len = FIELD_GET(QCA_HDR_MGMT_LENGTH, mgmt_ethhdr->command);
3949 -
3950 - /* Make sure the seq match the requested packet */
3951 - if (mgmt_ethhdr->seq == mgmt_eth_data->seq)
3952 - mgmt_eth_data->ack = true;
3953 -
3954 - if (cmd == MDIO_READ) {
3955 - mgmt_eth_data->data[0] = mgmt_ethhdr->mdio_data;
3956 -
3957 - /* Get the rest of the 12 byte of data.
3958 - * The read/write function will extract the requested data.
3959 - */
3960 - if (len > QCA_HDR_MGMT_DATA1_LEN)
3961 - memcpy(mgmt_eth_data->data + 1, skb->data,
3962 - QCA_HDR_MGMT_DATA2_LEN);
3963 - }
3964 -
3965 - complete(&mgmt_eth_data->rw_done);
3966 -}
3967 -
3968 -static struct sk_buff *qca8k_alloc_mdio_header(enum mdio_cmd cmd, u32 reg, u32 *val,
3969 - int priority, unsigned int len)
3970 -{
3971 - struct qca_mgmt_ethhdr *mgmt_ethhdr;
3972 - unsigned int real_len;
3973 - struct sk_buff *skb;
3974 - u32 *data2;
3975 - u16 hdr;
3976 -
3977 - skb = dev_alloc_skb(QCA_HDR_MGMT_PKT_LEN);
3978 - if (!skb)
3979 - return NULL;
3980 -
3981 - /* Max value for len reg is 15 (0xf) but the switch actually return 16 byte
3982 - * Actually for some reason the steps are:
3983 - * 0: nothing
3984 - * 1-4: first 4 byte
3985 - * 5-6: first 12 byte
3986 - * 7-15: all 16 byte
3987 - */
3988 - if (len == 16)
3989 - real_len = 15;
3990 - else
3991 - real_len = len;
3992 -
3993 - skb_reset_mac_header(skb);
3994 - skb_set_network_header(skb, skb->len);
3995 -
3996 - mgmt_ethhdr = skb_push(skb, QCA_HDR_MGMT_HEADER_LEN + QCA_HDR_LEN);
3997 -
3998 - hdr = FIELD_PREP(QCA_HDR_XMIT_VERSION, QCA_HDR_VERSION);
3999 - hdr |= FIELD_PREP(QCA_HDR_XMIT_PRIORITY, priority);
4000 - hdr |= QCA_HDR_XMIT_FROM_CPU;
4001 - hdr |= FIELD_PREP(QCA_HDR_XMIT_DP_BIT, BIT(0));
4002 - hdr |= FIELD_PREP(QCA_HDR_XMIT_CONTROL, QCA_HDR_XMIT_TYPE_RW_REG);
4003 -
4004 - mgmt_ethhdr->command = FIELD_PREP(QCA_HDR_MGMT_ADDR, reg);
4005 - mgmt_ethhdr->command |= FIELD_PREP(QCA_HDR_MGMT_LENGTH, real_len);
4006 - mgmt_ethhdr->command |= FIELD_PREP(QCA_HDR_MGMT_CMD, cmd);
4007 - mgmt_ethhdr->command |= FIELD_PREP(QCA_HDR_MGMT_CHECK_CODE,
4008 - QCA_HDR_MGMT_CHECK_CODE_VAL);
4009 -
4010 - if (cmd == MDIO_WRITE)
4011 - mgmt_ethhdr->mdio_data = *val;
4012 -
4013 - mgmt_ethhdr->hdr = htons(hdr);
4014 -
4015 - data2 = skb_put_zero(skb, QCA_HDR_MGMT_DATA2_LEN + QCA_HDR_MGMT_PADDING_LEN);
4016 - if (cmd == MDIO_WRITE && len > QCA_HDR_MGMT_DATA1_LEN)
4017 - memcpy(data2, val + 1, len - QCA_HDR_MGMT_DATA1_LEN);
4018 -
4019 - return skb;
4020 -}
4021 -
4022 -static void qca8k_mdio_header_fill_seq_num(struct sk_buff *skb, u32 seq_num)
4023 -{
4024 - struct qca_mgmt_ethhdr *mgmt_ethhdr;
4025 -
4026 - mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb->data;
4027 - mgmt_ethhdr->seq = FIELD_PREP(QCA_HDR_MGMT_SEQ_NUM, seq_num);
4028 -}
4029 -
4030 -static int qca8k_read_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
4031 -{
4032 - struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data;
4033 - struct sk_buff *skb;
4034 - bool ack;
4035 - int ret;
4036 -
4037 - skb = qca8k_alloc_mdio_header(MDIO_READ, reg, NULL,
4038 - QCA8K_ETHERNET_MDIO_PRIORITY, len);
4039 - if (!skb)
4040 - return -ENOMEM;
4041 -
4042 - mutex_lock(&mgmt_eth_data->mutex);
4043 -
4044 - /* Check mgmt_master if is operational */
4045 - if (!priv->mgmt_master) {
4046 - kfree_skb(skb);
4047 - mutex_unlock(&mgmt_eth_data->mutex);
4048 - return -EINVAL;
4049 - }
4050 -
4051 - skb->dev = priv->mgmt_master;
4052 -
4053 - reinit_completion(&mgmt_eth_data->rw_done);
4054 -
4055 - /* Increment seq_num and set it in the mdio pkt */
4056 - mgmt_eth_data->seq++;
4057 - qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
4058 - mgmt_eth_data->ack = false;
4059 -
4060 - dev_queue_xmit(skb);
4061 -
4062 - ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
4063 - msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT));
4064 -
4065 - *val = mgmt_eth_data->data[0];
4066 - if (len > QCA_HDR_MGMT_DATA1_LEN)
4067 - memcpy(val + 1, mgmt_eth_data->data + 1, len - QCA_HDR_MGMT_DATA1_LEN);
4068 -
4069 - ack = mgmt_eth_data->ack;
4070 -
4071 - mutex_unlock(&mgmt_eth_data->mutex);
4072 -
4073 - if (ret <= 0)
4074 - return -ETIMEDOUT;
4075 -
4076 - if (!ack)
4077 - return -EINVAL;
4078 -
4079 - return 0;
4080 -}
4081 -
4082 -static int qca8k_write_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
4083 -{
4084 - struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data;
4085 - struct sk_buff *skb;
4086 - bool ack;
4087 - int ret;
4088 -
4089 - skb = qca8k_alloc_mdio_header(MDIO_WRITE, reg, val,
4090 - QCA8K_ETHERNET_MDIO_PRIORITY, len);
4091 - if (!skb)
4092 - return -ENOMEM;
4093 -
4094 - mutex_lock(&mgmt_eth_data->mutex);
4095 -
4096 - /* Check mgmt_master if is operational */
4097 - if (!priv->mgmt_master) {
4098 - kfree_skb(skb);
4099 - mutex_unlock(&mgmt_eth_data->mutex);
4100 - return -EINVAL;
4101 - }
4102 -
4103 - skb->dev = priv->mgmt_master;
4104 -
4105 - reinit_completion(&mgmt_eth_data->rw_done);
4106 -
4107 - /* Increment seq_num and set it in the mdio pkt */
4108 - mgmt_eth_data->seq++;
4109 - qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
4110 - mgmt_eth_data->ack = false;
4111 -
4112 - dev_queue_xmit(skb);
4113 -
4114 - ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
4115 - msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT));
4116 -
4117 - ack = mgmt_eth_data->ack;
4118 -
4119 - mutex_unlock(&mgmt_eth_data->mutex);
4120 -
4121 - if (ret <= 0)
4122 - return -ETIMEDOUT;
4123 -
4124 - if (!ack)
4125 - return -EINVAL;
4126 -
4127 - return 0;
4128 -}
4129 -
4130 -static int
4131 -qca8k_regmap_update_bits_eth(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
4132 -{
4133 - u32 val = 0;
4134 - int ret;
4135 -
4136 - ret = qca8k_read_eth(priv, reg, &val, sizeof(val));
4137 - if (ret)
4138 - return ret;
4139 -
4140 - val &= ~mask;
4141 - val |= write_val;
4142 -
4143 - return qca8k_write_eth(priv, reg, &val, sizeof(val));
4144 -}
4145 -
4146 -static int
4147 -qca8k_bulk_read(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
4148 -{
4149 - int i, count = len / sizeof(u32), ret;
4150 -
4151 - if (priv->mgmt_master && !qca8k_read_eth(priv, reg, val, len))
4152 - return 0;
4153 -
4154 - for (i = 0; i < count; i++) {
4155 - ret = regmap_read(priv->regmap, reg + (i * 4), val + i);
4156 - if (ret < 0)
4157 - return ret;
4158 - }
4159 -
4160 - return 0;
4161 -}
4162 -
4163 -static int
4164 -qca8k_bulk_write(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
4165 -{
4166 - int i, count = len / sizeof(u32), ret;
4167 - u32 tmp;
4168 -
4169 - if (priv->mgmt_master && !qca8k_write_eth(priv, reg, val, len))
4170 - return 0;
4171 -
4172 - for (i = 0; i < count; i++) {
4173 - tmp = val[i];
4174 -
4175 - ret = regmap_write(priv->regmap, reg + (i * 4), tmp);
4176 - if (ret < 0)
4177 - return ret;
4178 - }
4179 -
4180 - return 0;
4181 -}
4182 -
4183 -static int
4184 -qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
4185 -{
4186 - struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
4187 - struct mii_bus *bus = priv->bus;
4188 - u16 r1, r2, page;
4189 - int ret;
4190 -
4191 - if (!qca8k_read_eth(priv, reg, val, sizeof(*val)))
4192 - return 0;
4193 -
4194 - qca8k_split_addr(reg, &r1, &r2, &page);
4195 -
4196 - mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
4197 -
4198 - ret = qca8k_set_page(priv, page);
4199 - if (ret < 0)
4200 - goto exit;
4201 -
4202 - ret = qca8k_mii_read32(bus, 0x10 | r2, r1, val);
4203 -
4204 -exit:
4205 - mutex_unlock(&bus->mdio_lock);
4206 - return ret;
4207 -}
4208 -
4209 -static int
4210 -qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
4211 -{
4212 - struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
4213 - struct mii_bus *bus = priv->bus;
4214 - u16 r1, r2, page;
4215 - int ret;
4216 -
4217 - if (!qca8k_write_eth(priv, reg, &val, sizeof(val)))
4218 - return 0;
4219 -
4220 - qca8k_split_addr(reg, &r1, &r2, &page);
4221 -
4222 - mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
4223 -
4224 - ret = qca8k_set_page(priv, page);
4225 - if (ret < 0)
4226 - goto exit;
4227 -
4228 - qca8k_mii_write32(priv, 0x10 | r2, r1, val);
4229 -
4230 -exit:
4231 - mutex_unlock(&bus->mdio_lock);
4232 - return ret;
4233 -}
4234 -
4235 -static int
4236 -qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_val)
4237 -{
4238 - struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
4239 - struct mii_bus *bus = priv->bus;
4240 - u16 r1, r2, page;
4241 - u32 val;
4242 - int ret;
4243 -
4244 - if (!qca8k_regmap_update_bits_eth(priv, reg, mask, write_val))
4245 - return 0;
4246 -
4247 - qca8k_split_addr(reg, &r1, &r2, &page);
4248 -
4249 - mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
4250 -
4251 - ret = qca8k_set_page(priv, page);
4252 - if (ret < 0)
4253 - goto exit;
4254 -
4255 - ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
4256 - if (ret < 0)
4257 - goto exit;
4258 -
4259 - val &= ~mask;
4260 - val |= write_val;
4261 - qca8k_mii_write32(priv, 0x10 | r2, r1, val);
4262 -
4263 -exit:
4264 - mutex_unlock(&bus->mdio_lock);
4265 -
4266 - return ret;
4267 -}
4268 -
4269 -static const struct regmap_range qca8k_readable_ranges[] = {
4270 - regmap_reg_range(0x0000, 0x00e4), /* Global control */
4271 - regmap_reg_range(0x0100, 0x0168), /* EEE control */
4272 - regmap_reg_range(0x0200, 0x0270), /* Parser control */
4273 - regmap_reg_range(0x0400, 0x0454), /* ACL */
4274 - regmap_reg_range(0x0600, 0x0718), /* Lookup */
4275 - regmap_reg_range(0x0800, 0x0b70), /* QM */
4276 - regmap_reg_range(0x0c00, 0x0c80), /* PKT */
4277 - regmap_reg_range(0x0e00, 0x0e98), /* L3 */
4278 - regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
4279 - regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
4280 - regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
4281 - regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
4282 - regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
4283 - regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
4284 - regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
4285 -
4286 -};
4287 -
4288 -static const struct regmap_access_table qca8k_readable_table = {
4289 - .yes_ranges = qca8k_readable_ranges,
4290 - .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
4291 -};
4292 -
4293 -static struct regmap_config qca8k_regmap_config = {
4294 - .reg_bits = 16,
4295 - .val_bits = 32,
4296 - .reg_stride = 4,
4297 - .max_register = 0x16ac, /* end MIB - Port6 range */
4298 - .reg_read = qca8k_regmap_read,
4299 - .reg_write = qca8k_regmap_write,
4300 - .reg_update_bits = qca8k_regmap_update_bits,
4301 - .rd_table = &qca8k_readable_table,
4302 - .disable_locking = true, /* Locking is handled by qca8k read/write */
4303 - .cache_type = REGCACHE_NONE, /* Explicitly disable CACHE */
4304 -};
4305 -
4306 -static int
4307 -qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
4308 -{
4309 - u32 val;
4310 -
4311 - return regmap_read_poll_timeout(priv->regmap, reg, val, !(val & mask), 0,
4312 - QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC);
4313 -}
4314 -
4315 -static int
4316 -qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
4317 -{
4318 - u32 reg[3];
4319 - int ret;
4320 -
4321 - /* load the ARL table into an array */
4322 - ret = qca8k_bulk_read(priv, QCA8K_REG_ATU_DATA0, reg, sizeof(reg));
4323 - if (ret)
4324 - return ret;
4325 -
4326 - /* vid - 83:72 */
4327 - fdb->vid = FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]);
4328 - /* aging - 67:64 */
4329 - fdb->aging = FIELD_GET(QCA8K_ATU_STATUS_MASK, reg[2]);
4330 - /* portmask - 54:48 */
4331 - fdb->port_mask = FIELD_GET(QCA8K_ATU_PORT_MASK, reg[1]);
4332 - /* mac - 47:0 */
4333 - fdb->mac[0] = FIELD_GET(QCA8K_ATU_ADDR0_MASK, reg[1]);
4334 - fdb->mac[1] = FIELD_GET(QCA8K_ATU_ADDR1_MASK, reg[1]);
4335 - fdb->mac[2] = FIELD_GET(QCA8K_ATU_ADDR2_MASK, reg[0]);
4336 - fdb->mac[3] = FIELD_GET(QCA8K_ATU_ADDR3_MASK, reg[0]);
4337 - fdb->mac[4] = FIELD_GET(QCA8K_ATU_ADDR4_MASK, reg[0]);
4338 - fdb->mac[5] = FIELD_GET(QCA8K_ATU_ADDR5_MASK, reg[0]);
4339 -
4340 - return 0;
4341 -}
4342 -
4343 -static void
4344 -qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
4345 - u8 aging)
4346 -{
4347 - u32 reg[3] = { 0 };
4348 -
4349 - /* vid - 83:72 */
4350 - reg[2] = FIELD_PREP(QCA8K_ATU_VID_MASK, vid);
4351 - /* aging - 67:64 */
4352 - reg[2] |= FIELD_PREP(QCA8K_ATU_STATUS_MASK, aging);
4353 - /* portmask - 54:48 */
4354 - reg[1] = FIELD_PREP(QCA8K_ATU_PORT_MASK, port_mask);
4355 - /* mac - 47:0 */
4356 - reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR0_MASK, mac[0]);
4357 - reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR1_MASK, mac[1]);
4358 - reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR2_MASK, mac[2]);
4359 - reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR3_MASK, mac[3]);
4360 - reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR4_MASK, mac[4]);
4361 - reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]);
4362 -
4363 - /* load the array into the ARL table */
4364 - qca8k_bulk_write(priv, QCA8K_REG_ATU_DATA0, reg, sizeof(reg));
4365 -}
4366 -
4367 -static int
4368 -qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
4369 -{
4370 - u32 reg;
4371 - int ret;
4372 -
4373 - /* Set the command and FDB index */
4374 - reg = QCA8K_ATU_FUNC_BUSY;
4375 - reg |= cmd;
4376 - if (port >= 0) {
4377 - reg |= QCA8K_ATU_FUNC_PORT_EN;
4378 - reg |= FIELD_PREP(QCA8K_ATU_FUNC_PORT_MASK, port);
4379 - }
4380 -
4381 - /* Write the function register triggering the table access */
4382 - ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
4383 - if (ret)
4384 - return ret;
4385 -
4386 - /* wait for completion */
4387 - ret = qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY);
4388 - if (ret)
4389 - return ret;
4390 -
4391 - /* Check for table full violation when adding an entry */
4392 - if (cmd == QCA8K_FDB_LOAD) {
4393 - ret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, &reg);
4394 - if (ret < 0)
4395 - return ret;
4396 - if (reg & QCA8K_ATU_FUNC_FULL)
4397 - return -1;
4398 - }
4399 -
4400 - return 0;
4401 -}
4402 -
4403 -static int
4404 -qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
4405 -{
4406 - int ret;
4407 -
4408 - qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
4409 - ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
4410 - if (ret < 0)
4411 - return ret;
4412 -
4413 - return qca8k_fdb_read(priv, fdb);
4414 -}
4415 -
4416 -static int
4417 -qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
4418 - u16 vid, u8 aging)
4419 -{
4420 - int ret;
4421 -
4422 - mutex_lock(&priv->reg_mutex);
4423 - qca8k_fdb_write(priv, vid, port_mask, mac, aging);
4424 - ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
4425 - mutex_unlock(&priv->reg_mutex);
4426 -
4427 - return ret;
4428 -}
4429 -
4430 -static int
4431 -qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
4432 -{
4433 - int ret;
4434 -
4435 - mutex_lock(&priv->reg_mutex);
4436 - qca8k_fdb_write(priv, vid, port_mask, mac, 0);
4437 - ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
4438 - mutex_unlock(&priv->reg_mutex);
4439 -
4440 - return ret;
4441 -}
4442 -
4443 -static void
4444 -qca8k_fdb_flush(struct qca8k_priv *priv)
4445 -{
4446 - mutex_lock(&priv->reg_mutex);
4447 - qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
4448 - mutex_unlock(&priv->reg_mutex);
4449 -}
4450 -
4451 -static int
4452 -qca8k_fdb_search_and_insert(struct qca8k_priv *priv, u8 port_mask,
4453 - const u8 *mac, u16 vid)
4454 -{
4455 - struct qca8k_fdb fdb = { 0 };
4456 - int ret;
4457 -
4458 - mutex_lock(&priv->reg_mutex);
4459 -
4460 - qca8k_fdb_write(priv, vid, 0, mac, 0);
4461 - ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1);
4462 - if (ret < 0)
4463 - goto exit;
4464 -
4465 - ret = qca8k_fdb_read(priv, &fdb);
4466 - if (ret < 0)
4467 - goto exit;
4468 -
4469 - /* Rule exist. Delete first */
4470 - if (!fdb.aging) {
4471 - ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
4472 - if (ret)
4473 - goto exit;
4474 - }
4475 -
4476 - /* Add port to fdb portmask */
4477 - fdb.port_mask |= port_mask;
4478 -
4479 - qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging);
4480 - ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
4481 -
4482 -exit:
4483 - mutex_unlock(&priv->reg_mutex);
4484 - return ret;
4485 -}
4486 -
4487 -static int
4488 -qca8k_fdb_search_and_del(struct qca8k_priv *priv, u8 port_mask,
4489 - const u8 *mac, u16 vid)
4490 -{
4491 - struct qca8k_fdb fdb = { 0 };
4492 - int ret;
4493 -
4494 - mutex_lock(&priv->reg_mutex);
4495 -
4496 - qca8k_fdb_write(priv, vid, 0, mac, 0);
4497 - ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1);
4498 - if (ret < 0)
4499 - goto exit;
4500 -
4501 - /* Rule doesn't exist. Why delete? */
4502 - if (!fdb.aging) {
4503 - ret = -EINVAL;
4504 - goto exit;
4505 - }
4506 -
4507 - ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
4508 - if (ret)
4509 - goto exit;
4510 -
4511 - /* Only port in the rule is this port. Don't re insert */
4512 - if (fdb.port_mask == port_mask)
4513 - goto exit;
4514 -
4515 - /* Remove port from port mask */
4516 - fdb.port_mask &= ~port_mask;
4517 -
4518 - qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging);
4519 - ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
4520 -
4521 -exit:
4522 - mutex_unlock(&priv->reg_mutex);
4523 - return ret;
4524 -}
4525 -
4526 -static int
4527 -qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)
4528 -{
4529 - u32 reg;
4530 - int ret;
4531 -
4532 - /* Set the command and VLAN index */
4533 - reg = QCA8K_VTU_FUNC1_BUSY;
4534 - reg |= cmd;
4535 - reg |= FIELD_PREP(QCA8K_VTU_FUNC1_VID_MASK, vid);
4536 -
4537 - /* Write the function register triggering the table access */
4538 - ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
4539 - if (ret)
4540 - return ret;
4541 -
4542 - /* wait for completion */
4543 - ret = qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY);
4544 - if (ret)
4545 - return ret;
4546 -
4547 - /* Check for table full violation when adding an entry */
4548 - if (cmd == QCA8K_VLAN_LOAD) {
4549 - ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, &reg);
4550 - if (ret < 0)
4551 - return ret;
4552 - if (reg & QCA8K_VTU_FUNC1_FULL)
4553 - return -ENOMEM;
4554 - }
4555 -
4556 - return 0;
4557 -}
4558 -
4559 -static int
4560 -qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged)
4561 -{
4562 - u32 reg;
4563 - int ret;
4564 -
4565 - /*
4566 - We do the right thing with VLAN 0 and treat it as untagged while
4567 - preserving the tag on egress.
4568 - */
4569 - if (vid == 0)
4570 - return 0;
4571 -
4572 - mutex_lock(&priv->reg_mutex);
4573 - ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
4574 - if (ret < 0)
4575 - goto out;
4576 -
4577 - ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
4578 - if (ret < 0)
4579 - goto out;
4580 - reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;
4581 - reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);
4582 - if (untagged)
4583 - reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(port);
4584 - else
4585 - reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(port);
4586 -
4587 - ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
4588 - if (ret)
4589 - goto out;
4590 - ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
4591 -
4592 -out:
4593 - mutex_unlock(&priv->reg_mutex);
4594 -
4595 - return ret;
4596 -}
4597 -
4598 -static int
4599 -qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid)
4600 -{
4601 - u32 reg, mask;
4602 - int ret, i;
4603 - bool del;
4604 -
4605 - mutex_lock(&priv->reg_mutex);
4606 - ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
4607 - if (ret < 0)
4608 - goto out;
4609 -
4610 - ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
4611 - if (ret < 0)
4612 - goto out;
4613 - reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);
4614 - reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(port);
4615 -
4616 - /* Check if we're the last member to be removed */
4617 - del = true;
4618 - for (i = 0; i < QCA8K_NUM_PORTS; i++) {
4619 - mask = QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i);
4620 -
4621 - if ((reg & mask) != mask) {
4622 - del = false;
4623 - break;
4624 - }
4625 - }
4626 -
4627 - if (del) {
4628 - ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid);
4629 - } else {
4630 - ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
4631 - if (ret)
4632 - goto out;
4633 - ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
4634 - }
4635 -
4636 -out:
4637 - mutex_unlock(&priv->reg_mutex);
4638 -
4639 - return ret;
4640 -}
4641 -
4642 -static int
4643 -qca8k_mib_init(struct qca8k_priv *priv)
4644 -{
4645 - int ret;
4646 -
4647 - mutex_lock(&priv->reg_mutex);
4648 - ret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB,
4649 - QCA8K_MIB_FUNC | QCA8K_MIB_BUSY,
4650 - FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_FLUSH) |
4651 - QCA8K_MIB_BUSY);
4652 - if (ret)
4653 - goto exit;
4654 -
4655 - ret = qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
4656 - if (ret)
4657 - goto exit;
4658 -
4659 - ret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
4660 - if (ret)
4661 - goto exit;
4662 -
4663 - ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
4664 -
4665 -exit:
4666 - mutex_unlock(&priv->reg_mutex);
4667 - return ret;
4668 -}
4669 -
4670 -static void
4671 -qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
4672 -{
4673 - u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
4674 -
4675 - /* Port 0 and 6 have no internal PHY */
4676 - if (port > 0 && port < 6)
4677 - mask |= QCA8K_PORT_STATUS_LINK_AUTO;
4678 -
4679 - if (enable)
4680 - regmap_set_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);
4681 - else
4682 - regmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);
4683 -}
4684 -
4685 -static int
4686 -qca8k_phy_eth_busy_wait(struct qca8k_mgmt_eth_data *mgmt_eth_data,
4687 - struct sk_buff *read_skb, u32 *val)
4688 -{
4689 - struct sk_buff *skb = skb_copy(read_skb, GFP_KERNEL);
4690 - bool ack;
4691 - int ret;
4692 -
4693 - reinit_completion(&mgmt_eth_data->rw_done);
4694 -
4695 - /* Increment seq_num and set it in the copy pkt */
4696 - mgmt_eth_data->seq++;
4697 - qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq);
4698 - mgmt_eth_data->ack = false;
4699 -
4700 - dev_queue_xmit(skb);
4701 -
4702 - ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
4703 - QCA8K_ETHERNET_TIMEOUT);
4704 -
4705 - ack = mgmt_eth_data->ack;
4706 -
4707 - if (ret <= 0)
4708 - return -ETIMEDOUT;
4709 -
4710 - if (!ack)
4711 - return -EINVAL;
4712 -
4713 - *val = mgmt_eth_data->data[0];
4714 -
4715 - return 0;
4716 -}
4717 -
4718 -static int
4719 -qca8k_phy_eth_command(struct qca8k_priv *priv, bool read, int phy,
4720 - int regnum, u16 data)
4721 -{
4722 - struct sk_buff *write_skb, *clear_skb, *read_skb;
4723 - struct qca8k_mgmt_eth_data *mgmt_eth_data;
4724 - u32 write_val, clear_val = 0, val;
4725 - struct net_device *mgmt_master;
4726 - int ret, ret1;
4727 - bool ack;
4728 -
4729 - if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
4730 - return -EINVAL;
4731 -
4732 - mgmt_eth_data = &priv->mgmt_eth_data;
4733 -
4734 - write_val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
4735 - QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
4736 - QCA8K_MDIO_MASTER_REG_ADDR(regnum);
4737 -
4738 - if (read) {
4739 - write_val |= QCA8K_MDIO_MASTER_READ;
4740 - } else {
4741 - write_val |= QCA8K_MDIO_MASTER_WRITE;
4742 - write_val |= QCA8K_MDIO_MASTER_DATA(data);
4743 - }
4744 -
4745 - /* Prealloc all the needed skb before the lock */
4746 - write_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, &write_val,
4747 - QCA8K_ETHERNET_PHY_PRIORITY, sizeof(write_val));
4748 - if (!write_skb)
4749 - return -ENOMEM;
4750 -
4751 - clear_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, &clear_val,
4752 - QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val));
4753 - if (!clear_skb) {
4754 - ret = -ENOMEM;
4755 - goto err_clear_skb;
4756 - }
4757 -
4758 - read_skb = qca8k_alloc_mdio_header(MDIO_READ, QCA8K_MDIO_MASTER_CTRL, &clear_val,
4759 - QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val));
4760 - if (!read_skb) {
4761 - ret = -ENOMEM;
4762 - goto err_read_skb;
4763 - }
4764 -
4765 - /* Actually start the request:
4766 - * 1. Send mdio master packet
4767 - * 2. Busy Wait for mdio master command
4768 - * 3. Get the data if we are reading
4769 - * 4. Reset the mdio master (even with error)
4770 - */
4771 - mutex_lock(&mgmt_eth_data->mutex);
4772 -
4773 - /* Check if mgmt_master is operational */
4774 - mgmt_master = priv->mgmt_master;
4775 - if (!mgmt_master) {
4776 - mutex_unlock(&mgmt_eth_data->mutex);
4777 - ret = -EINVAL;
4778 - goto err_mgmt_master;
4779 - }
4780 -
4781 - read_skb->dev = mgmt_master;
4782 - clear_skb->dev = mgmt_master;
4783 - write_skb->dev = mgmt_master;
4784 -
4785 - reinit_completion(&mgmt_eth_data->rw_done);
4786 -
4787 - /* Increment seq_num and set it in the write pkt */
4788 - mgmt_eth_data->seq++;
4789 - qca8k_mdio_header_fill_seq_num(write_skb, mgmt_eth_data->seq);
4790 - mgmt_eth_data->ack = false;
4791 -
4792 - dev_queue_xmit(write_skb);
4793 -
4794 - ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
4795 - QCA8K_ETHERNET_TIMEOUT);
4796 -
4797 - ack = mgmt_eth_data->ack;
4798 -
4799 - if (ret <= 0) {
4800 - ret = -ETIMEDOUT;
4801 - kfree_skb(read_skb);
4802 - goto exit;
4803 - }
4804 -
4805 - if (!ack) {
4806 - ret = -EINVAL;
4807 - kfree_skb(read_skb);
4808 - goto exit;
4809 - }
4810 -
4811 - ret = read_poll_timeout(qca8k_phy_eth_busy_wait, ret1,
4812 - !(val & QCA8K_MDIO_MASTER_BUSY), 0,
4813 - QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
4814 - mgmt_eth_data, read_skb, &val);
4815 -
4816 - if (ret < 0 && ret1 < 0) {
4817 - ret = ret1;
4818 - goto exit;
4819 - }
4820 -
4821 - if (read) {
4822 - reinit_completion(&mgmt_eth_data->rw_done);
4823 -
4824 - /* Increment seq_num and set it in the read pkt */
4825 - mgmt_eth_data->seq++;
4826 - qca8k_mdio_header_fill_seq_num(read_skb, mgmt_eth_data->seq);
4827 - mgmt_eth_data->ack = false;
4828 -
4829 - dev_queue_xmit(read_skb);
4830 -
4831 - ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done,
4832 - QCA8K_ETHERNET_TIMEOUT);
4833 -
4834 - ack = mgmt_eth_data->ack;
4835 -
4836 - if (ret <= 0) {
4837 - ret = -ETIMEDOUT;
4838 - goto exit;
4839 - }
4840 -
4841 - if (!ack) {
4842 - ret = -EINVAL;
4843 - goto exit;
4844 - }
4845 -
4846 - ret = mgmt_eth_data->data[0] & QCA8K_MDIO_MASTER_DATA_MASK;
4847 - } else {
4848 - kfree_skb(read_skb);
4849 - }
4850 -exit:
4851 - reinit_completion(&mgmt_eth_data->rw_done);
4852 -
4853 - /* Increment seq_num and set it in the clear pkt */
4854 - mgmt_eth_data->seq++;
4855 - qca8k_mdio_header_fill_seq_num(clear_skb, mgmt_eth_data->seq);
4856 - mgmt_eth_data->ack = false;
4857 -
4858 - dev_queue_xmit(clear_skb);
4859 -
4860 - wait_for_completion_timeout(&mgmt_eth_data->rw_done,
4861 - QCA8K_ETHERNET_TIMEOUT);
4862 -
4863 - mutex_unlock(&mgmt_eth_data->mutex);
4864 -
4865 - return ret;
4866 -
4867 - /* Error handling before lock */
4868 -err_mgmt_master:
4869 - kfree_skb(read_skb);
4870 -err_read_skb:
4871 - kfree_skb(clear_skb);
4872 -err_clear_skb:
4873 - kfree_skb(write_skb);
4874 -
4875 - return ret;
4876 -}
4877 -
4878 -static u32
4879 -qca8k_port_to_phy(int port)
4880 -{
4881 - /* From Andrew Lunn:
4882 - * Port 0 has no internal phy.
4883 - * Port 1 has an internal PHY at MDIO address 0.
4884 - * Port 2 has an internal PHY at MDIO address 1.
4885 - * ...
4886 - * Port 5 has an internal PHY at MDIO address 4.
4887 - * Port 6 has no internal PHY.
4888 - */
4889 -
4890 - return port - 1;
4891 -}
4892 -
4893 -static int
4894 -qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask)
4895 -{
4896 - u16 r1, r2, page;
4897 - u32 val;
4898 - int ret, ret1;
4899 -
4900 - qca8k_split_addr(reg, &r1, &r2, &page);
4901 -
4902 - ret = read_poll_timeout(qca8k_mii_read32, ret1, !(val & mask), 0,
4903 - QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false,
4904 - bus, 0x10 | r2, r1, &val);
4905 -
4906 - /* Check if qca8k_read has failed for a different reason
4907 - * before returnting -ETIMEDOUT
4908 - */
4909 - if (ret < 0 && ret1 < 0)
4910 - return ret1;
4911 -
4912 - return ret;
4913 -}
4914 -
4915 -static int
4916 -qca8k_mdio_write(struct qca8k_priv *priv, int phy, int regnum, u16 data)
4917 -{
4918 - struct mii_bus *bus = priv->bus;
4919 - u16 r1, r2, page;
4920 - u32 val;
4921 - int ret;
4922 -
4923 - if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
4924 - return -EINVAL;
4925 -
4926 - val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
4927 - QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
4928 - QCA8K_MDIO_MASTER_REG_ADDR(regnum) |
4929 - QCA8K_MDIO_MASTER_DATA(data);
4930 -
4931 - qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
4932 -
4933 - mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
4934 -
4935 - ret = qca8k_set_page(priv, page);
4936 - if (ret)
4937 - goto exit;
4938 -
4939 - qca8k_mii_write32(priv, 0x10 | r2, r1, val);
4940 -
4941 - ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
4942 - QCA8K_MDIO_MASTER_BUSY);
4943 -
4944 -exit:
4945 - /* even if the busy_wait timeouts try to clear the MASTER_EN */
4946 - qca8k_mii_write32(priv, 0x10 | r2, r1, 0);
4947 -
4948 - mutex_unlock(&bus->mdio_lock);
4949 -
4950 - return ret;
4951 -}
4952 -
4953 -static int
4954 -qca8k_mdio_read(struct qca8k_priv *priv, int phy, int regnum)
4955 -{
4956 - struct mii_bus *bus = priv->bus;
4957 - u16 r1, r2, page;
4958 - u32 val;
4959 - int ret;
4960 -
4961 - if (regnum >= QCA8K_MDIO_MASTER_MAX_REG)
4962 - return -EINVAL;
4963 -
4964 - val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN |
4965 - QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) |
4966 - QCA8K_MDIO_MASTER_REG_ADDR(regnum);
4967 -
4968 - qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page);
4969 -
4970 - mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
4971 -
4972 - ret = qca8k_set_page(priv, page);
4973 - if (ret)
4974 - goto exit;
4975 -
4976 - qca8k_mii_write32(priv, 0x10 | r2, r1, val);
4977 -
4978 - ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL,
4979 - QCA8K_MDIO_MASTER_BUSY);
4980 - if (ret)
4981 - goto exit;
4982 -
4983 - ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val);
4984 -
4985 -exit:
4986 - /* even if the busy_wait timeouts try to clear the MASTER_EN */
4987 - qca8k_mii_write32(priv, 0x10 | r2, r1, 0);
4988 -
4989 - mutex_unlock(&bus->mdio_lock);
4990 -
4991 - if (ret >= 0)
4992 - ret = val & QCA8K_MDIO_MASTER_DATA_MASK;
4993 -
4994 - return ret;
4995 -}
4996 -
4997 -static int
4998 -qca8k_internal_mdio_write(struct mii_bus *slave_bus, int phy, int regnum, u16 data)
4999 -{
5000 - struct qca8k_priv *priv = slave_bus->priv;
5001 - int ret;
5002 -
5003 - /* Use mdio Ethernet when available, fallback to legacy one on error */
5004 - ret = qca8k_phy_eth_command(priv, false, phy, regnum, data);
5005 - if (!ret)
5006 - return 0;
5007 -
5008 - return qca8k_mdio_write(priv, phy, regnum, data);
5009 -}
5010 -
5011 -static int
5012 -qca8k_internal_mdio_read(struct mii_bus *slave_bus, int phy, int regnum)
5013 -{
5014 - struct qca8k_priv *priv = slave_bus->priv;
5015 - int ret;
5016 -
5017 - /* Use mdio Ethernet when available, fallback to legacy one on error */
5018 - ret = qca8k_phy_eth_command(priv, true, phy, regnum, 0);
5019 - if (ret >= 0)
5020 - return ret;
5021 -
5022 - ret = qca8k_mdio_read(priv, phy, regnum);
5023 -
5024 - if (ret < 0)
5025 - return 0xffff;
5026 -
5027 - return ret;
5028 -}
5029 -
5030 -static int
5031 -qca8k_legacy_mdio_write(struct mii_bus *slave_bus, int port, int regnum, u16 data)
5032 -{
5033 - port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
5034 -
5035 - return qca8k_internal_mdio_write(slave_bus, port, regnum, data);
5036 -}
5037 -
5038 -static int
5039 -qca8k_legacy_mdio_read(struct mii_bus *slave_bus, int port, int regnum)
5040 -{
5041 - port = qca8k_port_to_phy(port) % PHY_MAX_ADDR;
5042 -
5043 - return qca8k_internal_mdio_read(slave_bus, port, regnum);
5044 -}
5045 -
5046 -static int
5047 -qca8k_mdio_register(struct qca8k_priv *priv)
5048 -{
5049 - struct dsa_switch *ds = priv->ds;
5050 - struct device_node *mdio;
5051 - struct mii_bus *bus;
5052 -
5053 - bus = devm_mdiobus_alloc(ds->dev);
5054 - if (!bus)
5055 - return -ENOMEM;
5056 -
5057 - bus->priv = (void *)priv;
5058 - snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d.%d",
5059 - ds->dst->index, ds->index);
5060 - bus->parent = ds->dev;
5061 - bus->phy_mask = ~ds->phys_mii_mask;
5062 - ds->slave_mii_bus = bus;
5063 -
5064 - /* Check if the devicetree declare the port:phy mapping */
5065 - mdio = of_get_child_by_name(priv->dev->of_node, "mdio");
5066 - if (of_device_is_available(mdio)) {
5067 - bus->name = "qca8k slave mii";
5068 - bus->read = qca8k_internal_mdio_read;
5069 - bus->write = qca8k_internal_mdio_write;
5070 - return devm_of_mdiobus_register(priv->dev, bus, mdio);
5071 - }
5072 -
5073 - /* If a mapping can't be found the legacy mapping is used,
5074 - * using the qca8k_port_to_phy function
5075 - */
5076 - bus->name = "qca8k-legacy slave mii";
5077 - bus->read = qca8k_legacy_mdio_read;
5078 - bus->write = qca8k_legacy_mdio_write;
5079 - return devm_mdiobus_register(priv->dev, bus);
5080 -}
5081 -
5082 -static int
5083 -qca8k_setup_mdio_bus(struct qca8k_priv *priv)
5084 -{
5085 - u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg;
5086 - struct device_node *ports, *port;
5087 - phy_interface_t mode;
5088 - int err;
5089 -
5090 - ports = of_get_child_by_name(priv->dev->of_node, "ports");
5091 - if (!ports)
5092 - ports = of_get_child_by_name(priv->dev->of_node, "ethernet-ports");
5093 -
5094 - if (!ports)
5095 - return -EINVAL;
5096 -
5097 - for_each_available_child_of_node(ports, port) {
5098 - err = of_property_read_u32(port, "reg", &reg);
5099 - if (err) {
5100 - of_node_put(port);
5101 - of_node_put(ports);
5102 - return err;
5103 - }
5104 -
5105 - if (!dsa_is_user_port(priv->ds, reg))
5106 - continue;
5107 -
5108 - of_get_phy_mode(port, &mode);
5109 -
5110 - if (of_property_read_bool(port, "phy-handle") &&
5111 - mode != PHY_INTERFACE_MODE_INTERNAL)
5112 - external_mdio_mask |= BIT(reg);
5113 - else
5114 - internal_mdio_mask |= BIT(reg);
5115 - }
5116 -
5117 - of_node_put(ports);
5118 - if (!external_mdio_mask && !internal_mdio_mask) {
5119 - dev_err(priv->dev, "no PHYs are defined.\n");
5120 - return -EINVAL;
5121 - }
5122 -
5123 - /* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through
5124 - * the MDIO_MASTER register also _disconnects_ the external MDC
5125 - * passthrough to the internal PHYs. It's not possible to use both
5126 - * configurations at the same time!
5127 - *
5128 - * Because this came up during the review process:
5129 - * If the external mdio-bus driver is capable magically disabling
5130 - * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's
5131 - * accessors for the time being, it would be possible to pull this
5132 - * off.
5133 - */
5134 - if (!!external_mdio_mask && !!internal_mdio_mask) {
5135 - dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n");
5136 - return -EINVAL;
5137 - }
5138 -
5139 - if (external_mdio_mask) {
5140 - /* Make sure to disable the internal mdio bus in cases
5141 - * a dt-overlay and driver reload changed the configuration
5142 - */
5143 -
5144 - return regmap_clear_bits(priv->regmap, QCA8K_MDIO_MASTER_CTRL,
5145 - QCA8K_MDIO_MASTER_EN);
5146 - }
5147 -
5148 - return qca8k_mdio_register(priv);
5149 -}
5150 -
5151 -static int
5152 -qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
5153 -{
5154 - u32 mask = 0;
5155 - int ret = 0;
5156 -
5157 - /* SoC specific settings for ipq8064.
5158 - * If more device require this consider adding
5159 - * a dedicated binding.
5160 - */
5161 - if (of_machine_is_compatible("qcom,ipq8064"))
5162 - mask |= QCA8K_MAC_PWR_RGMII0_1_8V;
5163 -
5164 - /* SoC specific settings for ipq8065 */
5165 - if (of_machine_is_compatible("qcom,ipq8065"))
5166 - mask |= QCA8K_MAC_PWR_RGMII1_1_8V;
5167 -
5168 - if (mask) {
5169 - ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL,
5170 - QCA8K_MAC_PWR_RGMII0_1_8V |
5171 - QCA8K_MAC_PWR_RGMII1_1_8V,
5172 - mask);
5173 - }
5174 -
5175 - return ret;
5176 -}
5177 -
5178 -static int qca8k_find_cpu_port(struct dsa_switch *ds)
5179 -{
5180 - struct qca8k_priv *priv = ds->priv;
5181 -
5182 - /* Find the connected cpu port. Valid port are 0 or 6 */
5183 - if (dsa_is_cpu_port(ds, 0))
5184 - return 0;
5185 -
5186 - dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6");
5187 -
5188 - if (dsa_is_cpu_port(ds, 6))
5189 - return 6;
5190 -
5191 - return -EINVAL;
5192 -}
5193 -
5194 -static int
5195 -qca8k_setup_of_pws_reg(struct qca8k_priv *priv)
5196 -{
5197 - struct device_node *node = priv->dev->of_node;
5198 - const struct qca8k_match_data *data;
5199 - u32 val = 0;
5200 - int ret;
5201 -
5202 - /* QCA8327 require to set to the correct mode.
5203 - * His bigger brother QCA8328 have the 172 pin layout.
5204 - * Should be applied by default but we set this just to make sure.
5205 - */
5206 - if (priv->switch_id == QCA8K_ID_QCA8327) {
5207 - data = of_device_get_match_data(priv->dev);
5208 -
5209 - /* Set the correct package of 148 pin for QCA8327 */
5210 - if (data->reduced_package)
5211 - val |= QCA8327_PWS_PACKAGE148_EN;
5212 -
5213 - ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN,
5214 - val);
5215 - if (ret)
5216 - return ret;
5217 - }
5218 -
5219 - if (of_property_read_bool(node, "qca,ignore-power-on-sel"))
5220 - val |= QCA8K_PWS_POWER_ON_SEL;
5221 -
5222 - if (of_property_read_bool(node, "qca,led-open-drain")) {
5223 - if (!(val & QCA8K_PWS_POWER_ON_SEL)) {
5224 - dev_err(priv->dev, "qca,led-open-drain require qca,ignore-power-on-sel to be set.");
5225 - return -EINVAL;
5226 - }
5227 -
5228 - val |= QCA8K_PWS_LED_OPEN_EN_CSR;
5229 - }
5230 -
5231 - return qca8k_rmw(priv, QCA8K_REG_PWS,
5232 - QCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL,
5233 - val);
5234 -}
5235 -
5236 -static int
5237 -qca8k_parse_port_config(struct qca8k_priv *priv)
5238 -{
5239 - int port, cpu_port_index = -1, ret;
5240 - struct device_node *port_dn;
5241 - phy_interface_t mode;
5242 - struct dsa_port *dp;
5243 - u32 delay;
5244 -
5245 - /* We have 2 CPU port. Check them */
5246 - for (port = 0; port < QCA8K_NUM_PORTS; port++) {
5247 - /* Skip every other port */
5248 - if (port != 0 && port != 6)
5249 - continue;
5250 -
5251 - dp = dsa_to_port(priv->ds, port);
5252 - port_dn = dp->dn;
5253 - cpu_port_index++;
5254 -
5255 - if (!of_device_is_available(port_dn))
5256 - continue;
5257 -
5258 - ret = of_get_phy_mode(port_dn, &mode);
5259 - if (ret)
5260 - continue;
5261 -
5262 - switch (mode) {
5263 - case PHY_INTERFACE_MODE_RGMII:
5264 - case PHY_INTERFACE_MODE_RGMII_ID:
5265 - case PHY_INTERFACE_MODE_RGMII_TXID:
5266 - case PHY_INTERFACE_MODE_RGMII_RXID:
5267 - case PHY_INTERFACE_MODE_SGMII:
5268 - delay = 0;
5269 -
5270 - if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay))
5271 - /* Switch regs accept value in ns, convert ps to ns */
5272 - delay = delay / 1000;
5273 - else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
5274 - mode == PHY_INTERFACE_MODE_RGMII_TXID)
5275 - delay = 1;
5276 -
5277 - if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, delay)) {
5278 - dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
5279 - delay = 3;
5280 - }
5281 -
5282 - priv->ports_config.rgmii_tx_delay[cpu_port_index] = delay;
5283 -
5284 - delay = 0;
5285 -
5286 - if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay))
5287 - /* Switch regs accept value in ns, convert ps to ns */
5288 - delay = delay / 1000;
5289 - else if (mode == PHY_INTERFACE_MODE_RGMII_ID ||
5290 - mode == PHY_INTERFACE_MODE_RGMII_RXID)
5291 - delay = 2;
5292 -
5293 - if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, delay)) {
5294 - dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
5295 - delay = 3;
5296 - }
5297 -
5298 - priv->ports_config.rgmii_rx_delay[cpu_port_index] = delay;
5299 -
5300 - /* Skip sgmii parsing for rgmii* mode */
5301 - if (mode == PHY_INTERFACE_MODE_RGMII ||
5302 - mode == PHY_INTERFACE_MODE_RGMII_ID ||
5303 - mode == PHY_INTERFACE_MODE_RGMII_TXID ||
5304 - mode == PHY_INTERFACE_MODE_RGMII_RXID)
5305 - break;
5306 -
5307 - if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge"))
5308 - priv->ports_config.sgmii_tx_clk_falling_edge = true;
5309 -
5310 - if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
5311 - priv->ports_config.sgmii_rx_clk_falling_edge = true;
5312 -
5313 - if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) {
5314 - priv->ports_config.sgmii_enable_pll = true;
5315 -
5316 - if (priv->switch_id == QCA8K_ID_QCA8327) {
5317 - dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling");
5318 - priv->ports_config.sgmii_enable_pll = false;
5319 - }
5320 -
5321 - if (priv->switch_revision < 2)
5322 - dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more.");
5323 - }
5324 -
5325 - break;
5326 - default:
5327 - continue;
5328 - }
5329 - }
5330 -
5331 - return 0;
5332 -}
5333 -
5334 -static int
5335 -qca8k_setup(struct dsa_switch *ds)
5336 -{
5337 - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
5338 - int cpu_port, ret, i;
5339 - u32 mask;
5340 -
5341 - cpu_port = qca8k_find_cpu_port(ds);
5342 - if (cpu_port < 0) {
5343 - dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6");
5344 - return cpu_port;
5345 - }
5346 -
5347 - /* Parse CPU port config to be later used in phy_link mac_config */
5348 - ret = qca8k_parse_port_config(priv);
5349 - if (ret)
5350 - return ret;
5351 -
5352 - ret = qca8k_setup_mdio_bus(priv);
5353 - if (ret)
5354 - return ret;
5355 -
5356 - ret = qca8k_setup_of_pws_reg(priv);
5357 - if (ret)
5358 - return ret;
5359 -
5360 - ret = qca8k_setup_mac_pwr_sel(priv);
5361 - if (ret)
5362 - return ret;
5363 -
5364 - /* Make sure MAC06 is disabled */
5365 - ret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT0_PAD_CTRL,
5366 - QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN);
5367 - if (ret) {
5368 - dev_err(priv->dev, "failed disabling MAC06 exchange");
5369 - return ret;
5370 - }
5371 -
5372 - /* Enable CPU Port */
5373 - ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
5374 - QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
5375 - if (ret) {
5376 - dev_err(priv->dev, "failed enabling CPU port");
5377 - return ret;
5378 - }
5379 -
5380 - /* Enable MIB counters */
5381 - ret = qca8k_mib_init(priv);
5382 - if (ret)
5383 - dev_warn(priv->dev, "mib init failed");
5384 -
5385 - /* Initial setup of all ports */
5386 - for (i = 0; i < QCA8K_NUM_PORTS; i++) {
5387 - /* Disable forwarding by default on all ports */
5388 - ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
5389 - QCA8K_PORT_LOOKUP_MEMBER, 0);
5390 - if (ret)
5391 - return ret;
5392 -
5393 - /* Enable QCA header mode on all cpu ports */
5394 - if (dsa_is_cpu_port(ds, i)) {
5395 - ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i),
5396 - FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |
5397 - FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));
5398 - if (ret) {
5399 - dev_err(priv->dev, "failed enabling QCA header mode");
5400 - return ret;
5401 - }
5402 - }
5403 -
5404 - /* Disable MAC by default on all user ports */
5405 - if (dsa_is_user_port(ds, i))
5406 - qca8k_port_set_status(priv, i, 0);
5407 - }
5408 -
5409 - /* Forward all unknown frames to CPU port for Linux processing
5410 - * Notice that in multi-cpu config only one port should be set
5411 - * for igmp, unknown, multicast and broadcast packet
5412 - */
5413 - ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
5414 - FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) |
5415 - FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) |
5416 - FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) |
5417 - FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port)));
5418 - if (ret)
5419 - return ret;
5420 -
5421 - /* Setup connection between CPU port & user ports
5422 - * Configure specific switch configuration for ports
5423 - */
5424 - for (i = 0; i < QCA8K_NUM_PORTS; i++) {
5425 - /* CPU port gets connected to all user ports of the switch */
5426 - if (dsa_is_cpu_port(ds, i)) {
5427 - ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
5428 - QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
5429 - if (ret)
5430 - return ret;
5431 - }
5432 -
5433 - /* Individual user ports get connected to CPU port only */
5434 - if (dsa_is_user_port(ds, i)) {
5435 - ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
5436 - QCA8K_PORT_LOOKUP_MEMBER,
5437 - BIT(cpu_port));
5438 - if (ret)
5439 - return ret;
5440 -
5441 - /* Enable ARP Auto-learning by default */
5442 - ret = regmap_set_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(i),
5443 - QCA8K_PORT_LOOKUP_LEARN);
5444 - if (ret)
5445 - return ret;
5446 -
5447 - /* For port based vlans to work we need to set the
5448 - * default egress vid
5449 - */
5450 - ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
5451 - QCA8K_EGREES_VLAN_PORT_MASK(i),
5452 - QCA8K_EGREES_VLAN_PORT(i, QCA8K_PORT_VID_DEF));
5453 - if (ret)
5454 - return ret;
5455 -
5456 - ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
5457 - QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
5458 - QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
5459 - if (ret)
5460 - return ret;
5461 - }
5462 -
5463 - /* The port 5 of the qca8337 have some problem in flood condition. The
5464 - * original legacy driver had some specific buffer and priority settings
5465 - * for the different port suggested by the QCA switch team. Add this
5466 - * missing settings to improve switch stability under load condition.
5467 - * This problem is limited to qca8337 and other qca8k switch are not affected.
5468 - */
5469 - if (priv->switch_id == QCA8K_ID_QCA8337) {
5470 - switch (i) {
5471 - /* The 2 CPU port and port 5 requires some different
5472 - * priority than any other ports.
5473 - */
5474 - case 0:
5475 - case 5:
5476 - case 6:
5477 - mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
5478 - QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
5479 - QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |
5480 - QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |
5481 - QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |
5482 - QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |
5483 - QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
5484 - break;
5485 - default:
5486 - mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
5487 - QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
5488 - QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |
5489 - QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |
5490 - QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
5491 - }
5492 - qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask);
5493 -
5494 - mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |
5495 - QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
5496 - QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
5497 - QCA8K_PORT_HOL_CTRL1_WRED_EN;
5498 - qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),
5499 - QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |
5500 - QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
5501 - QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
5502 - QCA8K_PORT_HOL_CTRL1_WRED_EN,
5503 - mask);
5504 - }
5505 - }
5506 -
5507 - /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */
5508 - if (priv->switch_id == QCA8K_ID_QCA8327) {
5509 - mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |
5510 - QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);
5511 - qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,
5512 - QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK |
5513 - QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK,
5514 - mask);
5515 - }
5516 -
5517 - /* Setup our port MTUs to match power on defaults */
5518 - ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
5519 - if (ret)
5520 - dev_warn(priv->dev, "failed setting MTU settings");
5521 -
5522 - /* Flush the FDB table */
5523 - qca8k_fdb_flush(priv);
5524 -
5525 - /* We don't have interrupts for link changes, so we need to poll */
5526 - ds->pcs_poll = true;
5527 -
5528 - /* Set min a max ageing value supported */
5529 - ds->ageing_time_min = 7000;
5530 - ds->ageing_time_max = 458745000;
5531 -
5532 - /* Set max number of LAGs supported */
5533 - ds->num_lag_ids = QCA8K_NUM_LAGS;
5534 -
5535 - return 0;
5536 -}
5537 -
5538 -static void
5539 -qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_index,
5540 - u32 reg)
5541 -{
5542 - u32 delay, val = 0;
5543 - int ret;
5544 -
5545 - /* Delay can be declared in 3 different way.
5546 - * Mode to rgmii and internal-delay standard binding defined
5547 - * rgmii-id or rgmii-tx/rx phy mode set.
5548 - * The parse logic set a delay different than 0 only when one
5549 - * of the 3 different way is used. In all other case delay is
5550 - * not enabled. With ID or TX/RXID delay is enabled and set
5551 - * to the default and recommended value.
5552 - */
5553 - if (priv->ports_config.rgmii_tx_delay[cpu_port_index]) {
5554 - delay = priv->ports_config.rgmii_tx_delay[cpu_port_index];
5555 -
5556 - val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
5557 - QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
5558 - }
5559 -
5560 - if (priv->ports_config.rgmii_rx_delay[cpu_port_index]) {
5561 - delay = priv->ports_config.rgmii_rx_delay[cpu_port_index];
5562 -
5563 - val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
5564 - QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
5565 - }
5566 -
5567 - /* Set RGMII delay based on the selected values */
5568 - ret = qca8k_rmw(priv, reg,
5569 - QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK |
5570 - QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK |
5571 - QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
5572 - QCA8K_PORT_PAD_RGMII_RX_DELAY_EN,
5573 - val);
5574 - if (ret)
5575 - dev_err(priv->dev, "Failed to set internal delay for CPU port%d",
5576 - cpu_port_index == QCA8K_CPU_PORT0 ? 0 : 6);
5577 -}
5578 -
5579 -static void
5580 -qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
5581 - const struct phylink_link_state *state)
5582 -{
5583 - struct qca8k_priv *priv = ds->priv;
5584 - int cpu_port_index, ret;
5585 - u32 reg, val;
5586 -
5587 - switch (port) {
5588 - case 0: /* 1st CPU port */
5589 - if (state->interface != PHY_INTERFACE_MODE_RGMII &&
5590 - state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
5591 - state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
5592 - state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
5593 - state->interface != PHY_INTERFACE_MODE_SGMII)
5594 - return;
5595 -
5596 - reg = QCA8K_REG_PORT0_PAD_CTRL;
5597 - cpu_port_index = QCA8K_CPU_PORT0;
5598 - break;
5599 - case 1:
5600 - case 2:
5601 - case 3:
5602 - case 4:
5603 - case 5:
5604 - /* Internal PHY, nothing to do */
5605 - return;
5606 - case 6: /* 2nd CPU port / external PHY */
5607 - if (state->interface != PHY_INTERFACE_MODE_RGMII &&
5608 - state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
5609 - state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
5610 - state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
5611 - state->interface != PHY_INTERFACE_MODE_SGMII &&
5612 - state->interface != PHY_INTERFACE_MODE_1000BASEX)
5613 - return;
5614 -
5615 - reg = QCA8K_REG_PORT6_PAD_CTRL;
5616 - cpu_port_index = QCA8K_CPU_PORT6;
5617 - break;
5618 - default:
5619 - dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
5620 - return;
5621 - }
5622 -
5623 - if (port != 6 && phylink_autoneg_inband(mode)) {
5624 - dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
5625 - __func__);
5626 - return;
5627 - }
5628 -
5629 - switch (state->interface) {
5630 - case PHY_INTERFACE_MODE_RGMII:
5631 - case PHY_INTERFACE_MODE_RGMII_ID:
5632 - case PHY_INTERFACE_MODE_RGMII_TXID:
5633 - case PHY_INTERFACE_MODE_RGMII_RXID:
5634 - qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
5635 -
5636 - /* Configure rgmii delay */
5637 - qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
5638 -
5639 - /* QCA8337 requires to set rgmii rx delay for all ports.
5640 - * This is enabled through PORT5_PAD_CTRL for all ports,
5641 - * rather than individual port registers.
5642 - */
5643 - if (priv->switch_id == QCA8K_ID_QCA8337)
5644 - qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
5645 - QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
5646 - break;
5647 - case PHY_INTERFACE_MODE_SGMII:
5648 - case PHY_INTERFACE_MODE_1000BASEX:
5649 - /* Enable SGMII on the port */
5650 - qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
5651 -
5652 - /* Enable/disable SerDes auto-negotiation as necessary */
5653 - ret = qca8k_read(priv, QCA8K_REG_PWS, &val);
5654 - if (ret)
5655 - return;
5656 - if (phylink_autoneg_inband(mode))
5657 - val &= ~QCA8K_PWS_SERDES_AEN_DIS;
5658 - else
5659 - val |= QCA8K_PWS_SERDES_AEN_DIS;
5660 - qca8k_write(priv, QCA8K_REG_PWS, val);
5661 -
5662 - /* Configure the SGMII parameters */
5663 - ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
5664 - if (ret)
5665 - return;
5666 -
5667 - val |= QCA8K_SGMII_EN_SD;
5668 -
5669 - if (priv->ports_config.sgmii_enable_pll)
5670 - val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
5671 - QCA8K_SGMII_EN_TX;
5672 -
5673 - if (dsa_is_cpu_port(ds, port)) {
5674 - /* CPU port, we're talking to the CPU MAC, be a PHY */
5675 - val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
5676 - val |= QCA8K_SGMII_MODE_CTRL_PHY;
5677 - } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
5678 - val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
5679 - val |= QCA8K_SGMII_MODE_CTRL_MAC;
5680 - } else if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
5681 - val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
5682 - val |= QCA8K_SGMII_MODE_CTRL_BASEX;
5683 - }
5684 -
5685 - qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
5686 -
5687 - /* From original code is reported port instability as SGMII also
5688 - * require delay set. Apply advised values here or take them from DT.
5689 - */
5690 - if (state->interface == PHY_INTERFACE_MODE_SGMII)
5691 - qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
5692 -
5693 - /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
5694 - * falling edge is set writing in the PORT0 PAD reg
5695 - */
5696 - if (priv->switch_id == QCA8K_ID_QCA8327 ||
5697 - priv->switch_id == QCA8K_ID_QCA8337)
5698 - reg = QCA8K_REG_PORT0_PAD_CTRL;
5699 -
5700 - val = 0;
5701 -
5702 - /* SGMII Clock phase configuration */
5703 - if (priv->ports_config.sgmii_rx_clk_falling_edge)
5704 - val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
5705 -
5706 - if (priv->ports_config.sgmii_tx_clk_falling_edge)
5707 - val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
5708 -
5709 - if (val)
5710 - ret = qca8k_rmw(priv, reg,
5711 - QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
5712 - QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
5713 - val);
5714 -
5715 - break;
5716 - default:
5717 - dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
5718 - phy_modes(state->interface), port);
5719 - return;
5720 - }
5721 -}
5722 -
5723 -static void
5724 -qca8k_phylink_validate(struct dsa_switch *ds, int port,
5725 - unsigned long *supported,
5726 - struct phylink_link_state *state)
5727 -{
5728 - __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
5729 -
5730 - switch (port) {
5731 - case 0: /* 1st CPU port */
5732 - if (state->interface != PHY_INTERFACE_MODE_NA &&
5733 - state->interface != PHY_INTERFACE_MODE_RGMII &&
5734 - state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
5735 - state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
5736 - state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
5737 - state->interface != PHY_INTERFACE_MODE_SGMII)
5738 - goto unsupported;
5739 - break;
5740 - case 1:
5741 - case 2:
5742 - case 3:
5743 - case 4:
5744 - case 5:
5745 - /* Internal PHY */
5746 - if (state->interface != PHY_INTERFACE_MODE_NA &&
5747 - state->interface != PHY_INTERFACE_MODE_GMII &&
5748 - state->interface != PHY_INTERFACE_MODE_INTERNAL)
5749 - goto unsupported;
5750 - break;
5751 - case 6: /* 2nd CPU port / external PHY */
5752 - if (state->interface != PHY_INTERFACE_MODE_NA &&
5753 - state->interface != PHY_INTERFACE_MODE_RGMII &&
5754 - state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
5755 - state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
5756 - state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
5757 - state->interface != PHY_INTERFACE_MODE_SGMII &&
5758 - state->interface != PHY_INTERFACE_MODE_1000BASEX)
5759 - goto unsupported;
5760 - break;
5761 - default:
5762 -unsupported:
5763 - linkmode_zero(supported);
5764 - return;
5765 - }
5766 -
5767 - phylink_set_port_modes(mask);
5768 - phylink_set(mask, Autoneg);
5769 -
5770 - phylink_set(mask, 1000baseT_Full);
5771 - phylink_set(mask, 10baseT_Half);
5772 - phylink_set(mask, 10baseT_Full);
5773 - phylink_set(mask, 100baseT_Half);
5774 - phylink_set(mask, 100baseT_Full);
5775 -
5776 - if (state->interface == PHY_INTERFACE_MODE_1000BASEX)
5777 - phylink_set(mask, 1000baseX_Full);
5778 -
5779 - phylink_set(mask, Pause);
5780 - phylink_set(mask, Asym_Pause);
5781 -
5782 - linkmode_and(supported, supported, mask);
5783 - linkmode_and(state->advertising, state->advertising, mask);
5784 -}
5785 -
5786 -static int
5787 -qca8k_phylink_mac_link_state(struct dsa_switch *ds, int port,
5788 - struct phylink_link_state *state)
5789 -{
5790 - struct qca8k_priv *priv = ds->priv;
5791 - u32 reg;
5792 - int ret;
5793 -
5794 - ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), &reg);
5795 - if (ret < 0)
5796 - return ret;
5797 -
5798 - state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
5799 - state->an_complete = state->link;
5800 - state->an_enabled = !!(reg & QCA8K_PORT_STATUS_LINK_AUTO);
5801 - state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
5802 - DUPLEX_HALF;
5803 -
5804 - switch (reg & QCA8K_PORT_STATUS_SPEED) {
5805 - case QCA8K_PORT_STATUS_SPEED_10:
5806 - state->speed = SPEED_10;
5807 - break;
5808 - case QCA8K_PORT_STATUS_SPEED_100:
5809 - state->speed = SPEED_100;
5810 - break;
5811 - case QCA8K_PORT_STATUS_SPEED_1000:
5812 - state->speed = SPEED_1000;
5813 - break;
5814 - default:
5815 - state->speed = SPEED_UNKNOWN;
5816 - break;
5817 - }
5818 -
5819 - state->pause = MLO_PAUSE_NONE;
5820 - if (reg & QCA8K_PORT_STATUS_RXFLOW)
5821 - state->pause |= MLO_PAUSE_RX;
5822 - if (reg & QCA8K_PORT_STATUS_TXFLOW)
5823 - state->pause |= MLO_PAUSE_TX;
5824 -
5825 - return 1;
5826 -}
5827 -
5828 -static void
5829 -qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
5830 - phy_interface_t interface)
5831 -{
5832 - struct qca8k_priv *priv = ds->priv;
5833 -
5834 - qca8k_port_set_status(priv, port, 0);
5835 -}
5836 -
5837 -static void
5838 -qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
5839 - phy_interface_t interface, struct phy_device *phydev,
5840 - int speed, int duplex, bool tx_pause, bool rx_pause)
5841 -{
5842 - struct qca8k_priv *priv = ds->priv;
5843 - u32 reg;
5844 -
5845 - if (phylink_autoneg_inband(mode)) {
5846 - reg = QCA8K_PORT_STATUS_LINK_AUTO;
5847 - } else {
5848 - switch (speed) {
5849 - case SPEED_10:
5850 - reg = QCA8K_PORT_STATUS_SPEED_10;
5851 - break;
5852 - case SPEED_100:
5853 - reg = QCA8K_PORT_STATUS_SPEED_100;
5854 - break;
5855 - case SPEED_1000:
5856 - reg = QCA8K_PORT_STATUS_SPEED_1000;
5857 - break;
5858 - default:
5859 - reg = QCA8K_PORT_STATUS_LINK_AUTO;
5860 - break;
5861 - }
5862 -
5863 - if (duplex == DUPLEX_FULL)
5864 - reg |= QCA8K_PORT_STATUS_DUPLEX;
5865 -
5866 - if (rx_pause || dsa_is_cpu_port(ds, port))
5867 - reg |= QCA8K_PORT_STATUS_RXFLOW;
5868 -
5869 - if (tx_pause || dsa_is_cpu_port(ds, port))
5870 - reg |= QCA8K_PORT_STATUS_TXFLOW;
5871 - }
5872 -
5873 - reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
5874 -
5875 - qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
5876 -}
5877 -
5878 -static void
5879 -qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)
5880 -{
5881 - const struct qca8k_match_data *match_data;
5882 - struct qca8k_priv *priv = ds->priv;
5883 - int i;
5884 -
5885 - if (stringset != ETH_SS_STATS)
5886 - return;
5887 -
5888 - match_data = of_device_get_match_data(priv->dev);
5889 -
5890 - for (i = 0; i < match_data->mib_count; i++)
5891 - strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
5892 - ETH_GSTRING_LEN);
5893 -}
5894 -
5895 -static void qca8k_mib_autocast_handler(struct dsa_switch *ds, struct sk_buff *skb)
5896 -{
5897 - const struct qca8k_match_data *match_data;
5898 - struct qca8k_mib_eth_data *mib_eth_data;
5899 - struct qca8k_priv *priv = ds->priv;
5900 - const struct qca8k_mib_desc *mib;
5901 - struct mib_ethhdr *mib_ethhdr;
5902 - int i, mib_len, offset = 0;
5903 - u64 *data;
5904 - u8 port;
5905 -
5906 - mib_ethhdr = (struct mib_ethhdr *)skb_mac_header(skb);
5907 - mib_eth_data = &priv->mib_eth_data;
5908 -
5909 - /* The switch autocast every port. Ignore other packet and
5910 - * parse only the requested one.
5911 - */
5912 - port = FIELD_GET(QCA_HDR_RECV_SOURCE_PORT, ntohs(mib_ethhdr->hdr));
5913 - if (port != mib_eth_data->req_port)
5914 - goto exit;
5915 -
5916 - match_data = device_get_match_data(priv->dev);
5917 - data = mib_eth_data->data;
5918 -
5919 - for (i = 0; i < match_data->mib_count; i++) {
5920 - mib = &ar8327_mib[i];
5921 -
5922 - /* First 3 mib are present in the skb head */
5923 - if (i < 3) {
5924 - data[i] = mib_ethhdr->data[i];
5925 - continue;
5926 - }
5927 -
5928 - mib_len = sizeof(uint32_t);
5929 -
5930 - /* Some mib are 64 bit wide */
5931 - if (mib->size == 2)
5932 - mib_len = sizeof(uint64_t);
5933 -
5934 - /* Copy the mib value from packet to the */
5935 - memcpy(data + i, skb->data + offset, mib_len);
5936 -
5937 - /* Set the offset for the next mib */
5938 - offset += mib_len;
5939 - }
5940 -
5941 -exit:
5942 - /* Complete on receiving all the mib packet */
5943 - if (refcount_dec_and_test(&mib_eth_data->port_parsed))
5944 - complete(&mib_eth_data->rw_done);
5945 -}
5946 -
5947 -static int
5948 -qca8k_get_ethtool_stats_eth(struct dsa_switch *ds, int port, u64 *data)
5949 -{
5950 - struct dsa_port *dp = dsa_to_port(ds, port);
5951 - struct qca8k_mib_eth_data *mib_eth_data;
5952 - struct qca8k_priv *priv = ds->priv;
5953 - int ret;
5954 -
5955 - mib_eth_data = &priv->mib_eth_data;
5956 -
5957 - mutex_lock(&mib_eth_data->mutex);
5958 -
5959 - reinit_completion(&mib_eth_data->rw_done);
5960 -
5961 - mib_eth_data->req_port = dp->index;
5962 - mib_eth_data->data = data;
5963 - refcount_set(&mib_eth_data->port_parsed, QCA8K_NUM_PORTS);
5964 -
5965 - mutex_lock(&priv->reg_mutex);
5966 -
5967 - /* Send mib autocast request */
5968 - ret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB,
5969 - QCA8K_MIB_FUNC | QCA8K_MIB_BUSY,
5970 - FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_CAST) |
5971 - QCA8K_MIB_BUSY);
5972 -
5973 - mutex_unlock(&priv->reg_mutex);
5974 -
5975 - if (ret)
5976 - goto exit;
5977 -
5978 - ret = wait_for_completion_timeout(&mib_eth_data->rw_done, QCA8K_ETHERNET_TIMEOUT);
5979 -
5980 -exit:
5981 - mutex_unlock(&mib_eth_data->mutex);
5982 -
5983 - return ret;
5984 -}
5985 -
5986 -static void
5987 -qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
5988 - uint64_t *data)
5989 -{
5990 - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
5991 - const struct qca8k_match_data *match_data;
5992 - const struct qca8k_mib_desc *mib;
5993 - u32 reg, i, val;
5994 - u32 hi = 0;
5995 - int ret;
5996 -
5997 - if (priv->mgmt_master &&
5998 - qca8k_get_ethtool_stats_eth(ds, port, data) > 0)
5999 - return;
6000 -
6001 - match_data = of_device_get_match_data(priv->dev);
6002 -
6003 - for (i = 0; i < match_data->mib_count; i++) {
6004 - mib = &ar8327_mib[i];
6005 - reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
6006 -
6007 - ret = qca8k_read(priv, reg, &val);
6008 - if (ret < 0)
6009 - continue;
6010 -
6011 - if (mib->size == 2) {
6012 - ret = qca8k_read(priv, reg + 4, &hi);
6013 - if (ret < 0)
6014 - continue;
6015 - }
6016 -
6017 - data[i] = val;
6018 - if (mib->size == 2)
6019 - data[i] |= (u64)hi << 32;
6020 - }
6021 -}
6022 -
6023 -static int
6024 -qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
6025 -{
6026 - const struct qca8k_match_data *match_data;
6027 - struct qca8k_priv *priv = ds->priv;
6028 -
6029 - if (sset != ETH_SS_STATS)
6030 - return 0;
6031 -
6032 - match_data = of_device_get_match_data(priv->dev);
6033 -
6034 - return match_data->mib_count;
6035 -}
6036 -
6037 -static int
6038 -qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
6039 -{
6040 - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
6041 - u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
6042 - u32 reg;
6043 - int ret;
6044 -
6045 - mutex_lock(&priv->reg_mutex);
6046 - ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, &reg);
6047 - if (ret < 0)
6048 - goto exit;
6049 -
6050 - if (eee->eee_enabled)
6051 - reg |= lpi_en;
6052 - else
6053 - reg &= ~lpi_en;
6054 - ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
6055 -
6056 -exit:
6057 - mutex_unlock(&priv->reg_mutex);
6058 - return ret;
6059 -}
6060 -
6061 -static int
6062 -qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
6063 -{
6064 - /* Nothing to do on the port's MAC */
6065 - return 0;
6066 -}
6067 -
6068 -static void
6069 -qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
6070 -{
6071 - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
6072 - u32 stp_state;
6073 -
6074 - switch (state) {
6075 - case BR_STATE_DISABLED:
6076 - stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
6077 - break;
6078 - case BR_STATE_BLOCKING:
6079 - stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
6080 - break;
6081 - case BR_STATE_LISTENING:
6082 - stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
6083 - break;
6084 - case BR_STATE_LEARNING:
6085 - stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
6086 - break;
6087 - case BR_STATE_FORWARDING:
6088 - default:
6089 - stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
6090 - break;
6091 - }
6092 -
6093 - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
6094 - QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
6095 -}
6096 -
6097 -static int
6098 -qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
6099 -{
6100 - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
6101 - int port_mask, cpu_port;
6102 - int i, ret;
6103 -
6104 - cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
6105 - port_mask = BIT(cpu_port);
6106 -
6107 - for (i = 0; i < QCA8K_NUM_PORTS; i++) {
6108 - if (dsa_is_cpu_port(ds, i))
6109 - continue;
6110 - if (dsa_to_port(ds, i)->bridge_dev != br)
6111 - continue;
6112 - /* Add this port to the portvlan mask of the other ports
6113 - * in the bridge
6114 - */
6115 - ret = regmap_set_bits(priv->regmap,
6116 - QCA8K_PORT_LOOKUP_CTRL(i),
6117 - BIT(port));
6118 - if (ret)
6119 - return ret;
6120 - if (i != port)
6121 - port_mask |= BIT(i);
6122 - }
6123 -
6124 - /* Add all other ports to this ports portvlan mask */
6125 - ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
6126 - QCA8K_PORT_LOOKUP_MEMBER, port_mask);
6127 -
6128 - return ret;
6129 -}
6130 -
6131 -static void
6132 -qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
6133 -{
6134 - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
6135 - int cpu_port, i;
6136 -
6137 - cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
6138 -
6139 - for (i = 0; i < QCA8K_NUM_PORTS; i++) {
6140 - if (dsa_is_cpu_port(ds, i))
6141 - continue;
6142 - if (dsa_to_port(ds, i)->bridge_dev != br)
6143 - continue;
6144 - /* Remove this port to the portvlan mask of the other ports
6145 - * in the bridge
6146 - */
6147 - regmap_clear_bits(priv->regmap,
6148 - QCA8K_PORT_LOOKUP_CTRL(i),
6149 - BIT(port));
6150 - }
6151 -
6152 - /* Set the cpu port to be the only one in the portvlan mask of
6153 - * this port
6154 - */
6155 - qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
6156 - QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port));
6157 -}
6158 -
6159 -static void
6160 -qca8k_port_fast_age(struct dsa_switch *ds, int port)
6161 -{
6162 - struct qca8k_priv *priv = ds->priv;
6163 -
6164 - mutex_lock(&priv->reg_mutex);
6165 - qca8k_fdb_access(priv, QCA8K_FDB_FLUSH_PORT, port);
6166 - mutex_unlock(&priv->reg_mutex);
6167 -}
6168 -
6169 -static int
6170 -qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
6171 -{
6172 - struct qca8k_priv *priv = ds->priv;
6173 - unsigned int secs = msecs / 1000;
6174 - u32 val;
6175 -
6176 - /* AGE_TIME reg is set in 7s step */
6177 - val = secs / 7;
6178 -
6179 - /* Handle case with 0 as val to NOT disable
6180 - * learning
6181 - */
6182 - if (!val)
6183 - val = 1;
6184 -
6185 - return regmap_update_bits(priv->regmap, QCA8K_REG_ATU_CTRL, QCA8K_ATU_AGE_TIME_MASK,
6186 - QCA8K_ATU_AGE_TIME(val));
6187 -}
6188 -
6189 -static int
6190 -qca8k_port_enable(struct dsa_switch *ds, int port,
6191 - struct phy_device *phy)
6192 -{
6193 - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
6194 -
6195 - qca8k_port_set_status(priv, port, 1);
6196 - priv->port_enabled_map |= BIT(port);
6197 -
6198 - if (dsa_is_user_port(ds, port))
6199 - phy_support_asym_pause(phy);
6200 -
6201 - return 0;
6202 -}
6203 -
6204 -static void
6205 -qca8k_port_disable(struct dsa_switch *ds, int port)
6206 -{
6207 - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
6208 -
6209 - qca8k_port_set_status(priv, port, 0);
6210 - priv->port_enabled_map &= ~BIT(port);
6211 -}
6212 -
6213 -static int
6214 -qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
6215 -{
6216 - struct qca8k_priv *priv = ds->priv;
6217 - int ret;
6218 -
6219 - /* We have only have a general MTU setting.
6220 - * DSA always set the CPU port's MTU to the largest MTU of the slave
6221 - * ports.
6222 - * Setting MTU just for the CPU port is sufficient to correctly set a
6223 - * value for every port.
6224 - */
6225 - if (!dsa_is_cpu_port(ds, port))
6226 - return 0;
6227 -
6228 - /* To change the MAX_FRAME_SIZE the cpu ports must be off or
6229 - * the switch panics.
6230 - * Turn off both cpu ports before applying the new value to prevent
6231 - * this.
6232 - */
6233 - if (priv->port_enabled_map & BIT(0))
6234 - qca8k_port_set_status(priv, 0, 0);
6235 -
6236 - if (priv->port_enabled_map & BIT(6))
6237 - qca8k_port_set_status(priv, 6, 0);
6238 -
6239 - /* Include L2 header / FCS length */
6240 - ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, new_mtu + ETH_HLEN + ETH_FCS_LEN);
6241 -
6242 - if (priv->port_enabled_map & BIT(0))
6243 - qca8k_port_set_status(priv, 0, 1);
6244 -
6245 - if (priv->port_enabled_map & BIT(6))
6246 - qca8k_port_set_status(priv, 6, 1);
6247 -
6248 - return ret;
6249 -}
6250 -
6251 -static int
6252 -qca8k_port_max_mtu(struct dsa_switch *ds, int port)
6253 -{
6254 - return QCA8K_MAX_MTU;
6255 -}
6256 -
6257 -static int
6258 -qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
6259 - u16 port_mask, u16 vid)
6260 -{
6261 - /* Set the vid to the port vlan id if no vid is set */
6262 - if (!vid)
6263 - vid = QCA8K_PORT_VID_DEF;
6264 -
6265 - return qca8k_fdb_add(priv, addr, port_mask, vid,
6266 - QCA8K_ATU_STATUS_STATIC);
6267 -}
6268 -
6269 -static int
6270 -qca8k_port_fdb_add(struct dsa_switch *ds, int port,
6271 - const unsigned char *addr, u16 vid)
6272 -{
6273 - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
6274 - u16 port_mask = BIT(port);
6275 -
6276 - return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
6277 -}
6278 -
6279 -static int
6280 -qca8k_port_fdb_del(struct dsa_switch *ds, int port,
6281 - const unsigned char *addr, u16 vid)
6282 -{
6283 - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
6284 - u16 port_mask = BIT(port);
6285 -
6286 - if (!vid)
6287 - vid = QCA8K_PORT_VID_DEF;
6288 -
6289 - return qca8k_fdb_del(priv, addr, port_mask, vid);
6290 -}
6291 -
6292 -static int
6293 -qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
6294 - dsa_fdb_dump_cb_t *cb, void *data)
6295 -{
6296 - struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
6297 - struct qca8k_fdb _fdb = { 0 };
6298 - int cnt = QCA8K_NUM_FDB_RECORDS;
6299 - bool is_static;
6300 - int ret = 0;
6301 -
6302 - mutex_lock(&priv->reg_mutex);
6303 - while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
6304 - if (!_fdb.aging)
6305 - break;
6306 - is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
6307 - ret = cb(_fdb.mac, _fdb.vid, is_static, data);
6308 - if (ret)
6309 - break;
6310 - }
6311 - mutex_unlock(&priv->reg_mutex);
6312 -
6313 - return 0;
6314 -}
6315 -
6316 -static int
6317 -qca8k_port_mdb_add(struct dsa_switch *ds, int port,
6318 - const struct switchdev_obj_port_mdb *mdb)
6319 -{
6320 - struct qca8k_priv *priv = ds->priv;
6321 - const u8 *addr = mdb->addr;
6322 - u16 vid = mdb->vid;
6323 -
6324 - return qca8k_fdb_search_and_insert(priv, BIT(port), addr, vid);
6325 -}
6326 -
6327 -static int
6328 -qca8k_port_mdb_del(struct dsa_switch *ds, int port,
6329 - const struct switchdev_obj_port_mdb *mdb)
6330 -{
6331 - struct qca8k_priv *priv = ds->priv;
6332 - const u8 *addr = mdb->addr;
6333 - u16 vid = mdb->vid;
6334 -
6335 - return qca8k_fdb_search_and_del(priv, BIT(port), addr, vid);
6336 -}
6337 -
6338 -static int
6339 -qca8k_port_mirror_add(struct dsa_switch *ds, int port,
6340 - struct dsa_mall_mirror_tc_entry *mirror,
6341 - bool ingress)
6342 -{
6343 - struct qca8k_priv *priv = ds->priv;
6344 - int monitor_port, ret;
6345 - u32 reg, val;
6346 -
6347 - /* Check for existent entry */
6348 - if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
6349 - return -EEXIST;
6350 -
6351 - ret = regmap_read(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, &val);
6352 - if (ret)
6353 - return ret;
6354 -
6355 - /* QCA83xx can have only one port set to mirror mode.
6356 - * Check that the correct port is requested and return error otherwise.
6357 - * When no mirror port is set, the values is set to 0xF
6358 - */
6359 - monitor_port = FIELD_GET(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
6360 - if (monitor_port != 0xF && monitor_port != mirror->to_local_port)
6361 - return -EEXIST;
6362 -
6363 - /* Set the monitor port */
6364 - val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM,
6365 - mirror->to_local_port);
6366 - ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
6367 - QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
6368 - if (ret)
6369 - return ret;
6370 -
6371 - if (ingress) {
6372 - reg = QCA8K_PORT_LOOKUP_CTRL(port);
6373 - val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN;
6374 - } else {
6375 - reg = QCA8K_REG_PORT_HOL_CTRL1(port);
6376 - val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN;
6377 - }
6378 -
6379 - ret = regmap_update_bits(priv->regmap, reg, val, val);
6380 - if (ret)
6381 - return ret;
6382 -
6383 - /* Track mirror port for tx and rx to decide when the
6384 - * mirror port has to be disabled.
6385 - */
6386 - if (ingress)
6387 - priv->mirror_rx |= BIT(port);
6388 - else
6389 - priv->mirror_tx |= BIT(port);
6390 -
6391 - return 0;
6392 -}
6393 -
6394 -static void
6395 -qca8k_port_mirror_del(struct dsa_switch *ds, int port,
6396 - struct dsa_mall_mirror_tc_entry *mirror)
6397 -{
6398 - struct qca8k_priv *priv = ds->priv;
6399 - u32 reg, val;
6400 - int ret;
6401 -
6402 - if (mirror->ingress) {
6403 - reg = QCA8K_PORT_LOOKUP_CTRL(port);
6404 - val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN;
6405 - } else {
6406 - reg = QCA8K_REG_PORT_HOL_CTRL1(port);
6407 - val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN;
6408 - }
6409 -
6410 - ret = regmap_clear_bits(priv->regmap, reg, val);
6411 - if (ret)
6412 - goto err;
6413 -
6414 - if (mirror->ingress)
6415 - priv->mirror_rx &= ~BIT(port);
6416 - else
6417 - priv->mirror_tx &= ~BIT(port);
6418 -
6419 - /* No port set to send packet to mirror port. Disable mirror port */
6420 - if (!priv->mirror_rx && !priv->mirror_tx) {
6421 - val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, 0xF);
6422 - ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
6423 - QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
6424 - if (ret)
6425 - goto err;
6426 - }
6427 -err:
6428 - dev_err(priv->dev, "Failed to del mirror port from %d", port);
6429 -}
6430 -
6431 -static int
6432 -qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
6433 - struct netlink_ext_ack *extack)
6434 -{
6435 - struct qca8k_priv *priv = ds->priv;
6436 - int ret;
6437 -
6438 - if (vlan_filtering) {
6439 - ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
6440 - QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,
6441 - QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);
6442 - } else {
6443 - ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
6444 - QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,
6445 - QCA8K_PORT_LOOKUP_VLAN_MODE_NONE);
6446 - }
6447 -
6448 - return ret;
6449 -}
6450 -
6451 -static int
6452 -qca8k_port_vlan_add(struct dsa_switch *ds, int port,
6453 - const struct switchdev_obj_port_vlan *vlan,
6454 - struct netlink_ext_ack *extack)
6455 -{
6456 - bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
6457 - bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
6458 - struct qca8k_priv *priv = ds->priv;
6459 - int ret;
6460 -
6461 - ret = qca8k_vlan_add(priv, port, vlan->vid, untagged);
6462 - if (ret) {
6463 - dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret);
6464 - return ret;
6465 - }
6466 -
6467 - if (pvid) {
6468 - ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
6469 - QCA8K_EGREES_VLAN_PORT_MASK(port),
6470 - QCA8K_EGREES_VLAN_PORT(port, vlan->vid));
6471 - if (ret)
6472 - return ret;
6473 -
6474 - ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
6475 - QCA8K_PORT_VLAN_CVID(vlan->vid) |
6476 - QCA8K_PORT_VLAN_SVID(vlan->vid));
6477 - }
6478 -
6479 - return ret;
6480 -}
6481 -
6482 -static int
6483 -qca8k_port_vlan_del(struct dsa_switch *ds, int port,
6484 - const struct switchdev_obj_port_vlan *vlan)
6485 -{
6486 - struct qca8k_priv *priv = ds->priv;
6487 - int ret;
6488 -
6489 - ret = qca8k_vlan_del(priv, port, vlan->vid);
6490 - if (ret)
6491 - dev_err(priv->dev, "Failed to delete VLAN from port %d (%d)", port, ret);
6492 -
6493 - return ret;
6494 -}
6495 -
6496 -static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port)
6497 -{
6498 - struct qca8k_priv *priv = ds->priv;
6499 -
6500 - /* Communicate to the phy internal driver the switch revision.
6501 - * Based on the switch revision different values needs to be
6502 - * set to the dbg and mmd reg on the phy.
6503 - * The first 2 bit are used to communicate the switch revision
6504 - * to the phy driver.
6505 - */
6506 - if (port > 0 && port < 6)
6507 - return priv->switch_revision;
6508 -
6509 - return 0;
6510 -}
6511 -
6512 -static enum dsa_tag_protocol
6513 -qca8k_get_tag_protocol(struct dsa_switch *ds, int port,
6514 - enum dsa_tag_protocol mp)
6515 -{
6516 - return DSA_TAG_PROTO_QCA;
6517 -}
6518 -
6519 -static bool
6520 -qca8k_lag_can_offload(struct dsa_switch *ds,
6521 - struct net_device *lag,
6522 - struct netdev_lag_upper_info *info)
6523 -{
6524 - struct dsa_port *dp;
6525 - int id, members = 0;
6526 -
6527 - id = dsa_lag_id(ds->dst, lag);
6528 - if (id < 0 || id >= ds->num_lag_ids)
6529 - return false;
6530 -
6531 - dsa_lag_foreach_port(dp, ds->dst, lag)
6532 - /* Includes the port joining the LAG */
6533 - members++;
6534 -
6535 - if (members > QCA8K_NUM_PORTS_FOR_LAG)
6536 - return false;
6537 -
6538 - if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
6539 - return false;
6540 -
6541 - if (info->hash_type != NETDEV_LAG_HASH_L2 &&
6542 - info->hash_type != NETDEV_LAG_HASH_L23)
6543 - return false;
6544 -
6545 - return true;
6546 -}
6547 -
6548 -static int
6549 -qca8k_lag_setup_hash(struct dsa_switch *ds,
6550 - struct net_device *lag,
6551 - struct netdev_lag_upper_info *info)
6552 -{
6553 - struct qca8k_priv *priv = ds->priv;
6554 - bool unique_lag = true;
6555 - u32 hash = 0;
6556 - int i, id;
6557 -
6558 - id = dsa_lag_id(ds->dst, lag);
6559 -
6560 - switch (info->hash_type) {
6561 - case NETDEV_LAG_HASH_L23:
6562 - hash |= QCA8K_TRUNK_HASH_SIP_EN;
6563 - hash |= QCA8K_TRUNK_HASH_DIP_EN;
6564 - fallthrough;
6565 - case NETDEV_LAG_HASH_L2:
6566 - hash |= QCA8K_TRUNK_HASH_SA_EN;
6567 - hash |= QCA8K_TRUNK_HASH_DA_EN;
6568 - break;
6569 - default: /* We should NEVER reach this */
6570 - return -EOPNOTSUPP;
6571 - }
6572 -
6573 - /* Check if we are the unique configured LAG */
6574 - dsa_lags_foreach_id(i, ds->dst)
6575 - if (i != id && dsa_lag_dev(ds->dst, i)) {
6576 - unique_lag = false;
6577 - break;
6578 - }
6579 -
6580 - /* Hash Mode is global. Make sure the same Hash Mode
6581 - * is set to all the 4 possible lag.
6582 - * If we are the unique LAG we can set whatever hash
6583 - * mode we want.
6584 - * To change hash mode it's needed to remove all LAG
6585 - * and change the mode with the latest.
6586 - */
6587 - if (unique_lag) {
6588 - priv->lag_hash_mode = hash;
6589 - } else if (priv->lag_hash_mode != hash) {
6590 - netdev_err(lag, "Error: Mismateched Hash Mode across different lag is not supported\n");
6591 - return -EOPNOTSUPP;
6592 - }
6593 -
6594 - return regmap_update_bits(priv->regmap, QCA8K_TRUNK_HASH_EN_CTRL,
6595 - QCA8K_TRUNK_HASH_MASK, hash);
6596 -}
6597 -
6598 -static int
6599 -qca8k_lag_refresh_portmap(struct dsa_switch *ds, int port,
6600 - struct net_device *lag, bool delete)
6601 -{
6602 - struct qca8k_priv *priv = ds->priv;
6603 - int ret, id, i;
6604 - u32 val;
6605 -
6606 - id = dsa_lag_id(ds->dst, lag);
6607 -
6608 - /* Read current port member */
6609 - ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0, &val);
6610 - if (ret)
6611 - return ret;
6612 -
6613 - /* Shift val to the correct trunk */
6614 - val >>= QCA8K_REG_GOL_TRUNK_SHIFT(id);
6615 - val &= QCA8K_REG_GOL_TRUNK_MEMBER_MASK;
6616 - if (delete)
6617 - val &= ~BIT(port);
6618 - else
6619 - val |= BIT(port);
6620 -
6621 - /* Update port member. With empty portmap disable trunk */
6622 - ret = regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0,
6623 - QCA8K_REG_GOL_TRUNK_MEMBER(id) |
6624 - QCA8K_REG_GOL_TRUNK_EN(id),
6625 - !val << QCA8K_REG_GOL_TRUNK_SHIFT(id) |
6626 - val << QCA8K_REG_GOL_TRUNK_SHIFT(id));
6627 -
6628 - /* Search empty member if adding or port on deleting */
6629 - for (i = 0; i < QCA8K_NUM_PORTS_FOR_LAG; i++) {
6630 - ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id), &val);
6631 - if (ret)
6632 - return ret;
6633 -
6634 - val >>= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i);
6635 - val &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK;
6636 -
6637 - if (delete) {
6638 - /* If port flagged to be disabled assume this member is
6639 - * empty
6640 - */
6641 - if (val != QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK)
6642 - continue;
6643 -
6644 - val &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK;
6645 - if (val != port)
6646 - continue;
6647 - } else {
6648 - /* If port flagged to be enabled assume this member is
6649 - * already set
6650 - */
6651 - if (val == QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK)
6652 - continue;
6653 - }
6654 -
6655 - /* We have found the member to add/remove */
6656 - break;
6657 - }
6658 -
6659 - /* Set port in the correct port mask or disable port if in delete mode */
6660 - return regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id),
6661 - QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(id, i) |
6662 - QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(id, i),
6663 - !delete << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i) |
6664 - port << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i));
6665 -}
6666 -
6667 -static int
6668 -qca8k_port_lag_join(struct dsa_switch *ds, int port,
6669 - struct net_device *lag,
6670 - struct netdev_lag_upper_info *info)
6671 -{
6672 - int ret;
6673 -
6674 - if (!qca8k_lag_can_offload(ds, lag, info))
6675 - return -EOPNOTSUPP;
6676 -
6677 - ret = qca8k_lag_setup_hash(ds, lag, info);
6678 - if (ret)
6679 - return ret;
6680 -
6681 - return qca8k_lag_refresh_portmap(ds, port, lag, false);
6682 -}
6683 -
6684 -static int
6685 -qca8k_port_lag_leave(struct dsa_switch *ds, int port,
6686 - struct net_device *lag)
6687 -{
6688 - return qca8k_lag_refresh_portmap(ds, port, lag, true);
6689 -}
6690 -
6691 -static void
6692 -qca8k_master_change(struct dsa_switch *ds, const struct net_device *master,
6693 - bool operational)
6694 -{
6695 - struct dsa_port *dp = master->dsa_ptr;
6696 - struct qca8k_priv *priv = ds->priv;
6697 -
6698 - /* Ethernet MIB/MDIO is only supported for CPU port 0 */
6699 - if (dp->index != 0)
6700 - return;
6701 -
6702 - mutex_lock(&priv->mgmt_eth_data.mutex);
6703 - mutex_lock(&priv->mib_eth_data.mutex);
6704 -
6705 - priv->mgmt_master = operational ? (struct net_device *)master : NULL;
6706 -
6707 - mutex_unlock(&priv->mib_eth_data.mutex);
6708 - mutex_unlock(&priv->mgmt_eth_data.mutex);
6709 -}
6710 -
6711 -static int qca8k_connect_tag_protocol(struct dsa_switch *ds,
6712 - enum dsa_tag_protocol proto)
6713 -{
6714 - struct qca_tagger_data *tagger_data;
6715 -
6716 - switch (proto) {
6717 - case DSA_TAG_PROTO_QCA:
6718 - tagger_data = ds->tagger_data;
6719 -
6720 - tagger_data->rw_reg_ack_handler = qca8k_rw_reg_ack_handler;
6721 - tagger_data->mib_autocast_handler = qca8k_mib_autocast_handler;
6722 -
6723 - break;
6724 - default:
6725 - return -EOPNOTSUPP;
6726 - }
6727 -
6728 - return 0;
6729 -}
6730 -
6731 -static const struct dsa_switch_ops qca8k_switch_ops = {
6732 - .get_tag_protocol = qca8k_get_tag_protocol,
6733 - .setup = qca8k_setup,
6734 - .get_strings = qca8k_get_strings,
6735 - .get_ethtool_stats = qca8k_get_ethtool_stats,
6736 - .get_sset_count = qca8k_get_sset_count,
6737 - .set_ageing_time = qca8k_set_ageing_time,
6738 - .get_mac_eee = qca8k_get_mac_eee,
6739 - .set_mac_eee = qca8k_set_mac_eee,
6740 - .port_enable = qca8k_port_enable,
6741 - .port_disable = qca8k_port_disable,
6742 - .port_change_mtu = qca8k_port_change_mtu,
6743 - .port_max_mtu = qca8k_port_max_mtu,
6744 - .port_stp_state_set = qca8k_port_stp_state_set,
6745 - .port_bridge_join = qca8k_port_bridge_join,
6746 - .port_bridge_leave = qca8k_port_bridge_leave,
6747 - .port_fast_age = qca8k_port_fast_age,
6748 - .port_fdb_add = qca8k_port_fdb_add,
6749 - .port_fdb_del = qca8k_port_fdb_del,
6750 - .port_fdb_dump = qca8k_port_fdb_dump,
6751 - .port_mdb_add = qca8k_port_mdb_add,
6752 - .port_mdb_del = qca8k_port_mdb_del,
6753 - .port_mirror_add = qca8k_port_mirror_add,
6754 - .port_mirror_del = qca8k_port_mirror_del,
6755 - .port_vlan_filtering = qca8k_port_vlan_filtering,
6756 - .port_vlan_add = qca8k_port_vlan_add,
6757 - .port_vlan_del = qca8k_port_vlan_del,
6758 - .phylink_validate = qca8k_phylink_validate,
6759 - .phylink_mac_link_state = qca8k_phylink_mac_link_state,
6760 - .phylink_mac_config = qca8k_phylink_mac_config,
6761 - .phylink_mac_link_down = qca8k_phylink_mac_link_down,
6762 - .phylink_mac_link_up = qca8k_phylink_mac_link_up,
6763 - .get_phy_flags = qca8k_get_phy_flags,
6764 - .port_lag_join = qca8k_port_lag_join,
6765 - .port_lag_leave = qca8k_port_lag_leave,
6766 - .master_state_change = qca8k_master_change,
6767 - .connect_tag_protocol = qca8k_connect_tag_protocol,
6768 -};
6769 -
6770 -static int qca8k_read_switch_id(struct qca8k_priv *priv)
6771 -{
6772 - const struct qca8k_match_data *data;
6773 - u32 val;
6774 - u8 id;
6775 - int ret;
6776 -
6777 - /* get the switches ID from the compatible */
6778 - data = of_device_get_match_data(priv->dev);
6779 - if (!data)
6780 - return -ENODEV;
6781 -
6782 - ret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, &val);
6783 - if (ret < 0)
6784 - return -ENODEV;
6785 -
6786 - id = QCA8K_MASK_CTRL_DEVICE_ID(val);
6787 - if (id != data->id) {
6788 - dev_err(priv->dev, "Switch id detected %x but expected %x", id, data->id);
6789 - return -ENODEV;
6790 - }
6791 -
6792 - priv->switch_id = id;
6793 -
6794 - /* Save revision to communicate to the internal PHY driver */
6795 - priv->switch_revision = QCA8K_MASK_CTRL_REV_ID(val);
6796 -
6797 - return 0;
6798 -}
6799 -
6800 -static int
6801 -qca8k_sw_probe(struct mdio_device *mdiodev)
6802 -{
6803 - struct qca8k_priv *priv;
6804 - int ret;
6805 -
6806 - /* allocate the private data struct so that we can probe the switches
6807 - * ID register
6808 - */
6809 - priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
6810 - if (!priv)
6811 - return -ENOMEM;
6812 -
6813 - priv->bus = mdiodev->bus;
6814 - priv->dev = &mdiodev->dev;
6815 -
6816 - priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset",
6817 - GPIOD_ASIS);
6818 - if (IS_ERR(priv->reset_gpio))
6819 - return PTR_ERR(priv->reset_gpio);
6820 -
6821 - if (priv->reset_gpio) {
6822 - gpiod_set_value_cansleep(priv->reset_gpio, 1);
6823 - /* The active low duration must be greater than 10 ms
6824 - * and checkpatch.pl wants 20 ms.
6825 - */
6826 - msleep(20);
6827 - gpiod_set_value_cansleep(priv->reset_gpio, 0);
6828 - }
6829 -
6830 - /* Start by setting up the register mapping */
6831 - priv->regmap = devm_regmap_init(&mdiodev->dev, NULL, priv,
6832 - &qca8k_regmap_config);
6833 - if (IS_ERR(priv->regmap)) {
6834 - dev_err(priv->dev, "regmap initialization failed");
6835 - return PTR_ERR(priv->regmap);
6836 - }
6837 -
6838 - priv->mdio_cache.page = 0xffff;
6839 - priv->mdio_cache.lo = 0xffff;
6840 - priv->mdio_cache.hi = 0xffff;
6841 -
6842 - /* Check the detected switch id */
6843 - ret = qca8k_read_switch_id(priv);
6844 - if (ret)
6845 - return ret;
6846 -
6847 - priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
6848 - if (!priv->ds)
6849 - return -ENOMEM;
6850 -
6851 - mutex_init(&priv->mgmt_eth_data.mutex);
6852 - init_completion(&priv->mgmt_eth_data.rw_done);
6853 -
6854 - mutex_init(&priv->mib_eth_data.mutex);
6855 - init_completion(&priv->mib_eth_data.rw_done);
6856 -
6857 - priv->ds->dev = &mdiodev->dev;
6858 - priv->ds->num_ports = QCA8K_NUM_PORTS;
6859 - priv->ds->priv = priv;
6860 - priv->ds->ops = &qca8k_switch_ops;
6861 - mutex_init(&priv->reg_mutex);
6862 - dev_set_drvdata(&mdiodev->dev, priv);
6863 -
6864 - return dsa_register_switch(priv->ds);
6865 -}
6866 -
6867 -static void
6868 -qca8k_sw_remove(struct mdio_device *mdiodev)
6869 -{
6870 - struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
6871 - int i;
6872 -
6873 - if (!priv)
6874 - return;
6875 -
6876 - for (i = 0; i < QCA8K_NUM_PORTS; i++)
6877 - qca8k_port_set_status(priv, i, 0);
6878 -
6879 - dsa_unregister_switch(priv->ds);
6880 -
6881 - dev_set_drvdata(&mdiodev->dev, NULL);
6882 -}
6883 -
6884 -static void qca8k_sw_shutdown(struct mdio_device *mdiodev)
6885 -{
6886 - struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
6887 -
6888 - if (!priv)
6889 - return;
6890 -
6891 - dsa_switch_shutdown(priv->ds);
6892 -
6893 - dev_set_drvdata(&mdiodev->dev, NULL);
6894 -}
6895 -
6896 -#ifdef CONFIG_PM_SLEEP
6897 -static void
6898 -qca8k_set_pm(struct qca8k_priv *priv, int enable)
6899 -{
6900 - int port;
6901 -
6902 - for (port = 0; port < QCA8K_NUM_PORTS; port++) {
6903 - /* Do not enable on resume if the port was
6904 - * disabled before.
6905 - */
6906 - if (!(priv->port_enabled_map & BIT(port)))
6907 - continue;
6908 -
6909 - qca8k_port_set_status(priv, port, enable);
6910 - }
6911 -}
6912 -
6913 -static int qca8k_suspend(struct device *dev)
6914 -{
6915 - struct qca8k_priv *priv = dev_get_drvdata(dev);
6916 -
6917 - qca8k_set_pm(priv, 0);
6918 -
6919 - return dsa_switch_suspend(priv->ds);
6920 -}
6921 -
6922 -static int qca8k_resume(struct device *dev)
6923 -{
6924 - struct qca8k_priv *priv = dev_get_drvdata(dev);
6925 -
6926 - qca8k_set_pm(priv, 1);
6927 -
6928 - return dsa_switch_resume(priv->ds);
6929 -}
6930 -#endif /* CONFIG_PM_SLEEP */
6931 -
6932 -static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
6933 - qca8k_suspend, qca8k_resume);
6934 -
6935 -static const struct qca8k_match_data qca8327 = {
6936 - .id = QCA8K_ID_QCA8327,
6937 - .reduced_package = true,
6938 - .mib_count = QCA8K_QCA832X_MIB_COUNT,
6939 -};
6940 -
6941 -static const struct qca8k_match_data qca8328 = {
6942 - .id = QCA8K_ID_QCA8327,
6943 - .mib_count = QCA8K_QCA832X_MIB_COUNT,
6944 -};
6945 -
6946 -static const struct qca8k_match_data qca833x = {
6947 - .id = QCA8K_ID_QCA8337,
6948 - .mib_count = QCA8K_QCA833X_MIB_COUNT,
6949 -};
6950 -
6951 -static const struct of_device_id qca8k_of_match[] = {
6952 - { .compatible = "qca,qca8327", .data = &qca8327 },
6953 - { .compatible = "qca,qca8328", .data = &qca8328 },
6954 - { .compatible = "qca,qca8334", .data = &qca833x },
6955 - { .compatible = "qca,qca8337", .data = &qca833x },
6956 - { /* sentinel */ },
6957 -};
6958 -
6959 -static struct mdio_driver qca8kmdio_driver = {
6960 - .probe = qca8k_sw_probe,
6961 - .remove = qca8k_sw_remove,
6962 - .shutdown = qca8k_sw_shutdown,
6963 - .mdiodrv.driver = {
6964 - .name = "qca8k",
6965 - .of_match_table = qca8k_of_match,
6966 - .pm = &qca8k_pm_ops,
6967 - },
6968 -};
6969 -
6970 -mdio_module_driver(qca8kmdio_driver);
6971 -
6972 -MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
6973 -MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
6974 -MODULE_LICENSE("GPL v2");
6975 -MODULE_ALIAS("platform:qca8k");
6976 --- a/drivers/net/dsa/qca8k.h
6977 +++ /dev/null
6978 @@ -1,411 +0,0 @@
6979 -/* SPDX-License-Identifier: GPL-2.0-only */
6980 -/*
6981 - * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
6982 - * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6983 - * Copyright (c) 2015, The Linux Foundation. All rights reserved.
6984 - */
6985 -
6986 -#ifndef __QCA8K_H
6987 -#define __QCA8K_H
6988 -
6989 -#include <linux/delay.h>
6990 -#include <linux/regmap.h>
6991 -#include <linux/gpio.h>
6992 -#include <linux/dsa/tag_qca.h>
6993 -
6994 -#define QCA8K_ETHERNET_MDIO_PRIORITY 7
6995 -#define QCA8K_ETHERNET_PHY_PRIORITY 6
6996 -#define QCA8K_ETHERNET_TIMEOUT 100
6997 -
6998 -#define QCA8K_NUM_PORTS 7
6999 -#define QCA8K_NUM_CPU_PORTS 2
7000 -#define QCA8K_MAX_MTU 9000
7001 -#define QCA8K_NUM_LAGS 4
7002 -#define QCA8K_NUM_PORTS_FOR_LAG 4
7003 -
7004 -#define PHY_ID_QCA8327 0x004dd034
7005 -#define QCA8K_ID_QCA8327 0x12
7006 -#define PHY_ID_QCA8337 0x004dd036
7007 -#define QCA8K_ID_QCA8337 0x13
7008 -
7009 -#define QCA8K_QCA832X_MIB_COUNT 39
7010 -#define QCA8K_QCA833X_MIB_COUNT 41
7011 -
7012 -#define QCA8K_BUSY_WAIT_TIMEOUT 2000
7013 -
7014 -#define QCA8K_NUM_FDB_RECORDS 2048
7015 -
7016 -#define QCA8K_PORT_VID_DEF 1
7017 -
7018 -/* Global control registers */
7019 -#define QCA8K_REG_MASK_CTRL 0x000
7020 -#define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0)
7021 -#define QCA8K_MASK_CTRL_REV_ID(x) FIELD_GET(QCA8K_MASK_CTRL_REV_ID_MASK, x)
7022 -#define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8)
7023 -#define QCA8K_MASK_CTRL_DEVICE_ID(x) FIELD_GET(QCA8K_MASK_CTRL_DEVICE_ID_MASK, x)
7024 -#define QCA8K_REG_PORT0_PAD_CTRL 0x004
7025 -#define QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN BIT(31)
7026 -#define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE BIT(19)
7027 -#define QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE BIT(18)
7028 -#define QCA8K_REG_PORT5_PAD_CTRL 0x008
7029 -#define QCA8K_REG_PORT6_PAD_CTRL 0x00c
7030 -#define QCA8K_PORT_PAD_RGMII_EN BIT(26)
7031 -#define QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK GENMASK(23, 22)
7032 -#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) FIELD_PREP(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, x)
7033 -#define QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK GENMASK(21, 20)
7034 -#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) FIELD_PREP(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, x)
7035 -#define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25)
7036 -#define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
7037 -#define QCA8K_PORT_PAD_SGMII_EN BIT(7)
7038 -#define QCA8K_REG_PWS 0x010
7039 -#define QCA8K_PWS_POWER_ON_SEL BIT(31)
7040 -/* This reg is only valid for QCA832x and toggle the package
7041 - * type from 176 pin (by default) to 148 pin used on QCA8327
7042 - */
7043 -#define QCA8327_PWS_PACKAGE148_EN BIT(30)
7044 -#define QCA8K_PWS_LED_OPEN_EN_CSR BIT(24)
7045 -#define QCA8K_PWS_SERDES_AEN_DIS BIT(7)
7046 -#define QCA8K_REG_MODULE_EN 0x030
7047 -#define QCA8K_MODULE_EN_MIB BIT(0)
7048 -#define QCA8K_REG_MIB 0x034
7049 -#define QCA8K_MIB_FUNC GENMASK(26, 24)
7050 -#define QCA8K_MIB_CPU_KEEP BIT(20)
7051 -#define QCA8K_MIB_BUSY BIT(17)
7052 -#define QCA8K_MDIO_MASTER_CTRL 0x3c
7053 -#define QCA8K_MDIO_MASTER_BUSY BIT(31)
7054 -#define QCA8K_MDIO_MASTER_EN BIT(30)
7055 -#define QCA8K_MDIO_MASTER_READ BIT(27)
7056 -#define QCA8K_MDIO_MASTER_WRITE 0
7057 -#define QCA8K_MDIO_MASTER_SUP_PRE BIT(26)
7058 -#define QCA8K_MDIO_MASTER_PHY_ADDR_MASK GENMASK(25, 21)
7059 -#define QCA8K_MDIO_MASTER_PHY_ADDR(x) FIELD_PREP(QCA8K_MDIO_MASTER_PHY_ADDR_MASK, x)
7060 -#define QCA8K_MDIO_MASTER_REG_ADDR_MASK GENMASK(20, 16)
7061 -#define QCA8K_MDIO_MASTER_REG_ADDR(x) FIELD_PREP(QCA8K_MDIO_MASTER_REG_ADDR_MASK, x)
7062 -#define QCA8K_MDIO_MASTER_DATA_MASK GENMASK(15, 0)
7063 -#define QCA8K_MDIO_MASTER_DATA(x) FIELD_PREP(QCA8K_MDIO_MASTER_DATA_MASK, x)
7064 -#define QCA8K_MDIO_MASTER_MAX_PORTS 5
7065 -#define QCA8K_MDIO_MASTER_MAX_REG 32
7066 -#define QCA8K_GOL_MAC_ADDR0 0x60
7067 -#define QCA8K_GOL_MAC_ADDR1 0x64
7068 -#define QCA8K_MAX_FRAME_SIZE 0x78
7069 -#define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
7070 -#define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0)
7071 -#define QCA8K_PORT_STATUS_SPEED_10 0
7072 -#define QCA8K_PORT_STATUS_SPEED_100 0x1
7073 -#define QCA8K_PORT_STATUS_SPEED_1000 0x2
7074 -#define QCA8K_PORT_STATUS_TXMAC BIT(2)
7075 -#define QCA8K_PORT_STATUS_RXMAC BIT(3)
7076 -#define QCA8K_PORT_STATUS_TXFLOW BIT(4)
7077 -#define QCA8K_PORT_STATUS_RXFLOW BIT(5)
7078 -#define QCA8K_PORT_STATUS_DUPLEX BIT(6)
7079 -#define QCA8K_PORT_STATUS_LINK_UP BIT(8)
7080 -#define QCA8K_PORT_STATUS_LINK_AUTO BIT(9)
7081 -#define QCA8K_PORT_STATUS_LINK_PAUSE BIT(10)
7082 -#define QCA8K_PORT_STATUS_FLOW_AUTO BIT(12)
7083 -#define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4))
7084 -#define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2)
7085 -#define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)
7086 -#define QCA8K_PORT_HDR_CTRL_ALL 2
7087 -#define QCA8K_PORT_HDR_CTRL_MGMT 1
7088 -#define QCA8K_PORT_HDR_CTRL_NONE 0
7089 -#define QCA8K_REG_SGMII_CTRL 0x0e0
7090 -#define QCA8K_SGMII_EN_PLL BIT(1)
7091 -#define QCA8K_SGMII_EN_RX BIT(2)
7092 -#define QCA8K_SGMII_EN_TX BIT(3)
7093 -#define QCA8K_SGMII_EN_SD BIT(4)
7094 -#define QCA8K_SGMII_CLK125M_DELAY BIT(7)
7095 -#define QCA8K_SGMII_MODE_CTRL_MASK GENMASK(23, 22)
7096 -#define QCA8K_SGMII_MODE_CTRL(x) FIELD_PREP(QCA8K_SGMII_MODE_CTRL_MASK, x)
7097 -#define QCA8K_SGMII_MODE_CTRL_BASEX QCA8K_SGMII_MODE_CTRL(0x0)
7098 -#define QCA8K_SGMII_MODE_CTRL_PHY QCA8K_SGMII_MODE_CTRL(0x1)
7099 -#define QCA8K_SGMII_MODE_CTRL_MAC QCA8K_SGMII_MODE_CTRL(0x2)
7100 -
7101 -/* MAC_PWR_SEL registers */
7102 -#define QCA8K_REG_MAC_PWR_SEL 0x0e4
7103 -#define QCA8K_MAC_PWR_RGMII1_1_8V BIT(18)
7104 -#define QCA8K_MAC_PWR_RGMII0_1_8V BIT(19)
7105 -
7106 -/* EEE control registers */
7107 -#define QCA8K_REG_EEE_CTRL 0x100
7108 -#define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2)
7109 -
7110 -/* TRUNK_HASH_EN registers */
7111 -#define QCA8K_TRUNK_HASH_EN_CTRL 0x270
7112 -#define QCA8K_TRUNK_HASH_SIP_EN BIT(3)
7113 -#define QCA8K_TRUNK_HASH_DIP_EN BIT(2)
7114 -#define QCA8K_TRUNK_HASH_SA_EN BIT(1)
7115 -#define QCA8K_TRUNK_HASH_DA_EN BIT(0)
7116 -#define QCA8K_TRUNK_HASH_MASK GENMASK(3, 0)
7117 -
7118 -/* ACL registers */
7119 -#define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8))
7120 -#define QCA8K_PORT_VLAN_CVID_MASK GENMASK(27, 16)
7121 -#define QCA8K_PORT_VLAN_CVID(x) FIELD_PREP(QCA8K_PORT_VLAN_CVID_MASK, x)
7122 -#define QCA8K_PORT_VLAN_SVID_MASK GENMASK(11, 0)
7123 -#define QCA8K_PORT_VLAN_SVID(x) FIELD_PREP(QCA8K_PORT_VLAN_SVID_MASK, x)
7124 -#define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8))
7125 -#define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470
7126 -#define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474
7127 -
7128 -/* Lookup registers */
7129 -#define QCA8K_REG_ATU_DATA0 0x600
7130 -#define QCA8K_ATU_ADDR2_MASK GENMASK(31, 24)
7131 -#define QCA8K_ATU_ADDR3_MASK GENMASK(23, 16)
7132 -#define QCA8K_ATU_ADDR4_MASK GENMASK(15, 8)
7133 -#define QCA8K_ATU_ADDR5_MASK GENMASK(7, 0)
7134 -#define QCA8K_REG_ATU_DATA1 0x604
7135 -#define QCA8K_ATU_PORT_MASK GENMASK(22, 16)
7136 -#define QCA8K_ATU_ADDR0_MASK GENMASK(15, 8)
7137 -#define QCA8K_ATU_ADDR1_MASK GENMASK(7, 0)
7138 -#define QCA8K_REG_ATU_DATA2 0x608
7139 -#define QCA8K_ATU_VID_MASK GENMASK(19, 8)
7140 -#define QCA8K_ATU_STATUS_MASK GENMASK(3, 0)
7141 -#define QCA8K_ATU_STATUS_STATIC 0xf
7142 -#define QCA8K_REG_ATU_FUNC 0x60c
7143 -#define QCA8K_ATU_FUNC_BUSY BIT(31)
7144 -#define QCA8K_ATU_FUNC_PORT_EN BIT(14)
7145 -#define QCA8K_ATU_FUNC_MULTI_EN BIT(13)
7146 -#define QCA8K_ATU_FUNC_FULL BIT(12)
7147 -#define QCA8K_ATU_FUNC_PORT_MASK GENMASK(11, 8)
7148 -#define QCA8K_REG_VTU_FUNC0 0x610
7149 -#define QCA8K_VTU_FUNC0_VALID BIT(20)
7150 -#define QCA8K_VTU_FUNC0_IVL_EN BIT(19)
7151 -/* QCA8K_VTU_FUNC0_EG_MODE_MASK GENMASK(17, 4)
7152 - * It does contain VLAN_MODE for each port [5:4] for port0,
7153 - * [7:6] for port1 ... [17:16] for port6. Use virtual port
7154 - * define to handle this.
7155 - */
7156 -#define QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i) (4 + (_i) * 2)
7157 -#define QCA8K_VTU_FUNC0_EG_MODE_MASK GENMASK(1, 0)
7158 -#define QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(_i) (GENMASK(1, 0) << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
7159 -#define QCA8K_VTU_FUNC0_EG_MODE_UNMOD FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x0)
7160 -#define QCA8K_VTU_FUNC0_EG_MODE_PORT_UNMOD(_i) (QCA8K_VTU_FUNC0_EG_MODE_UNMOD << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
7161 -#define QCA8K_VTU_FUNC0_EG_MODE_UNTAG FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x1)
7162 -#define QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(_i) (QCA8K_VTU_FUNC0_EG_MODE_UNTAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
7163 -#define QCA8K_VTU_FUNC0_EG_MODE_TAG FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x2)
7164 -#define QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(_i) (QCA8K_VTU_FUNC0_EG_MODE_TAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
7165 -#define QCA8K_VTU_FUNC0_EG_MODE_NOT FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x3)
7166 -#define QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(_i) (QCA8K_VTU_FUNC0_EG_MODE_NOT << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
7167 -#define QCA8K_REG_VTU_FUNC1 0x614
7168 -#define QCA8K_VTU_FUNC1_BUSY BIT(31)
7169 -#define QCA8K_VTU_FUNC1_VID_MASK GENMASK(27, 16)
7170 -#define QCA8K_VTU_FUNC1_FULL BIT(4)
7171 -#define QCA8K_REG_ATU_CTRL 0x618
7172 -#define QCA8K_ATU_AGE_TIME_MASK GENMASK(15, 0)
7173 -#define QCA8K_ATU_AGE_TIME(x) FIELD_PREP(QCA8K_ATU_AGE_TIME_MASK, (x))
7174 -#define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
7175 -#define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
7176 -#define QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM GENMASK(7, 4)
7177 -#define QCA8K_REG_GLOBAL_FW_CTRL1 0x624
7178 -#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK GENMASK(30, 24)
7179 -#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK GENMASK(22, 16)
7180 -#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK GENMASK(14, 8)
7181 -#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK GENMASK(6, 0)
7182 -#define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc)
7183 -#define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0)
7184 -#define QCA8K_PORT_LOOKUP_VLAN_MODE_MASK GENMASK(9, 8)
7185 -#define QCA8K_PORT_LOOKUP_VLAN_MODE(x) FIELD_PREP(QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, x)
7186 -#define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE QCA8K_PORT_LOOKUP_VLAN_MODE(0x0)
7187 -#define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK QCA8K_PORT_LOOKUP_VLAN_MODE(0x1)
7188 -#define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK QCA8K_PORT_LOOKUP_VLAN_MODE(0x2)
7189 -#define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE QCA8K_PORT_LOOKUP_VLAN_MODE(0x3)
7190 -#define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16)
7191 -#define QCA8K_PORT_LOOKUP_STATE(x) FIELD_PREP(QCA8K_PORT_LOOKUP_STATE_MASK, x)
7192 -#define QCA8K_PORT_LOOKUP_STATE_DISABLED QCA8K_PORT_LOOKUP_STATE(0x0)
7193 -#define QCA8K_PORT_LOOKUP_STATE_BLOCKING QCA8K_PORT_LOOKUP_STATE(0x1)
7194 -#define QCA8K_PORT_LOOKUP_STATE_LISTENING QCA8K_PORT_LOOKUP_STATE(0x2)
7195 -#define QCA8K_PORT_LOOKUP_STATE_LEARNING QCA8K_PORT_LOOKUP_STATE(0x3)
7196 -#define QCA8K_PORT_LOOKUP_STATE_FORWARD QCA8K_PORT_LOOKUP_STATE(0x4)
7197 -#define QCA8K_PORT_LOOKUP_LEARN BIT(20)
7198 -#define QCA8K_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
7199 -
7200 -#define QCA8K_REG_GOL_TRUNK_CTRL0 0x700
7201 -/* 4 max trunk first
7202 - * first 6 bit for member bitmap
7203 - * 7th bit is to enable trunk port
7204 - */
7205 -#define QCA8K_REG_GOL_TRUNK_SHIFT(_i) ((_i) * 8)
7206 -#define QCA8K_REG_GOL_TRUNK_EN_MASK BIT(7)
7207 -#define QCA8K_REG_GOL_TRUNK_EN(_i) (QCA8K_REG_GOL_TRUNK_EN_MASK << QCA8K_REG_GOL_TRUNK_SHIFT(_i))
7208 -#define QCA8K_REG_GOL_TRUNK_MEMBER_MASK GENMASK(6, 0)
7209 -#define QCA8K_REG_GOL_TRUNK_MEMBER(_i) (QCA8K_REG_GOL_TRUNK_MEMBER_MASK << QCA8K_REG_GOL_TRUNK_SHIFT(_i))
7210 -/* 0x704 for TRUNK 0-1 --- 0x708 for TRUNK 2-3 */
7211 -#define QCA8K_REG_GOL_TRUNK_CTRL(_i) (0x704 + (((_i) / 2) * 4))
7212 -#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK GENMASK(3, 0)
7213 -#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK BIT(3)
7214 -#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK GENMASK(2, 0)
7215 -#define QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i) (((_i) / 2) * 16)
7216 -#define QCA8K_REG_GOL_MEM_ID_SHIFT(_i) ((_i) * 4)
7217 -/* Complex shift: FIRST shift for port THEN shift for trunk */
7218 -#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j) (QCA8K_REG_GOL_MEM_ID_SHIFT(_j) + QCA8K_REG_GOL_TRUNK_ID_SHIFT(_i))
7219 -#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(_i, _j) (QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j))
7220 -#define QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(_i, _j) (QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(_i, _j))
7221 -
7222 -#define QCA8K_REG_GLOBAL_FC_THRESH 0x800
7223 -#define QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK GENMASK(24, 16)
7224 -#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK, x)
7225 -#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK GENMASK(8, 0)
7226 -#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK, x)
7227 -
7228 -#define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8)
7229 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK GENMASK(3, 0)
7230 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK, x)
7231 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK GENMASK(7, 4)
7232 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK, x)
7233 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK GENMASK(11, 8)
7234 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK, x)
7235 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK GENMASK(15, 12)
7236 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK, x)
7237 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK GENMASK(19, 16)
7238 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK, x)
7239 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK GENMASK(23, 20)
7240 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK, x)
7241 -#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK GENMASK(29, 24)
7242 -#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK, x)
7243 -
7244 -#define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
7245 -#define QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK GENMASK(3, 0)
7246 -#define QCA8K_PORT_HOL_CTRL1_ING(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK, x)
7247 -#define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6)
7248 -#define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7)
7249 -#define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8)
7250 -#define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
7251 -
7252 -/* Pkt edit registers */
7253 -#define QCA8K_EGREES_VLAN_PORT_SHIFT(_i) (16 * ((_i) % 2))
7254 -#define QCA8K_EGREES_VLAN_PORT_MASK(_i) (GENMASK(11, 0) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
7255 -#define QCA8K_EGREES_VLAN_PORT(_i, x) ((x) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
7256 -#define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2)))
7257 -
7258 -/* L3 registers */
7259 -#define QCA8K_HROUTER_CONTROL 0xe00
7260 -#define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M GENMASK(17, 16)
7261 -#define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S 16
7262 -#define QCA8K_HROUTER_CONTROL_ARP_AGE_MODE 1
7263 -#define QCA8K_HROUTER_PBASED_CONTROL1 0xe08
7264 -#define QCA8K_HROUTER_PBASED_CONTROL2 0xe0c
7265 -#define QCA8K_HNAT_CONTROL 0xe38
7266 -
7267 -/* MIB registers */
7268 -#define QCA8K_PORT_MIB_COUNTER(_i) (0x1000 + (_i) * 0x100)
7269 -
7270 -/* QCA specific MII registers */
7271 -#define MII_ATH_MMD_ADDR 0x0d
7272 -#define MII_ATH_MMD_DATA 0x0e
7273 -
7274 -enum {
7275 - QCA8K_PORT_SPEED_10M = 0,
7276 - QCA8K_PORT_SPEED_100M = 1,
7277 - QCA8K_PORT_SPEED_1000M = 2,
7278 - QCA8K_PORT_SPEED_ERR = 3,
7279 -};
7280 -
7281 -enum qca8k_fdb_cmd {
7282 - QCA8K_FDB_FLUSH = 1,
7283 - QCA8K_FDB_LOAD = 2,
7284 - QCA8K_FDB_PURGE = 3,
7285 - QCA8K_FDB_FLUSH_PORT = 5,
7286 - QCA8K_FDB_NEXT = 6,
7287 - QCA8K_FDB_SEARCH = 7,
7288 -};
7289 -
7290 -enum qca8k_vlan_cmd {
7291 - QCA8K_VLAN_FLUSH = 1,
7292 - QCA8K_VLAN_LOAD = 2,
7293 - QCA8K_VLAN_PURGE = 3,
7294 - QCA8K_VLAN_REMOVE_PORT = 4,
7295 - QCA8K_VLAN_NEXT = 5,
7296 - QCA8K_VLAN_READ = 6,
7297 -};
7298 -
7299 -enum qca8k_mid_cmd {
7300 - QCA8K_MIB_FLUSH = 1,
7301 - QCA8K_MIB_FLUSH_PORT = 2,
7302 - QCA8K_MIB_CAST = 3,
7303 -};
7304 -
7305 -struct qca8k_match_data {
7306 - u8 id;
7307 - bool reduced_package;
7308 - u8 mib_count;
7309 -};
7310 -
7311 -enum {
7312 - QCA8K_CPU_PORT0,
7313 - QCA8K_CPU_PORT6,
7314 -};
7315 -
7316 -struct qca8k_mgmt_eth_data {
7317 - struct completion rw_done;
7318 - struct mutex mutex; /* Enforce one mdio read/write at time */
7319 - bool ack;
7320 - u32 seq;
7321 - u32 data[4];
7322 -};
7323 -
7324 -struct qca8k_mib_eth_data {
7325 - struct completion rw_done;
7326 - struct mutex mutex; /* Process one command at time */
7327 - refcount_t port_parsed; /* Counter to track parsed port */
7328 - u8 req_port;
7329 - u64 *data; /* pointer to ethtool data */
7330 -};
7331 -
7332 -struct qca8k_ports_config {
7333 - bool sgmii_rx_clk_falling_edge;
7334 - bool sgmii_tx_clk_falling_edge;
7335 - bool sgmii_enable_pll;
7336 - u8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
7337 - u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
7338 -};
7339 -
7340 -struct qca8k_mdio_cache {
7341 -/* The 32bit switch registers are accessed indirectly. To achieve this we need
7342 - * to set the page of the register. Track the last page that was set to reduce
7343 - * mdio writes
7344 - */
7345 - u16 page;
7346 -/* lo and hi can also be cached and from Documentation we can skip one
7347 - * extra mdio write if lo or hi is didn't change.
7348 - */
7349 - u16 lo;
7350 - u16 hi;
7351 -};
7352 -
7353 -struct qca8k_priv {
7354 - u8 switch_id;
7355 - u8 switch_revision;
7356 - u8 mirror_rx;
7357 - u8 mirror_tx;
7358 - u8 lag_hash_mode;
7359 - /* Each bit correspond to a port. This switch can support a max of 7 port.
7360 - * Bit 1: port enabled. Bit 0: port disabled.
7361 - */
7362 - u8 port_enabled_map;
7363 - struct qca8k_ports_config ports_config;
7364 - struct regmap *regmap;
7365 - struct mii_bus *bus;
7366 - struct dsa_switch *ds;
7367 - struct mutex reg_mutex;
7368 - struct device *dev;
7369 - struct gpio_desc *reset_gpio;
7370 - struct net_device *mgmt_master; /* Track if mdio/mib Ethernet is available */
7371 - struct qca8k_mgmt_eth_data mgmt_eth_data;
7372 - struct qca8k_mib_eth_data mib_eth_data;
7373 - struct qca8k_mdio_cache mdio_cache;
7374 -};
7375 -
7376 -struct qca8k_mib_desc {
7377 - unsigned int size;
7378 - unsigned int offset;
7379 - const char *name;
7380 -};
7381 -
7382 -struct qca8k_fdb {
7383 - u16 vid;
7384 - u8 port_mask;
7385 - u8 aging;
7386 - u8 mac[6];
7387 -};
7388 -
7389 -#endif /* __QCA8K_H */
OpenWrt Source Repository