target/linux/generic/backport-5.15/736-v6.1-0002-net-phy-aquantia-Add-support-for-rate-matching.patch

   1 From 3c42563b30417afc8855a3b4c1b38c2f36f78657 Mon Sep 17 00:00:00 2001
   2 From: Sean Anderson <sean.anderson@seco.com>
   3 Date: Tue, 20 Sep 2022 18:12:35 -0400
   4 Subject: [PATCH] net: phy: aquantia: Add support for rate matching
   5
   6 This adds support for rate matching for phys similar to the AQR107. We
   7 assume that all phys using aqr107_read_status support rate matching.
   8 However, it could be possible to determine support based on the firmware
   9 revision if there are phys discovered which do not support rate
  10 matching.  However, as rate matching is advertised in the datasheets for
  11 these phys, I suspect it is supported most boards.
  12
  13 Despite the name, the "config" registers are updated with the current
  14 rate matching method (if any). Because they appear to be updated
  15 automatically, I don't know if these registers can be used to disable
  16 rate matching.
  17
  18 Signed-off-by: Sean Anderson <sean.anderson@seco.com>
  19 Signed-off-by: David S. Miller <davem@davemloft.net>
  20 ---
  21  drivers/net/phy/aquantia_main.c | 51 ++++++++++++++++++++++++++++++---
  22  1 file changed, 47 insertions(+), 4 deletions(-)
  23
  24 --- a/drivers/net/phy/aquantia_main.c
  25 +++ b/drivers/net/phy/aquantia_main.c
  26 @@ -97,6 +97,19 @@
  27  #define VEND1_GLOBAL_GEN_STAT2                 0xc831
  28  #define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG      BIT(15)
  29
  30 +/* The following registers all have similar layouts; first the registers... */
  31 +#define VEND1_GLOBAL_CFG_10M                   0x0310
  32 +#define VEND1_GLOBAL_CFG_100M                  0x031b
  33 +#define VEND1_GLOBAL_CFG_1G                    0x031c
  34 +#define VEND1_GLOBAL_CFG_2_5G                  0x031d
  35 +#define VEND1_GLOBAL_CFG_5G                    0x031e
  36 +#define VEND1_GLOBAL_CFG_10G                   0x031f
  37 +/* ...and now the fields */
  38 +#define VEND1_GLOBAL_CFG_RATE_ADAPT            GENMASK(8, 7)
  39 +#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE       0
  40 +#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX                1
  41 +#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE      2
  42 +
  43  #define VEND1_GLOBAL_RSVD_STAT1                        0xc885
  44  #define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID    GENMASK(7, 4)
  45  #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID                GENMASK(3, 0)
  46 @@ -347,40 +360,57 @@ static int aqr_read_status(struct phy_de
  47
  48  static int aqr107_read_rate(struct phy_device *phydev)
  49  {
  50 +       u32 config_reg;
  51         int val;
  52
  53         val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
  54         if (val < 0)
  55                 return val;
  56
  57 +       if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
  58 +               phydev->duplex = DUPLEX_FULL;
  59 +       else
  60 +               phydev->duplex = DUPLEX_HALF;
  61 +
  62         switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
  63         case MDIO_AN_TX_VEND_STATUS1_10BASET:
  64                 phydev->speed = SPEED_10;
  65 +               config_reg = VEND1_GLOBAL_CFG_10M;
  66                 break;
  67         case MDIO_AN_TX_VEND_STATUS1_100BASETX:
  68                 phydev->speed = SPEED_100;
  69 +               config_reg = VEND1_GLOBAL_CFG_100M;
  70                 break;
  71         case MDIO_AN_TX_VEND_STATUS1_1000BASET:
  72                 phydev->speed = SPEED_1000;
  73 +               config_reg = VEND1_GLOBAL_CFG_1G;
  74                 break;
  75         case MDIO_AN_TX_VEND_STATUS1_2500BASET:
  76                 phydev->speed = SPEED_2500;
  77 +               config_reg = VEND1_GLOBAL_CFG_2_5G;
  78                 break;
  79         case MDIO_AN_TX_VEND_STATUS1_5000BASET:
  80                 phydev->speed = SPEED_5000;
  81 +               config_reg = VEND1_GLOBAL_CFG_5G;
  82                 break;
  83         case MDIO_AN_TX_VEND_STATUS1_10GBASET:
  84                 phydev->speed = SPEED_10000;
  85 +               config_reg = VEND1_GLOBAL_CFG_10G;
  86                 break;
  87         default:
  88                 phydev->speed = SPEED_UNKNOWN;
  89 -               break;
  90 +               return 0;
  91         }
  92
  93 -       if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
  94 -               phydev->duplex = DUPLEX_FULL;
  95 +       val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);
  96 +       if (val < 0)
  97 +               return val;
  98 +
  99 +       if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) ==
 100 +           VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)
 101 +               phydev->rate_matching = RATE_MATCH_PAUSE;
 102         else
 103 -               phydev->duplex = DUPLEX_HALF;
 104 +               phydev->rate_matching = RATE_MATCH_NONE;
 105
 106         return 0;
 107  }
 108 @@ -647,6 +677,16 @@ static int aqr107_wait_processor_intensi
 109         return 0;
 110  }
 111
 112 +static int aqr107_get_rate_matching(struct phy_device *phydev,
 113 +                                   phy_interface_t iface)
 114 +{
 115 +       if (iface == PHY_INTERFACE_MODE_10GBASER ||
 116 +           iface == PHY_INTERFACE_MODE_2500BASEX ||
 117 +           iface == PHY_INTERFACE_MODE_NA)
 118 +               return RATE_MATCH_PAUSE;
 119 +       return RATE_MATCH_NONE;
 120 +}
 121 +
 122  static int aqr107_suspend(struct phy_device *phydev)
 123  {
 124         int err;
 125 @@ -720,6 +760,7 @@ static struct phy_driver aqr_driver[] =
 126         PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
 127         .name           = "Aquantia AQR107",
 128         .probe          = aqr107_probe,
 129 +       .get_rate_matching = aqr107_get_rate_matching,
 130         .config_init    = aqr107_config_init,
 131         .config_aneg    = aqr_config_aneg,
 132         .config_intr    = aqr_config_intr,
 133 @@ -738,6 +779,7 @@ static struct phy_driver aqr_driver[] =
 134         PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
 135         .name           = "Aquantia AQCS109",
 136         .probe          = aqr107_probe,
 137 +       .get_rate_matching = aqr107_get_rate_matching,
 138         .config_init    = aqcs109_config_init,
 139         .config_aneg    = aqr_config_aneg,
 140         .config_intr    = aqr_config_intr,
 141 @@ -764,6 +806,7 @@ static struct phy_driver aqr_driver[] =
 142         PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
 143         .name           = "Aquantia AQR113C",
 144         .probe          = aqr107_probe,
 145 +       .get_rate_matching = aqr107_get_rate_matching,
 146         .config_init    = aqr107_config_init,
 147         .config_aneg    = aqr_config_aneg,
 148         .config_intr    = aqr_config_intr,