kernel: backport fixes for realtek r8152
[openwrt/openwrt.git] / target / linux / generic / backport-5.15 / 330-v5.16-01-MIPS-kernel-proc-add-CPU-option-reporting.patch
1 From 626bfa03729959ea9917181fb3d8ffaa1594d02a Mon Sep 17 00:00:00 2001
2 From: Hauke Mehrtens <hauke@hauke-m.de>
3 Date: Wed, 13 Oct 2021 22:40:18 -0700
4 Subject: [PATCH 1/1] MIPS: kernel: proc: add CPU option reporting
5
6 Many MIPS CPUs have optional CPU features which are not activated for
7 all CPU cores. Print the CPU options, which are implemented in the core,
8 in /proc/cpuinfo. This makes it possible to see which features are
9 supported and which are not supported. This should cover all standard
10 MIPS extensions. Before, it only printed information about the main MIPS
11 ASEs.
12
13 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
14
15 Changes from original patch[0]:
16 - Remove cpu_has_6k_cache and cpu_has_8k_cache due to commit 6ce91ba8589a
17 ("MIPS: Remove cpu_has_6k_cache and cpu_has_8k_cache in cpu_cache_init()")
18 - Add new options: mac2008_only, ftlbparex, gsexcex, mmid, mm_sysad,
19 mm_full
20 - Use seq_puts instead of seq_printf as suggested by checkpatch
21 - Minor commit message reword
22
23 [0]: https://lore.kernel.org/linux-mips/20181223225224.23042-1-hauke@hauke-m.de/
24
25 Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
26 Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
27 Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
28 ---
29 arch/mips/kernel/proc.c | 122 ++++++++++++++++++++++++++++++++++++++++
30 1 file changed, 122 insertions(+)
31
32 --- a/arch/mips/kernel/proc.c
33 +++ b/arch/mips/kernel/proc.c
34 @@ -138,6 +138,128 @@ static int show_cpuinfo(struct seq_file
35 seq_printf(m, "micromips kernel\t: %s\n",
36 (read_c0_config3() & MIPS_CONF3_ISA_OE) ? "yes" : "no");
37 }
38 +
39 + seq_puts(m, "Options implemented\t:");
40 + if (cpu_has_tlb)
41 + seq_puts(m, " tlb");
42 + if (cpu_has_ftlb)
43 + seq_puts(m, " ftlb");
44 + if (cpu_has_tlbinv)
45 + seq_puts(m, " tlbinv");
46 + if (cpu_has_segments)
47 + seq_puts(m, " segments");
48 + if (cpu_has_rixiex)
49 + seq_puts(m, " rixiex");
50 + if (cpu_has_ldpte)
51 + seq_puts(m, " ldpte");
52 + if (cpu_has_maar)
53 + seq_puts(m, " maar");
54 + if (cpu_has_rw_llb)
55 + seq_puts(m, " rw_llb");
56 + if (cpu_has_4kex)
57 + seq_puts(m, " 4kex");
58 + if (cpu_has_3k_cache)
59 + seq_puts(m, " 3k_cache");
60 + if (cpu_has_4k_cache)
61 + seq_puts(m, " 4k_cache");
62 + if (cpu_has_tx39_cache)
63 + seq_puts(m, " tx39_cache");
64 + if (cpu_has_octeon_cache)
65 + seq_puts(m, " octeon_cache");
66 + if (cpu_has_fpu)
67 + seq_puts(m, " fpu");
68 + if (cpu_has_32fpr)
69 + seq_puts(m, " 32fpr");
70 + if (cpu_has_cache_cdex_p)
71 + seq_puts(m, " cache_cdex_p");
72 + if (cpu_has_cache_cdex_s)
73 + seq_puts(m, " cache_cdex_s");
74 + if (cpu_has_prefetch)
75 + seq_puts(m, " prefetch");
76 + if (cpu_has_mcheck)
77 + seq_puts(m, " mcheck");
78 + if (cpu_has_ejtag)
79 + seq_puts(m, " ejtag");
80 + if (cpu_has_llsc)
81 + seq_puts(m, " llsc");
82 + if (cpu_has_guestctl0ext)
83 + seq_puts(m, " guestctl0ext");
84 + if (cpu_has_guestctl1)
85 + seq_puts(m, " guestctl1");
86 + if (cpu_has_guestctl2)
87 + seq_puts(m, " guestctl2");
88 + if (cpu_has_guestid)
89 + seq_puts(m, " guestid");
90 + if (cpu_has_drg)
91 + seq_puts(m, " drg");
92 + if (cpu_has_rixi)
93 + seq_puts(m, " rixi");
94 + if (cpu_has_lpa)
95 + seq_puts(m, " lpa");
96 + if (cpu_has_mvh)
97 + seq_puts(m, " mvh");
98 + if (cpu_has_vtag_icache)
99 + seq_puts(m, " vtag_icache");
100 + if (cpu_has_dc_aliases)
101 + seq_puts(m, " dc_aliases");
102 + if (cpu_has_ic_fills_f_dc)
103 + seq_puts(m, " ic_fills_f_dc");
104 + if (cpu_has_pindexed_dcache)
105 + seq_puts(m, " pindexed_dcache");
106 + if (cpu_has_userlocal)
107 + seq_puts(m, " userlocal");
108 + if (cpu_has_nofpuex)
109 + seq_puts(m, " nofpuex");
110 + if (cpu_has_vint)
111 + seq_puts(m, " vint");
112 + if (cpu_has_veic)
113 + seq_puts(m, " veic");
114 + if (cpu_has_inclusive_pcaches)
115 + seq_puts(m, " inclusive_pcaches");
116 + if (cpu_has_perf_cntr_intr_bit)
117 + seq_puts(m, " perf_cntr_intr_bit");
118 + if (cpu_has_ufr)
119 + seq_puts(m, " ufr");
120 + if (cpu_has_fre)
121 + seq_puts(m, " fre");
122 + if (cpu_has_cdmm)
123 + seq_puts(m, " cdmm");
124 + if (cpu_has_small_pages)
125 + seq_puts(m, " small_pages");
126 + if (cpu_has_nan_legacy)
127 + seq_puts(m, " nan_legacy");
128 + if (cpu_has_nan_2008)
129 + seq_puts(m, " nan_2008");
130 + if (cpu_has_ebase_wg)
131 + seq_puts(m, " ebase_wg");
132 + if (cpu_has_badinstr)
133 + seq_puts(m, " badinstr");
134 + if (cpu_has_badinstrp)
135 + seq_puts(m, " badinstrp");
136 + if (cpu_has_contextconfig)
137 + seq_puts(m, " contextconfig");
138 + if (cpu_has_perf)
139 + seq_puts(m, " perf");
140 + if (cpu_has_mac2008_only)
141 + seq_puts(m, " mac2008_only");
142 + if (cpu_has_ftlbparex)
143 + seq_puts(m, " ftlbparex");
144 + if (cpu_has_gsexcex)
145 + seq_puts(m, " gsexcex");
146 + if (cpu_has_shared_ftlb_ram)
147 + seq_puts(m, " shared_ftlb_ram");
148 + if (cpu_has_shared_ftlb_entries)
149 + seq_puts(m, " shared_ftlb_entries");
150 + if (cpu_has_mipsmt_pertccounters)
151 + seq_puts(m, " mipsmt_pertccounters");
152 + if (cpu_has_mmid)
153 + seq_puts(m, " mmid");
154 + if (cpu_has_mm_sysad)
155 + seq_puts(m, " mm_sysad");
156 + if (cpu_has_mm_full)
157 + seq_puts(m, " mm_full");
158 + seq_puts(m, "\n");
159 +
160 seq_printf(m, "shadow register sets\t: %d\n",
161 cpu_data[n].srsets);
162 seq_printf(m, "kscratch registers\t: %d\n",