target/linux/d1/patches-6.1/0107-drm-panel-Add-driver-for-Clockwork-cwd686-panel.patch

   1 From 5bf84a1a0a282a18bf9dd2d752537525aefc2e05 Mon Sep 17 00:00:00 2001
   2 From: Max Fierke <max@maxfierke.com>
   3 Date: Wed, 1 Jun 2022 00:17:48 -0500
   4 Subject: [PATCH 107/117] drm: panel: Add driver for Clockwork cwd686 panel
   5
   6 The Clockwork DevTerm (all models) uses a 6.86" IPS display
   7 of unknown provenance, which uses the Chipone ICNL9707 IC driver.
   8
   9 The display panel I have has two model numbers: TXW686001 and WTL068601G,
  10 but cannot find any manufacturer associated with either, so opting for the
  11 Clockwork model number.
  12
  13 This driver is based on the GPL-licensed driver released by Clockwork,
  14 authored by Pinfan Zhu, with some additional cleanup, rotation support,
  15 and display sleep re-enabling done by me.
  16
  17 Original driver here for reference: https://github.com/clockworkpi/DevTerm/blob/main/Code/patch/armbian_build_a06/patch/kernel-004-panel.patch
  18 Display IC datasheet provided here: https://github.com/clockworkpi/DevTerm/blob/main/Schematics/ICNL9707_Datasheet.pdf
  19
  20 Signed-off-by: Max Fierke <max@maxfierke.com>
  21 Signed-off-by: Samuel Holland <samuel@sholland.org>
  22 ---
  23  drivers/gpu/drm/panel/Kconfig                 |  12 +
  24  drivers/gpu/drm/panel/Makefile                |   1 +
  25  .../gpu/drm/panel/panel-clockwork-cwd686.c    | 456 ++++++++++++++++++
  26  3 files changed, 469 insertions(+)
  27  create mode 100644 drivers/gpu/drm/panel/panel-clockwork-cwd686.c
  28
  29 --- a/drivers/gpu/drm/panel/Kconfig
  30 +++ b/drivers/gpu/drm/panel/Kconfig
  31 @@ -68,6 +68,18 @@ config DRM_PANEL_BOE_TV101WUM_NL6
  32           Say Y here if you want to support for BOE TV101WUM and AUO KD101N80
  33           45NA WUXGA PANEL DSI Video Mode panel
  34
  35 +config DRM_PANEL_CLOCKWORK_CWD686
  36 +       tristate "Clockwork CWD686 panel"
  37 +       depends on OF
  38 +       depends on DRM_MIPI_DSI
  39 +       depends on BACKLIGHT_CLASS_DEVICE
  40 +       help
  41 +         Say Y here if you want to enable support for the Clockwork CWD686
  42 +         ICNL9707-based panel, e.g. as used within the Clockwork DevTerm.
  43 +         The panel has a 480x1280 resolution and uses 24 bit RGB per pixel.
  44 +
  45 +         To compile this driver as a module, choose M here.
  46 +
  47  config DRM_PANEL_DSI_CM
  48         tristate "Generic DSI command mode panels"
  49         depends on OF
  50 --- a/drivers/gpu/drm/panel/Makefile
  51 +++ b/drivers/gpu/drm/panel/Makefile
  52 @@ -5,6 +5,7 @@ obj-$(CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_N
  53  obj-$(CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0) += panel-boe-bf060y8m-aj0.o
  54  obj-$(CONFIG_DRM_PANEL_BOE_HIMAX8279D) += panel-boe-himax8279d.o
  55  obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
  56 +obj-$(CONFIG_DRM_PANEL_CLOCKWORK_CWD686) += panel-clockwork-cwd686.o
  57  obj-$(CONFIG_DRM_PANEL_DSI_CM) += panel-dsi-cm.o
  58  obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
  59  obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
  60 --- /dev/null
  61 +++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
  62 @@ -0,0 +1,456 @@
  63 +// SPDX-License-Identifier: GPL-2.0+
  64 +/*
  65 + * Copyright (c) 2021 Clockwork Tech LLC
  66 + * Copyright (c) 2021-2022 Max Fierke <max@maxfierke.com>
  67 + *
  68 + * Based on Pinfan Zhu's work on panel-cwd686.c for ClockworkPi's 5.10 BSP
  69 + */
  70 +
  71 +#include <drm/drm_modes.h>
  72 +#include <drm/drm_mipi_dsi.h>
  73 +#include <drm/drm_panel.h>
  74 +#include <linux/backlight.h>
  75 +#include <linux/gpio/consumer.h>
  76 +#include <linux/regulator/consumer.h>
  77 +#include <linux/delay.h>
  78 +#include <linux/of_device.h>
  79 +#include <linux/module.h>
  80 +#include <video/mipi_display.h>
  81 +
  82 +struct cwd686 {
  83 +       struct device *dev;
  84 +       struct drm_panel panel;
  85 +       struct regulator *supply;
  86 +       struct gpio_desc *enable_gpio;
  87 +       struct gpio_desc *reset_gpio;
  88 +       struct backlight_device *backlight;
  89 +       enum drm_panel_orientation orientation;
  90 +       bool prepared;
  91 +       bool enabled;
  92 +};
  93 +
  94 +static const struct drm_display_mode default_mode = {
  95 +       .clock = 54465,
  96 +       .hdisplay = 480,
  97 +       .hsync_start = 480 + 150,
  98 +       .hsync_end = 480 + 150 + 24,
  99 +       .htotal = 480 + 150 + 24 + 40,
 100 +       .vdisplay = 1280,
 101 +       .vsync_start = 1280 + 12,
 102 +       .vsync_end = 1280 + 12 + 6,
 103 +       .vtotal = 1280 + 12 + 6 + 10,
 104 +};
 105 +
 106 +static inline struct cwd686 *panel_to_cwd686(struct drm_panel *panel)
 107 +{
 108 +       return container_of(panel, struct cwd686, panel);
 109 +}
 110 +
 111 +#define ICNL9707_DCS(seq...)                              \
 112 +({                                                              \
 113 +       static const u8 d[] = { seq };                          \
 114 +       mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d));        \
 115 +})
 116 +
 117 +#define ICNL9707_CMD_CGOUTL 0xB3
 118 +#define ICNL9707_CMD_CGOUTR 0xB4
 119 +#define ICNL9707_P_CGOUT_VGL 0x00
 120 +#define ICNL9707_P_CGOUT_VGH 0x01
 121 +#define ICNL9707_P_CGOUT_HZ 0x02
 122 +#define ICNL9707_P_CGOUT_GND 0x03
 123 +#define ICNL9707_P_CGOUT_GSP1 0x04
 124 +#define ICNL9707_P_CGOUT_GSP2 0x05
 125 +#define ICNL9707_P_CGOUT_GSP3 0x06
 126 +#define ICNL9707_P_CGOUT_GSP4 0x07
 127 +#define ICNL9707_P_CGOUT_GSP5 0x08
 128 +#define ICNL9707_P_CGOUT_GSP6 0x09
 129 +#define ICNL9707_P_CGOUT_GSP7 0x0A
 130 +#define ICNL9707_P_CGOUT_GSP8 0x0B
 131 +#define ICNL9707_P_CGOUT_GCK1 0x0C
 132 +#define ICNL9707_P_CGOUT_GCK2 0x0D
 133 +#define ICNL9707_P_CGOUT_GCK3 0x0E
 134 +#define ICNL9707_P_CGOUT_GCK4 0x0F
 135 +#define ICNL9707_P_CGOUT_GCK5 0x10
 136 +#define ICNL9707_P_CGOUT_GCK6 0x11
 137 +#define ICNL9707_P_CGOUT_GCK7 0x12
 138 +#define ICNL9707_P_CGOUT_GCK8 0x13
 139 +#define ICNL9707_P_CGOUT_GCK9 0x14
 140 +#define ICNL9707_P_CGOUT_GCK10 0x15
 141 +#define ICNL9707_P_CGOUT_GCK11 0x16
 142 +#define ICNL9707_P_CGOUT_GCK12 0x17
 143 +#define ICNL9707_P_CGOUT_GCK13 0x18
 144 +#define ICNL9707_P_CGOUT_GCK14 0x19
 145 +#define ICNL9707_P_CGOUT_GCK15 0x1A
 146 +#define ICNL9707_P_CGOUT_GCK16 0x1B
 147 +#define ICNL9707_P_CGOUT_DIR 0x1C
 148 +#define ICNL9707_P_CGOUT_DIRB 0x1D
 149 +#define ICNL9707_P_CGOUT_ECLK_AC 0x1E
 150 +#define ICNL9707_P_CGOUT_ECLK_ACB 0x1F
 151 +#define ICNL9707_P_CGOUT_ECLK_AC2 0x20
 152 +#define ICNL9707_P_CGOUT_ECLK_AC2B 0x21
 153 +#define ICNL9707_P_CGOUT_GCH 0x22
 154 +#define ICNL9707_P_CGOUT_GCL 0x23
 155 +#define ICNL9707_P_CGOUT_XDON 0x24
 156 +#define ICNL9707_P_CGOUT_XDONB 0x25
 157 +
 158 +#define ICNL9707_MADCTL_ML  0x10
 159 +#define ICNL9707_MADCTL_RGB 0x00
 160 +#define ICNL9707_MADCTL_BGR 0x08
 161 +#define ICNL9707_MADCTL_MH  0x04
 162 +
 163 +#define ICNL9707_CMD_PWRCON_VCOM 0xB6
 164 +#define ICNL9707_P_PWRCON_VCOM_0495V 0x0D
 165 +
 166 +#define ICNL9707_CMD_PWRCON_SEQ 0xB7
 167 +#define ICNL9707_CMD_PWRCON_CLK 0xB8
 168 +#define ICNL9707_CMD_PWRCON_BTA 0xB9
 169 +#define ICNL9707_CMD_PWRCON_MODE 0xBA
 170 +#define ICNL9707_CMD_PWRCON_REG 0xBD
 171 +
 172 +#define ICNL9707_CMD_TCON 0xC1
 173 +#define ICNL9707_CMD_TCON2 0xC2
 174 +#define ICNL9707_CMD_TCON3 0xC3
 175 +#define ICNL9707_CMD_SRC_TIM 0xC6
 176 +#define ICNL9707_CMD_SRCCON 0xC7
 177 +#define ICNL9707_CMD_SET_GAMMA 0xC8
 178 +
 179 +#define ICNL9707_CMD_ETC 0xD0
 180 +
 181 +#define ICNL9707_CMD_PASSWORD1 0xF0
 182 +#define ICNL9707_P_PASSWORD1_DEFAULT 0xA5
 183 +#define ICNL9707_P_PASSWORD1_ENABLE_LVL2 0x5A
 184 +
 185 +#define ICNL9707_CMD_PASSWORD2 0xF1
 186 +#define ICNL9707_P_PASSWORD2_DEFAULT 0x5A
 187 +#define ICNL9707_P_PASSWORD2_ENABLE_LVL2 0xA5
 188 +
 189 +static int cwd686_init_sequence(struct cwd686 *ctx)
 190 +{
 191 +       struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
 192 +       int err;
 193 +
 194 +       /* Enable access to Level 2 registers */
 195 +       ICNL9707_DCS(ICNL9707_CMD_PASSWORD1,
 196 +                    ICNL9707_P_PASSWORD1_ENABLE_LVL2,
 197 +                    ICNL9707_P_PASSWORD1_ENABLE_LVL2);
 198 +       ICNL9707_DCS(ICNL9707_CMD_PASSWORD2,
 199 +                    ICNL9707_P_PASSWORD2_ENABLE_LVL2,
 200 +                    ICNL9707_P_PASSWORD2_ENABLE_LVL2);
 201 +
 202 +       /* Set PWRCON_VCOM (-0.495V, -0.495V) */
 203 +       ICNL9707_DCS(ICNL9707_CMD_PWRCON_VCOM,
 204 +                    ICNL9707_P_PWRCON_VCOM_0495V,
 205 +                    ICNL9707_P_PWRCON_VCOM_0495V);
 206 +
 207 +       /* Map ASG output signals */
 208 +       ICNL9707_DCS(ICNL9707_CMD_CGOUTR,
 209 +                    ICNL9707_P_CGOUT_GSP7, ICNL9707_P_CGOUT_GSP5,
 210 +                    ICNL9707_P_CGOUT_GCK7, ICNL9707_P_CGOUT_GCK5,
 211 +                    ICNL9707_P_CGOUT_GCK3, ICNL9707_P_CGOUT_GCK1,
 212 +                    ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL,
 213 +                    ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
 214 +                    ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
 215 +                    ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
 216 +                    ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
 217 +                    ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
 218 +                    ICNL9707_P_CGOUT_GSP1, ICNL9707_P_CGOUT_GSP3);
 219 +       ICNL9707_DCS(ICNL9707_CMD_CGOUTL,
 220 +                    ICNL9707_P_CGOUT_GSP8, ICNL9707_P_CGOUT_GSP6,
 221 +                    ICNL9707_P_CGOUT_GCK8, ICNL9707_P_CGOUT_GCK6,
 222 +                    ICNL9707_P_CGOUT_GCK4, ICNL9707_P_CGOUT_GCK2,
 223 +                    ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL,
 224 +                    ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
 225 +                    ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
 226 +                    ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
 227 +                    ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
 228 +                    ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
 229 +                    ICNL9707_P_CGOUT_GSP2, ICNL9707_P_CGOUT_GSP4);
 230 +
 231 +       /* Undocumented commands provided by the vendor */
 232 +       ICNL9707_DCS(0xB0, 0x54, 0x32, 0x23, 0x45, 0x44, 0x44, 0x44, 0x44, 0x90, 0x01, 0x90, 0x01);
 233 +       ICNL9707_DCS(0xB1, 0x32, 0x84, 0x02, 0x83, 0x30, 0x01, 0x6B, 0x01);
 234 +       ICNL9707_DCS(0xB2, 0x73);
 235 +
 236 +       ICNL9707_DCS(ICNL9707_CMD_PWRCON_REG,
 237 +                    0x4E, 0x0E, 0x50, 0x50, 0x26,
 238 +                    0x1D, 0x00, 0x14, 0x42, 0x03);
 239 +       ICNL9707_DCS(ICNL9707_CMD_PWRCON_SEQ,
 240 +                    0x01, 0x01, 0x09, 0x11, 0x0D, 0x55,
 241 +                    0x19, 0x19, 0x21, 0x1D, 0x00, 0x00,
 242 +                    0x00, 0x00, 0x02, 0xFF, 0x3C);
 243 +       ICNL9707_DCS(ICNL9707_CMD_PWRCON_CLK, 0x23, 0x01, 0x30, 0x34, 0x63);
 244 +
 245 +       /* Disable abnormal power-off flag */
 246 +       ICNL9707_DCS(ICNL9707_CMD_PWRCON_BTA, 0xA0, 0x22, 0x00, 0x44);
 247 +
 248 +       ICNL9707_DCS(ICNL9707_CMD_PWRCON_MODE, 0x12, 0x63);
 249 +
 250 +       /* Set VBP, VFP, VSW, HBP, HFP, HSW */
 251 +       ICNL9707_DCS(ICNL9707_CMD_TCON, 0x0C, 0x16, 0x04, 0x0C, 0x10, 0x04);
 252 +
 253 +       /* Set resolution */
 254 +       ICNL9707_DCS(ICNL9707_CMD_TCON2, 0x11, 0x41);
 255 +
 256 +       /* Set frame blanking */
 257 +       ICNL9707_DCS(ICNL9707_CMD_TCON3, 0x22, 0x31, 0x04);
 258 +
 259 +       ICNL9707_DCS(ICNL9707_CMD_SRCCON, 0x05, 0x23, 0x6B, 0x49, 0x00);
 260 +
 261 +       /* Another undocumented command */
 262 +       ICNL9707_DCS(0xC5, 0x00);
 263 +
 264 +       ICNL9707_DCS(ICNL9707_CMD_ETC, 0x37, 0xFF, 0xFF);
 265 +
 266 +       /* Another set of undocumented commands */
 267 +       ICNL9707_DCS(0xD2, 0x63, 0x0B, 0x08, 0x88);
 268 +       ICNL9707_DCS(0xD3, 0x01, 0x00, 0x00, 0x01, 0x01, 0x37, 0x25, 0x38, 0x31, 0x06, 0x07);
 269 +
 270 +       /* Set Gamma to 2.2 */
 271 +       ICNL9707_DCS(ICNL9707_CMD_SET_GAMMA,
 272 +                    0x7C, 0x6A, 0x5D, 0x53, 0x53, 0x45, 0x4B,
 273 +                    0x35, 0x4D, 0x4A, 0x49, 0x66, 0x53, 0x57,
 274 +                    0x4A, 0x48, 0x3B, 0x2A, 0x06, 0x7C, 0x6A,
 275 +                    0x5D, 0x53, 0x53, 0x45, 0x4B, 0x35, 0x4D,
 276 +                    0x4A, 0x49, 0x66, 0x53, 0x57, 0x4A, 0x48,
 277 +                    0x3B, 0x2A, 0x06);
 278 +
 279 +       ICNL9707_DCS(ICNL9707_CMD_SRC_TIM, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00);
 280 +
 281 +       /* Another undocumented command */
 282 +       ICNL9707_DCS(0xF4, 0x08, 0x77);
 283 +
 284 +       ICNL9707_DCS(MIPI_DCS_SET_ADDRESS_MODE,
 285 +                    ICNL9707_MADCTL_RGB | ICNL9707_MADCTL_ML | ICNL9707_MADCTL_MH);
 286 +
 287 +       /* Enable tearing mode at VBLANK */
 288 +       err = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
 289 +       if (err) {
 290 +               dev_err(ctx->dev, "failed to enable vblank TE (%d)\n", err);
 291 +               return err;
 292 +       }
 293 +
 294 +       /* Disable access to Level 2 registers */
 295 +       ICNL9707_DCS(ICNL9707_CMD_PASSWORD2,
 296 +                    ICNL9707_P_PASSWORD2_DEFAULT,
 297 +                    ICNL9707_P_PASSWORD2_DEFAULT);
 298 +       ICNL9707_DCS(ICNL9707_CMD_PASSWORD1,
 299 +                    ICNL9707_P_PASSWORD1_DEFAULT,
 300 +                    ICNL9707_P_PASSWORD1_DEFAULT);
 301 +
 302 +       return 0;
 303 +}
 304 +
 305 +static int cwd686_disable(struct drm_panel *panel)
 306 +{
 307 +       struct cwd686 *ctx = panel_to_cwd686(panel);
 308 +
 309 +       if (!ctx->enabled)
 310 +               return 0;
 311 +
 312 +       backlight_disable(ctx->backlight);
 313 +
 314 +       ctx->enabled = false;
 315 +
 316 +       return 0;
 317 +}
 318 +
 319 +static int cwd686_unprepare(struct drm_panel *panel)
 320 +{
 321 +       struct cwd686 *ctx = panel_to_cwd686(panel);
 322 +       struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
 323 +       int err;
 324 +
 325 +       if (!ctx->prepared)
 326 +               return 0;
 327 +
 328 +       err = mipi_dsi_dcs_set_display_off(dsi);
 329 +       if (err) {
 330 +               dev_err(ctx->dev, "failed to turn display off (%d)\n", err);
 331 +               return err;
 332 +       }
 333 +
 334 +       err = mipi_dsi_dcs_enter_sleep_mode(dsi);
 335 +       if (err) {
 336 +               dev_err(ctx->dev, "failed to enter sleep mode (%d)\n", err);
 337 +               return err;
 338 +       }
 339 +
 340 +       msleep(120);
 341 +
 342 +       gpiod_set_value_cansleep(ctx->reset_gpio, 1);
 343 +
 344 +       ctx->prepared = false;
 345 +
 346 +       return 0;
 347 +}
 348 +
 349 +static int cwd686_prepare(struct drm_panel *panel)
 350 +{
 351 +       struct cwd686 *ctx = panel_to_cwd686(panel);
 352 +       struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
 353 +       int err;
 354 +
 355 +       if (ctx->prepared)
 356 +               return 0;
 357 +
 358 +       gpiod_set_value_cansleep(ctx->reset_gpio, 1);
 359 +       /* T2 */
 360 +       msleep(10);
 361 +
 362 +       gpiod_set_value_cansleep(ctx->reset_gpio, 0);
 363 +       /* T3 */
 364 +       msleep(20);
 365 +
 366 +       /* Exit sleep mode and power on */
 367 +
 368 +       err = cwd686_init_sequence(ctx);
 369 +       if (err) {
 370 +               dev_err(ctx->dev, "failed to initialize display (%d)\n", err);
 371 +               return err;
 372 +       }
 373 +
 374 +       err = mipi_dsi_dcs_exit_sleep_mode(dsi);
 375 +       if (err) {
 376 +               dev_err(ctx->dev, "failed to exit sleep mode (%d)\n", err);
 377 +               return err;
 378 +       }
 379 +       /* T6 */
 380 +       msleep(120);
 381 +
 382 +       err = mipi_dsi_dcs_set_display_on(dsi);
 383 +       if (err) {
 384 +               dev_err(ctx->dev, "failed to turn display on (%d)\n", err);
 385 +               return err;
 386 +       }
 387 +       msleep(20);
 388 +
 389 +       ctx->prepared = true;
 390 +
 391 +       return 0;
 392 +}
 393 +
 394 +static int cwd686_enable(struct drm_panel *panel)
 395 +{
 396 +       struct cwd686 *ctx = panel_to_cwd686(panel);
 397 +
 398 +       if (ctx->enabled)
 399 +               return 0;
 400 +
 401 +       backlight_enable(ctx->backlight);
 402 +
 403 +       ctx->enabled = true;
 404 +
 405 +       return 0;
 406 +}
 407 +
 408 +static int cwd686_get_modes(struct drm_panel *panel, struct drm_connector *connector)
 409 +{
 410 +       struct cwd686 *ctx = panel_to_cwd686(panel);
 411 +       struct drm_display_mode *mode;
 412 +
 413 +       mode = drm_mode_duplicate(connector->dev, &default_mode);
 414 +       if (!mode) {
 415 +               dev_err(panel->dev, "bad mode or failed to add mode\n");
 416 +               return -EINVAL;
 417 +       }
 418 +       drm_mode_set_name(mode);
 419 +       mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
 420 +
 421 +       connector->display_info.width_mm = mode->width_mm;
 422 +       connector->display_info.height_mm = mode->height_mm;
 423 +
 424 +       /* set up connector's "panel orientation" property */
 425 +       drm_connector_set_panel_orientation(connector, ctx->orientation);
 426 +
 427 +       drm_mode_probed_add(connector, mode);
 428 +
 429 +       return 1; /* Number of modes */
 430 +}
 431 +
 432 +static const struct drm_panel_funcs cwd686_drm_funcs = {
 433 +       .disable = cwd686_disable,
 434 +       .unprepare = cwd686_unprepare,
 435 +       .prepare = cwd686_prepare,
 436 +       .enable = cwd686_enable,
 437 +       .get_modes = cwd686_get_modes,
 438 +};
 439 +
 440 +static int cwd686_probe(struct mipi_dsi_device *dsi)
 441 +{
 442 +       struct device *dev = &dsi->dev;
 443 +       struct cwd686 *ctx;
 444 +       int err;
 445 +
 446 +       ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 447 +       if (!ctx)
 448 +               return -ENOMEM;
 449 +
 450 +       mipi_dsi_set_drvdata(dsi, ctx);
 451 +       ctx->dev = dev;
 452 +
 453 +       dsi->lanes = 4;
 454 +       dsi->format = MIPI_DSI_FMT_RGB888;
 455 +       dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
 456 +                         MIPI_DSI_MODE_VIDEO_BURST |
 457 +                         MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
 458 +
 459 +       ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
 460 +       if (IS_ERR(ctx->reset_gpio)) {
 461 +               err = PTR_ERR(ctx->reset_gpio);
 462 +               if (err != -EPROBE_DEFER)
 463 +                       dev_err(dev, "failed to request GPIO (%d)\n", err);
 464 +               return err;
 465 +       }
 466 +
 467 +       ctx->backlight = devm_of_find_backlight(dev);
 468 +       if (IS_ERR(ctx->backlight))
 469 +               return PTR_ERR(ctx->backlight);
 470 +
 471 +       err = of_drm_get_panel_orientation(dev->of_node, &ctx->orientation);
 472 +       if (err) {
 473 +               dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
 474 +               return err;
 475 +       }
 476 +
 477 +       drm_panel_init(&ctx->panel, dev, &cwd686_drm_funcs, DRM_MODE_CONNECTOR_DSI);
 478 +
 479 +       drm_panel_add(&ctx->panel);
 480 +
 481 +       err = mipi_dsi_attach(dsi);
 482 +       if (err < 0) {
 483 +               dev_err(dev, "mipi_dsi_attach() failed: %d\n", err);
 484 +               drm_panel_remove(&ctx->panel);
 485 +               return err;
 486 +       }
 487 +
 488 +       return 0;
 489 +}
 490 +
 491 +static void cwd686_remove(struct mipi_dsi_device *dsi)
 492 +{
 493 +       struct cwd686 *ctx = mipi_dsi_get_drvdata(dsi);
 494 +
 495 +       mipi_dsi_detach(dsi);
 496 +       drm_panel_remove(&ctx->panel);
 497 +}
 498 +
 499 +static const struct of_device_id cwd686_of_match[] = {
 500 +       { .compatible = "clockwork,cwd686" },
 501 +       { /* sentinel */ }
 502 +};
 503 +MODULE_DEVICE_TABLE(of, cwd686_of_match);
 504 +
 505 +static struct mipi_dsi_driver cwd686_driver = {
 506 +       .probe = cwd686_probe,
 507 +       .remove = cwd686_remove,
 508 +       .driver = {
 509 +               .name = "panel-clockwork-cwd686",
 510 +               .of_match_table = cwd686_of_match,
 511 +       },
 512 +};
 513 +module_mipi_dsi_driver(cwd686_driver);
 514 +
 515 +MODULE_AUTHOR("Pinfan Zhu <zhu@clockworkpi.com>");
 516 +MODULE_AUTHOR("Max Fierke <max@maxfierke.com>");
 517 +MODULE_DESCRIPTION("ClockworkPi CWD686 panel driver");
 518 +MODULE_LICENSE("GPL");