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[openwrt/openwrt.git] / target / linux / coldfire / patches / 004-MCF54418-support-in-Linux-2.6.38.patch
1 From b23f9dc392de5be8a2bc17342d6aee49208a80d8 Mon Sep 17 00:00:00 2001
2 From: Alison Wang <b18965@freescale.com>
3 Date: Thu, 4 Aug 2011 09:59:39 +0800
4 Subject: [PATCH 04/52] MCF54418 support in Linux 2.6.38
5
6 Add MCF54418 support in Linux 2.6.38.
7
8 Signed-off-by: Alison Wang <b18965@freescale.com>
9 ---
10 arch/m68k/coldfire/m5441x/Makefile | 38 +
11 arch/m68k/coldfire/m5441x/config.c | 604 +++++++++++++
12 arch/m68k/coldfire/m5441x/devices.c | 787 +++++++++++++++++
13 arch/m68k/configs/m54418twr_defconfig | 1244 +++++++++++++++++++++++++++
14 arch/m68k/include/asm/cf_5441x_cacheflush.h | 527 ++++++++++++
15 arch/m68k/include/asm/mcf5441x_ccm.h | 157 ++++
16 arch/m68k/include/asm/mcf5441x_clock.h | 22 +
17 arch/m68k/include/asm/mcf5441x_dspi.h | 671 +++++++++++++++
18 arch/m68k/include/asm/mcf5441x_dtim.h | 95 ++
19 arch/m68k/include/asm/mcf5441x_edma.h | 303 +++++++
20 arch/m68k/include/asm/mcf5441x_eport.h | 94 ++
21 arch/m68k/include/asm/mcf5441x_fbcs.h | 204 +++++
22 arch/m68k/include/asm/mcf5441x_flexcan.h | 139 +++
23 arch/m68k/include/asm/mcf5441x_gpio.h | 509 +++++++++++
24 arch/m68k/include/asm/mcf5441x_intc.h | 727 ++++++++++++++++
25 arch/m68k/include/asm/mcf5441x_pm.h | 33 +
26 arch/m68k/include/asm/mcf5441x_rtc.h | 127 +++
27 arch/m68k/include/asm/mcf5441x_scm.h | 33 +
28 arch/m68k/include/asm/mcf5441x_sdramc.h | 141 +++
29 arch/m68k/include/asm/mcf5441x_xbs.h | 77 ++
30 20 files changed, 6532 insertions(+), 0 deletions(-)
31 create mode 100644 arch/m68k/coldfire/m5441x/Makefile
32 create mode 100644 arch/m68k/coldfire/m5441x/config.c
33 create mode 100644 arch/m68k/coldfire/m5441x/devices.c
34 create mode 100644 arch/m68k/configs/m54418twr_defconfig
35 create mode 100644 arch/m68k/include/asm/cf_5441x_cacheflush.h
36 create mode 100644 arch/m68k/include/asm/mcf5441x_ccm.h
37 create mode 100644 arch/m68k/include/asm/mcf5441x_clock.h
38 create mode 100644 arch/m68k/include/asm/mcf5441x_dspi.h
39 create mode 100644 arch/m68k/include/asm/mcf5441x_dtim.h
40 create mode 100644 arch/m68k/include/asm/mcf5441x_edma.h
41 create mode 100644 arch/m68k/include/asm/mcf5441x_eport.h
42 create mode 100644 arch/m68k/include/asm/mcf5441x_fbcs.h
43 create mode 100644 arch/m68k/include/asm/mcf5441x_flexcan.h
44 create mode 100644 arch/m68k/include/asm/mcf5441x_gpio.h
45 create mode 100644 arch/m68k/include/asm/mcf5441x_intc.h
46 create mode 100644 arch/m68k/include/asm/mcf5441x_pm.h
47 create mode 100644 arch/m68k/include/asm/mcf5441x_rtc.h
48 create mode 100644 arch/m68k/include/asm/mcf5441x_scm.h
49 create mode 100644 arch/m68k/include/asm/mcf5441x_sdramc.h
50 create mode 100644 arch/m68k/include/asm/mcf5441x_xbs.h
51
52 --- /dev/null
53 +++ b/arch/m68k/coldfire/m5441x/Makefile
54 @@ -0,0 +1,38 @@
55 +#
56 +# Makefile for Linux arch/m68k/coldfire/m5441x source directory
57 +#
58 +
59 +obj-$(CONFIG_M5441X) += devices.o config.o
60 +
61 +ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_FSL_USB2)),)
62 + obj-y += usb.o
63 +endif
64 +ifneq ($(strip $(CONFIG_USB_GADGET_FSL_USB2) $(CONFIG_USB_EHCI_HCD)),)
65 +ifeq ($(strip $(CONFIG_USB_M5441X_FSLS)),)
66 + obj-y += usb_dr.o
67 +endif
68 +endif
69 +
70 +#ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_FSL_USB2)),)
71 +ifneq ($(strip $(CONFIG_USB_OTG) $(CONFIG_USB_M5441X_MAX3353_FSLS)),)
72 + obj-y += xcvr.o
73 +endif
74 +ifneq ($(strip $(CONFIG_USB_M5441X_MAX3353_FSLS)), )
75 + obj-y += max3353_xc.o
76 +ifneq ($(strip $(CONFIG_USB_OTG)),)
77 + obj-m += max3353_otg.o
78 +endif
79 +endif
80 +
81 +# USB Host controller support
82 +ifneq ($(strip $(CONFIG_USB_M5441X_H1)),)
83 + obj-y += usb_host.o xcvr_host.o
84 +endif
85 +
86 +ifneq ($(CONFIG_FEC),)
87 +obj-y += fec.o
88 +endif
89 +
90 +ifneq ($(CONFIG_MODELO_SWITCH),)
91 +obj-y += l2switch.o
92 +endif
93 --- /dev/null
94 +++ b/arch/m68k/coldfire/m5441x/config.c
95 @@ -0,0 +1,604 @@
96 +/*
97 + * linux/arch/m68k/coldfire/m5441x/config.c
98 + *
99 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
100 + *
101 + * This program is free software; you can redistribute it and/or modify
102 + * it under the terms of the GNU General Public License as published by
103 + * the Free Software Foundation; either version 2 of the License, or
104 + * (at your option) any later version.
105 + */
106 +
107 +#include <linux/module.h>
108 +#include <linux/init.h>
109 +#include <linux/string.h>
110 +#include <linux/kernel.h>
111 +#include <linux/console.h>
112 +#include <linux/bootmem.h>
113 +#include <linux/mm.h>
114 +#include <linux/sched.h>
115 +#include <linux/clockchips.h>
116 +#include <linux/delay.h>
117 +#include <asm/bootinfo.h>
118 +#include <asm/machdep.h>
119 +#include <asm/coldfire.h>
120 +#include <asm/cfcache.h>
121 +#include <asm/cacheflush.h>
122 +#include <asm/io.h>
123 +#include <asm/cfmmu.h>
124 +#include <asm/setup.h>
125 +#include <asm/irq.h>
126 +#include <asm/traps.h>
127 +#include <asm/movs.h>
128 +#include <asm/movs.h>
129 +#include <asm/page.h>
130 +#include <asm/pgalloc.h>
131 +#include <asm/cf-sram.h>
132 +
133 +#include <asm/mcfsim.h>
134 +
135 +#define UBOOT_EXTRA_CLOCKS
136 +#include <asm/bootinfo.h>
137 +
138 +#include <asm/mcf5441x_intc.h>
139 +#include <asm/mcf5441x_sdramc.h>
140 +#include <asm/mcf5441x_fbcs.h>
141 +#include <asm/mcf5441x_dtim.h>
142 +#include <asm/mcf5441x_xbs.h>
143 +
144 +extern int get_irq_list(struct seq_file *p, void *v);
145 +extern char _text, _end;
146 +extern char _etext, _edata, __init_begin, __init_end;
147 +extern struct console mcfrs_console;
148 +extern char m68k_command_line[CL_SIZE];
149 +extern unsigned long availmem;
150 +extern unsigned long shadow_cacr;
151 +EXPORT_SYMBOL(shadow_cacr);
152 +extern struct mem_info m68k_ramdisk;
153 +
154 +static int irq_enable[NR_IRQS];
155 +unsigned long num_pages;
156 +
157 +/* cf dma physical addresses */
158 +unsigned long cf_dma_base;
159 +EXPORT_SYMBOL(cf_dma_base);
160 +unsigned long cf_dma_end;
161 +EXPORT_SYMBOL(cf_dma_end);
162 +unsigned long cf_dma_size;
163 +EXPORT_SYMBOL(cf_dma_size);
164 +
165 +/* ethernet mac addresses from uboot */
166 +unsigned char uboot_enet0[6];
167 +unsigned char uboot_enet1[6];
168 +
169 +void coldfire_sort_memrec(void)
170 +{
171 + int i, j;
172 +
173 + /* Sort the m68k_memory records by address */
174 + for (i = 0; i < m68k_num_memory; ++i) {
175 + for (j = i + 1; j < m68k_num_memory; ++j) {
176 + if (m68k_memory[i].addr > m68k_memory[j].addr) {
177 + struct mem_info tmp;
178 + tmp = m68k_memory[i];
179 + m68k_memory[i] = m68k_memory[j];
180 + m68k_memory[j] = tmp;
181 + }
182 + }
183 + }
184 + /* Trim off discontiguous bits */
185 + for (i = 1; i < m68k_num_memory; ++i) {
186 + if ((m68k_memory[i-1].addr + m68k_memory[i-1].size) !=
187 + m68k_memory[i].addr) {
188 + printk(KERN_DEBUG "m68k_parse_bootinfo: "
189 + "addr gap between 0x%lx & 0x%lx\n",
190 + m68k_memory[i-1].addr+m68k_memory[i-1].size,
191 + m68k_memory[i].addr);
192 + m68k_num_memory = i;
193 + break;
194 + }
195 + }
196 +}
197 +
198 +/*
199 + * UBoot Handler
200 + */
201 +int __init uboot_commandline(char *bootargs)
202 +{
203 + int len = 0, cmd_line_len;
204 + static struct uboot_record uboot_info;
205 + u32 offset = PAGE_OFFSET_RAW - PHYS_OFFSET;
206 +
207 + extern unsigned long uboot_info_stk;
208 +
209 + /* validate address */
210 + if ((uboot_info_stk < PAGE_OFFSET_RAW) ||
211 + (uboot_info_stk >= (PAGE_OFFSET_RAW + CONFIG_SDRAM_SIZE)))
212 + return 0;
213 +
214 + /* Add offset to get post-remapped kernel memory location */
215 + uboot_info.bdi = (struct bd_info *)
216 + ((*(u32 *)(uboot_info_stk)) + offset);
217 + uboot_info.initrd_start = (*(u32 *)(uboot_info_stk+4)) + offset;
218 + uboot_info.initrd_end = (*(u32 *)(uboot_info_stk+8)) + offset;
219 + uboot_info.cmd_line_start = (*(u32 *)(uboot_info_stk+12)) + offset;
220 + uboot_info.cmd_line_stop = (*(u32 *)(uboot_info_stk+16)) + offset;
221 +
222 +#if defined(CONFIG_BLK_DEV_INITRD)
223 + m68k_ramdisk.addr = uboot_info.initrd_start;
224 + m68k_ramdisk.size = (uboot_info.initrd_end - uboot_info.initrd_start) ?
225 + (uboot_info.initrd_end - uboot_info.initrd_start + 1) : 0;
226 +#endif
227 +
228 + /* copy over mac addresses */
229 + memcpy(uboot_enet0, uboot_info.bdi->bi_enet0addr, 6);
230 + memcpy(uboot_enet1, uboot_info.bdi->bi_enet1addr, 6);
231 +
232 + /* copy command line */
233 + cmd_line_len = uboot_info.cmd_line_stop - uboot_info.cmd_line_start;
234 + if ((cmd_line_len > 0) && (cmd_line_len < CL_SIZE-1))
235 + len = (int)strncpy(bootargs, (char *)uboot_info.cmd_line_start,\
236 + cmd_line_len);
237 +
238 + return len;
239 +}
240 +
241 +#define DEFAULT_COMMAND_LINE \
242 + "debug root=/dev/nfs rw \
243 + nfsroot=172.27.155.1:/tftpboot/redstripe/rootfs/ \
244 + ip=172.27.155.51:172.27.155.1"
245 +
246 +/*
247 + * Early Coldfire Initialization.
248 + */
249 +asmlinkage void __init cf_early_init(void)
250 +{
251 + SET_VBR((void *)MCF_RAMBAR1);
252 +
253 + /* Mask all interrupts */
254 + MCF_INTC0_IMRL = 0xFFFFFFFF;
255 + MCF_INTC0_IMRH = 0xFFFFFFFF;
256 + MCF_INTC1_IMRL = 0xFFFFFFFF;
257 + MCF_INTC1_IMRH = 0xFFFFFFFF;
258 +
259 +#if defined(CONFIG_USB)
260 + /* reset USB3300 */
261 + asm ("moveb #0x40, %%d0\n\t"
262 + "moveb %%d0, 0xec090000\n\t"
263 + : : : "%d0");
264 + mdelay(1);
265 + asm ("moveb #0x0, %%d0\n\t"
266 + "moveb %%d0, 0xec090000\n\t"
267 + : : : "%d0");
268 +#endif
269 +
270 +#if defined(CONFIG_NOR_FLASH_BASE)
271 + MCF_FBCS_CSAR(1) = CONFIG_NOR_FLASH_BASE;
272 +#else
273 + MCF_FBCS_CSAR(1) = 0x00000000;
274 +#endif
275 +
276 +#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
277 + MCF_FBCS_CSAR(0) = FLEXBUS_LCD_CMD_ADDRESS;
278 + MCF_FBCS_CSMR(0) = MCF_FBCS_CSMR_BAM_128K | MCF_FBCS_CSMR_V;
279 + MCF_FBCS_CSCR(0) = MCF_FBCS_CSCR_BLS | MCF_FBCS_CSCR_AA |
280 + MCF_FBCS_CSCR_PS_16;
281 +#endif
282 +
283 +#if CONFIG_SDRAM_SIZE > (256*1024*1024)
284 + /* Init optional SDRAM chip select */
285 + MCF_SDRAMC_SDCS(1) = (256*1024*1024) | 0x1B;
286 +#endif
287 +
288 + MCF_XBS_CRS2 = 0x100;
289 + /* Setup SDRAM crossbar(XBS) priorities */
290 + MCF_XBS_PRS2 = (MCF_XBS_PRS_M0(MCF_XBS_PRI_2) | /*CPU*/
291 + MCF_XBS_PRS_M1(MCF_XBS_PRI_3) | /*eDMA*/
292 + MCF_XBS_PRS_M2(MCF_XBS_PRI_1) | /*FEC0*/
293 + MCF_XBS_PRS_M3(MCF_XBS_PRI_5) | /*FEC1*/
294 + MCF_XBS_PRS_M5(MCF_XBS_PRI_6) | /*PCI*/
295 + MCF_XBS_PRS_M6(MCF_XBS_PRI_4) | /*USB*/
296 + MCF_XBS_PRS_M7(MCF_XBS_PRI_7)); /*SBF*/
297 +
298 + m68k_machtype = MACH_CFMMU;
299 + m68k_fputype = FPU_CFV4E;
300 + m68k_mmutype = MMU_CFV4E;
301 + m68k_cputype = CPU_CFV4E;
302 +
303 + /* initialize PHYSRAM */
304 + m68k_num_memory = 0;
305 + m68k_memory[m68k_num_memory].addr = CONFIG_SDRAM_BASE; /* phys */
306 + m68k_memory[m68k_num_memory++].size = CONFIG_SDRAM_SIZE;
307 +
308 + if (!uboot_commandline(m68k_command_line)) {
309 +#if defined(CONFIG_BOOTPARAM)
310 + strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE-1);
311 +#else
312 + strcpy(m68k_command_line, DEFAULT_COMMAND_LINE);
313 +#endif
314 + }
315 +
316 + /* Invalidate caches via CACR */
317 + flush_bcache();
318 + cacr_set(CACHE_DISABLE_MODE);
319 +
320 + /* Turn on caches via CACR, enable EUSP */
321 + cacr_set(CACHE_INITIAL_MODE);
322 +}
323 +
324 +/* Assembler routines */
325 +asmlinkage void buserr(void);
326 +asmlinkage void trap(void);
327 +asmlinkage void system_call(void);
328 +asmlinkage void inthandler(void);
329 +
330 +void __init coldfire_trap_init(void)
331 +{
332 + int i = 0;
333 + e_vector *vectors;
334 +
335 + vectors = (e_vector *)MCF_RAMBAR1;
336 + /*
337 + * There is a common trap handler and common interrupt
338 + * handler that handle almost every vector. We treat
339 + * the system call and bus error special, they get their
340 + * own first level handlers.
341 + */
342 + for (i = 3; (i <= 23); i++)
343 + vectors[i] = trap;
344 + for (i = 33; (i <= 63); i++)
345 + vectors[i] = trap;
346 + for (i = 24; (i <= 31); i++)
347 + vectors[i] = inthandler;
348 + for (i = 64; (i < 255); i++)
349 + vectors[i] = inthandler;
350 +
351 + vectors[255] = 0;
352 + vectors[2] = buserr;
353 + vectors[32] = system_call;
354 +}
355 +
356 +void settimericr(unsigned int timer, unsigned int level)
357 +{
358 + volatile unsigned char *icrp;
359 + unsigned int icr = 0;
360 + unsigned char irq = 0;
361 +
362 + if (timer <= 3) {
363 + switch (timer) {
364 + case 0:
365 + irq = 32;
366 + icr = MCFSIM_ICR_TIMER0;
367 + break;
368 + case 1:
369 + irq = 33;
370 + icr = MCFSIM_ICR_TIMER1;
371 + break;
372 + case 2:
373 + irq = 34;
374 + icr = MCFSIM_ICR_TIMER2;
375 + break;
376 + case 3:
377 + irq = 35;
378 + icr = MCFSIM_ICR_TIMER3;
379 + break;
380 + }
381 +
382 + icrp = (volatile unsigned char *) (icr);
383 + *icrp = level;
384 + coldfire_enable_irq0(irq);
385 + }
386 +}
387 +
388 +void coldfire_sched_clk_init(void);
389 +
390 +void coldfire_tick(void)
391 +{
392 + /* Reset the ColdFire timer */
393 + __raw_writeb(MCF_DTIM_DTER_CAP | MCF_DTIM_DTER_REF, MCF_DTIM0_DTER);
394 +}
395 +
396 +void __init coldfire_sched_init(irq_handler_t handler)
397 +{
398 + unsigned int mcf_timerlevel = 5;
399 + unsigned int mcf_timervector = 64+32;
400 +
401 + __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM0_DTMR);
402 + __raw_writel(((MCF_BUSCLK / 16) / HZ), MCF_DTIM0_DTRR);
403 + __raw_writew(MCF_DTIM_DTMR_ORRI | MCF_DTIM_DTMR_CLK_DIV16 |
404 + MCF_DTIM_DTMR_FRR | MCF_DTIM_DTMR_RST_EN, \
405 + MCF_DTIM0_DTMR);
406 +
407 + request_irq(mcf_timervector, handler, IRQF_DISABLED, \
408 + "timer", (void *)MCF_DTIM0_DTMR);
409 +
410 + settimericr(0, mcf_timerlevel);
411 +
412 + /* initialize the fast clock */
413 + coldfire_sched_clk_init();
414 +}
415 +
416 +int timerirqpending(int timer)
417 +{
418 + unsigned int imr = 0;
419 + unsigned ret = 0;
420 +
421 + switch (timer) {
422 + case 1:
423 + imr = 0x1;
424 + break;
425 + case 2:
426 + imr = 0x2;
427 + break;
428 + default:
429 + break;
430 + }
431 +
432 + ret = getiprh() & imr;
433 + return ret;
434 +}
435 +
436 +unsigned long coldfire_gettimeoffset(void)
437 +{
438 + volatile unsigned long trr, tcn, offset;
439 +
440 + tcn = __raw_readw(MCF_DTIM0_DTCN);
441 + trr = __raw_readl(MCF_DTIM0_DTRR);
442 + offset = (tcn * (1000000 / HZ)) / trr;
443 +
444 + /* Check if we just wrapped the counters and maybe missed a tick */
445 + if ((offset < (1000000 / HZ / 2)) && timerirqpending(1))
446 + offset += 1000000 / HZ;
447 + return offset;
448 +}
449 +
450 +/* sched_clock support */
451 +
452 +static unsigned long long sched_clk_val;
453 +
454 +static irqreturn_t coldfire_sched_clk_irq(int irq, void *dev)
455 +{
456 + __raw_writeb(MCF_DTIM_DTER_CAP | MCF_DTIM_DTER_REF, MCF_DTIM3_DTER);
457 + sched_clk_val += 0x100000000LL;
458 +
459 + return IRQ_HANDLED;
460 +}
461 +
462 +/*
463 + * Setup DTIM3 as the 5441x sched_clock() implementation. The
464 + * input frequency to the clock is the internal bus clock (MCF_BUSCLK)
465 + * which is the system clock (MCF_CLK) / 2.
466 + *
467 + * On a system running at 266Mhz:
468 + * MCF_CLK = 266Mhz (266000000)
469 + * MCF_BUSCLK = 133Mhz (133000000)
470 + * DTIM3 Tick = 133Mhz (133000000)
471 + * Tick Resolution = 7.5ns (round to 8ns/Tick)
472 + *
473 + * On a system running at 240Mhz:
474 + * MCF_CLK = 240Mhz (240000000)
475 + * MCF_BUSCLK = 120Mhz (120000000)
476 + * DTIM3 Tick = 120Mhz (120000000)
477 + * Tick Resolution = 8.4ns (round to 8ns/Tick)
478 + */
479 +void __init coldfire_sched_clk_init(void)
480 +{
481 + unsigned int mcf_timerlevel = 5;
482 + unsigned int mcf_timervector = 64+32+3; /* DTIM3 */
483 +
484 + printk(KERN_INFO "Initializing DTIM3 for sched_clock\n");
485 + __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM3_DTMR);
486 + __raw_writel(0xffffffff, MCF_DTIM3_DTRR);
487 + __raw_writew(MCF_DTIM_DTMR_ORRI | MCF_DTIM_DTMR_CLK_DIV1 | \
488 + MCF_DTIM_DTMR_RST_EN, MCF_DTIM3_DTMR);
489 +
490 + sched_clk_val = 0;
491 + request_irq(mcf_timervector, coldfire_sched_clk_irq, IRQF_DISABLED, \
492 + "timer", (void *)MCF_DTIM3_DTMR);
493 +
494 + settimericr(3, mcf_timerlevel);
495 +}
496 +
497 +#ifndef CONFIG_GENERIC_CLOCKEVENTS
498 +/* get highres timer */
499 +unsigned long long sched_clock(void)
500 +{
501 + unsigned long long ret = 0;
502 + ret = sched_clk_val | (unsigned long long)(MCF_REG32(MCF_DTIM3_DTCN));
503 + ret = ret << 3;
504 + return ret;
505 +}
506 +
507 +#else /*CONFIG_GENERIC_CLOCKEVENTS*/
508 +
509 +static unsigned long long sched_dtim_clk_val;
510 +
511 +unsigned long long sched_clock(void)
512 +{
513 + unsigned long flags;
514 + unsigned long long tcn, cycles;
515 +
516 + local_irq_save(flags);
517 + tcn = ((unsigned long long)(MCF_REG32(MCF_DTIM2_DTCN)));
518 + cycles = sched_dtim_clk_val;
519 + local_irq_restore(flags);
520 + return cycles + tcn;
521 +}
522 +
523 +unsigned long long sys_dtim2_read(void)
524 +{
525 + unsigned long flags;
526 + unsigned long long tcn, cycles;
527 +
528 + local_irq_save(flags);
529 + tcn = ((unsigned long long)(MCF_REG32(MCF_DTIM2_DTCN)));
530 + cycles = sched_dtim_clk_val;
531 + local_irq_restore(flags);
532 +
533 + return cycles + tcn;
534 +}
535 +
536 +static irqreturn_t coldfire_dtim_clk_irq(int irq, void *dev)
537 +{
538 + struct clock_event_device *evt = (struct clock_event_device *)dev;
539 +
540 + __raw_writeb(MCF_DTIM_DTER_CAP | MCF_DTIM_DTER_REF, MCF_DTIM2_DTER);
541 + sched_dtim_clk_val += (MCF_BUSCLK / 16) / HZ;
542 + evt->event_handler(evt);
543 + return IRQ_HANDLED;
544 +}
545 +
546 +void sys_dtim2_init(struct clock_event_device *evt)
547 +{
548 + unsigned int mcf_timerlevel = 5;
549 + unsigned int mcf_timervector = 64+32+2; /* DTIM2 */
550 +
551 + printk(KERN_INFO "Initializing DTIM2 for sched_clock\n");
552 + __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM2_DTMR);
553 + __raw_writel(((MCF_BUSCLK / 16) / HZ)-1, MCF_DTIM2_DTRR);
554 + __raw_writew(MCF_DTIM_DTMR_ORRI | MCF_DTIM_DTMR_CLK_DIV16 |
555 + MCF_DTIM_DTMR_FRR | MCF_DTIM_DTMR_RST_EN, \
556 + MCF_DTIM2_DTMR);
557 +
558 + request_irq(mcf_timervector, coldfire_dtim_clk_irq, IRQF_DISABLED, \
559 + "timer2", (void *)evt);
560 +
561 + settimericr(3, mcf_timerlevel);
562 + return;
563 +}
564 +
565 +#endif
566 +
567 +void coldfire_reboot(void)
568 +{
569 + /* disable interrupts and do a software reset */
570 + asm("movew #0x2700, %%sr\n\t"
571 + "moveb #0x40, %%d0\n\t"
572 + "moveb %%d0, 0xec090000\n\t"
573 + : : : "%d0");
574 +
575 + mdelay(10);
576 +
577 + asm("moveb #0xc0, %%d0\n\t"
578 + "moveb %%d0, 0xec090000\n\t"
579 + : : : "%d0");
580 +}
581 +
582 +static void coldfire_get_model(char *model)
583 +{
584 + sprintf(model, "Version 4 ColdFire");
585 +}
586 +
587 +/*
588 + * Setup the nodes and the boot memory.
589 + *
590 + * memory_start and memory_end are VIRTUAL addresses
591 + */
592 +static void __init
593 +coldfire_bootmem_alloc(unsigned long memory_start, unsigned long memory_end)
594 +{
595 + unsigned long base_pfn;
596 +
597 + /* compute total pages in system */
598 + num_pages = PAGE_ALIGN(memory_end - PAGE_OFFSET) >> PAGE_SHIFT;
599 +
600 + /* align start/end to page boundries */
601 + memory_start = PAGE_ALIGN(memory_start);
602 + memory_end = memory_end & PAGE_MASK;
603 +
604 + /* page numbers */
605 + base_pfn = __pa(PAGE_OFFSET) >> PAGE_SHIFT;
606 + min_low_pfn = __pa(memory_start) >> PAGE_SHIFT;
607 + max_low_pfn = __pa(memory_end) >> PAGE_SHIFT;
608 +
609 + high_memory = (void *)memory_end;
610 + availmem = memory_start;
611 +
612 + /* setup bootmem data */
613 + m68k_setup_node(0);
614 + availmem += init_bootmem_node(NODE_DATA(0), min_low_pfn,
615 + base_pfn, max_low_pfn);
616 + availmem = PAGE_ALIGN(availmem);
617 +
618 + printk(KERN_INFO "** availmem=0x%lx pa(am)=0x%lx\n",
619 + availmem, __pa(availmem));
620 + printk(KERN_INFO "** mstart=0x%lx mend=0x%lx\n",
621 + memory_start, memory_end);
622 + printk(KERN_INFO "bpfn=0x%lx minpfn=0x%lx maxpfn=0x%lx\n",
623 + base_pfn, min_low_pfn, max_low_pfn);
624 +
625 + /* turn over physram */
626 + free_bootmem(__pa(availmem), memory_end - availmem);
627 +
628 + /* configure physical dma area */
629 + cf_dma_base = __pa(PAGE_ALIGN(memory_start));
630 + cf_dma_size = CONFIG_DMA_SIZE;
631 + cf_dma_end = CONFIG_SDRAM_BASE + cf_dma_size - 1;
632 +
633 + printk(KERN_INFO "dma: phys base=0x%lx phys end=0x%lx virt base=0x%x\n",
634 + cf_dma_base, cf_dma_end, CONFIG_DMA_BASE);
635 +
636 + printk(KERN_INFO "mdma=0x%x pa(mdma)=0x%lx\n",
637 + MAX_DMA_ADDRESS, __pa(MAX_DMA_ADDRESS));
638 +}
639 +
640 +/*
641 + * Architecture setup for Coldfire
642 + */
643 +void __init config_coldfire(void)
644 +{
645 + unsigned long endmem, startmem;
646 +
647 + /*
648 + * Calculate endmem from m68k_memory[0] assuming that a single
649 + * chunk of ram is being configured.
650 + */
651 + startmem = ((((int) &_end) + (PAGE_SIZE - 1)) & PAGE_MASK);
652 + endmem = PAGE_OFFSET + m68k_memory[0].size;
653 +
654 + /* set virt to node shift to be the high nibble byte */
655 + m68k_virt_to_node_shift = 28;
656 +
657 + printk(KERN_INFO "starting up linux startmem 0x%lx, endmem 0x%lx, \
658 + size %luMB\n", startmem, endmem, (endmem - startmem) >> 20);
659 +
660 + memset(irq_enable, 0, sizeof(irq_enable));
661 +
662 +/* JKM -- moved early*/
663 +/*register_console(&mcfrs_console);*/
664 +
665 + /*
666 + * Setup coldfire mach-specific handlers
667 + */
668 + mach_max_dma_address = 0xffffffff;
669 + mach_sched_init = coldfire_sched_init;
670 + mach_tick = coldfire_tick;
671 + mach_gettimeoffset = coldfire_gettimeoffset;
672 + mach_reset = coldfire_reboot;
673 + mach_get_model = coldfire_get_model;
674 +
675 + coldfire_bootmem_alloc(startmem, endmem-1);
676 +
677 +#if defined(CONFIG_DUMMY_CONSOLE) || defined(CONFIG_FRAMEBUFFER_CONSOLE)
678 + conswitchp = &dummy_con;
679 +#endif
680 +
681 +#if defined(CONFIG_SERIAL_COLDFIRE)
682 + /*
683 + * This causes trouble when it is re-registered later.
684 + * Currently this is fixed by conditionally commenting
685 + * out the register_console in mcf_serial.c
686 + */
687 +/*JKM -- moved earlier*/
688 + register_console(&mcfrs_console);
689 +#endif
690 +}
691 +
692 +#ifdef CONFIG_SRAM
693 +static int __init setup_sram_pool(void)
694 +{
695 + declare_sram_pool((void *)CONFIG_SRAM_BASE, CONFIG_SRAM_SIZE);
696 + return 0;
697 +}
698 +postcore_initcall(setup_sram_pool);
699 +#endif
700 --- /dev/null
701 +++ b/arch/m68k/coldfire/m5441x/devices.c
702 @@ -0,0 +1,787 @@
703 +/*
704 + * Coldfire M5441x Platform Device Configuration
705 + *
706 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
707 + *
708 + * Lanttor.Guo@freescale.com
709 + *
710 + * This program is free software; you can redistribute it and/or modify
711 + * it under the terms of the GNU General Public License as published by
712 + * the Free Software Foundation; either version 2 of the License, or
713 + * (at your option) any later version.
714 + */
715 +#include <linux/module.h>
716 +#include <linux/kernel.h>
717 +#include <linux/init.h>
718 +#include <linux/platform_device.h>
719 +#include <linux/fsl_devices.h>
720 +#include <linux/spi/spi.h>
721 +#include <linux/spi/flash.h>
722 +#include <linux/i2c.h>
723 +
724 +#include <linux/interrupt.h>
725 +#include <linux/init.h>
726 +#include <linux/mtd/partitions.h>
727 +#ifdef CONFIG_MMC_SPI
728 +#include <linux/mmc/host.h>
729 +#include <linux/spi/mmc_spi.h>
730 +#endif
731 +
732 +#include <asm/coldfire.h>
733 +#include <asm/mcfsim.h>
734 +#include <asm/mcfuart.h>
735 +#include <asm/mcfqspi.h>
736 +#include <asm/mcfdspi.h>
737 +#include <asm/cf_io.h>
738 +
739 +/*
740 + * I2C: only support i2c0 module on m5441x platform
741 + */
742 +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
743 +static struct resource coldfire_i2c_resources[] = {
744 + { /* I/O */
745 + .start = 0xFC058000,
746 + .end = 0xFC058010,
747 + .flags = IORESOURCE_MEM,
748 + },
749 + { /* IRQ */
750 + .start = (64 + 30),
751 + .end = (64 + 30),
752 + .flags = IORESOURCE_IRQ,
753 + },
754 +};
755 +
756 +static struct platform_device coldfire_i2c_device = {
757 + .name = "mcf-i2c",
758 + .id = 0, /*bus number*/
759 + .num_resources = ARRAY_SIZE(coldfire_i2c_resources),
760 + .resource = coldfire_i2c_resources,
761 +};
762 +
763 +static void mcf5441x_init_i2c(void)
764 +{
765 + MCF_PM_PPMCR0 = 22;
766 + platform_device_register(&coldfire_i2c_device);
767 +}
768 +
769 +#ifdef CONFIG_I2C_BOARDINFO
770 +static struct i2c_board_info mcf_i2c_devices[] = {
771 +#ifdef CONFIG_USB_M5441X_MAX3353_FSLS
772 + {
773 + I2C_BOARD_INFO("max3353", 0x2c),
774 + },
775 +#endif
776 +};
777 +#endif
778 +
779 +#endif
780 +
781 +#if defined(CONFIG_MMC_ESDHC)
782 +static struct resource sd_mmc_esdhc_resources[] = {
783 + [0] = {
784 + .name = "esdhc-module",
785 + .start = 0xFC0CC000,
786 + .end = 0xFC0CC000 + 0x100,
787 + .flags = IORESOURCE_MEM,
788 + },
789 + [1] = {
790 + .name = "esdhc-int-level",
791 + .start = (64 + 64 + 64 + 31),
792 + .end = (64 + 64 + 64 + 31),
793 + .flags = IORESOURCE_IRQ,
794 + },
795 + [2] = {
796 + .name = "esdhc-pin",
797 + .start = &MCF_GPIO_PAR_ESDHCH,
798 + .end = &MCF_GPIO_PAR_ESDHCL,
799 + .flags = IORESOURCE_MEM,
800 + },
801 + [3] = {
802 + .name = "esdhc-slew",
803 + .start = &MCF_GPIO_SRCR_SDHC,
804 + .end = &MCF_GPIO_SRCR_SDHC,
805 + .flags = IORESOURCE_MEM,
806 + },
807 +};
808 +
809 +static struct platform_device sd_mmc_esdhc_device = {
810 + .name = "esdhc",
811 + .id = -1,
812 + .resource = sd_mmc_esdhc_resources,
813 + .num_resources = ARRAY_SIZE(sd_mmc_esdhc_resources),
814 +};
815 +#endif
816 +
817 +#if defined(CONFIG_MTD_NAND_FSL_NFC)
818 +static struct resource nfc_resources[] = {
819 + [0] = {
820 + .name = "nfc-config",
821 + .start = 0xFC0FC000,
822 + .end = 0xFC0FFF3B,
823 + .flags = IORESOURCE_MEM,
824 +
825 + },
826 + [1] = {
827 + .name = "nfc-int-level",
828 + .start = (64 + 64 + 64 + 25),
829 + .end = (64 + 64 + 64 + 25),
830 + .flags = IORESOURCE_IRQ,
831 + },
832 +
833 +};
834 +static struct platform_device nfc_device = {
835 + .name = "fsl_nfc",
836 + .id = -1,
837 + .resource = nfc_resources,
838 + .num_resources = ARRAY_SIZE(nfc_resources),
839 +};
840 +#endif
841 +
842 +/*
843 + * DSPI
844 + */
845 +#ifdef CONFIG_SPI
846 +
847 +#if defined(CONFIG_DSPI0) /* DSPI0 initialization */
848 +#define M5441X_DSPI0_MCR 0xFC05C000 /* base */
849 +
850 +#define M5441X_DSPI0_IRQ_SOURCE (31)
851 +#define M5441X_DSPI0_IRQ_VECTOR (64 + M5441X_DSPI0_IRQ_SOURCE)
852 +
853 +/* number of supported SPI selects */
854 +#define SPI_NUM_CHIPSELECTS 8
855 +
856 +#define M5441X_SPI0_PAR_VAL (MCF_GPIO_PAR_DSPI0_SCK_DSPI0SCK | \
857 + MCF_GPIO_PAR_DSPI0_SOUT_DSPI0SOUT | \
858 + MCF_GPIO_PAR_DSPI0_SIN_DSPI0SIN | \
859 + MCF_GPIO_PAR_DSPI0_PCS0_DSPI0PCS0)
860 +
861 +
862 +#ifdef CONFIG_MTD_PARTITIONS
863 +static struct mtd_partition at26df081a_partitions[] = {
864 + {
865 + .name = "at26df081a",
866 + .size = (1024*64*16),
867 + .offset = 0x00000000,
868 + .mask_flags = 0,
869 + }
870 +};
871 +#endif
872 +
873 +#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
874 +static struct flash_platform_data at26df081a_platform_data = {
875 + .name = "Atmel at26df081a SPI Flash chip",
876 +#ifdef CONFIG_MTD_PARTITIONS
877 + .parts = at26df081a_partitions,
878 + .nr_parts =
879 + sizeof(at26df081a_partitions) / sizeof(*at26df081a_partitions),
880 +#endif
881 + .type = "at26df081a"
882 +};
883 +
884 +static struct coldfire_dspi_chip at26df081a_chip_info = {
885 + .mode = SPI_MODE_0,
886 + .bits_per_word = 16, /* How many bits per word to transfer
887 + per one time (8 or 16) */
888 + .void_write_data = 0,
889 + .dbr = 0,
890 + .pbr = 0,
891 + .br = 0,
892 + .pcssck = 1,
893 + .pasc = 1,
894 + .pdt = 1,
895 + .cssck = 4,
896 + .asc = 4,
897 + .dt = 14,
898 +};
899 +#endif
900 +
901 +#if defined(CONFIG_FB_FSL_SSD1289) || defined(CONFIG_FB_FSL_SSD1289_MODULE)
902 +static struct fsl_ssd1289_fb_display fsl_ssd1289_data = {
903 + .width = 320,
904 + .height = 240,
905 + .xres = 320,
906 + .yres = 240,
907 + .bpp = 16,
908 +};
909 +#endif
910 +
911 +#if defined(CONFIG_SSD1289_SPI_MODE)
912 +static struct coldfire_dspi_chip ssd1289_chip_info = {
913 + .mode = SPI_MODE_0,
914 + .bits_per_word = 9,
915 + .void_write_data = 0,
916 + .dbr = 0,
917 + .pbr = 0,
918 + .br = 1,
919 + .pcssck = 0,
920 + .pasc = 0,
921 + .pdt = 0,
922 + .cssck = 0,
923 + .asc = 0,
924 + .dt = 0,
925 +};
926 +#endif
927 +
928 +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
929 +static struct coldfire_dspi_chip spidev_chip_info = {
930 + .bits_per_word = 8,
931 +};
932 +#endif
933 +
934 +
935 +static struct coldfire_spi_master spi0_master_info = {
936 + .bus_num = 1,
937 + .num_chipselect = SPI_NUM_CHIPSELECTS,
938 + .irq_list = 0, /* not used */
939 + .irq_source = M5441X_DSPI0_IRQ_SOURCE,
940 + .irq_vector = M5441X_DSPI0_IRQ_VECTOR,
941 + .irq_mask = (1 << M5441X_DSPI0_IRQ_SOURCE),
942 + .irq_lp = 0x2, /* irq level */
943 + .par_val = M5441X_SPI0_PAR_VAL,
944 + .cs_control = NULL,
945 +};
946 +
947 +static struct resource coldfire_spi0_resources[] = {
948 + [0] = {
949 + .name = "spi-par",
950 + .start = (u32)&MCF_GPIO_PAR_DSPI0WH, /* PAR_DSPI0 */
951 + .end = (u32)&MCF_GPIO_PAR_DSPI0WH, /* PAR_DSPI0 */
952 + .flags = IORESOURCE_MEM
953 + },
954 +
955 + [1] = {
956 + .name = "spi-module",
957 + .start = M5441X_DSPI0_MCR, /* DSPI MCR Base */
958 + .end = M5441X_DSPI0_MCR + 0xc0, /* DSPI mem map end */
959 + .flags = IORESOURCE_MEM
960 + },
961 +
962 + [2] = {
963 + .name = "spi-int-level",
964 + .start = (u32)&MCF_INTC0_ICR31, /* ICR start */
965 + .end = (u32)&MCF_INTC0_ICR31, /* ICR end */
966 + .flags = IORESOURCE_MEM
967 + },
968 +
969 + [3] = {
970 + .name = "spi-int-mask",
971 + .start = (u32)&MCF_INTC0_IMRL, /* IMRL */
972 + .end = (u32)&MCF_INTC0_IMRL, /* IMRL */
973 + .flags = IORESOURCE_MEM
974 + }
975 +};
976 +
977 +static struct platform_device coldfire_spi0 = {
978 + .name = "spi_coldfire",
979 + .id = -1,
980 + .resource = coldfire_spi0_resources,
981 + .num_resources = ARRAY_SIZE(coldfire_spi0_resources),
982 + .dev = {
983 + .platform_data = &spi0_master_info,
984 + }
985 +};
986 +
987 +#elif defined(CONFIG_DSPI1) /* DSPI1 initialization */
988 +#define M5441X_DSPI1_MCR 0xFC03C000 /* base */
989 +
990 +#define M5441X_DSPI1_IRQ_SOURCE (54)
991 +#define M5441X_DSPI1_IRQ_VECTOR (64 + 64 + M5441X_DSPI1_IRQ_SOURCE)
992 +
993 +/* number of supported SPI selects */
994 +#define SPI_NUM_CHIPSELECTS 8
995 +
996 +
997 +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
998 +static struct coldfire_dspi_chip spidev_chip_info = {
999 + .bits_per_word = 8,
1000 +};
1001 +#endif
1002 +
1003 +static struct coldfire_spi_master spi1_master_info = {
1004 + .bus_num = 1,
1005 + .num_chipselect = SPI_NUM_CHIPSELECTS,
1006 + .irq_list = 0, /* not used */
1007 + .irq_source = M5441X_DSPI1_IRQ_SOURCE,
1008 + .irq_vector = M5441X_DSPI1_IRQ_VECTOR,
1009 + .irq_mask = (1 << (M5441X_DSPI1_IRQ_SOURCE - 32)),
1010 + .irq_lp = 0x2, /* irq level */
1011 + .cs_control = NULL,
1012 +};
1013 +
1014 +static struct resource coldfire_spi1_resources[] = {
1015 + [0] = {
1016 + .name = "spi-par",
1017 + .start = (u32)&MCF_GPIO_PAR_ESDHCH, /* PAR_ESDHCH */
1018 + .end = (u32)&MCF_GPIO_PAR_ESDHCL, /* PAR_ESDHCL */
1019 + .flags = IORESOURCE_MEM
1020 + },
1021 +
1022 + [1] = {
1023 + .name = "spi-module",
1024 + .start = M5441X_DSPI1_MCR, /* DSPI MCR Base */
1025 + .end = M5441X_DSPI1_MCR + 0xc0, /* DSPI mem map end */
1026 + .flags = IORESOURCE_MEM
1027 + },
1028 +
1029 + [2] = {
1030 + .name = "spi-int-level",
1031 + .start = (u32)&MCF_INTC1_ICR54, /* ICR start */
1032 + .end = (u32)&MCF_INTC1_ICR54, /* ICR end */
1033 + .flags = IORESOURCE_MEM
1034 + },
1035 +
1036 + [3] = {
1037 + .name = "spi-int-mask",
1038 + .start = (u32)&MCF_INTC1_IMRH, /* IMRL */
1039 + .end = (u32)&MCF_INTC1_IMRH, /* IMRL */
1040 + .flags = IORESOURCE_MEM
1041 + }
1042 +};
1043 +
1044 +static struct platform_device coldfire_spi1 = {
1045 + .name = "spi_coldfire",
1046 + .id = -1,
1047 + .resource = coldfire_spi1_resources,
1048 + .num_resources = ARRAY_SIZE(coldfire_spi1_resources),
1049 + .dev = {
1050 + .platform_data = &spi1_master_info,
1051 + }
1052 +};
1053 +
1054 +#ifdef CONFIG_MMC_SPI
1055 +static struct coldfire_dspi_chip dspi_sd_chip_info = {
1056 + .mode = SPI_MODE_0,
1057 + .bits_per_word = 8,
1058 + .void_write_data = 0xff,
1059 + .dbr = 0,
1060 + .pbr = 1,
1061 + .br = 1,
1062 + .pcssck = 2,
1063 + .pasc = 2,
1064 + .pdt = 2,
1065 + .cssck = 5,
1066 + .asc = 5,
1067 + .dt = 5,
1068 +};
1069 +
1070 +int mmc_spi_init(struct device *mmc_spi_device,
1071 + irqreturn_t mmc_spi_irq_handler(int irq, void *private),
1072 + void *irq_privatedata)
1073 +{
1074 + int ret;
1075 +#if defined(CONFIG_DETECT_USE_EXTERN_IRQ1)
1076 + int card_detect_extern_irq = 64 + 1;
1077 + /*this is irq1 hardware work round*/
1078 + MCF_GPIO_PAR_IRQ0H |= 0x3;
1079 +
1080 + MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA1_BOTH;
1081 + MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE1;
1082 +
1083 + MCF_INTC0_ICR1 = 7; /* IRQ1 */
1084 +#if debug_mmc_spi
1085 + printk(KERN_INFO "MCF_INTC0_ICR1 %x MCF_EPORT_EPPAR %x "
1086 + "MCF_EPORT_EPFR %x MCF_EPORT_EPIER %x "
1087 + "MCF_INTC0_IMRL %x MCF_INTC0_INTFRCL %x "
1088 + "MCF_INTC0_IPRL %x\n",
1089 + MCF_INTC0_ICR1, MCF_EPORT_EPPAR, MCF_EPORT_EPFR,
1090 + MCF_EPORT_EPIER, MCF_INTC0_IMRL, MCF_INTC0_INTFRCL,
1091 + MCF_INTC0_IPRL);
1092 +#endif
1093 +#elif defined(CONFIG_DETECT_USE_EXTERN_IRQ7)
1094 + int card_detect_extern_irq = 64 + 7;
1095 + MCF_GPIO_PAR_IRQ0H |= MCF_GPIO_PAR_IRQH_IRQ7;
1096 +
1097 + MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_BOTH;
1098 + MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7;
1099 +
1100 + MCF_INTC0_ICR7 = 2; /* IRQ7 */
1101 +#ifdef debug_mmc_spi
1102 + printk("MCF_INTC0_ICR7 %x MCF_EPORT_EPPAR %x\n",
1103 + MCF_INTC0_ICR7, MCF_EPORT_EPPAR);
1104 +#endif
1105 +#else
1106 + int card_detect_extern_irq = 64 + 7;
1107 + MCF_GPIO_PAR_IRQ0H |= MCF_GPIO_PAR_IRQH_IRQ7;
1108 +
1109 + MCF_EPORT_EPPAR = MCF_EPORT_EPPAR | MCF_EPORT_EPPAR_EPPA7_BOTH;
1110 + MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7;
1111 +
1112 + MCF_INTC0_ICR7 = 2; /* IRQ7 */
1113 +#ifdef debug_mmc_spi
1114 + printk(KERN_INFO "MCF_INTC0_ICR1 %x MCF_EPORT_EPPAR %x\n",
1115 + MCF_INTC0_ICR7, MCF_EPORT_EPPAR);
1116 +#endif
1117 +#endif
1118 +
1119 + ret = request_irq(card_detect_extern_irq,
1120 + mmc_spi_irq_handler, IRQF_DISABLED,
1121 + "mmc_spi_irq", irq_privatedata);
1122 + if (ret) {
1123 + printk(KERN_INFO "%s: request irq fail %x\n", __func__, ret);
1124 + return -EBUSY;
1125 + }
1126 +
1127 + return 0;
1128 +}
1129 +
1130 +static struct mmc_spi_platform_data mcf5441x_mmc_pdata = {
1131 + .ocr_mask = MMC_VDD_33_34,
1132 + .init = mmc_spi_init,
1133 +};
1134 +#endif
1135 +
1136 +#endif
1137 +
1138 +/* DSPI device */
1139 +static struct spi_board_info spi_board_info[] = {
1140 +
1141 +#if defined(CONFIG_DSPI1) && defined(CONFIG_MMC_SPI)
1142 + {
1143 + .modalias = "mmc_spi",
1144 + .max_speed_hz = 50000000,
1145 + .bus_num = 1,
1146 + .chip_select = 0,
1147 + .platform_data = &mcf5441x_mmc_pdata,
1148 + .controller_data = &dspi_sd_chip_info,
1149 + },
1150 +#endif
1151 +#if defined(CONFIG_DSPI0) && (defined(CONFIG_MTD_M25P80) || \
1152 + defined(CONFIG_MTD_M25P80_MODULE))
1153 + {
1154 + .modalias = "m25p80", /* Name of spi driver for this device */
1155 + .max_speed_hz = 70000000, /* max spi clock in HZ */
1156 + .bus_num = 1,
1157 + .chip_select = CONFIG_DSP0_SBF_CS,
1158 + .platform_data = &at26df081a_platform_data,
1159 + .controller_data = &at26df081a_chip_info
1160 + },
1161 +#endif
1162 +
1163 +#if defined(CONFIG_DSPI0) && defined(CONFIG_SSD1289_SPI_MODE)
1164 + {
1165 + .modalias = "spi-ssd1289",
1166 + .max_speed_hz = 50000000,
1167 + .bus_num = 1,
1168 + .chip_select = 0,
1169 + .platform_data = &fsl_ssd1289_data,
1170 + .controller_data = &ssd1289_chip_info
1171 + },
1172 +#endif
1173 +
1174 +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
1175 + {
1176 + .modalias = "spidev",
1177 + .max_speed_hz = 16000000, /* max clk (SCK) speed in HZ */
1178 + .bus_num = 1,
1179 + .chip_select = 0, /* CS0 */
1180 + .controller_data = &spidev_chip_info,
1181 + },
1182 +#endif
1183 +};
1184 +
1185 +/*
1186 + * m5441x_spi_init - Initialize SPI
1187 + */
1188 +static int __init m5441x_spi_init(void)
1189 +{
1190 + int retval;
1191 +
1192 + /* register device */
1193 +#if defined(CONFIG_DSPI0)
1194 + MCF_GPIO_PAR_DSPI0WH =
1195 + (MCF_GPIO_PAR_DSPI0WH & MCF_GPIO_PAR_DSPI0_SCK_MASK) |
1196 + MCF_GPIO_PAR_DSPI0_SCK_DSPI0SCK;
1197 + MCF_GPIO_PAR_DSPI0WH =
1198 + (MCF_GPIO_PAR_DSPI0WH & MCF_GPIO_PAR_DSPI0_SOUT_MASK) |
1199 + MCF_GPIO_PAR_DSPI0_SOUT_DSPI0SOUT;
1200 + MCF_GPIO_PAR_DSPI0WH =
1201 + (MCF_GPIO_PAR_DSPI0WH & MCF_GPIO_PAR_DSPI0_SIN_MASK) |
1202 + MCF_GPIO_PAR_DSPI0_SIN_DSPI0SIN;
1203 + MCF_GPIO_PAR_DSPI0WH =
1204 + (MCF_GPIO_PAR_DSPI0WH & MCF_GPIO_PAR_DSPI0_PCS0_MASK) |
1205 + MCF_GPIO_PAR_DSPI0_PCS0_DSPI0PCS0;
1206 + MCF_GPIO_PAR_DSPI0WL = 0x80;
1207 + retval = platform_device_register(&coldfire_spi0);
1208 + if (retval < 0)
1209 + goto out;
1210 +#elif defined(CONFIG_DSPI1)
1211 + MCF_PM_PPMCR0 = 0xf;
1212 + MCF_GPIO_PAR_ESDHCH = 0x55; /* DAT[3:0] */
1213 + MCF_GPIO_PAR_ESDHCL = 0x05; /* CMD, CLK */
1214 + MCF_GPIO_SRCR_IRQ0 = 3;
1215 + MCF_GPIO_SRCR_SDHC = 3;
1216 + retval = platform_device_register(&coldfire_spi1);
1217 + if (retval < 0)
1218 + goto out;
1219 +#endif
1220 +
1221 + /* register board info */
1222 + if (ARRAY_SIZE(spi_board_info))
1223 + retval = spi_register_board_info(spi_board_info,
1224 + ARRAY_SIZE(spi_board_info));
1225 +
1226 +out:
1227 + return retval;
1228 +}
1229 +#endif
1230 +
1231 +#if defined(CONFIG_SERIAL_MCF) || defined(CONFIG_SERIAL_MCF_MODULE)
1232 +/*
1233 + * UART initialization
1234 + */
1235 +static struct mcf_platform_uart m5441x_uart_platform[] = {
1236 +#ifdef CONFIG_SERIAL_MCF_UART0
1237 + {
1238 + .mapbase = MCFUART_BASE0,
1239 + .irq = MCFINT0_VECBASE + MCFINT_UART0,
1240 + },
1241 +#endif
1242 +#ifdef CONFIG_SERIAL_MCF_UART1
1243 + {
1244 + .mapbase = MCFUART_BASE1,
1245 + .irq = MCFINT0_VECBASE + MCFINT_UART1,
1246 + },
1247 +#endif
1248 +#ifdef CONFIG_SERIAL_MCF_UART2
1249 + {
1250 + .mapbase = MCFUART_BASE2,
1251 + .irq = MCFINT0_VECBASE + MCFINT_UART2,
1252 + },
1253 +#endif
1254 +#ifdef CONFIG_SERIAL_MCF_UART3
1255 + {
1256 + .mapbase = MCFUART_BASE3,
1257 + .irq = MCFINT0_VECBASE + MCFINT_UART3,
1258 + },
1259 +#endif
1260 +#ifdef CONFIG_SERIAL_MCF_UART4
1261 + {
1262 + .mapbase = MCFUART_BASE4,
1263 + .irq = MCFINT1_VECBASE + MCFINT_UART4,
1264 + },
1265 +#endif
1266 +#ifdef CONFIG_SERIAL_MCF_UART5
1267 + {
1268 + .mapbase = MCFUART_BASE5,
1269 + .irq = MCFINT1_VECBASE + MCFINT_UART5,
1270 + },
1271 +#endif
1272 +#ifdef CONFIG_SERIAL_MCF_UART6
1273 + {
1274 + .mapbase = MCFUART_BASE6,
1275 + .irq = MCFINT1_VECBASE + MCFINT_UART6,
1276 + },
1277 +#endif
1278 +#ifdef CONFIG_SERIAL_MCF_UART7
1279 + {
1280 + .mapbase = MCFUART_BASE7,
1281 + .irq = MCFINT1_VECBASE + MCFINT_UART7,
1282 + },
1283 +#endif
1284 +#ifdef CONFIG_SERIAL_MCF_UART8
1285 + {
1286 + .mapbase = MCFUART_BASE8,
1287 + .irq = MCFINT1_VECBASE + MCFINT_UART8,
1288 + },
1289 +#endif
1290 +#ifdef CONFIG_SERIAL_MCF_UART9
1291 + {
1292 + .mapbase = MCFUART_BASE9,
1293 + .irq = MCFINT1_VECBASE + MCFINT_UART9,
1294 + },
1295 +#endif
1296 + {}
1297 +};
1298 +
1299 +static struct platform_device m5441x_uart = {
1300 + .name = "mcfuart",
1301 + .id = 0,
1302 + .dev.platform_data = m5441x_uart_platform,
1303 +};
1304 +
1305 +static void m5441x_uarts_init(void)
1306 +{
1307 +#ifdef CONFIG_SERIAL_MCF_UART0
1308 + /* enable uart0 clock */
1309 + MCF_PM_PPMCR0 = 24;
1310 + /* gpio pin assignment for uart0 */
1311 + MCF_GPIO_PAR_UART0 =
1312 + (MCF_GPIO_PAR_UART0 & MCF_GPIO_PAR_UART0_U0RXD_MASK) |
1313 + MCF_GPIO_PAR_UART0_U0RXD_U0RXD;
1314 + MCF_GPIO_PAR_UART0 =
1315 + (MCF_GPIO_PAR_UART0 & MCF_GPIO_PAR_UART0_U0TXD_MASK) |
1316 + MCF_GPIO_PAR_UART0_U0TXD_U0TXD;
1317 +#endif
1318 +#ifdef CONFIG_SERIAL_MCF_UART1
1319 + /* enable uart1 clock */
1320 + MCF_PM_PPMCR0 = 25;
1321 + /* gpio pin assignment for uart1 */
1322 + MCF_GPIO_PAR_UART1 =
1323 + (MCF_GPIO_PAR_UART1 & MCF_GPIO_PAR_UART1_U1RXD_MASK) |
1324 + MCF_GPIO_PAR_UART1_U1RXD_U1RXD;
1325 + MCF_GPIO_PAR_UART1 =
1326 + (MCF_GPIO_PAR_UART1 & MCF_GPIO_PAR_UART1_U1TXD_MASK) |
1327 + MCF_GPIO_PAR_UART1_U1TXD_U1TXD;
1328 +#endif
1329 +#ifdef CONFIG_SERIAL_MCF_UART2
1330 + /* enable uart2 clock */
1331 + MCF_PM_PPMCR0 = 26;
1332 + /* gpio pin assignment for uart2 */
1333 + MCF_GPIO_PAR_UART2 =
1334 + (MCF_GPIO_PAR_UART2 & MCF_GPIO_PAR_UART2_U2RXD_MASK) |
1335 + MCF_GPIO_PAR_UART2_U2RXD_U2RXD;
1336 + MCF_GPIO_PAR_UART2 =
1337 + (MCF_GPIO_PAR_UART2 & MCF_GPIO_PAR_UART2_U2TXD_MASK) |
1338 + MCF_GPIO_PAR_UART2_U2TXD_U2TXD;
1339 +#endif
1340 +#ifdef CONFIG_SERIAL_MCF_UART3
1341 + /* enable uart3 clock */
1342 + MCF_PM_PPMCR0 = 27;
1343 + /* gpio pin assignment for uart3 */
1344 + MCF_GPIO_PAR_DSPI0WH =
1345 + (MCF_GPIO_PAR_DSPI0WH & MCF_GPIO_PAR_DSPI0_SIN_MASK) |
1346 + MCF_GPIO_PAR_DSPI0_SIN_U3RXD;
1347 + MCF_GPIO_PAR_DSPI0WH =
1348 + (MCF_GPIO_PAR_DSPI0WH & MCF_GPIO_PAR_DSPI0_SOUT_MASK) |
1349 + MCF_GPIO_PAR_DSPI0_SOUT_U3TXD;
1350 +#endif
1351 +#ifdef CONFIG_SERIAL_MCF_UART4
1352 + /* enable uart4 clock */
1353 + MCF_PM_PPMCR1 = 24;
1354 + /* gpio pin assignment for uart4 */
1355 + MCF_GPIO_PAR_UART0 =
1356 + (MCF_GPIO_PAR_UART0 & MCF_GPIO_PAR_UART0_U0RTS_MASK) |
1357 + MCF_GPIO_PAR_UART0_U0RTS_U4RXD;
1358 + MCF_GPIO_PAR_UART0 =
1359 + (MCF_GPIO_PAR_UART0 & MCF_GPIO_PAR_UART0_U0CTS_MASK) |
1360 + MCF_GPIO_PAR_UART0_U0CTS_U4TXD;
1361 +#endif
1362 +#ifdef CONFIG_SERIAL_MCF_UART5
1363 + /* enable uart5 clock */
1364 + MCF_PM_PPMCR1 = 25;
1365 + /* gpio pin assignment for uart5 */
1366 + MCF_GPIO_PAR_UART1 =
1367 + (MCF_GPIO_PAR_UART1 & MCF_GPIO_PAR_UART1_U1RTS_MASK) |
1368 + MCF_GPIO_PAR_UART1_U1RTS_U5RXD;
1369 + MCF_GPIO_PAR_UART1 =
1370 + (MCF_GPIO_PAR_UART1 & MCF_GPIO_PAR_UART1_U1CTS_MASK) |
1371 + MCF_GPIO_PAR_UART1_U1CTS_U5TXD;
1372 +#endif
1373 +#ifdef CONFIG_SERIAL_MCF_UART6
1374 + /* enable uart6 clock */
1375 + MCF_PM_PPMCR1 = 26;
1376 + /* gpio pin assignment for uart6 */
1377 + MCF_GPIO_PAR_UART2 =
1378 + (MCF_GPIO_PAR_UART2 & MCF_GPIO_PAR_UART2_U2RTS_MASK) |
1379 + MCF_GPIO_PAR_UART2_U2RTS_U6RXD;
1380 + MCF_GPIO_PAR_UART2 =
1381 + (MCF_GPIO_PAR_UART2 & MCF_GPIO_PAR_UART2_U2CTS_MASK) |
1382 + MCF_GPIO_PAR_UART2_U2CTS_U6TXD;
1383 +#endif
1384 +#ifdef CONFIG_SERIAL_MCF_UART7
1385 + /* enable uart7 clock */
1386 + MCF_PM_PPMCR1 = 27;
1387 + /* gpio pin assignment for uart7 */
1388 + MCF_GPIO_PAR_SSI0H &= (MCF_GPIO_PAR_SSI0H_FS_MASK);
1389 + MCF_GPIO_PAR_SSI0H |= (MCF_GPIO_PAR_SSI0H_FS_U7TXD);
1390 + MCF_GPIO_PAR_SSI0L &= (MCF_GPIO_PAR_SSI0L_BCLK_MASK);
1391 + MCF_GPIO_PAR_SSI0L |= (MCF_GPIO_PAR_SSI0L_BCLK_U7RXD);
1392 +#endif
1393 +#ifdef CONFIG_SERIAL_MCF_UART8
1394 + /* enable uart8 clock */
1395 + MCF_PM_PPMCR1 = 28;
1396 + /* gpio pin assignment for uart8 */
1397 + MCF_GPIO_PAR_CANI2C =
1398 + (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_I2C0SCL_MASK) |
1399 + MCF_GPIO_PAR_CANI2C_I2C0SCL_U8TXD;
1400 + MCF_GPIO_PAR_CANI2C =
1401 + (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_I2C0SDA_MASK) |
1402 + MCF_GPIO_PAR_CANI2C_I2C0SDA_U8RXD;
1403 +#endif
1404 +#ifdef CONFIG_SERIAL_MCF_UART9
1405 + /* enable uart4 clock */
1406 + MCF_PM_PPMCR1 = 29;
1407 + /* gpio pin assignment for uart9 */
1408 + MCF_GPIO_PAR_CANI2C =
1409 + (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_CAN1TX_MASK) |
1410 + MCF_GPIO_PAR_CANI2C_CAN1TX_U9TXD;
1411 + MCF_GPIO_PAR_CANI2C =
1412 + (MCF_GPIO_PAR_CANI2C & MCF_GPIO_PAR_CANI2C_CAN1RX_MASK) |
1413 + MCF_GPIO_PAR_CANI2C_CAN1RX_U9RXD;
1414 +#endif
1415 +}
1416 +#endif
1417 +
1418 +#if defined(CONFIG_RTC_M5441X) || defined(CONFIG_RTC_M5441X_MODULE)
1419 +/*
1420 + * RTC initialization
1421 + */
1422 +static struct platform_device rtc_device = {
1423 + .name = "rtc-m5441x",
1424 + .id = -1,
1425 +};
1426 +
1427 +static void m5441x_rtc_init(void)
1428 +{
1429 + /* Power management: enable RTC clock */
1430 + MCF_PM_PPMCR0 = 42;
1431 +}
1432 +#endif
1433 +
1434 +
1435 +#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
1436 +static struct platform_device fsl_ssd1289_device = {
1437 + .name = "fsl-ssd1289",
1438 + .id = -1,
1439 + .dev = {
1440 + .platform_data = &fsl_ssd1289_data,
1441 + },
1442 +};
1443 +#endif
1444 +
1445 +static struct platform_device *m5441x_devices[] __initdata = {
1446 +#if defined(CONFIG_SERIAL_MCF) || defined(CONFIG_SERIAL_MCF_MODULE)
1447 + &m5441x_uart,
1448 +#endif
1449 +#if defined(CONFIG_RTC_M5441X) || defined(CONFIG_RTC_M5441X_MODULE)
1450 + &rtc_device,
1451 +#endif
1452 +#if defined(CONFIG_MMC_ESDHC)
1453 + &sd_mmc_esdhc_device,
1454 +#endif
1455 +#if defined(CONFIG_MTD_NAND_FSL_NFC)
1456 + &nfc_device,
1457 +#endif
1458 +#if defined(CONFIG_SSD1289_FLEXBUS_MODE)
1459 + &fsl_ssd1289_device,
1460 +#endif
1461 +};
1462 +
1463 +static int __init mcf5441x_init_devices(void)
1464 +{
1465 + printk(KERN_INFO "mcf5441x_init_devices: %s.\n", __func__);
1466 +
1467 +#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1468 +#ifdef CONFIG_I2C_BOARDINFO
1469 + i2c_register_board_info(0, mcf_i2c_devices,
1470 + ARRAY_SIZE(mcf_i2c_devices));
1471 +#endif
1472 + mcf5441x_init_i2c();
1473 +#endif
1474 +#if defined(CONFIG_SPI) || defined(CONFIG_SPI_MODULE)
1475 + m5441x_spi_init();
1476 +#endif
1477 +#if defined(CONFIG_SERIAL_MCF) || defined(CONFIG_SERIAL_MCF_MODULE)
1478 + m5441x_uarts_init();
1479 +#endif
1480 +#if defined(CONFIG_RTC_M5441X) || defined(CONFIG_RTC_M5441X_MODULE)
1481 + m5441x_rtc_init();
1482 +#endif
1483 + platform_add_devices(m5441x_devices, ARRAY_SIZE(m5441x_devices));
1484 + return 0;
1485 +}
1486 +
1487 +arch_initcall(mcf5441x_init_devices);
1488 +
1489 +
1490 --- /dev/null
1491 +++ b/arch/m68k/configs/m54418twr_defconfig
1492 @@ -0,0 +1,1244 @@
1493 +#
1494 +# Automatically generated make config: don't edit
1495 +# Linux kernel version: 2.6.29
1496 +# Fri Apr 23 14:36:43 2010
1497 +#
1498 +CONFIG_M68K=y
1499 +CONFIG_MMU=y
1500 +CONFIG_GENERIC_TIME=y
1501 +CONFIG_GENERIC_CLOCKEVENTS=y
1502 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
1503 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
1504 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
1505 +CONFIG_GENERIC_HWEIGHT=y
1506 +CONFIG_GENERIC_CALIBRATE_DELAY=y
1507 +# CONFIG_TIME_LOW_RES is not set
1508 +CONFIG_GENERIC_IOMAP=y
1509 +# CONFIG_NO_IOPORT is not set
1510 +# CONFIG_NO_DMA is not set
1511 +CONFIG_HZ=100
1512 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
1513 +
1514 +#
1515 +# General setup
1516 +#
1517 +CONFIG_EXPERIMENTAL=y
1518 +CONFIG_BROKEN_ON_SMP=y
1519 +CONFIG_INIT_ENV_ARG_LIMIT=32
1520 +CONFIG_LOCALVERSION=""
1521 +CONFIG_LOCALVERSION_AUTO=y
1522 +CONFIG_SWAP=y
1523 +CONFIG_SYSVIPC=y
1524 +CONFIG_SYSVIPC_SYSCTL=y
1525 +# CONFIG_POSIX_MQUEUE is not set
1526 +# CONFIG_BSD_PROCESS_ACCT is not set
1527 +# CONFIG_TASKSTATS is not set
1528 +# CONFIG_AUDIT is not set
1529 +
1530 +#
1531 +# RCU Subsystem
1532 +#
1533 +CONFIG_CLASSIC_RCU=y
1534 +# CONFIG_TREE_RCU is not set
1535 +# CONFIG_PREEMPT_RCU is not set
1536 +# CONFIG_TREE_RCU_TRACE is not set
1537 +# CONFIG_PREEMPT_RCU_TRACE is not set
1538 +CONFIG_IKCONFIG=y
1539 +CONFIG_IKCONFIG_PROC=y
1540 +CONFIG_LOG_BUF_SHIFT=17
1541 +CONFIG_GROUP_SCHED=y
1542 +CONFIG_FAIR_GROUP_SCHED=y
1543 +# CONFIG_RT_GROUP_SCHED is not set
1544 +CONFIG_USER_SCHED=y
1545 +# CONFIG_CGROUP_SCHED is not set
1546 +# CONFIG_CGROUPS is not set
1547 +CONFIG_SYSFS_DEPRECATED=y
1548 +CONFIG_SYSFS_DEPRECATED_V2=y
1549 +# CONFIG_RELAY is not set
1550 +# CONFIG_NAMESPACES is not set
1551 +CONFIG_BLK_DEV_INITRD=y
1552 +CONFIG_INITRAMFS_SOURCE=""
1553 +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
1554 +CONFIG_SYSCTL=y
1555 +CONFIG_ANON_INODES=y
1556 +CONFIG_EMBEDDED=y
1557 +CONFIG_UID16=y
1558 +CONFIG_SYSCTL_SYSCALL=y
1559 +CONFIG_KALLSYMS=y
1560 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
1561 +CONFIG_HOTPLUG=y
1562 +CONFIG_PRINTK=y
1563 +CONFIG_BUG=y
1564 +CONFIG_ELF_CORE=y
1565 +CONFIG_BASE_FULL=y
1566 +CONFIG_FUTEX=y
1567 +CONFIG_EPOLL=y
1568 +CONFIG_SIGNALFD=y
1569 +CONFIG_TIMERFD=y
1570 +CONFIG_EVENTFD=y
1571 +CONFIG_SHMEM=y
1572 +CONFIG_AIO=y
1573 +CONFIG_VM_EVENT_COUNTERS=y
1574 +CONFIG_COMPAT_BRK=y
1575 +CONFIG_SLAB=y
1576 +# CONFIG_SLUB is not set
1577 +# CONFIG_SLOB is not set
1578 +# CONFIG_PROFILING is not set
1579 +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
1580 +CONFIG_SLABINFO=y
1581 +CONFIG_RT_MUTEXES=y
1582 +CONFIG_BASE_SMALL=0
1583 +CONFIG_MODULES=y
1584 +# CONFIG_MODULE_FORCE_LOAD is not set
1585 +CONFIG_MODULE_UNLOAD=y
1586 +CONFIG_MODULE_FORCE_UNLOAD=y
1587 +# CONFIG_MODVERSIONS is not set
1588 +# CONFIG_MODULE_SRCVERSION_ALL is not set
1589 +CONFIG_BLOCK=y
1590 +CONFIG_LBD=y
1591 +# CONFIG_BLK_DEV_IO_TRACE is not set
1592 +# CONFIG_BLK_DEV_BSG is not set
1593 +# CONFIG_BLK_DEV_INTEGRITY is not set
1594 +
1595 +#
1596 +# IO Schedulers
1597 +#
1598 +CONFIG_IOSCHED_NOOP=y
1599 +CONFIG_IOSCHED_AS=y
1600 +CONFIG_IOSCHED_DEADLINE=y
1601 +CONFIG_IOSCHED_CFQ=y
1602 +# CONFIG_DEFAULT_AS is not set
1603 +# CONFIG_DEFAULT_DEADLINE is not set
1604 +CONFIG_DEFAULT_CFQ=y
1605 +# CONFIG_DEFAULT_NOOP is not set
1606 +CONFIG_DEFAULT_IOSCHED="cfq"
1607 +# CONFIG_FREEZER is not set
1608 +
1609 +#
1610 +# Platform dependent setup
1611 +#
1612 +CONFIG_COLDFIRE=y
1613 +CONFIG_CFV4E=y
1614 +# CONFIG_FPU is not set
1615 +# CONFIG_AMIGA is not set
1616 +# CONFIG_ATARI is not set
1617 +# CONFIG_MAC is not set
1618 +# CONFIG_APOLLO is not set
1619 +# CONFIG_VME is not set
1620 +# CONFIG_HP300 is not set
1621 +# CONFIG_SUN3X is not set
1622 +# CONFIG_Q40 is not set
1623 +# CONFIG_SUN3 is not set
1624 +
1625 +#
1626 +# Processor type
1627 +#
1628 +# CONFIG_M68020 is not set
1629 +# CONFIG_M68030 is not set
1630 +# CONFIG_M68040 is not set
1631 +# CONFIG_M68060 is not set
1632 +# CONFIG_M5445X is not set
1633 +CONFIG_HAVE_FSL_USB_DR=y
1634 +# CONFIG_M547X_8X is not set
1635 +CONFIG_M5441X=y
1636 +CONFIG_M54418=y
1637 +CONFIG_M54418EVB=y
1638 +CONFIG_MCFCLK=250000000
1639 +# CONFIG_MCF_USER_HALT is not set
1640 +CONFIG_MMU_CFV4E=y
1641 +CONFIG_SDRAM_BASE=0x40000000
1642 +CONFIG_SDRAM_SIZE=0x08000000
1643 +CONFIG_NOR_FLASH_BASE=0x00000000
1644 +CONFIG_DMA_BASE=0xdf000000
1645 +CONFIG_DMA_SIZE=0x1000000
1646 +# CONFIG_VDSO is not set
1647 +# CONFIG_M68KFPU_EMU is not set
1648 +CONFIG_ADVANCED=y
1649 +# CONFIG_RMW_INSNS is not set
1650 +CONFIG_SINGLE_MEMORY_CHUNK=y
1651 +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
1652 +CONFIG_SELECT_MEMORY_MODEL=y
1653 +CONFIG_FLATMEM_MANUAL=y
1654 +# CONFIG_DISCONTIGMEM_MANUAL is not set
1655 +# CONFIG_SPARSEMEM_MANUAL is not set
1656 +CONFIG_FLATMEM=y
1657 +CONFIG_FLAT_NODE_MEM_MAP=y
1658 +CONFIG_NEED_MULTIPLE_NODES=y
1659 +CONFIG_PAGEFLAGS_EXTENDED=y
1660 +CONFIG_SPLIT_PTLOCK_CPUS=4
1661 +# CONFIG_PHYS_ADDR_T_64BIT is not set
1662 +CONFIG_ZONE_DMA_FLAG=1
1663 +CONFIG_BOUNCE=y
1664 +CONFIG_VIRT_TO_BUS=y
1665 +CONFIG_UNEVICTABLE_LRU=y
1666 +
1667 +#
1668 +# General setup
1669 +#
1670 +CONFIG_BINFMT_ELF=y
1671 +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
1672 +CONFIG_HAVE_AOUT=y
1673 +# CONFIG_BINFMT_AOUT is not set
1674 +# CONFIG_BINFMT_MISC is not set
1675 +CONFIG_PROC_HARDWARE=y
1676 +CONFIG_ZONE_DMA=y
1677 +# CONFIG_ARCH_SUPPORTS_MSI is not set
1678 +
1679 +#
1680 +# Power management options
1681 +#
1682 +CONFIG_PM=y
1683 +CONFIG_NET=y
1684 +
1685 +#
1686 +# Networking options
1687 +#
1688 +CONFIG_COMPAT_NET_DEV_OPS=y
1689 +CONFIG_PACKET=y
1690 +# CONFIG_PACKET_MMAP is not set
1691 +CONFIG_UNIX=y
1692 +CONFIG_XFRM=y
1693 +# CONFIG_XFRM_USER is not set
1694 +# CONFIG_XFRM_SUB_POLICY is not set
1695 +# CONFIG_XFRM_MIGRATE is not set
1696 +# CONFIG_XFRM_STATISTICS is not set
1697 +CONFIG_NET_KEY=y
1698 +# CONFIG_NET_KEY_MIGRATE is not set
1699 +CONFIG_INET=y
1700 +# CONFIG_IP_MULTICAST is not set
1701 +CONFIG_IP_ADVANCED_ROUTER=y
1702 +CONFIG_ASK_IP_FIB_HASH=y
1703 +# CONFIG_IP_FIB_TRIE is not set
1704 +CONFIG_IP_FIB_HASH=y
1705 +# CONFIG_IP_MULTIPLE_TABLES is not set
1706 +# CONFIG_IP_ROUTE_MULTIPATH is not set
1707 +# CONFIG_IP_ROUTE_VERBOSE is not set
1708 +CONFIG_IP_PNP=y
1709 +# CONFIG_IP_PNP_DHCP is not set
1710 +# CONFIG_IP_PNP_BOOTP is not set
1711 +# CONFIG_IP_PNP_RARP is not set
1712 +# CONFIG_NET_IPIP is not set
1713 +# CONFIG_NET_IPGRE is not set
1714 +# CONFIG_ARPD is not set
1715 +# CONFIG_SYN_COOKIES is not set
1716 +CONFIG_INET_AH=y
1717 +CONFIG_INET_ESP=y
1718 +# CONFIG_INET_IPCOMP is not set
1719 +# CONFIG_INET_XFRM_TUNNEL is not set
1720 +# CONFIG_INET_TUNNEL is not set
1721 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
1722 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
1723 +# CONFIG_INET_XFRM_MODE_BEET is not set
1724 +# CONFIG_INET_LRO is not set
1725 +CONFIG_INET_DIAG=y
1726 +CONFIG_INET_TCP_DIAG=y
1727 +# CONFIG_TCP_CONG_ADVANCED is not set
1728 +CONFIG_TCP_CONG_CUBIC=y
1729 +CONFIG_DEFAULT_TCP_CONG="cubic"
1730 +# CONFIG_TCP_MD5SIG is not set
1731 +# CONFIG_IPV6 is not set
1732 +# CONFIG_NETWORK_SECMARK is not set
1733 +# CONFIG_NETFILTER is not set
1734 +# CONFIG_IP_DCCP is not set
1735 +# CONFIG_IP_SCTP is not set
1736 +# CONFIG_TIPC is not set
1737 +# CONFIG_ATM is not set
1738 +# CONFIG_BRIDGE is not set
1739 +# CONFIG_NET_DSA is not set
1740 +# CONFIG_VLAN_8021Q is not set
1741 +# CONFIG_DECNET is not set
1742 +# CONFIG_LLC2 is not set
1743 +# CONFIG_IPX is not set
1744 +# CONFIG_ATALK is not set
1745 +# CONFIG_X25 is not set
1746 +# CONFIG_LAPB is not set
1747 +# CONFIG_ECONET is not set
1748 +# CONFIG_WAN_ROUTER is not set
1749 +# CONFIG_NET_SCHED is not set
1750 +# CONFIG_DCB is not set
1751 +
1752 +#
1753 +# Network testing
1754 +#
1755 +# CONFIG_NET_PKTGEN is not set
1756 +# CONFIG_HAMRADIO is not set
1757 +# CONFIG_CAN is not set
1758 +# CONFIG_IRDA is not set
1759 +# CONFIG_BT is not set
1760 +# CONFIG_AF_RXRPC is not set
1761 +# CONFIG_PHONET is not set
1762 +CONFIG_WIRELESS=y
1763 +# CONFIG_CFG80211 is not set
1764 +CONFIG_WIRELESS_OLD_REGULATORY=y
1765 +# CONFIG_WIRELESS_EXT is not set
1766 +# CONFIG_LIB80211 is not set
1767 +# CONFIG_MAC80211 is not set
1768 +# CONFIG_WIMAX is not set
1769 +# CONFIG_RFKILL is not set
1770 +# CONFIG_NET_9P is not set
1771 +# CONFIG_KLIPS is not set
1772 +
1773 +#
1774 +# Device Drivers
1775 +#
1776 +
1777 +#
1778 +# Generic Driver Options
1779 +#
1780 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
1781 +# CONFIG_STANDALONE is not set
1782 +CONFIG_PREVENT_FIRMWARE_BUILD=y
1783 +CONFIG_FW_LOADER=y
1784 +CONFIG_FIRMWARE_IN_KERNEL=y
1785 +CONFIG_EXTRA_FIRMWARE=""
1786 +# CONFIG_SYS_HYPERVISOR is not set
1787 +# CONFIG_CONNECTOR is not set
1788 +CONFIG_MTD=y
1789 +# CONFIG_MTD_DEBUG is not set
1790 +# CONFIG_MTD_CONCAT is not set
1791 +CONFIG_MTD_PARTITIONS=y
1792 +# CONFIG_MTD_TESTS is not set
1793 +# CONFIG_MTD_REDBOOT_PARTS is not set
1794 +CONFIG_MTD_CMDLINE_PARTS=y
1795 +# CONFIG_MTD_AR7_PARTS is not set
1796 +
1797 +#
1798 +# User Modules And Translation Layers
1799 +#
1800 +CONFIG_MTD_CHAR=y
1801 +CONFIG_MTD_BLKDEVS=y
1802 +CONFIG_MTD_BLOCK=y
1803 +# CONFIG_FTL is not set
1804 +# CONFIG_NFTL is not set
1805 +# CONFIG_INFTL is not set
1806 +# CONFIG_RFD_FTL is not set
1807 +# CONFIG_SSFDC is not set
1808 +# CONFIG_MTD_OOPS is not set
1809 +
1810 +#
1811 +# RAM/ROM/Flash chip drivers
1812 +#
1813 +# CONFIG_MTD_CFI is not set
1814 +# CONFIG_MTD_JEDECPROBE is not set
1815 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
1816 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
1817 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
1818 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
1819 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
1820 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
1821 +CONFIG_MTD_CFI_I1=y
1822 +CONFIG_MTD_CFI_I2=y
1823 +# CONFIG_MTD_CFI_I4 is not set
1824 +# CONFIG_MTD_CFI_I8 is not set
1825 +# CONFIG_MTD_RAM is not set
1826 +# CONFIG_MTD_ROM is not set
1827 +# CONFIG_MTD_ABSENT is not set
1828 +
1829 +#
1830 +# Mapping drivers for chip access
1831 +#
1832 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
1833 +# CONFIG_MTD_PLATRAM is not set
1834 +
1835 +#
1836 +# Self-contained MTD device drivers
1837 +#
1838 +# CONFIG_MTD_DATAFLASH is not set
1839 +CONFIG_MTD_M25P80=y
1840 +CONFIG_M25PXX_USE_FAST_READ=y
1841 +# CONFIG_MTD_SLRAM is not set
1842 +# CONFIG_MTD_PHRAM is not set
1843 +# CONFIG_MTD_MTDRAM is not set
1844 +CONFIG_MTD_BLOCK2MTD=y
1845 +
1846 +#
1847 +# Disk-On-Chip Device Drivers
1848 +#
1849 +# CONFIG_MTD_DOC2000 is not set
1850 +# CONFIG_MTD_DOC2001 is not set
1851 +# CONFIG_MTD_DOC2001PLUS is not set
1852 +CONFIG_MTD_NAND=y
1853 +# CONFIG_MTD_NAND_VERIFY_WRITE is not set
1854 +# CONFIG_MTD_NAND_ECC_SMC is not set
1855 +# CONFIG_MTD_NAND_MUSEUM_IDS is not set
1856 +CONFIG_MTD_NAND_IDS=y
1857 +# CONFIG_MTD_NAND_DISKONCHIP is not set
1858 +# CONFIG_MTD_NAND_NANDSIM is not set
1859 +# CONFIG_MTD_NAND_PLATFORM is not set
1860 +# CONFIG_MTD_ALAUDA is not set
1861 +CONFIG_MTD_NAND_FSL_NFC=y
1862 +# CONFIG_MTD_ONENAND is not set
1863 +
1864 +#
1865 +# LPDDR flash memory drivers
1866 +#
1867 +# CONFIG_MTD_LPDDR is not set
1868 +
1869 +#
1870 +# UBI - Unsorted block images
1871 +#
1872 +# CONFIG_MTD_UBI is not set
1873 +# CONFIG_PARPORT is not set
1874 +CONFIG_BLK_DEV=y
1875 +# CONFIG_BLK_DEV_COW_COMMON is not set
1876 +CONFIG_BLK_DEV_LOOP=y
1877 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
1878 +# CONFIG_BLK_DEV_NBD is not set
1879 +# CONFIG_BLK_DEV_UB is not set
1880 +CONFIG_BLK_DEV_RAM=y
1881 +CONFIG_BLK_DEV_RAM_COUNT=16
1882 +CONFIG_BLK_DEV_RAM_SIZE=64000
1883 +# CONFIG_BLK_DEV_XIP is not set
1884 +# CONFIG_CDROM_PKTCDVD is not set
1885 +# CONFIG_ATA_OVER_ETH is not set
1886 +# CONFIG_BLK_DEV_HD is not set
1887 +# CONFIG_MISC_DEVICES is not set
1888 +CONFIG_HAVE_IDE=y
1889 +# CONFIG_IDE is not set
1890 +
1891 +#
1892 +# SCSI device support
1893 +#
1894 +# CONFIG_RAID_ATTRS is not set
1895 +CONFIG_SCSI=y
1896 +CONFIG_SCSI_DMA=y
1897 +# CONFIG_SCSI_TGT is not set
1898 +# CONFIG_SCSI_NETLINK is not set
1899 +CONFIG_SCSI_PROC_FS=y
1900 +
1901 +#
1902 +# SCSI support type (disk, tape, CD-ROM)
1903 +#
1904 +CONFIG_BLK_DEV_SD=y
1905 +# CONFIG_CHR_DEV_ST is not set
1906 +# CONFIG_CHR_DEV_OSST is not set
1907 +# CONFIG_BLK_DEV_SR is not set
1908 +# CONFIG_CHR_DEV_SG is not set
1909 +# CONFIG_CHR_DEV_SCH is not set
1910 +
1911 +#
1912 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
1913 +#
1914 +CONFIG_SCSI_MULTI_LUN=y
1915 +# CONFIG_SCSI_CONSTANTS is not set
1916 +# CONFIG_SCSI_LOGGING is not set
1917 +# CONFIG_SCSI_SCAN_ASYNC is not set
1918 +CONFIG_SCSI_WAIT_SCAN=m
1919 +
1920 +#
1921 +# SCSI Transports
1922 +#
1923 +# CONFIG_SCSI_SPI_ATTRS is not set
1924 +# CONFIG_SCSI_FC_ATTRS is not set
1925 +# CONFIG_SCSI_ISCSI_ATTRS is not set
1926 +# CONFIG_SCSI_SAS_LIBSAS is not set
1927 +# CONFIG_SCSI_SRP_ATTRS is not set
1928 +CONFIG_SCSI_LOWLEVEL=y
1929 +# CONFIG_ISCSI_TCP is not set
1930 +# CONFIG_LIBFC is not set
1931 +# CONFIG_SCSI_DEBUG is not set
1932 +# CONFIG_SCSI_DH is not set
1933 +# CONFIG_ATA is not set
1934 +# CONFIG_MD is not set
1935 +CONFIG_NETDEVICES=y
1936 +# CONFIG_DUMMY is not set
1937 +# CONFIG_BONDING is not set
1938 +# CONFIG_MACVLAN is not set
1939 +# CONFIG_EQUALIZER is not set
1940 +# CONFIG_TUN is not set
1941 +# CONFIG_VETH is not set
1942 +CONFIG_PHYLIB=y
1943 +
1944 +#
1945 +# MII PHY device drivers
1946 +#
1947 +# CONFIG_MARVELL_PHY is not set
1948 +# CONFIG_DAVICOM_PHY is not set
1949 +# CONFIG_QSEMI_PHY is not set
1950 +# CONFIG_LXT_PHY is not set
1951 +# CONFIG_CICADA_PHY is not set
1952 +# CONFIG_VITESSE_PHY is not set
1953 +# CONFIG_SMSC_PHY is not set
1954 +# CONFIG_BROADCOM_PHY is not set
1955 +# CONFIG_BROADCOM5222_PHY is not set
1956 +# CONFIG_ICPLUS_PHY is not set
1957 +# CONFIG_REALTEK_PHY is not set
1958 +# CONFIG_NATIONAL_PHY is not set
1959 +CONFIG_NATIONAL8364x_PHY=y
1960 +CONFIG_NATIONAL8384x_PHY=y
1961 +CONFIG_MicrelKSZ8041_PHY=y
1962 +# CONFIG_STE10XP is not set
1963 +# CONFIG_LSI_ET1011C_PHY is not set
1964 +# CONFIG_FIXED_PHY is not set
1965 +# CONFIG_MDIO_BITBANG is not set
1966 +CONFIG_NET_ETHERNET=y
1967 +CONFIG_MII=y
1968 +# CONFIG_ENC28J60 is not set
1969 +# CONFIG_DNET is not set
1970 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
1971 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
1972 +# CONFIG_IBM_NEW_EMAC_TAH is not set
1973 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
1974 +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
1975 +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
1976 +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
1977 +# CONFIG_B44 is not set
1978 +CONFIG_FEC=y
1979 +CONFIG_FEC2=y
1980 +CONFIG_FEC_SHARED_PHY=y
1981 +# CONFIG_MODELO_SWITCH is not set
1982 +# CONFIG_NETDEV_1000 is not set
1983 +# CONFIG_NETDEV_10000 is not set
1984 +
1985 +#
1986 +# Wireless LAN
1987 +#
1988 +# CONFIG_WLAN_PRE80211 is not set
1989 +# CONFIG_WLAN_80211 is not set
1990 +# CONFIG_IWLWIFI_LEDS is not set
1991 +
1992 +#
1993 +# Enable WiMAX (Networking options) to see the WiMAX drivers
1994 +#
1995 +
1996 +#
1997 +# USB Network Adapters
1998 +#
1999 +# CONFIG_USB_CATC is not set
2000 +# CONFIG_USB_KAWETH is not set
2001 +# CONFIG_USB_PEGASUS is not set
2002 +# CONFIG_USB_RTL8150 is not set
2003 +# CONFIG_USB_USBNET is not set
2004 +# CONFIG_WAN is not set
2005 +# CONFIG_PPP is not set
2006 +# CONFIG_SLIP is not set
2007 +# CONFIG_NETCONSOLE is not set
2008 +# CONFIG_NETPOLL is not set
2009 +# CONFIG_NET_POLL_CONTROLLER is not set
2010 +# CONFIG_ISDN is not set
2011 +# CONFIG_PHONE is not set
2012 +
2013 +#
2014 +# Input device support
2015 +#
2016 +CONFIG_INPUT=y
2017 +# CONFIG_INPUT_FF_MEMLESS is not set
2018 +# CONFIG_INPUT_POLLDEV is not set
2019 +
2020 +#
2021 +# Userland interfaces
2022 +#
2023 +CONFIG_INPUT_MOUSEDEV=y
2024 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
2025 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
2026 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
2027 +# CONFIG_INPUT_JOYDEV is not set
2028 +CONFIG_INPUT_EVDEV=y
2029 +# CONFIG_INPUT_EVBUG is not set
2030 +
2031 +#
2032 +# Input Device Drivers
2033 +#
2034 +CONFIG_INPUT_KEYBOARD=y
2035 +# CONFIG_KEYBOARD_ATKBD is not set
2036 +# CONFIG_KEYBOARD_SUNKBD is not set
2037 +# CONFIG_KEYBOARD_LKKBD is not set
2038 +# CONFIG_KEYBOARD_XTKBD is not set
2039 +# CONFIG_KEYBOARD_NEWTON is not set
2040 +# CONFIG_KEYBOARD_STOWAWAY is not set
2041 +# CONFIG_INPUT_MOUSE is not set
2042 +# CONFIG_INPUT_JOYSTICK is not set
2043 +# CONFIG_INPUT_TABLET is not set
2044 +# CONFIG_INPUT_TOUCHSCREEN is not set
2045 +# CONFIG_INPUT_MISC is not set
2046 +
2047 +#
2048 +# Hardware I/O ports
2049 +#
2050 +CONFIG_SERIO=y
2051 +CONFIG_SERIO_SERPORT=y
2052 +# CONFIG_SERIO_LIBPS2 is not set
2053 +# CONFIG_SERIO_RAW is not set
2054 +# CONFIG_GAMEPORT is not set
2055 +
2056 +#
2057 +# Character devices
2058 +#
2059 +CONFIG_VT=y
2060 +CONFIG_CONSOLE_TRANSLATIONS=y
2061 +CONFIG_VT_CONSOLE=y
2062 +CONFIG_HW_CONSOLE=y
2063 +# CONFIG_VT_HW_CONSOLE_BINDING is not set
2064 +CONFIG_DEVKMEM=y
2065 +# CONFIG_SERIAL_NONSTANDARD is not set
2066 +
2067 +#
2068 +# Serial drivers
2069 +#
2070 +# CONFIG_SERIAL_8250 is not set
2071 +
2072 +#
2073 +# Non-8250 serial port support
2074 +#
2075 +CONFIG_SERIAL_CORE=y
2076 +CONFIG_SERIAL_CORE_CONSOLE=y
2077 +# CONFIG_SERIAL_COLDFIRE_IRDA is not set
2078 +# CONFIG_SERIAL_COLDFIRE_EDMA is not set
2079 +CONFIG_SERIAL_MCF=y
2080 +CONFIG_SERIAL_MCF_BAUDRATE=115200
2081 +CONFIG_SERIAL_MCF_CONSOLE=y
2082 +CONFIG_SERIAL_MCF_UART0=y
2083 +# CONFIG_SERIAL_MCF_UART1 is not set
2084 +# CONFIG_SERIAL_MCF_UART2 is not set
2085 +# CONFIG_SERIAL_MCF_UART3 is not set
2086 +# CONFIG_SERIAL_MCF_UART4 is not set
2087 +# CONFIG_SERIAL_MCF_UART5 is not set
2088 +# CONFIG_SERIAL_MCF_UART6 is not set
2089 +# CONFIG_SERIAL_MCF_UART7 is not set
2090 +# CONFIG_SERIAL_MCF_UART8 is not set
2091 +# CONFIG_SERIAL_MCF_UART9 is not set
2092 +CONFIG_UNIX98_PTYS=y
2093 +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
2094 +# CONFIG_LEGACY_PTYS is not set
2095 +# CONFIG_IPMI_HANDLER is not set
2096 +# CONFIG_HW_RANDOM is not set
2097 +# CONFIG_R3964 is not set
2098 +# CONFIG_RAW_DRIVER is not set
2099 +# CONFIG_TCG_TPM is not set
2100 +# CONFIG_I2C is not set
2101 +CONFIG_SPI=y
2102 +CONFIG_SPI_MASTER=y
2103 +
2104 +#
2105 +# SPI Master Controller Drivers
2106 +#
2107 +# CONFIG_SPI_BITBANG is not set
2108 +CONFIG_SPI_DSPI=y
2109 +# CONFIG_SPI_COLDFIRE_DSPI_EDMA is not set
2110 +
2111 +#
2112 +# SPI Protocol Masters
2113 +#
2114 +# CONFIG_SPI_SPIDEV is not set
2115 +# CONFIG_SPI_TLE62X0 is not set
2116 +# CONFIG_W1 is not set
2117 +# CONFIG_POWER_SUPPLY is not set
2118 +# CONFIG_HWMON is not set
2119 +# CONFIG_THERMAL is not set
2120 +# CONFIG_THERMAL_HWMON is not set
2121 +CONFIG_WATCHDOG=y
2122 +# CONFIG_WATCHDOG_NOWAYOUT is not set
2123 +
2124 +#
2125 +# Watchdog Device Drivers
2126 +#
2127 +# CONFIG_SOFT_WATCHDOG is not set
2128 +CONFIG_COLDFIRE_WATCHDOG=y
2129 +
2130 +#
2131 +# USB-based Watchdog Cards
2132 +#
2133 +# CONFIG_USBPCWATCHDOG is not set
2134 +CONFIG_SSB_POSSIBLE=y
2135 +
2136 +#
2137 +# Sonics Silicon Backplane
2138 +#
2139 +# CONFIG_SSB is not set
2140 +
2141 +#
2142 +# Multifunction device drivers
2143 +#
2144 +# CONFIG_MFD_CORE is not set
2145 +# CONFIG_MFD_SM501 is not set
2146 +# CONFIG_HTC_PASIC3 is not set
2147 +# CONFIG_MFD_TMIO is not set
2148 +# CONFIG_REGULATOR is not set
2149 +
2150 +#
2151 +# Multimedia devices
2152 +#
2153 +
2154 +#
2155 +# Multimedia core support
2156 +#
2157 +# CONFIG_VIDEO_DEV is not set
2158 +# CONFIG_DVB_CORE is not set
2159 +# CONFIG_VIDEO_MEDIA is not set
2160 +
2161 +#
2162 +# Multimedia drivers
2163 +#
2164 +CONFIG_DAB=y
2165 +# CONFIG_USB_DABUSB is not set
2166 +
2167 +#
2168 +# Graphics support
2169 +#
2170 +# CONFIG_VGASTATE is not set
2171 +CONFIG_VIDEO_OUTPUT_CONTROL=m
2172 +# CONFIG_FB is not set
2173 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
2174 +
2175 +#
2176 +# Display device support
2177 +#
2178 +# CONFIG_DISPLAY_SUPPORT is not set
2179 +
2180 +#
2181 +# Console display driver support
2182 +#
2183 +CONFIG_DUMMY_CONSOLE=y
2184 +# CONFIG_SOUND is not set
2185 +# CONFIG_HID_SUPPORT is not set
2186 +CONFIG_USB_SUPPORT=y
2187 +CONFIG_USB_ARCH_HAS_HCD=y
2188 +# CONFIG_USB_ARCH_HAS_OHCI is not set
2189 +CONFIG_USB_ARCH_HAS_EHCI=y
2190 +CONFIG_USB=y
2191 +# CONFIG_USB_DEBUG is not set
2192 +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
2193 +
2194 +#
2195 +# Miscellaneous USB options
2196 +#
2197 +CONFIG_USB_DEVICEFS=y
2198 +CONFIG_USB_DEVICE_CLASS=y
2199 +# CONFIG_USB_DYNAMIC_MINORS is not set
2200 +CONFIG_USB_SUSPEND=y
2201 +CONFIG_USB_OTG=y
2202 +# CONFIG_USB_OTG_WHITELIST is not set
2203 +# CONFIG_USB_OTG_BLACKLIST_HUB is not set
2204 +# CONFIG_USB_MON is not set
2205 +# CONFIG_USB_WUSB is not set
2206 +# CONFIG_USB_WUSB_CBAF is not set
2207 +
2208 +#
2209 +# USB Host Controller Drivers
2210 +#
2211 +# CONFIG_USB_C67X00_HCD is not set
2212 +CONFIG_USB_EHCI_HCD=m
2213 +CONFIG_USB_EHCI_ROOT_HUB_TT=y
2214 +# CONFIG_USB_EHCI_TT_NEWSCHED is not set
2215 +CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
2216 +CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
2217 +CONFIG_USB_EHCI_FSL=y
2218 +# CONFIG_USB_OXU210HP_HCD is not set
2219 +# CONFIG_USB_ISP116X_HCD is not set
2220 +# CONFIG_USB_SL811_HCD is not set
2221 +# CONFIG_USB_R8A66597_HCD is not set
2222 +# CONFIG_USB_HWA_HCD is not set
2223 +# CONFIG_USB_M5445X_ULPI is not set
2224 +# CONFIG_USB_M5445X_FSLS is not set
2225 +CONFIG_USB_M5441X_ULPI=y
2226 +# CONFIG_USB_M5441X_FSLS is not set
2227 +# CONFIG_USB_GADGET_MUSB_HDRC is not set
2228 +
2229 +#
2230 +# USB Device Class drivers
2231 +#
2232 +# CONFIG_USB_ACM is not set
2233 +# CONFIG_USB_PRINTER is not set
2234 +# CONFIG_USB_WDM is not set
2235 +# CONFIG_USB_TMC is not set
2236 +
2237 +#
2238 +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
2239 +#
2240 +
2241 +#
2242 +# see USB_STORAGE Help for more information
2243 +#
2244 +CONFIG_USB_STORAGE=y
2245 +# CONFIG_USB_STORAGE_DEBUG is not set
2246 +# CONFIG_USB_STORAGE_DATAFAB is not set
2247 +# CONFIG_USB_STORAGE_FREECOM is not set
2248 +# CONFIG_USB_STORAGE_ISD200 is not set
2249 +# CONFIG_USB_STORAGE_USBAT is not set
2250 +# CONFIG_USB_STORAGE_SDDR09 is not set
2251 +# CONFIG_USB_STORAGE_SDDR55 is not set
2252 +# CONFIG_USB_STORAGE_JUMPSHOT is not set
2253 +# CONFIG_USB_STORAGE_ALAUDA is not set
2254 +# CONFIG_USB_STORAGE_ONETOUCH is not set
2255 +# CONFIG_USB_STORAGE_KARMA is not set
2256 +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
2257 +# CONFIG_USB_LIBUSUAL is not set
2258 +
2259 +#
2260 +# USB Imaging devices
2261 +#
2262 +# CONFIG_USB_MDC800 is not set
2263 +# CONFIG_USB_MICROTEK is not set
2264 +
2265 +#
2266 +# USB port drivers
2267 +#
2268 +# CONFIG_USB_SERIAL is not set
2269 +
2270 +#
2271 +# USB Miscellaneous drivers
2272 +#
2273 +# CONFIG_USB_EMI62 is not set
2274 +# CONFIG_USB_EMI26 is not set
2275 +# CONFIG_USB_ADUTUX is not set
2276 +# CONFIG_USB_SEVSEG is not set
2277 +# CONFIG_USB_RIO500 is not set
2278 +# CONFIG_USB_LEGOTOWER is not set
2279 +# CONFIG_USB_LCD is not set
2280 +# CONFIG_USB_BERRY_CHARGE is not set
2281 +# CONFIG_USB_LED is not set
2282 +# CONFIG_USB_CYPRESS_CY7C63 is not set
2283 +# CONFIG_USB_CYTHERM is not set
2284 +# CONFIG_USB_PHIDGET is not set
2285 +# CONFIG_USB_IDMOUSE is not set
2286 +# CONFIG_USB_FTDI_ELAN is not set
2287 +# CONFIG_USB_APPLEDISPLAY is not set
2288 +# CONFIG_USB_SISUSBVGA is not set
2289 +# CONFIG_USB_LD is not set
2290 +# CONFIG_USB_TRANCEVIBRATOR is not set
2291 +# CONFIG_USB_IOWARRIOR is not set
2292 +# CONFIG_USB_TEST is not set
2293 +# CONFIG_USB_ISIGHTFW is not set
2294 +# CONFIG_USB_VST is not set
2295 +CONFIG_USB_GADGET=m
2296 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
2297 +CONFIG_USB_GADGET_VBUS_DRAW=2
2298 +CONFIG_USB_GADGET_SELECTED=y
2299 +# CONFIG_USB_GADGET_AT91 is not set
2300 +# CONFIG_USB_GADGET_ATMEL_USBA is not set
2301 +CONFIG_USB_GADGET_FSL_USB2=y
2302 +CONFIG_USB_FSL_USB2=m
2303 +# CONFIG_USB_GADGET_LH7A40X is not set
2304 +# CONFIG_USB_GADGET_OMAP is not set
2305 +# CONFIG_USB_GADGET_PXA25X is not set
2306 +# CONFIG_USB_GADGET_PXA27X is not set
2307 +# CONFIG_USB_GADGET_S3C2410 is not set
2308 +# CONFIG_USB_GADGET_IMX is not set
2309 +# CONFIG_USB_GADGET_M66592 is not set
2310 +# CONFIG_USB_GADGET_AMD5536UDC is not set
2311 +# CONFIG_USB_GADGET_FSL_QE is not set
2312 +# CONFIG_USB_GADGET_CI13XXX is not set
2313 +# CONFIG_USB_GADGET_NET2280 is not set
2314 +# CONFIG_USB_GADGET_GOKU is not set
2315 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
2316 +CONFIG_USB_GADGET_DUALSPEED=y
2317 +# CONFIG_USB_ZERO is not set
2318 +# CONFIG_USB_ETH is not set
2319 +CONFIG_USB_GADGETFS=m
2320 +CONFIG_USB_FILE_STORAGE=m
2321 +CONFIG_USB_FILE_STORAGE_TEST=y
2322 +# CONFIG_USB_G_SERIAL is not set
2323 +# CONFIG_USB_MIDI_GADGET is not set
2324 +# CONFIG_USB_G_PRINTER is not set
2325 +# CONFIG_USB_CDC_COMPOSITE is not set
2326 +
2327 +#
2328 +# OTG and related infrastructure
2329 +#
2330 +CONFIG_MMC=y
2331 +# CONFIG_MMC_DEBUG is not set
2332 +# CONFIG_MMC_UNSAFE_RESUME is not set
2333 +
2334 +#
2335 +# MMC/SD/SDIO Card Drivers
2336 +#
2337 +CONFIG_MMC_BLOCK=y
2338 +CONFIG_MMC_BLOCK_BOUNCE=y
2339 +# CONFIG_SDIO_UART is not set
2340 +# CONFIG_MMC_TEST is not set
2341 +
2342 +#
2343 +# MMC/SD/SDIO Host Controller Drivers
2344 +#
2345 +# CONFIG_MMC_SDHCI is not set
2346 +# CONFIG_MMC_SPI is not set
2347 +# CONFIG_MMC_ESDHC is not set
2348 +# CONFIG_MEMSTICK is not set
2349 +# CONFIG_NEW_LEDS is not set
2350 +# CONFIG_ACCESSIBILITY is not set
2351 +CONFIG_RTC_LIB=y
2352 +CONFIG_RTC_CLASS=y
2353 +CONFIG_RTC_HCTOSYS=y
2354 +CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
2355 +# CONFIG_RTC_DEBUG is not set
2356 +
2357 +#
2358 +# RTC interfaces
2359 +#
2360 +CONFIG_RTC_INTF_SYSFS=y
2361 +CONFIG_RTC_INTF_PROC=y
2362 +CONFIG_RTC_INTF_DEV=y
2363 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
2364 +# CONFIG_RTC_DRV_TEST is not set
2365 +
2366 +#
2367 +# SPI RTC drivers
2368 +#
2369 +# CONFIG_RTC_DRV_M41T94 is not set
2370 +# CONFIG_RTC_DRV_DS1305 is not set
2371 +# CONFIG_RTC_DRV_DS1390 is not set
2372 +# CONFIG_RTC_DRV_MAX6902 is not set
2373 +# CONFIG_RTC_DRV_R9701 is not set
2374 +# CONFIG_RTC_DRV_RS5C348 is not set
2375 +# CONFIG_RTC_DRV_DS3234 is not set
2376 +
2377 +#
2378 +# Platform RTC drivers
2379 +#
2380 +# CONFIG_RTC_DRV_DS1286 is not set
2381 +# CONFIG_RTC_DRV_DS1511 is not set
2382 +# CONFIG_RTC_DRV_DS1553 is not set
2383 +# CONFIG_RTC_DRV_DS1742 is not set
2384 +# CONFIG_RTC_DRV_STK17TA8 is not set
2385 +# CONFIG_RTC_DRV_M48T86 is not set
2386 +# CONFIG_RTC_DRV_M48T35 is not set
2387 +# CONFIG_RTC_DRV_M48T59 is not set
2388 +# CONFIG_RTC_DRV_BQ4802 is not set
2389 +# CONFIG_RTC_DRV_V3020 is not set
2390 +
2391 +#
2392 +# on-CPU RTC drivers
2393 +#
2394 +# CONFIG_RTC_MCF is not set
2395 +CONFIG_RTC_M5441X=y
2396 +CONFIG_DMADEVICES=y
2397 +
2398 +#
2399 +# DMA Devices
2400 +#
2401 +CONFIG_COLDFIRE_EDMA=y
2402 +CONFIG_COLDFIRE_EDMA_TEST=m
2403 +# CONFIG_UIO is not set
2404 +# CONFIG_STAGING is not set
2405 +
2406 +#
2407 +# Character devices
2408 +#
2409 +CONFIG_TICK_ONESHOT=y
2410 +CONFIG_NO_HZ=y
2411 +CONFIG_HIGH_RES_TIMERS=y
2412 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
2413 +
2414 +#
2415 +# File systems
2416 +#
2417 +CONFIG_EXT2_FS=y
2418 +# CONFIG_EXT2_FS_XATTR is not set
2419 +# CONFIG_EXT2_FS_XIP is not set
2420 +CONFIG_EXT3_FS=y
2421 +CONFIG_EXT3_FS_XATTR=y
2422 +# CONFIG_EXT3_FS_POSIX_ACL is not set
2423 +# CONFIG_EXT3_FS_SECURITY is not set
2424 +# CONFIG_EXT4_FS is not set
2425 +CONFIG_JBD=y
2426 +CONFIG_FS_MBCACHE=y
2427 +# CONFIG_REISERFS_FS is not set
2428 +# CONFIG_JFS_FS is not set
2429 +# CONFIG_FS_POSIX_ACL is not set
2430 +CONFIG_FILE_LOCKING=y
2431 +# CONFIG_XFS_FS is not set
2432 +# CONFIG_GFS2_FS is not set
2433 +# CONFIG_OCFS2_FS is not set
2434 +# CONFIG_BTRFS_FS is not set
2435 +CONFIG_DNOTIFY=y
2436 +CONFIG_INOTIFY=y
2437 +CONFIG_INOTIFY_USER=y
2438 +# CONFIG_QUOTA is not set
2439 +# CONFIG_AUTOFS_FS is not set
2440 +# CONFIG_AUTOFS4_FS is not set
2441 +# CONFIG_FUSE_FS is not set
2442 +
2443 +#
2444 +# CD-ROM/DVD Filesystems
2445 +#
2446 +# CONFIG_ISO9660_FS is not set
2447 +# CONFIG_UDF_FS is not set
2448 +
2449 +#
2450 +# DOS/FAT/NT Filesystems
2451 +#
2452 +CONFIG_FAT_FS=y
2453 +CONFIG_MSDOS_FS=y
2454 +CONFIG_VFAT_FS=y
2455 +CONFIG_FAT_DEFAULT_CODEPAGE=437
2456 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
2457 +CONFIG_NTFS_FS=y
2458 +# CONFIG_NTFS_DEBUG is not set
2459 +CONFIG_NTFS_RW=y
2460 +
2461 +#
2462 +# Pseudo filesystems
2463 +#
2464 +CONFIG_PROC_FS=y
2465 +# CONFIG_PROC_KCORE is not set
2466 +CONFIG_PROC_SYSCTL=y
2467 +CONFIG_PROC_PAGE_MONITOR=y
2468 +CONFIG_SYSFS=y
2469 +CONFIG_TMPFS=y
2470 +# CONFIG_TMPFS_POSIX_ACL is not set
2471 +# CONFIG_HUGETLB_PAGE is not set
2472 +# CONFIG_CONFIGFS_FS is not set
2473 +CONFIG_MISC_FILESYSTEMS=y
2474 +# CONFIG_ADFS_FS is not set
2475 +# CONFIG_AFFS_FS is not set
2476 +# CONFIG_HFS_FS is not set
2477 +# CONFIG_HFSPLUS_FS is not set
2478 +# CONFIG_BEFS_FS is not set
2479 +# CONFIG_BFS_FS is not set
2480 +# CONFIG_EFS_FS is not set
2481 +CONFIG_JFFS2_FS=y
2482 +CONFIG_JFFS2_FS_DEBUG=0
2483 +CONFIG_JFFS2_FS_WRITEBUFFER=y
2484 +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
2485 +# CONFIG_JFFS2_SUMMARY is not set
2486 +# CONFIG_JFFS2_FS_XATTR is not set
2487 +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
2488 +CONFIG_JFFS2_ZLIB=y
2489 +# CONFIG_JFFS2_LZO is not set
2490 +CONFIG_JFFS2_RTIME=y
2491 +# CONFIG_JFFS2_RUBIN is not set
2492 +# CONFIG_CRAMFS is not set
2493 +# CONFIG_SQUASHFS is not set
2494 +# CONFIG_VXFS_FS is not set
2495 +CONFIG_MINIX_FS=y
2496 +# CONFIG_OMFS_FS is not set
2497 +# CONFIG_HPFS_FS is not set
2498 +# CONFIG_QNX4FS_FS is not set
2499 +# CONFIG_ROMFS_FS is not set
2500 +# CONFIG_SYSV_FS is not set
2501 +# CONFIG_UFS_FS is not set
2502 +CONFIG_NETWORK_FILESYSTEMS=y
2503 +CONFIG_NFS_FS=y
2504 +# CONFIG_NFS_V3 is not set
2505 +# CONFIG_NFS_V4 is not set
2506 +CONFIG_ROOT_NFS=y
2507 +# CONFIG_NFSD is not set
2508 +CONFIG_LOCKD=y
2509 +CONFIG_NFS_COMMON=y
2510 +CONFIG_SUNRPC=y
2511 +# CONFIG_SUNRPC_REGISTER_V4 is not set
2512 +# CONFIG_RPCSEC_GSS_KRB5 is not set
2513 +# CONFIG_RPCSEC_GSS_SPKM3 is not set
2514 +# CONFIG_SMB_FS is not set
2515 +# CONFIG_CIFS is not set
2516 +# CONFIG_NCP_FS is not set
2517 +# CONFIG_CODA_FS is not set
2518 +# CONFIG_AFS_FS is not set
2519 +
2520 +#
2521 +# Partition Types
2522 +#
2523 +CONFIG_PARTITION_ADVANCED=y
2524 +# CONFIG_ACORN_PARTITION is not set
2525 +# CONFIG_OSF_PARTITION is not set
2526 +# CONFIG_AMIGA_PARTITION is not set
2527 +# CONFIG_ATARI_PARTITION is not set
2528 +# CONFIG_MAC_PARTITION is not set
2529 +CONFIG_MSDOS_PARTITION=y
2530 +# CONFIG_BSD_DISKLABEL is not set
2531 +# CONFIG_MINIX_SUBPARTITION is not set
2532 +# CONFIG_SOLARIS_X86_PARTITION is not set
2533 +# CONFIG_UNIXWARE_DISKLABEL is not set
2534 +# CONFIG_LDM_PARTITION is not set
2535 +# CONFIG_SGI_PARTITION is not set
2536 +# CONFIG_ULTRIX_PARTITION is not set
2537 +# CONFIG_SUN_PARTITION is not set
2538 +# CONFIG_KARMA_PARTITION is not set
2539 +# CONFIG_EFI_PARTITION is not set
2540 +# CONFIG_SYSV68_PARTITION is not set
2541 +CONFIG_NLS=y
2542 +CONFIG_NLS_DEFAULT="iso8859-1"
2543 +CONFIG_NLS_CODEPAGE_437=y
2544 +# CONFIG_NLS_CODEPAGE_737 is not set
2545 +# CONFIG_NLS_CODEPAGE_775 is not set
2546 +# CONFIG_NLS_CODEPAGE_850 is not set
2547 +# CONFIG_NLS_CODEPAGE_852 is not set
2548 +# CONFIG_NLS_CODEPAGE_855 is not set
2549 +# CONFIG_NLS_CODEPAGE_857 is not set
2550 +# CONFIG_NLS_CODEPAGE_860 is not set
2551 +# CONFIG_NLS_CODEPAGE_861 is not set
2552 +# CONFIG_NLS_CODEPAGE_862 is not set
2553 +# CONFIG_NLS_CODEPAGE_863 is not set
2554 +# CONFIG_NLS_CODEPAGE_864 is not set
2555 +# CONFIG_NLS_CODEPAGE_865 is not set
2556 +# CONFIG_NLS_CODEPAGE_866 is not set
2557 +# CONFIG_NLS_CODEPAGE_869 is not set
2558 +# CONFIG_NLS_CODEPAGE_936 is not set
2559 +# CONFIG_NLS_CODEPAGE_950 is not set
2560 +# CONFIG_NLS_CODEPAGE_932 is not set
2561 +# CONFIG_NLS_CODEPAGE_949 is not set
2562 +# CONFIG_NLS_CODEPAGE_874 is not set
2563 +# CONFIG_NLS_ISO8859_8 is not set
2564 +# CONFIG_NLS_CODEPAGE_1250 is not set
2565 +# CONFIG_NLS_CODEPAGE_1251 is not set
2566 +# CONFIG_NLS_ASCII is not set
2567 +CONFIG_NLS_ISO8859_1=y
2568 +# CONFIG_NLS_ISO8859_2 is not set
2569 +# CONFIG_NLS_ISO8859_3 is not set
2570 +# CONFIG_NLS_ISO8859_4 is not set
2571 +# CONFIG_NLS_ISO8859_5 is not set
2572 +# CONFIG_NLS_ISO8859_6 is not set
2573 +# CONFIG_NLS_ISO8859_7 is not set
2574 +# CONFIG_NLS_ISO8859_9 is not set
2575 +# CONFIG_NLS_ISO8859_13 is not set
2576 +# CONFIG_NLS_ISO8859_14 is not set
2577 +# CONFIG_NLS_ISO8859_15 is not set
2578 +# CONFIG_NLS_KOI8_R is not set
2579 +# CONFIG_NLS_KOI8_U is not set
2580 +CONFIG_NLS_UTF8=y
2581 +# CONFIG_DLM is not set
2582 +
2583 +#
2584 +# Kernel hacking
2585 +#
2586 +# CONFIG_PRINTK_TIME is not set
2587 +CONFIG_ENABLE_WARN_DEPRECATED=y
2588 +# CONFIG_ENABLE_MUST_CHECK is not set
2589 +CONFIG_FRAME_WARN=1024
2590 +# CONFIG_MAGIC_SYSRQ is not set
2591 +# CONFIG_UNUSED_SYMBOLS is not set
2592 +# CONFIG_DEBUG_FS is not set
2593 +# CONFIG_HEADERS_CHECK is not set
2594 +# CONFIG_DEBUG_KERNEL is not set
2595 +# CONFIG_DEBUG_BUGVERBOSE is not set
2596 +# CONFIG_DEBUG_MEMORY_INIT is not set
2597 +# CONFIG_RCU_CPU_STALL_DETECTOR is not set
2598 +# CONFIG_SYSCTL_SYSCALL_CHECK is not set
2599 +
2600 +#
2601 +# Tracers
2602 +#
2603 +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
2604 +# CONFIG_SAMPLES is not set
2605 +# CONFIG_BOOTPARAM is not set
2606 +
2607 +#
2608 +# Security options
2609 +#
2610 +# CONFIG_KEYS is not set
2611 +# CONFIG_SECURITY is not set
2612 +# CONFIG_SECURITYFS is not set
2613 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
2614 +CONFIG_CRYPTO=y
2615 +
2616 +#
2617 +# Crypto core or helper
2618 +#
2619 +# CONFIG_CRYPTO_FIPS is not set
2620 +CONFIG_CRYPTO_ALGAPI=y
2621 +CONFIG_CRYPTO_ALGAPI2=y
2622 +CONFIG_CRYPTO_AEAD=y
2623 +CONFIG_CRYPTO_AEAD2=y
2624 +CONFIG_CRYPTO_BLKCIPHER=y
2625 +CONFIG_CRYPTO_BLKCIPHER2=y
2626 +CONFIG_CRYPTO_HASH=y
2627 +CONFIG_CRYPTO_HASH2=y
2628 +CONFIG_CRYPTO_RNG2=y
2629 +CONFIG_CRYPTO_MANAGER=y
2630 +CONFIG_CRYPTO_MANAGER2=y
2631 +# CONFIG_CRYPTO_GF128MUL is not set
2632 +# CONFIG_CRYPTO_NULL is not set
2633 +# CONFIG_CRYPTO_CRYPTD is not set
2634 +CONFIG_CRYPTO_AUTHENC=y
2635 +CONFIG_CRYPTO_TEST=m
2636 +
2637 +#
2638 +# Authenticated Encryption with Associated Data
2639 +#
2640 +# CONFIG_CRYPTO_CCM is not set
2641 +# CONFIG_CRYPTO_GCM is not set
2642 +# CONFIG_CRYPTO_SEQIV is not set
2643 +
2644 +#
2645 +# Block modes
2646 +#
2647 +CONFIG_CRYPTO_CBC=y
2648 +# CONFIG_CRYPTO_CTR is not set
2649 +# CONFIG_CRYPTO_CTS is not set
2650 +CONFIG_CRYPTO_ECB=y
2651 +# CONFIG_CRYPTO_LRW is not set
2652 +CONFIG_CRYPTO_PCBC=m
2653 +# CONFIG_CRYPTO_XTS is not set
2654 +
2655 +#
2656 +# Hash modes
2657 +#
2658 +CONFIG_CRYPTO_HMAC=y
2659 +# CONFIG_CRYPTO_XCBC is not set
2660 +
2661 +#
2662 +# Digest
2663 +#
2664 +CONFIG_CRYPTO_CRC32C=y
2665 +# CONFIG_CRYPTO_MD4 is not set
2666 +CONFIG_CRYPTO_MD5=y
2667 +# CONFIG_CRYPTO_MICHAEL_MIC is not set
2668 +# CONFIG_CRYPTO_RMD128 is not set
2669 +# CONFIG_CRYPTO_RMD160 is not set
2670 +# CONFIG_CRYPTO_RMD256 is not set
2671 +# CONFIG_CRYPTO_RMD320 is not set
2672 +CONFIG_CRYPTO_SHA1=y
2673 +# CONFIG_CRYPTO_SHA256 is not set
2674 +# CONFIG_CRYPTO_SHA512 is not set
2675 +# CONFIG_CRYPTO_TGR192 is not set
2676 +# CONFIG_CRYPTO_WP512 is not set
2677 +
2678 +#
2679 +# Ciphers
2680 +#
2681 +# CONFIG_CRYPTO_AES is not set
2682 +# CONFIG_CRYPTO_ANUBIS is not set
2683 +# CONFIG_CRYPTO_ARC4 is not set
2684 +# CONFIG_CRYPTO_BLOWFISH is not set
2685 +# CONFIG_CRYPTO_CAMELLIA is not set
2686 +# CONFIG_CRYPTO_CAST5 is not set
2687 +# CONFIG_CRYPTO_CAST6 is not set
2688 +CONFIG_CRYPTO_DES=y
2689 +# CONFIG_CRYPTO_FCRYPT is not set
2690 +# CONFIG_CRYPTO_KHAZAD is not set
2691 +# CONFIG_CRYPTO_SALSA20 is not set
2692 +# CONFIG_CRYPTO_SEED is not set
2693 +# CONFIG_CRYPTO_SERPENT is not set
2694 +# CONFIG_CRYPTO_TEA is not set
2695 +# CONFIG_CRYPTO_TWOFISH is not set
2696 +
2697 +#
2698 +# Compression
2699 +#
2700 +# CONFIG_CRYPTO_DEFLATE is not set
2701 +# CONFIG_CRYPTO_LZO is not set
2702 +
2703 +#
2704 +# Random Number Generation
2705 +#
2706 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
2707 +
2708 +#
2709 +# OCF Configuration
2710 +#
2711 +# CONFIG_OCF_OCF is not set
2712 +
2713 +#
2714 +# Talitos Driver
2715 +#
2716 +CONFIG_CRYPTO_HW=y
2717 +# CONFIG_CRYPTO_DEV_MCFCAU is not set
2718 +
2719 +#
2720 +# Library routines
2721 +#
2722 +CONFIG_BITREVERSE=y
2723 +CONFIG_GENERIC_FIND_LAST_BIT=y
2724 +CONFIG_CRC_CCITT=y
2725 +CONFIG_CRC16=y
2726 +# CONFIG_CRC_T10DIF is not set
2727 +CONFIG_CRC_ITU_T=y
2728 +CONFIG_CRC32=y
2729 +CONFIG_CRC7=y
2730 +CONFIG_LIBCRC32C=y
2731 +CONFIG_ZLIB_INFLATE=y
2732 +CONFIG_ZLIB_DEFLATE=y
2733 +CONFIG_PLIST=y
2734 +CONFIG_HAS_IOMEM=y
2735 +CONFIG_HAS_IOPORT=y
2736 +CONFIG_HAS_DMA=y
2737 --- /dev/null
2738 +++ b/arch/m68k/include/asm/cf_5441x_cacheflush.h
2739 @@ -0,0 +1,527 @@
2740 +/*
2741 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
2742 + *
2743 + * Based on include/asm-m68k/cacheflush.h
2744 + *
2745 + * This program is free software; you can redistribute it and/or modify it
2746 + * under the terms of the GNU General Public License as published by the
2747 + * Free Software Foundation; either version 2 of the License, or (at your
2748 + * option) any later version.
2749 + */
2750 +#ifndef M68K_CF_5441x_CACHEFLUSH_H
2751 +#define M68K_CF_5441x_CACHEFLUSH_H
2752 +
2753 +#include <asm/cfcache.h>
2754 +
2755 +/*
2756 + * Coldfire Cache Model
2757 + *
2758 + * The Coldfire processors use a Harvard architecture cache configured
2759 + * as four-way set associative. The cache does not implement bus snooping
2760 + * so cache coherency with other masters must be maintained in software.
2761 + *
2762 + * The cache is managed via the CPUSHL instruction in conjunction with
2763 + * bits set in the CACR (cache control register). Currently the code
2764 + * uses the CPUSHL enhancement which adds the ability to
2765 + * invalidate/clear/push a cacheline by physical address. This feature
2766 + * is designated in the Hardware Configuration Register [D1-CPES].
2767 + *
2768 + * CACR Bits:
2769 + * DPI[28] cpushl invalidate disable for d-cache
2770 + * IDPI[12] cpushl invalidate disable for i-cache
2771 + * SPA[14] cpushl search by physical address
2772 + * IVO[20] cpushl invalidate only
2773 + *
2774 + * Random Terminology:
2775 + * * invalidate = reset the cache line's valid bit
2776 + * * push = generate a line-sized store of the data if its contents are
2777 + * marked as modifed (the modified flag is cleared after
2778 + * the store)
2779 + * * clear = push + invalidate
2780 + */
2781 +
2782 +/**
2783 + * flush_icache - Flush all of the instruction cache
2784 + */
2785 +static inline void flush_icache(void)
2786 +{
2787 + asm volatile("nop\n"
2788 + "moveq%.l #0,%%d0\n"
2789 + "moveq%.l #0,%%d1\n"
2790 + "move%.l %%d0,%%a0\n"
2791 + "1:\n"
2792 + "cpushl %%ic,(%%a0)\n"
2793 + "add%.l #0x0010,%%a0\n"
2794 + "addq%.l #1,%%d1\n"
2795 + "cmpi%.l %0,%%d1\n"
2796 + "bne 1b\n"
2797 + "moveq%.l #0,%%d1\n"
2798 + "addq%.l #1,%%d0\n"
2799 + "move%.l %%d0,%%a0\n"
2800 + "cmpi%.l #4,%%d0\n"
2801 + "bne 1b\n"
2802 + : : "i" (CACHE_SETS)
2803 + : "a0", "d0", "d1");
2804 +}
2805 +
2806 +/**
2807 + * flush_dcache - Flush all of the data cache
2808 + */
2809 +static inline void flush_dcache(void)
2810 +{
2811 + asm volatile("nop\n"
2812 + "moveq%.l #0,%%d0\n"
2813 + "moveq%.l #0,%%d1\n"
2814 + "move%.l %%d0,%%a0\n"
2815 + "1:\n"
2816 + "cpushl %%dc,(%%a0)\n"
2817 + "add%.l #0x0010,%%a0\n"
2818 + "addq%.l #1,%%d1\n"
2819 + "cmpi%.l %0,%%d1\n"
2820 + "bne 1b\n"
2821 + "moveq%.l #0,%%d1\n"
2822 + "addq%.l #1,%%d0\n"
2823 + "move%.l %%d0,%%a0\n"
2824 + "cmpi%.l #4,%%d0\n"
2825 + "bne 1b\n"
2826 + : : "i" (CACHE_SETS)
2827 + : "a0", "d0", "d1");
2828 +}
2829 +
2830 +/**
2831 + * flush_bcache - Flush all of both caches
2832 + */
2833 +static inline void flush_bcache(void)
2834 +{
2835 + asm volatile("nop\n"
2836 + "moveq%.l #0,%%d0\n"
2837 + "moveq%.l #0,%%d1\n"
2838 + "move%.l %%d0,%%a0\n"
2839 + "1:\n"
2840 + "cpushl %%bc,(%%a0)\n"
2841 + "add%.l #0x0010,%%a0\n"
2842 + "addq%.l #1,%%d1\n"
2843 + "cmpi%.l %0,%%d1\n"
2844 + "bne 1b\n"
2845 + "moveq%.l #0,%%d1\n"
2846 + "addq%.l #1,%%d0\n"
2847 + "move%.l %%d0,%%a0\n"
2848 + "cmpi%.l #4,%%d0\n"
2849 + "bne 1b\n"
2850 + : : "i" (CACHE_SETS)
2851 + : "a0", "d0", "d1");
2852 +}
2853 +
2854 +/**
2855 + * cf_cache_clear - invalidate cache
2856 + * @paddr: starting physical address
2857 + * @len: number of bytes
2858 + *
2859 + * Invalidate cache lines starting at paddr for len bytes.
2860 + * Those lines are not pushed.
2861 + */
2862 +static inline void cf_cache_clear(unsigned long paddr, int len)
2863 +{
2864 + /* number of lines */
2865 + len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
2866 + if (len == 0)
2867 + return;
2868 +
2869 + /* align on set boundary */
2870 + paddr &= 0xfffffff0;
2871 +
2872 + asm volatile("nop\n"
2873 + "move%.l %2,%%d0\n"
2874 + "or%.l %3,%%d0\n"
2875 + "movec %%d0,%%cacr\n"
2876 + "move%.l %0,%%a0\n"
2877 + "move%.l %1,%%d0\n"
2878 + "1:\n"
2879 + "cpushl %%bc,(%%a0)\n"
2880 + "lea 0x10(%%a0),%%a0\n"
2881 + "subq%.l #1,%%d0\n"
2882 + "bne%.b 1b\n"
2883 + "movec %2,%%cacr\n"
2884 + : : "a" (paddr), "r" (len),
2885 + "r" (shadow_cacr),
2886 + "i" (CF_CACR_SPA+CF_CACR_IVO)
2887 + : "a0", "d0");
2888 +}
2889 +
2890 +/**
2891 + * cf_cache_push - Push dirty cache out with no invalidate
2892 + * @paddr: starting physical address
2893 + * @len: number of bytes
2894 + *
2895 + * Push the any dirty lines starting at paddr for len bytes.
2896 + * Those lines are not invalidated.
2897 + */
2898 +static inline void cf_cache_push(unsigned long paddr, int len)
2899 +{
2900 + /* number of lines */
2901 + len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
2902 + if (len == 0)
2903 + return;
2904 +
2905 + /* align on set boundary */
2906 + paddr &= 0xfffffff0;
2907 +
2908 + asm volatile("nop\n"
2909 + "move%.l %2,%%d0\n"
2910 + "or%.l %3,%%d0\n"
2911 + "movec %%d0,%%cacr\n"
2912 + "move%.l %0,%%a0\n"
2913 + "move%.l %1,%%d0\n"
2914 + "1:\n"
2915 + "cpushl %%bc,(%%a0)\n"
2916 + "lea 0x10(%%a0),%%a0\n"
2917 + "subq%.l #1,%%d0\n"
2918 + "bne.b 1b\n"
2919 + "movec %2,%%cacr\n"
2920 + : : "a" (paddr), "r" (len),
2921 + "r" (shadow_cacr),
2922 + "i" (CF_CACR_SPA+CF_CACR_DPI+CF_CACR_IDPI)
2923 + : "a0", "d0");
2924 +}
2925 +
2926 +/**
2927 + * cf_cache_flush - Push dirty cache out and invalidate
2928 + * @paddr: starting physical address
2929 + * @len: number of bytes
2930 + *
2931 + * Push the any dirty lines starting at paddr for len bytes and
2932 + * invalidate those lines.
2933 + */
2934 +static inline void cf_cache_flush(unsigned long paddr, int len)
2935 +{
2936 + /* number of lines */
2937 + len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
2938 + if (len == 0)
2939 + return;
2940 +
2941 + /* align on set boundary */
2942 + paddr &= 0xfffffff0;
2943 +
2944 + asm volatile("nop\n"
2945 + "move%.l %2,%%d0\n"
2946 + "or%.l %3,%%d0\n"
2947 + "movec %%d0,%%cacr\n"
2948 + "move%.l %0,%%a0\n"
2949 + "move%.l %1,%%d0\n"
2950 + "1:\n"
2951 + "cpushl %%bc,(%%a0)\n"
2952 + "lea 0x10(%%a0),%%a0\n"
2953 + "subq%.l #1,%%d0\n"
2954 + "bne.b 1b\n"
2955 + "movec %2,%%cacr\n"
2956 + : : "a" (paddr), "r" (len),
2957 + "r" (shadow_cacr),
2958 + "i" (CF_CACR_SPA)
2959 + : "a0", "d0");
2960 +}
2961 +
2962 +/**
2963 + * cf_cache_flush_range - Push dirty data/inst cache in range out and invalidate
2964 + * @vstart - starting virtual address
2965 + * @vend: ending virtual address
2966 + *
2967 + * Push the any dirty data/instr lines starting at paddr for len bytes and
2968 + * invalidate those lines.
2969 + */
2970 +static inline void cf_cache_flush_range(unsigned long vstart,
2971 + unsigned long vend)
2972 +{
2973 + int len;
2974 +
2975 + /* align on set boundary */
2976 + vstart &= 0xfffffff0;
2977 + vend = PAGE_ALIGN((vend + (CACHE_LINE_SIZE-1))) & 0xfffffff0;
2978 + len = vend - vstart;
2979 + if (len == 0)
2980 + return;
2981 + vstart = __pa(vstart);
2982 + vend = vstart + len;
2983 +
2984 + asm volatile("nop\n"
2985 + "move%.l %2,%%d0\n"
2986 + "or%.l %3,%%d0\n"
2987 + "movec %%d0,%%cacr\n"
2988 + "move%.l %0,%%a0\n"
2989 + "move%.l %1,%%a1\n"
2990 + "1:\n"
2991 + "cpushl %%bc,(%%a0)\n"
2992 + "lea 0x10(%%a0),%%a0\n"
2993 + "cmpa%.l %%a0,%%a1\n"
2994 + "bne.b 1b\n"
2995 + "movec %2,%%cacr\n"
2996 + : /* no return */
2997 + : "a" (vstart), "a" (vend),
2998 + "r" (shadow_cacr),
2999 + "i" (CF_CACR_SPA)
3000 + : "a0", "a1", "d0");
3001 +}
3002 +
3003 +/**
3004 + * cf_dcache_flush_range - Push dirty data cache in range out and invalidate
3005 + * @vstart - starting virtual address
3006 + * @vend: ending virtual address
3007 + *
3008 + * Push/Clear the virtual range *vstart* -> *vend* using the enhanced
3009 + * cpushl instruction to search by physical address.
3010 + *
3011 + * Assumes CACR[IVO] is 0
3012 + * CACR[DDPI] is 0
3013 + *
3014 + * Sets CACR[SPA] to 1 for the duration of this routine
3015 + */
3016 +static inline void cf_dcache_flush_range(unsigned long vstart,
3017 + unsigned long vend)
3018 +{
3019 + /* align on set boundary */
3020 + vstart &= 0xfffffff0;
3021 + vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
3022 +
3023 + asm volatile("nop\n"
3024 + "move%.l %2,%%d0\n"
3025 + "or%.l %3,%%d0\n"
3026 + "movec %%d0,%%cacr\n"
3027 + "move%.l %0,%%a0\n"
3028 + "move%.l %1,%%a1\n"
3029 + "1:\n"
3030 + "cpushl %%dc,(%%a0)\n"
3031 + "lea 0x10(%%a0),%%a0\n"
3032 + "cmpa%.l %%a0,%%a1\n"
3033 + "bne.b 1b\n"
3034 + "movec %2,%%cacr\n"
3035 + : /* no return */
3036 + : "a" (__pa(vstart)), "a" (__pa(vend)),
3037 + "r" (shadow_cacr),
3038 + "i" (CF_CACR_SPA)
3039 + : "a0", "a1", "d0");
3040 +}
3041 +
3042 +/**
3043 + * cf_dcache_inv_range - Invalidate data cache in range
3044 + * @vstart - starting virtual address
3045 + * @vend: ending virtual address
3046 + *
3047 + * Invalidate the virtual range *vstart* -> *vend* using the enhanced
3048 + * cpushl instruction to search by physical address.
3049 + *
3050 + * Assumes CACR[DDPI] is 0
3051 + *
3052 + * Sets CACR[SPA] and CACR[IVO] to 1 for the duration of this routine
3053 + */
3054 +static inline void cf_dcache_inv_range(unsigned long vstart,
3055 + unsigned long vend)
3056 +{
3057 + /* align on set boundary */
3058 + vstart &= 0xfffffff0;
3059 + vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
3060 +
3061 + asm volatile("nop\n"
3062 + "move%.l %2,%%d0\n"
3063 + "or%.l %3,%%d0\n"
3064 + "movec %%d0,%%cacr\n"
3065 + "move%.l %0,%%a0\n"
3066 + "move%.l %1,%%a1\n"
3067 + "1:\n"
3068 + "cpushl %%dc,(%%a0)\n"
3069 + "lea 0x10(%%a0),%%a0\n"
3070 + "cmpa%.l %%a0,%%a1\n"
3071 + "bne.b 1b\n"
3072 + "movec %2,%%cacr\n"
3073 + : /* no return */
3074 + : "a" (__pa(vstart)), "a" (__pa(vend)),
3075 + "r" (shadow_cacr),
3076 + "i" (CF_CACR_SPA | CF_CACR_IVO)
3077 + : "a0", "a1", "d0");
3078 +}
3079 +
3080 +/**
3081 + * cf_dcache_push_range - Push data cache in range
3082 + * @vstart - starting virtual address
3083 + * @vend: ending virtual address
3084 + *
3085 + * Push the virtual range *vstart* -> *vend* using the enhanced
3086 + * cpushl instruction to search by physical address.
3087 + *
3088 + * Assumes CACR[IVO] is 0
3089 + *
3090 + * Sets CACR[SPA] and CACR[DDPI] to 1 for the duration of this routine
3091 + */
3092 +static inline void cf_dcache_push_range(unsigned long vstart,
3093 + unsigned long vend)
3094 +{
3095 + /* align on set boundary */
3096 + vstart &= 0xfffffff0;
3097 + vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
3098 +
3099 + asm volatile("nop\n"
3100 + "move%.l %2,%%d0\n"
3101 + "or%.l %3,%%d0\n"
3102 + "movec %%d0,%%cacr\n"
3103 + "move%.l %0,%%a0\n"
3104 + "move%.l %1,%%a1\n"
3105 + "1:\n"
3106 + "cpushl %%dc,(%%a0)\n"
3107 + "lea 0x10(%%a0),%%a0\n"
3108 + "cmpa%.l %%a0,%%a1\n"
3109 + "bne.b 1b\n"
3110 + "movec %2,%%cacr\n"
3111 + : /* no return */
3112 + : "a" (__pa(vstart)), "a" (__pa(vend)),
3113 + "r" (shadow_cacr),
3114 + "i" (CF_CACR_SPA | CF_CACR_DPI)
3115 + : "a0", "a1", "d0");
3116 +}
3117 +
3118 +/**
3119 + * cf_icache_flush_range - Push dirty inst cache in range out and invalidate
3120 + * @vstart - starting virtual address
3121 + * @vend: ending virtual address
3122 + *
3123 + * Push the any dirty instr lines starting at paddr for len bytes and
3124 + * invalidate those lines. This should just be an invalidate since you
3125 + * shouldn't be able to have dirty instruction cache.
3126 + */
3127 +static inline void cf_icache_flush_range(unsigned long vstart,
3128 + unsigned long vend)
3129 +{
3130 + /* align on set boundary */
3131 + vstart &= 0xfffffff0;
3132 + vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
3133 +
3134 + asm volatile("nop\n"
3135 + "move%.l %2,%%d0\n"
3136 + "or%.l %3,%%d0\n"
3137 + "movec %%d0,%%cacr\n"
3138 + "move%.l %0,%%a0\n"
3139 + "move%.l %1,%%a1\n"
3140 + "1:\n"
3141 + "cpushl %%ic,(%%a0)\n"
3142 + "lea 0x10(%%a0),%%a0\n"
3143 + "cmpa%.l %%a0,%%a1\n"
3144 + "bne.b 1b\n"
3145 + "movec %2,%%cacr\n"
3146 + : /* no return */
3147 + : "a" (__pa(vstart)), "a" (__pa(vend)),
3148 + "r" (shadow_cacr),
3149 + "i" (CF_CACR_SPA)
3150 + : "a0", "a1", "d0");
3151 +}
3152 +
3153 +/**
3154 + * flush_cache_mm - Flush an mm_struct
3155 + * @mm: mm_struct to flush
3156 + */
3157 +static inline void flush_cache_mm(struct mm_struct *mm)
3158 +{
3159 + if (mm == current->mm)
3160 + flush_bcache();
3161 +}
3162 +
3163 +#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
3164 +
3165 +/**
3166 + * flush_cache_range - Flush a cache range
3167 + * @vma: vma struct
3168 + * @start: Starting address
3169 + * @end: Ending address
3170 + *
3171 + * flush_cache_range must be a macro to avoid a dependency on
3172 + * linux/mm.h which includes this file.
3173 + */
3174 +static inline void flush_cache_range(struct vm_area_struct *vma,
3175 + unsigned long start, unsigned long end)
3176 +{
3177 + if (vma->vm_mm == current->mm)
3178 + cf_cache_flush_range(start, end);
3179 +}
3180 +
3181 +/**
3182 + * flush_cache_page - Flush a page of the cache
3183 + * @vma: vma struct
3184 + * @vmaddr:
3185 + * @pfn: page numer
3186 + *
3187 + * flush_cache_page must be a macro to avoid a dependency on
3188 + * linux/mm.h which includes this file.
3189 + */
3190 +static inline void flush_cache_page(struct vm_area_struct *vma,
3191 + unsigned long vmaddr, unsigned long pfn)
3192 +{
3193 + if (vma->vm_mm == current->mm)
3194 + cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE);
3195 +}
3196 +
3197 +/**
3198 + * __flush_page_to_ram - Push a page out of the cache
3199 + * @vaddr: Virtual address at start of page
3200 + *
3201 + * Push the page at kernel virtual address *vaddr* and clear
3202 + * the icache.
3203 + */
3204 +static inline void __flush_page_to_ram(void *vaddr)
3205 +{
3206 + asm volatile("nop\n"
3207 + "move%.l %2,%%d0\n"
3208 + "or%.l %3,%%d0\n"
3209 + "movec %%d0,%%cacr\n"
3210 + "move%.l %0,%%d0\n"
3211 + "and%.l #0xfffffff0,%%d0\n"
3212 + "move%.l %%d0,%%a0\n"
3213 + "move%.l %1,%%d0\n"
3214 + "1:\n"
3215 + "cpushl %%bc,(%%a0)\n"
3216 + "lea 0x10(%%a0),%%a0\n"
3217 + "subq%.l #1,%%d0\n"
3218 + "bne.b 1b\n"
3219 + "movec %2,%%cacr\n"
3220 + : : "a" (__pa(vaddr)), "i" (PAGE_SIZE / CACHE_LINE_SIZE),
3221 + "r" (shadow_cacr), "i" (CF_CACR_SPA)
3222 + : "a0", "d0");
3223 +}
3224 +
3225 +/*
3226 + * Various defines for the kernel.
3227 + */
3228 +
3229 +extern void cache_clear(unsigned long paddr, int len);
3230 +extern void cache_push(unsigned long paddr, int len);
3231 +extern void flush_icache_range(unsigned long address, unsigned long endaddr);
3232 +
3233 +#define flush_cache_all() flush_bcache()
3234 +#define flush_cache_vmap(start, end) flush_bcache()
3235 +#define flush_cache_vunmap(start, end) flush_bcache()
3236 +
3237 +#define flush_dcache_range(vstart, vend) cf_dcache_flush_range(vstart, vend)
3238 +#define flush_dcache_page(page) __flush_page_to_ram(page_address(page))
3239 +#define flush_dcache_mmap_lock(mapping) do { } while (0)
3240 +#define flush_dcache_mmap_unlock(mapping) do { } while (0)
3241 +
3242 +#define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page))
3243 +
3244 +/**
3245 + * copy_to_user_page - Copy memory to user page
3246 + */
3247 +static inline void copy_to_user_page(struct vm_area_struct *vma,
3248 + struct page *page, unsigned long vaddr,
3249 + void *dst, void *src, int len)
3250 +{
3251 + memcpy(dst, src, len);
3252 + cf_cache_flush(page_to_phys(page), PAGE_SIZE);
3253 +}
3254 +
3255 +/**
3256 + * copy_from_user_page - Copy memory from user page
3257 + */
3258 +static inline void copy_from_user_page(struct vm_area_struct *vma,
3259 + struct page *page, unsigned long vaddr,
3260 + void *dst, void *src, int len)
3261 +{
3262 + cf_cache_flush(page_to_phys(page), PAGE_SIZE);
3263 + memcpy(dst, src, len);
3264 +}
3265 +
3266 +#endif /* M68K_CF_5441x_CACHEFLUSH_H */
3267 --- /dev/null
3268 +++ b/arch/m68k/include/asm/mcf5441x_ccm.h
3269 @@ -0,0 +1,157 @@
3270 +/*
3271 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
3272 + *
3273 + * This program is free software; you can redistribute it and/or modify it
3274 + * under the terms of the GNU General Public License as published by the
3275 + * Free Software Foundation; either version 2 of the License, or (at your
3276 + * option) any later version.
3277 + */
3278 +
3279 +#ifndef __MCF5441X_CCM_H__
3280 +#define __MCF5441X_CCM_H__
3281 +
3282 +/*********************************************************************
3283 +*
3284 +* Chip Configuration Module (CCM)
3285 +*
3286 +*********************************************************************/
3287 +
3288 +/* Register read/write macros */
3289 +/* Chip Configuration Register (Read-only) (256 or 360 TEPBGA) */
3290 +#define MCF_CCM_CCR MCF_REG16(0xEC090004)
3291 +/* Reset Configuration (Read-only) (256 or 360 TEPBGA) */
3292 +#define MCF_CCM_RCON MCF_REG16(0xEC090008)
3293 +/* Chip Identification Register (Read-only) */
3294 +#define MCF_CCM_CIR MCF_REG16(0xEC09000A)
3295 +/* Miscellaneous Control Register */
3296 +#define MCF_CCM_MISCCR MCF_REG16(0xEC09000E)
3297 +#define MCF_CCM_CDRH MCF_REG16(0xEC090010) /* Clock Divider Register */
3298 +#define MCF_CCM_CDRL MCF_REG16(0xEC090012) /* Clock Divider Register */
3299 +/* USB On-the-Go Controller Status Register */
3300 +#define MCF_CCM_UOCSR MCF_REG16(0xEC090014)
3301 +/* USB On-the-Go Controller Status Register */
3302 +#define MCF_CCM_UHCSR MCF_REG16(0xEC090016)
3303 +/* Miscellaneous Control Register */
3304 +#define MCF_CCM_MISCCR3 MCF_REG16(0xEC090018)
3305 +/* Miscellaneous Control Register */
3306 +#define MCF_CCM_MISCCR2 MCF_REG16(0xEC09001A)
3307 +#define MCF_CCM_ADCTSR MCF_REG16(0xEC09001C)
3308 +#define MCF_CCM_DACTSR MCF_REG16(0xEC09001E)
3309 +/* Serial Boot Facility Status Register (Read Only) */
3310 +#define MCF_CCM_SBFSR MCF_REG16(0xEC090020)
3311 +/* Serial Boot Facility Control Register */
3312 +#define MCF_CCM_SBFCR MCF_REG16(0xEC090022)
3313 +#define MCF_CCM_FNACR MCF_REG16(0xEC090024)
3314 +
3315 +/* Bit definitions and macros for CIR */
3316 +/* Part revision number */
3317 +#define MCF_CCM_CIR_PRN(x) (((x) & 0x003F))
3318 +/* Part identification number */
3319 +#define MCF_CCM_CIR_PIN(x) (((x) & 0x03FF) << 6)
3320 +#define MCF_CCM_CIR_PIN_MASK (0xFFC0)
3321 +#define MCF_CCM_CIR_PRN_MASK (0x003F)
3322 +#define MCF_CCM_CIR_PIN_MCF54410 (0x9F<<6)
3323 +#define MCF_CCM_CIR_PIN_MCF54415 (0xA0<<6)
3324 +#define MCF_CCM_CIR_PIN_MCF54416 (0xA1<<6)
3325 +#define MCF_CCM_CIR_PIN_MCF54417 (0xA2<<6)
3326 +#define MCF_CCM_CIR_PIN_MCF54418 (0xA3<<6)
3327 +
3328 +/* Bit definitions and macros for MISCCR */
3329 +/* Part revision number */
3330 +#define MCF_CCM_CIR_PRN(x) (((x) & 0x003F))
3331 +/* Part identification number */
3332 +#define MCF_CCM_CIR_PIN(x) (((x) & 0x03FF) << 6)
3333 +#define MCF_CCM_CIR_PIN_MASK (0xFFC0)
3334 +#define MCF_CCM_CIR_PRN_MASK (0x003F)
3335 +#define MCF_CCM_CIR_PIN_MCF54410 (0x9F<<6)
3336 +#define MCF_CCM_CIR_PIN_MCF54415 (0xA0<<6)
3337 +#define MCF_CCM_CIR_PIN_MCF54416 (0xA1<<6)
3338 +#define MCF_CCM_CIR_PIN_MCF54417 (0xA2<<6)
3339 +#define MCF_CCM_CIR_PIN_MCF54418 (0xA3<<6)
3340 +#define MCF_CCM_MISCCR_PWM_EXTCLK(x) (((x)&(0x0003)<<14)
3341 +#define MCF_CCM_MISCCR_PWM_EXTCLK_MASK (0x3FFF)
3342 +#define MCF_CCM_MISCCR_PWM_EXTCLK_TMR0 (0x0000)
3343 +#define MCF_CCM_MISCCR_PWM_EXTCLK_TMR1 (0x4000)
3344 +#define MCF_CCM_MISCCR_PWM_EXTCLK_TMR2 (0x8000)
3345 +#define MCF_CCM_MISCCR_PWM_EXTCLK_TMR3 (0xC000)
3346 +#define MCF_CCM_MISCCR_LIMP (0x1000)
3347 +#define MCF_CCM_MISCCR_BME (0x0800)
3348 +#define MCF_CCM_MISCCR_BMT(x) (((x)&0x0007)<<8)
3349 +#define MCF_CCM_MISCCR_BMT_MASK (0xF8FF)
3350 +#define MCF_CCM_MISCCR_BMT_65536 (0)
3351 +#define MCF_CCM_MISCCR_BMT_32768 (1)
3352 +#define MCF_CCM_MISCCR_BMT_16384 (2)
3353 +#define MCF_CCM_MISCCR_BMT_8192 (3)
3354 +#define MCF_CCM_MISCCR_BMT_4096 (4)
3355 +#define MCF_CCM_MISCCR_BMT_2048 (5)
3356 +#define MCF_CCM_MISCCR_BMT_1024 (6)
3357 +#define MCF_CCM_MISCCR_BMT_512 (7)
3358 +#define MCF_CCM_MISCCR_SDHCSRC (0x0040)
3359 +#define MCF_CCM_MISCCR_SSI1SRC (0x0020)
3360 +#define MCF_CCM_MISCCR_SSI0SRC (0x0010)
3361 +#define MCF_CCM_MISCCR_USBHOC (0x0008)
3362 +#define MCF_CCM_MISCCR_USBOOC (0x0004)
3363 +#define MCF_CCM_MISCCR_USBPUE (0x0002)
3364 +#define MCF_CCM_MISCCR_USBSRC (0x0001)
3365 +#define MCF_CCM_CDRH_SSI0DIV(x) (((x)&0x00FF)<<8)
3366 +#define MCF_CCM_CDRH_SSI0DIV_MASK (0x00FF)
3367 +#define MCF_CCM_CDRH_SSI1DIV(x) (((x)&0x00FF))
3368 +#define MCF_CCM_CDRH_SSI1DIV_MASK (0xFF00)
3369 +#define MCF_CCM_CDRL_LPDIV(x) (((x)&0x000F)<<8)
3370 +#define MCF_CCM_CDRL_LPDIV_MASK (0xFF0F)
3371 +#define MCF_CCM_CDR_LPDIV(x) CCM_CDRL_LPDIV(x)
3372 +
3373 +#define MCF_CCM_UOCSR_DPPD (0x2000)
3374 +#define MCF_CCM_UOCSR_DMPD (0x1000)
3375 +#define MCF_CCM_UOCSR_DRV_VBUS (0x0800)
3376 +#define MCF_CCM_UOCSR_CRG_VBUS (0x0400)
3377 +#define MCF_CCM_UOCSR_DCR_VBUS (0x0200)
3378 +#define MCF_CCM_UOCSR_DPPU (0x0100)
3379 +#define MCF_CCM_UOCSR_AVLD (0x0080)
3380 +#define MCF_CCM_UOCSR_BVLD (0x0040)
3381 +#define MCF_CCM_UOCSR_VVLD (0x0020)
3382 +#define MCF_CCM_UOCSR_SEND (0x0010)
3383 +#define MCF_CCM_UOCSR_PWRFLT (0x0008)
3384 +#define MCF_CCM_UOCSR_WKUP (0x0004)
3385 +#define MCF_CCM_UOCSR_UOMIE (0x0002)
3386 +#define MCF_CCM_UOCSR_XPDE (0x0001)
3387 +
3388 +#define MCF_CCM_UHCSR_DRV_VBUS (0x0010)
3389 +#define MCF_CCM_UHCSR_PWRFLT (0x0008)
3390 +#define MCF_CCM_UHCSR_WKUP (0x0004)
3391 +#define MCF_CCM_UHCSR_UOMIE (0x0002)
3392 +#define MCF_CCM_UHCSR_XPDE (0x0001)
3393 +
3394 +#define MCF_CCM_MISCCR3_TMR_ENET (0x1000)
3395 +#define MCF_CCM_MISCCR3_ENETCLK(x) ((((x)&7))<<8)
3396 +#define MCF_CCM_MISCCR3_ENETCLK_MASK (0xF8FF)
3397 +#define MCF_CCM_MISCCR3_ENETCLK_MII (0x0700)
3398 +#define MCF_CCM_MISCCR3_ENETCLK_OSC (0x0600)
3399 +#define MCF_CCM_MISCCR3_ENETCLK_USB (0x0500)
3400 +#define MCF_CCM_MISCCR3_ENETCLK_TMR3 (0x0400)
3401 +#define MCF_CCM_MISCCR3_ENETCLK_TMR2 (0x0300)
3402 +#define MCF_CCM_MISCCR3_ENETCLK_TMR1 (0x0200)
3403 +#define MCF_CCM_MISCCR3_ENETCLK_TMR0 (0x0100)
3404 +#define MCF_CCM_MISCCR3_ENETCLK_INTBUS (0x0000)
3405 +
3406 +#define MCF_CCM_MISCCR2_EXTCLKBYP (0x0800)
3407 +#define MCF_CCM_MISCCR2_DDR2CLK (0x0400)
3408 +#define MCF_CCM_MISCCR2_RGPIO_HALF (0x0200)
3409 +#define MCF_CCM_MISCCR2_SWTSCR (0x0100)
3410 +#define MCF_CCM_MISCCR2_PLLMODE(x) (((x)&7)<<8)
3411 +#define MCF_CCM_MISCCR2_PLLMODE_MASK (0xF8FF)
3412 +#define MCF_CCM_MISCCR2_DCCBYP (0x0080)
3413 +#define MCF_CCM_MISCCR2_DAC1SEL (0x0040)
3414 +#define MCF_CCM_MISCCR2_DAC0SEL (0x0020)
3415 +#define MCF_CCM_MISCCR2_ADCEN (0x0010)
3416 +#define MCF_CCM_MISCCR2_ADC7SEL (0x0008)
3417 +#define MCF_CCM_MISCCR2_ADC3SEL (0x0004)
3418 +#define MCF_CCM_MISCCR2_FBHALF (0x0002)
3419 +#define MCF_CCM_MISCCR2_ULPI (0x0001)
3420 +
3421 +#define MCF_CCM_FNACR_PCR(x) (((x)&0x0F)<<24)
3422 +#define MCF_CCM_FNACR_PCR_MASK (0xF0FFFFFF)
3423 +#define MCF_CCM_FNACR_MCC(x) ((x)&0xFFFF)
3424 +#define MCF_CCM_FNACR_MCC_MASK (0xFFFF0000)
3425 +
3426 +#endif /* __MCF5445X_CCM_H__ */
3427 --- /dev/null
3428 +++ b/arch/m68k/include/asm/mcf5441x_clock.h
3429 @@ -0,0 +1,22 @@
3430 +/*
3431 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
3432 + *
3433 + * This program is free software; you can redistribute it and/or modify it
3434 + * under the terms of the GNU General Public License as published by the
3435 + * Free Software Foundation; either version 2 of the License, or (at your
3436 + * option) any later version.
3437 + */
3438 +
3439 +#ifndef __MCF5441X_CLOCK_H__
3440 +#define __MCF5441X_CLOCK_H__
3441 +
3442 +#define MCF_PLL_CR MCF_REG32(0xFC000000)
3443 +#define MCF_PLL_DR MCF_REG32(0xFC000004)
3444 +#define MCF_PLL_SR MCF_REG32(0xFC000008)
3445 +
3446 +#define MCF_PLL_DR_OUTDIV4 0x001F0000
3447 +#define MCF_PLL_DR_OUTDIV1 0x1F
3448 +
3449 +
3450 +#endif /*__MCF5441X_CLOCK_H__*/
3451 +
3452 --- /dev/null
3453 +++ b/arch/m68k/include/asm/mcf5441x_dspi.h
3454 @@ -0,0 +1,671 @@
3455 +/*
3456 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
3457 + *
3458 + * Lanttor.Guo@freescale.com
3459 + *
3460 + * This program is free software; you can redistribute it and/or modify it
3461 + * under the terms of the GNU General Public License as published by the
3462 + * Free Software Foundation; either version 2 of the License, or (at your
3463 + * option) any later version.
3464 + */
3465 +
3466 +#ifndef __MCF5441X_DSPI_H__
3467 +#define __MCF5441X_DSPI_H__
3468 +
3469 +/*********************************************************************
3470 +*
3471 +* DMA Serial Peripheral Interface (DSPI)
3472 +*
3473 +*********************************************************************/
3474 +
3475 +/* Register read/write macros */
3476 +/* DSPI Module Configuration Register */
3477 +#define MCF_DSPI_DMCR MCF_REG32(0xFC05C000)
3478 +#define MCF_DSPI1_DMCR MCF_REG32(0xFC03C000)
3479 +/* DSPI Transfer Count Register */
3480 +#define MCF_DSPI_DTCR MCF_REG32(0xFC05C008)
3481 +#define MCF_DSPI1_DTCR MCF_REG32(0xFC03C008)
3482 +/* DSPI Clock and Transfer Attributes Register */
3483 +#define MCF_DSPI_DCTAR0 MCF_REG32(0xFC05C00C)
3484 +#define MCF_DSPI1_DCTAR0 MCF_REG32(0xFC03C00C)
3485 +/* DSPI Clock and Transfer Attributes Register */
3486 +#define MCF_DSPI_DCTAR1 MCF_REG32(0xFC05C010)
3487 +/* DSPI Clock and Transfer Attributes Register */
3488 +#define MCF_DSPI_DCTAR2 MCF_REG32(0xFC05C014)
3489 +/* DSPI Clock and Transfer Attributes Register */
3490 +#define MCF_DSPI_DCTAR3 MCF_REG32(0xFC05C018)
3491 +/* DSPI Clock and Transfer Attributes Register */
3492 +#define MCF_DSPI_DCTAR4 MCF_REG32(0xFC05C01C)
3493 +/* DSPI Clock and Transfer Attributes Register */
3494 +#define MCF_DSPI_DCTAR5 MCF_REG32(0xFC05C020)
3495 +/* DSPI Clock and Transfer Attributes Register */
3496 +#define MCF_DSPI_DCTAR6 MCF_REG32(0xFC05C024)
3497 +/* DSPI Clock and Transfer Attributes Register */
3498 +#define MCF_DSPI_DCTAR7 MCF_REG32(0xFC05C028
3499 +/* DSPI Status Register */
3500 +#define MCF_DSPI_DSR MCF_REG32(0xFC05C02C)
3501 +#define MCF_DSPI1_DSR MCF_REG32(0xFC03C02C)
3502 +/* DSPI DMA/Interrupt Request Select and Enable Register */
3503 +#define MCF_DSPI_DRSER MCF_REG32(0xFC05C030)
3504 +#define MCF_DSPI1_DRSER MCF_REG32(0xFC03C030)
3505 +/* DSPI Transmit FIFO Register */
3506 +#define MCF_DSPI_DTFR MCF_REG32(0xFC05C034)
3507 +#define MCF_DSPI1_DTFR MCF_REG32(0xFC03C034)
3508 +/* DSPI Receive FIFO Register */
3509 +#define MCF_DSPI_DRFR MCF_REG32(0xFC05C038)
3510 +#define MCF_DSPI1_DRFR MCF_REG32(0xFC03C038)
3511 +/* DSPI Transmit FIFO Debugging Registers */
3512 +#define MCF_DSPI_DTFDR0 MCF_REG32(0xFC05C03C)
3513 +/* DSPI Transmit FIFO Debugging Registers */
3514 +#define MCF_DSPI_DTFDR1 MCF_REG32(0xFC05C040)
3515 +/* DSPI Transmit FIFO Debugging Registers */
3516 +#define MCF_DSPI_DTFDR2 MCF_REG32(0xFC05C044)
3517 +/* DSPI Transmit FIFO Debugging Registers */
3518 +#define MCF_DSPI_DTFDR3 MCF_REG32(0xFC05C048)
3519 +/* DSPI Receive FIFO Debugging Registers */
3520 +#define MCF_DSPI_DRFDR0 MCF_REG32(0xFC05C07C)
3521 +/* DSPI Receive FIFO Debugging Registers */
3522 +#define MCF_DSPI_DRFDR1 MCF_REG32(0xFC05C080)
3523 +/* DSPI Receive FIFO Debugging Registers */
3524 +#define MCF_DSPI_DRFDR2 MCF_REG32(0xFC05C084)
3525 +/* DSPI Receive FIFO Debugging Registers */
3526 +#define MCF_DSPI_DRFDR3 MCF_REG32(0xFC05C088)
3527 +
3528 +/* Parameterized register read/write macros for multiple registers */
3529 +/* DSPI Clock and Transfer Attributes Register */
3530 +#define MCF_DSPI_DCTAR(x) MCF_REG32(0xFC05C00C+((x)*0x004))
3531 +/* DSPI Transmit FIFO Debugging Registers */
3532 +#define MCF_DSPI_DTFDR(x) MCF_REG32(0xFC05C03C+((x)*0x004))
3533 +/* DSPI Receive FIFO Debugging Registers */
3534 +#define MCF_DSPI_DRFDR(x) MCF_REG32(0xFC05C07C+((x)*0x004))
3535 +
3536 +/* Bit definitions and macros for DMCR */
3537 +/* Halt -- stops and starts DSPI transfers */
3538 +#define MCF_DSPI_DMCR_HALT (0x00000001)
3539 +/* Sample point selection */
3540 +#define MCF_DSPI_DMCR_SMPLPT(x) (((x)&0x00000003)<<8)
3541 +/* Clear receive FIFO */
3542 +#define MCF_DSPI_DMCR_CLRRXF (0x00000400)
3543 +/* Clear transmit FIFO */
3544 +#define MCF_DSPI_DMCR_CLRTXF (0x00000800)
3545 +/* Disable receive FIFO */
3546 +#define MCF_DSPI_DMCR_DISRXF (0x00001000)
3547 +/* Disable transmit FIFO */
3548 +#define MCF_DSPI_DMCR_DISTXF (0x00002000)
3549 +/* Module Disable */
3550 +#define MCF_DSPI_DMCR_MDIS (0x00004000)
3551 +/* Peripheral chip-select 0 inactive state */
3552 +#define MCF_DSPI_DMCR_PCSIS0 (0x00010000)
3553 +/* Peripheral chip-select 1 inactive state */
3554 +#define MCF_DSPI_DMCR_PCSIS1 (0x00020000)
3555 +/* Peripheral chip-select 2 inactive state */
3556 +#define MCF_DSPI_DMCR_PCSIS2 (0x00040000)
3557 +/* Peripheral chip-select 3 inactive state */
3558 +#define MCF_DSPI_DMCR_PCSIS3 (0x00080000)
3559 +/* Peripheral chip-select 4 inactive state */
3560 +#define MCF_DSPI_DMCR_PCSIS4 (0x00100000)
3561 +/* Peripheral chip-select 5 inactive state */
3562 +#define MCF_DSPI_DMCR_PCSIS5 (0x00200000)
3563 +/* Peripheral chip-select 6 inactive state */
3564 +#define MCF_DSPI_DMCR_PCSIS6 (0x00400000)
3565 +/* Peripheral chip-select 7 inactive state */
3566 +#define MCF_DSPI_DMCR_PCSIS7 (0x00800000)
3567 +/* Receive FIFO overflow overwrite enable */
3568 +#define MCF_DSPI_DMCR_ROOE (0x01000000)
3569 +/* Peripheral chip select strobe enable */
3570 +#define MCF_DSPI_DMCR_PCSSE (0x02000000)
3571 +/* Modified timing format enable */
3572 +#define MCF_DSPI_DMCR_MTFE (0x04000000)
3573 +/* Freeze */
3574 +#define MCF_DSPI_DMCR_FRZ (0x08000000)
3575 +/* DSPI configuration */
3576 +#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28)
3577 +/* Continuous SCK enable */
3578 +#define MCF_DSPI_DMCR_CONT_SCKE (0x40000000)
3579 +/* Master/Slave mode select */
3580 +#define MCF_DSPI_DMCR_MSTR (0x80000000)
3581 +#define MCF_DSPI_DMCR_DCONF_SPI (0x00000000)
3582 +#define MCF_DSPI_DMCR_PCSIS7_LOW (0x00000000)
3583 +#define MCF_DSPI_DMCR_PCSIS7_HIGH (0x00800000)
3584 +#define MCF_DSPI_DMCR_PCSIS6_LOW (0x00000000)
3585 +#define MCF_DSPI_DMCR_PCSIS6_HIGH (0x00400000)
3586 +#define MCF_DSPI_DMCR_PCSIS5_LOW (0x00000000)
3587 +#define MCF_DSPI_DMCR_PCSIS5_HIGH (0x00200000)
3588 +#define MCF_DSPI_DMCR_PCSIS4_LOW (0x00000000)
3589 +#define MCF_DSPI_DMCR_PCSIS4_HIGH (0x00100000)
3590 +#define MCF_DSPI_DMCR_PCSIS3_LOW (0x00000000)
3591 +#define MCF_DSPI_DMCR_PCSIS3_HIGH (0x00080000)
3592 +#define MCF_DSPI_DMCR_PCSIS2_LOW (0x00000000)
3593 +#define MCF_DSPI_DMCR_PCSIS2_HIGH (0x00040000)
3594 +#define MCF_DSPI_DMCR_PCSIS1_LOW (0x00000000)
3595 +#define MCF_DSPI_DMCR_PCSIS1_HIGH (0x00020000)
3596 +#define MCF_DSPI_DMCR_PCSIS0_LOW (0x00000000)
3597 +#define MCF_DSPI_DMCR_PCSIS0_HIGH (0x00010000)
3598 +
3599 +/* Bit definitions and macros for DTCR */
3600 +/* SPI transfer count */
3601 +#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
3602 +
3603 +/* Bit definitions and macros for DCTAR group */
3604 +/* Baud rate scaler */
3605 +#define MCF_DSPI_DCTAR_BR(x) (((x)&0x0000000F))
3606 +/* Delay after transfer scaler */
3607 +#define MCF_DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4)
3608 +/* After SCK delay scaler */
3609 +#define MCF_DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8)
3610 +/* PCS to SCK delay scaler */
3611 +#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12)
3612 +/* Baud rate prescaler */
3613 +#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16)
3614 +/* Delay after transfer prescaler */
3615 +#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18)
3616 +/* After SCK delay prescaler */
3617 +#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20)
3618 +/* PCS to SCK delay prescaler */
3619 +#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22)
3620 +/* LSB first enable */
3621 +#define MCF_DSPI_DCTAR_LSBFE (0x01000000)
3622 +/* Clock phase */
3623 +#define MCF_DSPI_DCTAR_CPHA (0x02000000)
3624 +/* Clock polarity */
3625 +#define MCF_DSPI_DCTAR_CPOL (0x04000000)
3626 +/* Frame size */
3627 +#define MCF_DSPI_DCTAR_FMSZ(x) (((x)&0x0000000F)<<27)
3628 +/* Double baud rate */
3629 +#define MCF_DSPI_DCTAR_DBR (0x80000000)
3630 +#define MCF_DSPI_DCTAR_CPOL_LOW (0x00000000)
3631 +#define MCF_DSPI_DCTAR_CPOL_HIGH (0x04000000)
3632 +#define MCF_DSPI_DCTAR_CPHA_LATCH_RISING (0x00000000)
3633 +#define MCF_DSPI_DCTAR_CPHA_LATCH_FALLING (0x02000000)
3634 +#define MCF_DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
3635 +#define MCF_DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
3636 +#define MCF_DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
3637 +#define MCF_DSPI_DCTAR_PCSSCK_7CLK (0x00C00000)
3638 +#define MCF_DSPI_DCTAR_PASC_1CLK (0x00000000)
3639 +#define MCF_DSPI_DCTAR_PASC_3CLK (0x00100000)
3640 +#define MCF_DSPI_DCTAR_PASC_5CLK (0x00200000)
3641 +#define MCF_DSPI_DCTAR_PASC_7CLK (0x00300000)
3642 +#define MCF_DSPI_DCTAR_PDT_1CLK (0x00000000)
3643 +#define MCF_DSPI_DCTAR_PDT_3CLK (0x00040000)
3644 +#define MCF_DSPI_DCTAR_PDT_5CLK (0x00080000)
3645 +#define MCF_DSPI_DCTAR_PDT_7CLK (0x000C0000)
3646 +#define MCF_DSPI_DCTAR_PBR_2CLK (0x00000000)
3647 +#define MCF_DSPI_DCTAR_PBR_3CLK (0x00010000)
3648 +#define MCF_DSPI_DCTAR_PBR_5CLK (0x00020000)
3649 +#define MCF_DSPI_DCTAR_PBR_7CLK (0x00030000)
3650 +
3651 +/* Bit definitions and macros for DCTAR0 */
3652 +/* Baud rate scaler */
3653 +#define MCF_DSPI_DCTAR0_BR(x) (((x)&0x0000000F))
3654 +/* Delay after transfer scaler */
3655 +#define MCF_DSPI_DCTAR0_DT(x) (((x)&0x0000000F)<<4)
3656 +/* After SCK delay scaler */
3657 +#define MCF_DSPI_DCTAR0_ASC(x) (((x)&0x0000000F)<<8)
3658 +/* PCS to SCK delay scaler */
3659 +#define MCF_DSPI_DCTAR0_CSSCK(x) (((x)&0x0000000F)<<12)
3660 +/* Baud rate prescaler */
3661 +#define MCF_DSPI_DCTAR0_PBR(x) (((x)&0x00000003)<<16)
3662 +/* Delay after transfer prescaler */
3663 +#define MCF_DSPI_DCTAR0_PDT(x) (((x)&0x00000003)<<18)
3664 +/* After SCK delay prescaler */
3665 +#define MCF_DSPI_DCTAR0_PASC(x) (((x)&0x00000003)<<20)
3666 +/* PCS to SCK delay prescaler */
3667 +#define MCF_DSPI_DCTAR0_PCSSCK(x) (((x)&0x00000003)<<22)
3668 +/* LSB first enable */
3669 +#define MCF_DSPI_DCTAR0_LSBFE (0x01000000)
3670 +/* Clock phase */
3671 +#define MCF_DSPI_DCTAR0_CPHA (0x02000000)
3672 +/* Clock polarity */
3673 +#define MCF_DSPI_DCTAR0_CPOL (0x04000000)
3674 +/* Frame size */
3675 +#define MCF_DSPI_DCTAR0_FMSZ(x) (((x)&0x0000000F)<<27)
3676 +/* Double baud rate */
3677 +#define MCF_DSPI_DCTAR0_DBR (0x80000000)
3678 +#define MCF_DSPI_DCTAR0_CPOL_LOW (0x00000000)
3679 +#define MCF_DSPI_DCTAR0_CPOL_HIGH (0x04000000)
3680 +#define MCF_DSPI_DCTAR0_CPHA_LATCH_RISING (0x00000000)
3681 +#define MCF_DSPI_DCTAR0_CPHA_LATCH_FALLING (0x02000000)
3682 +#define MCF_DSPI_DCTAR0_PCSSCK_1CLK (0x00000000)
3683 +#define MCF_DSPI_DCTAR0_PCSSCK_3CLK (0x00400000)
3684 +#define MCF_DSPI_DCTAR0_PCSSCK_5CLK (0x00800000)
3685 +#define MCF_DSPI_DCTAR0_PCSSCK_7CLK (0x00C00000)
3686 +#define MCF_DSPI_DCTAR0_PASC_1CLK (0x00000000)
3687 +#define MCF_DSPI_DCTAR0_PASC_3CLK (0x00100000)
3688 +#define MCF_DSPI_DCTAR0_PASC_5CLK (0x00200000)
3689 +#define MCF_DSPI_DCTAR0_PASC_7CLK (0x00300000)
3690 +#define MCF_DSPI_DCTAR0_PDT_1CLK (0x00000000)
3691 +#define MCF_DSPI_DCTAR0_PDT_3CLK (0x00040000)
3692 +#define MCF_DSPI_DCTAR0_PDT_5CLK (0x00080000)
3693 +#define MCF_DSPI_DCTAR0_PDT_7CLK (0x000C0000)
3694 +#define MCF_DSPI_DCTAR0_PBR_2CLK (0x00000000)
3695 +#define MCF_DSPI_DCTAR0_PBR_3CLK (0x00010000)
3696 +#define MCF_DSPI_DCTAR0_PBR_5CLK (0x00020000)
3697 +#define MCF_DSPI_DCTAR0_PBR_7CLK (0x00030000)
3698 +
3699 +/* Bit definitions and macros for DCTAR1 */
3700 +/* Baud rate scaler */
3701 +#define MCF_DSPI_DCTAR1_BR(x) (((x)&0x0000000F))
3702 +/* Delay after transfer scaler */
3703 +#define MCF_DSPI_DCTAR1_DT(x) (((x)&0x0000000F)<<4)
3704 +/* After SCK delay scaler */
3705 +#define MCF_DSPI_DCTAR1_ASC(x) (((x)&0x0000000F)<<8)
3706 +/* PCS to SCK delay scaler */
3707 +#define MCF_DSPI_DCTAR1_CSSCK(x) (((x)&0x0000000F)<<12)
3708 +/* Baud rate prescaler */
3709 +#define MCF_DSPI_DCTAR1_PBR(x) (((x)&0x00000003)<<16)
3710 +/* Delay after transfer prescaler */
3711 +#define MCF_DSPI_DCTAR1_PDT(x) (((x)&0x00000003)<<18)
3712 +/* After SCK delay prescaler */
3713 +#define MCF_DSPI_DCTAR1_PASC(x) (((x)&0x00000003)<<20)
3714 +/* PCS to SCK delay prescaler */
3715 +#define MCF_DSPI_DCTAR1_PCSSCK(x) (((x)&0x00000003)<<22)
3716 +/* LSB first enable */
3717 +#define MCF_DSPI_DCTAR1_LSBFE (0x01000000)
3718 +/* Clock phase */
3719 +#define MCF_DSPI_DCTAR1_CPHA (0x02000000)
3720 +/* Clock polarity */
3721 +#define MCF_DSPI_DCTAR1_CPOL (0x04000000)
3722 +/* Frame size */
3723 +#define MCF_DSPI_DCTAR1_FMSZ(x) (((x)&0x0000000F)<<27)
3724 +/* Double baud rate */
3725 +#define MCF_DSPI_DCTAR1_DBR (0x80000000)
3726 +
3727 +
3728 +/* Bit definitions and macros for DCTAR2 */
3729 +/* Baud rate scaler */
3730 +#define MCF_DSPI_DCTAR2_BR(x) (((x)&0x0000000F))
3731 +/* Delay after transfer scaler */
3732 +#define MCF_DSPI_DCTAR2_DT(x) (((x)&0x0000000F)<<4)
3733 +/* After SCK delay scaler */
3734 +#define MCF_DSPI_DCTAR2_ASC(x) (((x)&0x0000000F)<<8)
3735 +/* PCS to SCK delay scaler */
3736 +#define MCF_DSPI_DCTAR2_CSSCK(x) (((x)&0x0000000F)<<12)
3737 +/* Baud rate prescaler */
3738 +#define MCF_DSPI_DCTAR2_PBR(x) (((x)&0x00000003)<<16)
3739 +/* Delay after transfer prescaler */
3740 +#define MCF_DSPI_DCTAR2_PDT(x) (((x)&0x00000003)<<18)
3741 +/* After SCK delay prescaler */
3742 +#define MCF_DSPI_DCTAR2_PASC(x) (((x)&0x00000003)<<20)
3743 +/* PCS to SCK delay prescaler */
3744 +#define MCF_DSPI_DCTAR2_PCSSCK(x) (((x)&0x00000003)<<22)
3745 +/* LSB first enable */
3746 +#define MCF_DSPI_DCTAR2_LSBFE (0x01000000)
3747 +/* Clock phase */
3748 +#define MCF_DSPI_DCTAR2_CPHA (0x02000000)
3749 +/* Clock polarity */
3750 +#define MCF_DSPI_DCTAR2_CPOL (0x04000000)
3751 +/* Frame size */
3752 +#define MCF_DSPI_DCTAR2_FMSZ(x) (((x)&0x0000000F)<<27)
3753 +/* Double baud rate */
3754 +#define MCF_DSPI_DCTAR2_DBR (0x80000000)
3755 +
3756 +/* Bit definitions and macros for DCTAR3 */
3757 +/* Baud rate scaler */
3758 +#define MCF_DSPI_DCTAR3_BR(x) (((x)&0x0000000F))
3759 +/* Delay after transfer scaler */
3760 +#define MCF_DSPI_DCTAR3_DT(x) (((x)&0x0000000F)<<4)
3761 +/* After SCK delay scaler */
3762 +#define MCF_DSPI_DCTAR3_ASC(x) (((x)&0x0000000F)<<8)
3763 +/* PCS to SCK delay scaler */
3764 +#define MCF_DSPI_DCTAR3_CSSCK(x) (((x)&0x0000000F)<<12)
3765 +/* Baud rate prescaler */
3766 +#define MCF_DSPI_DCTAR3_PBR(x) (((x)&0x00000003)<<16)
3767 +/* Delay after transfer prescaler */
3768 +#define MCF_DSPI_DCTAR3_PDT(x) (((x)&0x00000003)<<18)
3769 +/* After SCK delay prescaler */
3770 +#define MCF_DSPI_DCTAR3_PASC(x) (((x)&0x00000003)<<20)
3771 +/* PCS to SCK delay prescaler */
3772 +#define MCF_DSPI_DCTAR3_PCSSCK(x) (((x)&0x00000003)<<22)
3773 +/* LSB first enable */
3774 +#define MCF_DSPI_DCTAR3_LSBFE (0x01000000)
3775 +/* Clock phase */
3776 +#define MCF_DSPI_DCTAR3_CPHA (0x02000000)
3777 +/* Clock polarity */
3778 +#define MCF_DSPI_DCTAR3_CPOL (0x04000000)
3779 +/* Frame size */
3780 +#define MCF_DSPI_DCTAR3_FMSZ(x) (((x)&0x0000000F)<<27)
3781 +/* Double baud rate */
3782 +#define MCF_DSPI_DCTAR3_DBR (0x80000000)
3783 +
3784 +/* Bit definitions and macros for DCTAR4 */
3785 +/* Baud rate scaler */
3786 +#define MCF_DSPI_DCTAR4_BR(x) (((x)&0x0000000F))
3787 +/* Delay after transfer scaler */
3788 +#define MCF_DSPI_DCTAR4_DT(x) (((x)&0x0000000F)<<4)
3789 +/* After SCK delay scaler */
3790 +#define MCF_DSPI_DCTAR4_ASC(x) (((x)&0x0000000F)<<8)
3791 +/* PCS to SCK delay scaler */
3792 +#define MCF_DSPI_DCTAR4_CSSCK(x) (((x)&0x0000000F)<<12)
3793 +/* Baud rate prescaler */
3794 +#define MCF_DSPI_DCTAR4_PBR(x) (((x)&0x00000003)<<16)
3795 +/* Delay after transfer prescaler */
3796 +#define MCF_DSPI_DCTAR4_PDT(x) (((x)&0x00000003)<<18)
3797 +/* After SCK delay prescaler */
3798 +#define MCF_DSPI_DCTAR4_PASC(x) (((x)&0x00000003)<<20)
3799 +/* PCS to SCK delay prescaler */
3800 +#define MCF_DSPI_DCTAR4_PCSSCK(x) (((x)&0x00000003)<<22)
3801 +/* LSB first enable */
3802 +#define MCF_DSPI_DCTAR4_LSBFE (0x01000000)
3803 +/* Clock phase */
3804 +#define MCF_DSPI_DCTAR4_CPHA (0x02000000)
3805 +/* Clock polarity */
3806 +#define MCF_DSPI_DCTAR4_CPOL (0x04000000)
3807 +/* Frame size */
3808 +#define MCF_DSPI_DCTAR4_FMSZ(x) (((x)&0x0000000F)<<27)
3809 +/* Double baud rate */
3810 +#define MCF_DSPI_DCTAR4_DBR (0x80000000)
3811 +
3812 +/* Bit definitions and macros for DCTAR5 */
3813 +/* Baud rate scaler */
3814 +#define MCF_DSPI_DCTAR5_BR(x) (((x)&0x0000000F))
3815 +/* Delay after transfer scaler */
3816 +#define MCF_DSPI_DCTAR5_DT(x) (((x)&0x0000000F)<<4)
3817 +/* After SCK delay scaler */
3818 +#define MCF_DSPI_DCTAR5_ASC(x) (((x)&0x0000000F)<<8)
3819 +/* PCS to SCK delay scaler */
3820 +#define MCF_DSPI_DCTAR5_CSSCK(x) (((x)&0x0000000F)<<12)
3821 +/* Baud rate prescaler */
3822 +#define MCF_DSPI_DCTAR5_PBR(x) (((x)&0x00000003)<<16)
3823 +/* Delay after transfer prescaler */
3824 +#define MCF_DSPI_DCTAR5_PDT(x) (((x)&0x00000003)<<18)
3825 +/* After SCK delay prescaler */
3826 +#define MCF_DSPI_DCTAR5_PASC(x) (((x)&0x00000003)<<20)
3827 +/* PCS to SCK delay prescaler */
3828 +#define MCF_DSPI_DCTAR5_PCSSCK(x) (((x)&0x00000003)<<22)
3829 +/* LSB first enable */
3830 +#define MCF_DSPI_DCTAR5_LSBFE (0x01000000)
3831 +/* Clock phase */
3832 +#define MCF_DSPI_DCTAR5_CPHA (0x02000000)
3833 +/* Clock polarity */
3834 +#define MCF_DSPI_DCTAR5_CPOL (0x04000000)
3835 +/* Frame size */
3836 +#define MCF_DSPI_DCTAR5_FMSZ(x) (((x)&0x0000000F)<<27)
3837 +/* Double baud rate */
3838 +#define MCF_DSPI_DCTAR5_DBR (0x80000000)
3839 +
3840 +/* Bit definitions and macros for DCTAR6 */
3841 +/* Baud rate scaler */
3842 +#define MCF_DSPI_DCTAR6_BR(x) (((x)&0x0000000F))
3843 +/* Delay after transfer scaler */
3844 +#define MCF_DSPI_DCTAR6_DT(x) (((x)&0x0000000F)<<4)
3845 +/* After SCK delay scaler */
3846 +#define MCF_DSPI_DCTAR6_ASC(x) (((x)&0x0000000F)<<8)
3847 +/* PCS to SCK delay scaler */
3848 +#define MCF_DSPI_DCTAR6_CSSCK(x) (((x)&0x0000000F)<<12)
3849 +/* Baud rate prescaler */
3850 +#define MCF_DSPI_DCTAR6_PBR(x) (((x)&0x00000003)<<16)
3851 +/* Delay after transfer prescaler */
3852 +#define MCF_DSPI_DCTAR6_PDT(x) (((x)&0x00000003)<<18)
3853 +/* After SCK delay prescaler */
3854 +#define MCF_DSPI_DCTAR6_PASC(x) (((x)&0x00000003)<<20)
3855 +/* PCS to SCK delay prescaler */
3856 +#define MCF_DSPI_DCTAR6_PCSSCK(x) (((x)&0x00000003)<<22)
3857 +/* LSB first enable */
3858 +#define MCF_DSPI_DCTAR6_LSBFE (0x01000000)
3859 +/* Clock phase */
3860 +#define MCF_DSPI_DCTAR6_CPHA (0x02000000)
3861 +/* Clock polarity */
3862 +#define MCF_DSPI_DCTAR6_CPOL (0x04000000)
3863 +/* Frame size */
3864 +#define MCF_DSPI_DCTAR6_FMSZ(x) (((x)&0x0000000F)<<27)
3865 +/* Double baud rate */
3866 +#define MCF_DSPI_DCTAR6_DBR (0x80000000)
3867 +
3868 +/* Bit definitions and macros for DCTAR7 */
3869 +/* Baud rate scaler */
3870 +#define MCF_DSPI_DCTAR7_BR(x) (((x)&0x0000000F))
3871 +/* Delay after transfer scaler */
3872 +#define MCF_DSPI_DCTAR7_DT(x) (((x)&0x0000000F)<<4)
3873 +/* After SCK delay scaler */
3874 +#define MCF_DSPI_DCTAR7_ASC(x) (((x)&0x0000000F)<<8)
3875 +/* PCS to SCK delay scaler */
3876 +#define MCF_DSPI_DCTAR7_CSSCK(x) (((x)&0x0000000F)<<12)
3877 +/* Baud rate prescaler */
3878 +#define MCF_DSPI_DCTAR7_PBR(x) (((x)&0x00000003)<<16)
3879 +/* Delay after transfer prescaler */
3880 +#define MCF_DSPI_DCTAR7_PDT(x) (((x)&0x00000003)<<18)
3881 +/* After SCK delay prescaler */
3882 +#define MCF_DSPI_DCTAR7_PASC(x) (((x)&0x00000003)<<20)
3883 +/* PCS to SCK delay prescaler */
3884 +#define MCF_DSPI_DCTAR7_PCSSCK(x) (((x)&0x00000003)<<22)
3885 +/* LSB first enable */
3886 +#define MCF_DSPI_DCTAR7_LSBFE (0x01000000)
3887 +/* Clock phase */
3888 +#define MCF_DSPI_DCTAR7_CPHA (0x02000000)
3889 +/* Clock polarity */
3890 +#define MCF_DSPI_DCTAR7_CPOL (0x04000000)
3891 +/* Frame size */
3892 +#define MCF_DSPI_DCTAR7_FMSZ(x) (((x)&0x0000000F)<<27)
3893 +/* Double baud rate */
3894 +#define MCF_DSPI_DCTAR7_DBR (0x80000000)
3895 +
3896 +/* Bit definitions and macros for DSR */
3897 +/* Receive next pointer */
3898 +#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F))
3899 +/* Receive FIFO counter */
3900 +#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4)
3901 +/* Transmit next pointer */
3902 +#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8)
3903 +/* Transmit FIFO counter */
3904 +#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12)
3905 +/* Receive FIFO drain flag */
3906 +#define MCF_DSPI_DSR_RFDF (0x00020000)
3907 +/* Receive FIFO overflow flag */
3908 +#define MCF_DSPI_DSR_RFOF (0x00080000)
3909 +/* Transmit FIFO fill flag */
3910 +#define MCF_DSPI_DSR_TFFF (0x02000000)
3911 +/* Transmit FIFO underflow flag */
3912 +#define MCF_DSPI_DSR_TFUF (0x08000000)
3913 +/* End of queue flag */
3914 +#define MCF_DSPI_DSR_EOQF (0x10000000)
3915 +/* Tx and Rx status (enabled | disabled) */
3916 +#define MCF_DSPI_DSR_TXRXS (0x40000000)
3917 +/* Transfer complete flag */
3918 +#define MCF_DSPI_DSR_TCF (0x80000000)
3919 +
3920 +/* Bit definitions and macros for DRSER */
3921 +/* Receive FIFO drain DMA or interrupt select */
3922 +#define MCF_DSPI_DRSER_RFDFS (0x00010000)
3923 +/* Receive FIFO drain request enable */
3924 +#define MCF_DSPI_DRSER_RFDFE (0x00020000)
3925 +/* Receive FIFO overflow request enable */
3926 +#define MCF_DSPI_DRSER_RFOFE (0x00080000)
3927 +/* Transmit FIFO fill DMA or interrupt select */
3928 +#define MCF_DSPI_DRSER_TFFFS (0x01000000)
3929 +/* Transmit FIFO fill request enable */
3930 +#define MCF_DSPI_DRSER_TFFFE (0x02000000)
3931 +/* Transmit FIFO underflow request enable */
3932 +#define MCF_DSPI_DRSER_TFUFE (0x08000000)
3933 +/* DSPI finished request enable */
3934 +#define MCF_DSPI_DRSER_EOQFE (0x10000000)
3935 +/* Transmission complete request enable */
3936 +#define MCF_DSPI_DRSER_TCFE (0x80000000)
3937 +
3938 +/* Bit definitions and macros for DTFR */
3939 +/* Transmit data */
3940 +#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF))
3941 +/* Peripheral chip select 0 */
3942 +#define MCF_DSPI_DTFR_PCS0 (0x00010000)
3943 +/* Peripheral chip select 1 */
3944 +#define MCF_DSPI_DTFR_PCS1 (0x00020000)
3945 +/* Peripheral chip select 2 */
3946 +#define MCF_DSPI_DTFR_PCS2 (0x00040000)
3947 +/* Peripheral chip select 3 */
3948 +#define MCF_DSPI_DTFR_PCS3 (0x00080000)
3949 +/* Peripheral chip select 4 */
3950 +#define MCF_DSPI_DTFR_PCS4 (0x00100000)
3951 +/* Peripheral chip select 5 */
3952 +#define MCF_DSPI_DTFR_PCS5 (0x00200000)
3953 +/* Peripheral chip select 6 */
3954 +#define MCF_DSPI_DTFR_PCS6 (0x00400000)
3955 +/* Peripheral chip select 7 */
3956 +#define MCF_DSPI_DTFR_PCS7 (0x00800000)
3957 +/* Clear SPI transfer counter */
3958 +#define MCF_DSPI_DTFR_CTCNT (0x04000000)
3959 +/* End of queue */
3960 +#define MCF_DSPI_DTFR_EOQ (0x08000000)
3961 +/* Clock and transfer attributes select */
3962 +#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28)
3963 +/* Continuous peripheral chip-select enable */
3964 +#define MCF_DSPI_DTFR_CONT (0x80000000)
3965 +
3966 +/* Bit definitions and macros for DRFR */
3967 +/* Receive data */
3968 +#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF))
3969 +
3970 +/* Bit definitions and macros for DTFDR group */
3971 +/* Transmit data */
3972 +#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF))
3973 +/* Peripheral chip select 0 */
3974 +#define MCF_DSPI_DTFDR_PCS0 (0x00010000)
3975 +/* Peripheral chip select 0 */
3976 +#define MCF_DSPI_DTFDR_PCS1 (0x00020000)
3977 +/* Peripheral chip select 0 */
3978 +#define MCF_DSPI_DTFDR_PCS2 (0x00040000)
3979 +/* Peripheral chip select 0 */
3980 +#define MCF_DSPI_DTFDR_PCS3 (0x00080000)
3981 +/* Peripheral chip select 0 */
3982 +#define MCF_DSPI_DTFDR_PCS4 (0x00100000)
3983 +/* Peripheral chip select 0 */
3984 +#define MCF_DSPI_DTFDR_PCS5 (0x00200000)
3985 +/* Peripheral chip select 0 */
3986 +#define MCF_DSPI_DTFDR_PCS6 (0x00400000)
3987 +/* Peripheral chip select 0 */
3988 +#define MCF_DSPI_DTFDR_PCS7 (0x00800000)
3989 +/* Clear SPI transfer counter */
3990 +#define MCF_DSPI_DTFDR_CTCNT (0x04000000)
3991 +/* End of queue */
3992 +#define MCF_DSPI_DTFDR_EOQ (0x08000000)
3993 +/* Clock and transfer attributes select */
3994 +#define MCF_DSPI_DTFDR_CTAS(x) (((x)&0x00000007)<<28)
3995 +/* Continuous peripheral chip-select enable */
3996 +#define MCF_DSPI_DTFDR_CONT (0x80000000)
3997 +
3998 +/* Bit definitions and macros for DTFDR0 */
3999 +/* Transmit data */
4000 +#define MCF_DSPI_DTFDR0_TXDATA(x) (((x)&0x0000FFFF))
4001 +/* Peripheral chip select 0 */
4002 +#define MCF_DSPI_DTFDR0_PCS0 (0x00010000)
4003 +/* Peripheral chip select 0 */
4004 +#define MCF_DSPI_DTFDR0_PCS1 (0x00020000)
4005 +/* Peripheral chip select 0 */
4006 +#define MCF_DSPI_DTFDR0_PCS2 (0x00040000)
4007 +/* Peripheral chip select 0 */
4008 +#define MCF_DSPI_DTFDR0_PCS3 (0x00080000)
4009 +/* Peripheral chip select 0 */
4010 +#define MCF_DSPI_DTFDR0_PCS4 (0x00100000)
4011 +/* Peripheral chip select 0 */
4012 +#define MCF_DSPI_DTFDR0_PCS5 (0x00200000)
4013 +/* Peripheral chip select 0 */
4014 +#define MCF_DSPI_DTFDR0_PCS6 (0x00400000)
4015 +/* Peripheral chip select 0 */
4016 +#define MCF_DSPI_DTFDR0_PCS7 (0x00800000)
4017 +/* Clear SPI transfer counter */
4018 +#define MCF_DSPI_DTFDR0_CTCNT (0x04000000)
4019 +/* End of queue */
4020 +#define MCF_DSPI_DTFDR0_EOQ (0x08000000)
4021 +/* Clock and transfer attributes select */
4022 +#define MCF_DSPI_DTFDR0_CTAS(x) (((x)&0x00000007)<<28)
4023 +/* Continuous peripheral chip-select enable */
4024 +#define MCF_DSPI_DTFDR0_CONT (0x80000000)
4025 +/* Bit definitions and macros for DTFDR1 */
4026 +/* Transmit data */
4027 +#define MCF_DSPI_DTFDR1_TXDATA(x) (((x)&0x0000FFFF))
4028 +/* Peripheral chip select 0 */
4029 +#define MCF_DSPI_DTFDR1_PCS0 (0x00010000)
4030 +/* Peripheral chip select 1 */
4031 +#define MCF_DSPI_DTFDR1_PCS1 (0x00020000)
4032 +/* Peripheral chip select 2 */
4033 +#define MCF_DSPI_DTFDR1_PCS2 (0x00040000)
4034 +/* Peripheral chip select 3 */
4035 +#define MCF_DSPI_DTFDR1_PCS3 (0x00080000)
4036 +/* Peripheral chip select 4 */
4037 +#define MCF_DSPI_DTFDR1_PCS4 (0x00100000)
4038 +/* Peripheral chip select 5 */
4039 +#define MCF_DSPI_DTFDR1_PCS5 (0x00200000)
4040 +/* Peripheral chip select 6 */
4041 +#define MCF_DSPI_DTFDR1_PCS6 (0x00400000)
4042 +/* Peripheral chip select 7 */
4043 +#define MCF_DSPI_DTFDR1_PCS7 (0x00800000)
4044 +/* Clear SPI transfer counter */
4045 +#define MCF_DSPI_DTFDR1_CTCNT (0x04000000)
4046 +/* End of queue */
4047 +#define MCF_DSPI_DTFDR1_EOQ (0x08000000)
4048 +/* Clock and transfer attributes select */
4049 +#define MCF_DSPI_DTFDR1_CTAS(x) (((x)&0x00000007)<<28)
4050 +/* Continuous peripheral chip-select enable */
4051 +#define MCF_DSPI_DTFDR1_CONT (0x80000000)
4052 +
4053 +/* Bit definitions and macros for DTFDR2 */
4054 +#define MCF_DSPI_DTFDR2_TXDATA(x) (((x)&0x0000FFFF))
4055 +/* Peripheral chip select 0 */
4056 +#define MCF_DSPI_DTFDR2_PCS0 (0x00010000)
4057 +/* Peripheral chip select 1 */
4058 +#define MCF_DSPI_DTFDR2_PCS1 (0x00020000)
4059 +/* Peripheral chip select 2 */
4060 +#define MCF_DSPI_DTFDR2_PCS2 (0x00040000)
4061 +/* Peripheral chip select 3 */
4062 +#define MCF_DSPI_DTFDR2_PCS3 (0x00080000)
4063 +/* Peripheral chip select 4 */
4064 +#define MCF_DSPI_DTFDR2_PCS4 (0x00100000)
4065 +/* Peripheral chip select 5 */
4066 +#define MCF_DSPI_DTFDR2_PCS5 (0x00200000)
4067 +/* Peripheral chip select 6 */
4068 +#define MCF_DSPI_DTFDR2_PCS6 (0x00400000)
4069 +/* Peripheral chip select 7 */
4070 +#define MCF_DSPI_DTFDR2_PCS7 (0x00800000)
4071 +/* Clear SPI transfer counter */
4072 +#define MCF_DSPI_DTFDR2_CTCNT (0x04000000)
4073 +/* End of queue */
4074 +#define MCF_DSPI_DTFDR2_EOQ (0x08000000)
4075 +/* Clock and transfer attributes select */
4076 +#define MCF_DSPI_DTFDR2_CTAS(x) (((x)&0x00000007)<<28)
4077 +/* Continuous peripheral chip-select enable */
4078 +#define MCF_DSPI_DTFDR2_CONT (0x80000000)
4079 +
4080 +/* Bit definitions and macros for DTFDR3 */
4081 +/* Transmit data */
4082 +#define MCF_DSPI_DTFDR3_TXDATA(x) (((x)&0x0000FFFF))
4083 +/* Peripheral chip select 0 */
4084 +#define MCF_DSPI_DTFDR3_PCS0 (0x00010000)
4085 +/* Peripheral chip select 1 */
4086 +#define MCF_DSPI_DTFDR3_PCS1 (0x00020000)
4087 +/* Peripheral chip select 2 */
4088 +#define MCF_DSPI_DTFDR3_PCS2 (0x00040000)
4089 +/* Peripheral chip select 3 */
4090 +#define MCF_DSPI_DTFDR3_PCS3 (0x00080000)
4091 +/* Peripheral chip select 4 */
4092 +#define MCF_DSPI_DTFDR3_PCS4 (0x00100000)
4093 +/* Peripheral chip select 5 */
4094 +#define MCF_DSPI_DTFDR3_PCS5 (0x00200000)
4095 +/* Peripheral chip select 6 */
4096 +#define MCF_DSPI_DTFDR3_PCS6 (0x00400000)
4097 +/* Peripheral chip select 7 */
4098 +#define MCF_DSPI_DTFDR3_PCS7 (0x00800000)
4099 +/* Clear SPI transfer counter */
4100 +#define MCF_DSPI_DTFDR3_CTCNT (0x04000000)
4101 +/* End of queue */
4102 +#define MCF_DSPI_DTFDR3_EOQ (0x08000000)
4103 +/* Clock and transfer attributes select */
4104 +#define MCF_DSPI_DTFDR3_CTAS(x) (((x)&0x00000007)<<28)
4105 +/* Continuous peripheral chip-select enable */
4106 +#define MCF_DSPI_DTFDR3_CONT (0x80000000)
4107 +
4108 +/* Bit definitions and macros for DRFDR group */
4109 +#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF))
4110 +
4111 +/* Bit definitions and macros for DRFDR0 */
4112 +#define MCF_DSPI_DRFDR0_RXDATA(x) (((x)&0x0000FFFF))
4113 +
4114 +/* Bit definitions and macros for DRFDR1 */
4115 +#define MCF_DSPI_DRFDR1_RXDATA(x) (((x)&0x0000FFFF))
4116 +
4117 +/* Bit definitions and macros for DRFDR2 */
4118 +#define MCF_DSPI_DRFDR2_RXDATA(x) (((x)&0x0000FFFF))
4119 +
4120 +/* Bit definitions and macros for DRFDR3 */
4121 +#define MCF_DSPI_DRFDR3_RXDATA(x) (((x)&0x0000FFFF))
4122 +
4123 +/********************************************************************/
4124 +
4125 +#endif /* __MCF5441X_DSPI_H__ */
4126 --- /dev/null
4127 +++ b/arch/m68k/include/asm/mcf5441x_dtim.h
4128 @@ -0,0 +1,95 @@
4129 +/*
4130 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
4131 + *
4132 + * This program is free software; you can redistribute it and/or modify it
4133 + * under the terms of the GNU General Public License as published by the
4134 + * Free Software Foundation; either version 2 of the License, or (at your
4135 + * option) any later version.
4136 + */
4137 +
4138 +#ifndef __MCF5441X_DTIM_H__
4139 +#define __MCF5441X_DTIM_H__
4140 +
4141 +/*********************************************************************
4142 +*
4143 +* DMA Timers (DTIM)
4144 +*
4145 +*********************************************************************/
4146 +/* Register read/write macros */
4147 +#define MCF_DTIM0_DTMR 0xFC070000 /* DMA Timer Mode Register */
4148 +#define MCF_DTIM0_DTXMR 0xFC070002 /* DMA Timer Extended Mode Register */
4149 +#define MCF_DTIM0_DTER 0xFC070003 /* DMA Timer Event Register */
4150 +#define MCF_DTIM0_DTRR 0xFC070004 /* DMA Timer Reference Register */
4151 +#define MCF_DTIM0_DTCR 0xFC070008 /* DMA Timer Capture Register */
4152 +#define MCF_DTIM0_DTCN 0xFC07000C /* DMA Timer Counter Register */
4153 +#define MCF_DTIM1_DTMR 0xFC074000 /* DMA Timer Mode Register */
4154 +#define MCF_DTIM1_DTXMR 0xFC074002 /* DMA Timer Extended Mode Register */
4155 +#define MCF_DTIM1_DTER 0xFC074003 /* DMA Timer Event Register */
4156 +#define MCF_DTIM1_DTRR 0xFC074004 /* DMA Timer Reference Register */
4157 +#define MCF_DTIM1_DTCR 0xFC074008 /* DMA Timer Capture Register */
4158 +#define MCF_DTIM1_DTCN 0xFC07400C /* DMA Timer Counter Register */
4159 +#define MCF_DTIM2_DTMR 0xFC078000 /* DMA Timer Mode Register */
4160 +#define MCF_DTIM2_DTXMR 0xFC078002 /* DMA Timer Extended Mode Register */
4161 +#define MCF_DTIM2_DTER 0xFC078003 /* DMA Timer Event Register */
4162 +#define MCF_DTIM2_DTRR 0xFC078004 /* DMA Timer Reference Register */
4163 +#define MCF_DTIM2_DTCR 0xFC078008 /* DMA Timer Capture Register */
4164 +#define MCF_DTIM2_DTCN 0xFC07800C /* DMA Timer Counter Register */
4165 +#define MCF_DTIM3_DTMR 0xFC07C000 /* DMA Timer Mode Register */
4166 +#define MCF_DTIM3_DTXMR 0xFC07C002 /* DMA Timer Extended Mode Register */
4167 +#define MCF_DTIM3_DTER 0xFC07C003 /* DMA Timer Event Register */
4168 +#define MCF_DTIM3_DTRR 0xFC07C004 /* DMA Timer Reference Register */
4169 +#define MCF_DTIM3_DTCR 0xFC07C008 /* DMA Timer Capture Register */
4170 +#define MCF_DTIM3_DTCN 0xFC07C00C /* DMA Timer Counter Register */
4171 +
4172 +/* Parameterized register read/write macros for multiple modules */
4173 +/* DMA Timer Mode Register */
4174 +#define MCF_DTIM_DTMR(x) (0xFC070000+((x)*0x4000))
4175 +/* DMA Timer Extended Mode Register */
4176 +#define MCF_DTIM_DTXMR(x) (0xFC070002+((x)*0x4000))
4177 +/* DMA Timer Event Register */
4178 +#define MCF_DTIM_DTER(x) (0xFC070003+((x)*0x4000))
4179 +/* DMA Timer Reference Register */
4180 +#define MCF_DTIM_DTRR(x) (0xFC070004+((x)*0x4000))
4181 +/* DMA Timer Capture Register */
4182 +#define MCF_DTIM_DTCR(x) (0xFC070008+((x)*0x4000))
4183 +/* DMA Timer Counter Register */
4184 +#define MCF_DTIM_DTCN(x) (0xFC07000C+((x)*0x4000))
4185 +
4186 +/* Bit definitions and macros for DTMR */
4187 +#define MCF_DTIM_DTMR_RST (0x0001) /* Reset */
4188 +#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */
4189 +#define MCF_DTIM_DTMR_FRR (0x0008) /* Free run/restart */
4190 +/* Output reference request/interrupt enable */
4191 +#define MCF_DTIM_DTMR_ORRI (0x0010)
4192 +#define MCF_DTIM_DTMR_OM (0x0020) /* Output Mode */
4193 +#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */
4194 +#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */
4195 +#define MCF_DTIM_DTMR_RST_EN (0x0001)
4196 +#define MCF_DTIM_DTMR_RST_RST (0x0000)
4197 +#define MCF_DTIM_DTMR_CE_ANY (0x00C0)
4198 +#define MCF_DTIM_DTMR_CE_FALL (0x0080)
4199 +#define MCF_DTIM_DTMR_CE_RISE (0x0040)
4200 +#define MCF_DTIM_DTMR_CE_NONE (0x0000)
4201 +#define MCF_DTIM_DTMR_CLK_DTIN (0x0006)
4202 +#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004)
4203 +#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002)
4204 +#define MCF_DTIM_DTMR_CLK_STOP (0x0000)
4205 +
4206 +/* Bit definitions and macros for DTXMR */
4207 +#define MCF_DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */
4208 +#define MCF_DTIM_DTXMR_DMAEN (0x80) /* DMA request */
4209 +#define MCF_DTIM_DTXMR_1588EN (0x20) /* Enable 1588 mode*/
4210 +
4211 +/* Bit definitions and macros for DTER */
4212 +#define MCF_DTIM_DTER_CAP (0x01) /* Capture event */
4213 +#define MCF_DTIM_DTER_REF (0x02) /* Output reference event */
4214 +
4215 +/* Interrupts used for system timers */
4216 +#define MCFSIM_ICR_TIMER0 (0xFC048040+32)
4217 +#define MCFSIM_ICR_TIMER1 (0xFC048040+33)
4218 +#define MCFSIM_ICR_TIMER2 (0xFC048040+34)
4219 +#define MCFSIM_ICR_TIMER3 (0xFC048040+35)
4220 +
4221 +/********************************************************************/
4222 +
4223 +#endif /* __MCF5441X_DTIM_H__ */
4224 --- /dev/null
4225 +++ b/arch/m68k/include/asm/mcf5441x_edma.h
4226 @@ -0,0 +1,303 @@
4227 +/* mcf5441x_edma.h
4228 + *
4229 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
4230 + * Lanttor.Guo@freescale.com
4231 + *
4232 + * This program is free software; you can redistribute it and/or modify it
4233 + * under the terms of the GNU General Public License as published by the
4234 + * Free Software Foundation; either version 2 of the License, or (at your
4235 + * option) any later version.
4236 + */
4237 +#ifndef __MCF5441X_EDMA_H__
4238 +#define __MCF5441X_EDMA_H__
4239 +
4240 +/*
4241 + * Enhanced DMA (EDMA)
4242 + */
4243 +
4244 +/* Channels */
4245 +#define MCF_EDMA_CHAN_DREQ0 0 /* External DMA request 0 */
4246 +#define MCF_EDMA_CHAN_DREQ1 1 /* External DMA request 1 */
4247 +#define MCF_EDMA_CHAN_UART0_RX 2 /* UART0 Receive */
4248 +#define MCF_EDMA_CHAN_UART0_TX 3 /* UART0 Transmit */
4249 +#define MCF_EDMA_CHAN_UART1_RX 4 /* UART1 Receive */
4250 +#define MCF_EDMA_CHAN_UART1_TX 5 /* UART1 Transmit */
4251 +#define MCF_EDMA_CHAN_UART2_RX 6 /* UART2 Receive */
4252 +#define MCF_EDMA_CHAN_UART2_TX 7 /* UART2 Transmit */
4253 +#define MCF_EDMA_CHAN_TIMER0 8 /* Timer 0 / SSI0 Rx */
4254 +#define MCF_EDMA_CHAN_TIMER1 9 /* Timer 1 / SSI1 Rx */
4255 +#define MCF_EDMA_CHAN_TIMER2 10 /* Timer 2 / SSI0 Tx */
4256 +#define MCF_EDMA_CHAN_TIMER3 11 /* Timer 3 / SSI1 Tx */
4257 +#define MCF_EDMA_CHAN_DSPI0_RX 12 /* DSPI0 Receive */
4258 +#define MCF_EDMA_CHAN_DSPI0_TX 13 /* DSPI0 Transmit */
4259 +#define MCF_EDMA_CHAN_DSPI1_RX 14 /* DSPI1 Receive */
4260 +#define MCF_EDMA_CHAN_DSPI1_TX 15 /* DSPI1 Transmit */
4261 +#define MCF_EDMA_CHAN_UART3_RX 16 /* UART3 Receive */
4262 +#define MCF_EDMA_CHAN_UART3_TX 17 /* UART3 Transmit */
4263 +#define MCF_EDMA_CHAN_UART4_RX 18 /* UART4 Receive */
4264 +#define MCF_EDMA_CHAN_UART4_TX 19 /* UART4 Transmit */
4265 +#define MCF_EDMA_CHAN_UART5_RX 20 /* UART5 Receive */
4266 +#define MCF_EDMA_CHAN_UART5_TX 21 /* UART5 Transmit */
4267 +#define MCF_EDMA_CHAN_UART6_RX 22 /* UART6 Receive */
4268 +#define MCF_EDMA_CHAN_UART6_TX 23 /* UART6 Transmit */
4269 +#define MCF_EDMA_CHAN_I2C0 24 /* I2C0 */
4270 +#define MCF_EDMA_CHAN_I2C1 25 /* I2C1 */
4271 +#define MCF_EDMA_CHAN_I2C2 26 /* I2C2 */
4272 +#define MCF_EDMA_CHAN_I2C3 27 /* I2C3 */
4273 +#define MCF_EDMA_CHAN_DSPI2_RX 28 /* DSPI2 Receive */
4274 +#define MCF_EDMA_CHAN_DSPI2_TX 29 /* DSPI2 Transmit */
4275 +#define MCF_EDMA_CHAN_N0 30 /* Available for software */
4276 +#define MCF_EDMA_CHAN_N1 31 /* Available for software */
4277 +#define MCF_EDMA_CHAN_UART7_RX 32 /* UART7 Receive */
4278 +#define MCF_EDMA_CHAN_UART7_TX 33 /* UART7 Transmit */
4279 +#define MCF_EDMA_CHAN_UART8_RX 34 /* UART8 Receive */
4280 +#define MCF_EDMA_CHAN_UART8_TX 35 /* UART8 Transmit */
4281 +#define MCF_EDMA_CHAN_UART9_RX 36 /* UART9 Receive */
4282 +#define MCF_EDMA_CHAN_UART9_TX 37 /* UART9 Transmit */
4283 +#define MCF_EDMA_CHAN_OW 38 /* 1-Wire */
4284 +#define MCF_EDMA_CHAN_RESERVED 39 /* Reserved */
4285 +#define MCF_EDMA_CHAN_I2C4 40 /* I2C4 */
4286 +#define MCF_EDMA_CHAN_I2C5 41 /* I2C5 */
4287 +#define MCF_EDMA_CHAN_N2 42 /* Available for software */
4288 +#define MCF_EDMA_CHAN_N3 43 /* Available for software */
4289 +#define MCF_EDMA_CHAN_DSPI3_RX 44 /* DSPI3 Receive */
4290 +#define MCF_EDMA_CHAN_DSPI3_TX 45 /* DSPI3 Transmit */
4291 +#define MCF_EDMA_CHAN_SSI0_RX0 48 /* SSI0 Receive 0 */
4292 +#define MCF_EDMA_CHAN_SSI0_RX1 49 /* SSI0 Receive 1 */
4293 +#define MCF_EDMA_CHAN_SSI0_TX0 50 /* SSI0 Transmit 0 */
4294 +#define MCF_EDMA_CHAN_SSI0_TX1 51 /* SSI0 Transmit 1 */
4295 +#define MCF_EDMA_CHAN_SSI1_RX0 52 /* SSI1 Receive 0 */
4296 +#define MCF_EDMA_CHAN_SSI1_RX1 53 /* SSI1 Receive 1 */
4297 +#define MCF_EDMA_CHAN_SSI1_TX0 54 /* SSI1 Transmit 0 */
4298 +#define MCF_EDMA_CHAN_SSI1_TX1 55 /* SSI1 Transmit 1 */
4299 +#define MCF_EDMA_CHAN_PWM_CAP 56 /* PWM Capture */
4300 +#define MCF_EDMA_CHAN_PWM_VAL 57 /* PWM Value */
4301 +#define MCF_EDMA_CHAN_RESERVED2 58 /* Reserved */
4302 +#define MCF_EDMA_CHAN_ESDHC 59 /* eSDHC */
4303 +#define MCF_EDMA_CHAN_ADC0 60 /* ADC 0 */
4304 +#define MCF_EDMA_CHAN_ADC1 61 /* ADC 1 */
4305 +#define MCF_EDMA_CHAN_DAC0 62 /* DAC 0 */
4306 +#define MCF_EDMA_CHAN_DAC1 63 /* DAC 1 */
4307 +
4308 +/* Register read/write macros */
4309 +#define MCF_EDMA_CR MCF_REG32(0xFC044000)
4310 +#define MCF_EDMA_ES MCF_REG32(0xFC044004)
4311 +#define MCF_EDMA_ERQH MCF_REG32(0xFC044008)
4312 +#define MCF_EDMA_ERQL MCF_REG32(0xFC04400C)
4313 +#define MCF_EDMA_EEIH MCF_REG32(0xFC044010)
4314 +#define MCF_EDMA_EEIL MCF_REG32(0xFC044014)
4315 +#define MCF_EDMA_SERQ MCF_REG08(0xFC044018)
4316 +#define MCF_EDMA_CERQ MCF_REG08(0xFC044019)
4317 +#define MCF_EDMA_SEEI MCF_REG08(0xFC04401A)
4318 +#define MCF_EDMA_CEEI MCF_REG08(0xFC04401B)
4319 +#define MCF_EDMA_CINT MCF_REG08(0xFC04401C)
4320 +#define MCF_EDMA_CERR MCF_REG08(0xFC04401D)
4321 +#define MCF_EDMA_SSRT MCF_REG08(0xFC04401E)
4322 +#define MCF_EDMA_CDNE MCF_REG08(0xFC04401F)
4323 +#define MCF_EDMA_INTH MCF_REG32(0xFC044020)
4324 +#define MCF_EDMA_INTL MCF_REG32(0xFC044024)
4325 +#define MCF_EDMA_ERRH MCF_REG32(0xFC044028)
4326 +#define MCF_EDMA_ERRL MCF_REG32(0xFC04402C)
4327 +#define MCF_EDMA_RSH MCF_REG32(0xFC044030)
4328 +#define MCF_EDMA_RSL MCF_REG32(0xFC044034)
4329 +
4330 +/* Parameterized register read/write macros for multiple registers */
4331 +#define MCF_EDMA_DCHPRI(x) MCF_REG08(0xFC044100+((x)*0x001))
4332 +#define MCF_EDMA_TCD_SADDR(x) MCF_REG32(0xFC045000+((x)*0x020))
4333 +#define MCF_EDMA_TCD_ATTR(x) MCF_REG16(0xFC045004+((x)*0x020))
4334 +#define MCF_EDMA_TCD_SOFF(x) MCF_REG16(0xFC045006+((x)*0x020))
4335 +#define MCF_EDMA_TCD_NBYTES(x) MCF_REG32(0xFC045008+((x)*0x020))
4336 +#define MCF_EDMA_TCD_SLAST(x) MCF_REG32(0xFC04500C+((x)*0x020))
4337 +#define MCF_EDMA_TCD_DADDR(x) MCF_REG32(0xFC045010+((x)*0x020))
4338 +#define MCF_EDMA_TCD_CITER_ELINK(x) MCF_REG16(0xFC045014+((x)*0x020))
4339 +#define MCF_EDMA_TCD_CITER(x) MCF_REG16(0xFC045014+((x)*0x020))
4340 +#define MCF_EDMA_TCD_DOFF(x) MCF_REG16(0xFC045016+((x)*0x020))
4341 +#define MCF_EDMA_TCD_DLAST_SGA(x) MCF_REG32(0xFC045018+((x)*0x020))
4342 +#define MCF_EDMA_TCD_BITER_ELINK(x) MCF_REG16(0xFC04501C+((x)*0x020))
4343 +#define MCF_EDMA_TCD_BITER(x) MCF_REG16(0xFC04501C+((x)*0x020))
4344 +#define MCF_EDMA_TCD_CSR(x) MCF_REG16((0xFC04501e)+((x)*0x020))
4345 +
4346 +/* Bit definitions and macros for CR */
4347 +#define MCF_EDMA_CR_EDBG (0x00000002)
4348 +#define MCF_EDMA_CR_ERCA (0x00000004)
4349 +#define MCF_EDMA_CR_ERGA (0x00000008)
4350 +#define MCF_EDMA_CR_HOE (0x00000010)
4351 +#define MCF_EDMA_CR_HALT (0x00000020)
4352 +#define MCF_EDMA_CR_CLM (0x00000040)
4353 +#define MCF_EDMA_CR_EMLM (0x00000080)
4354 +#define MCF_EDMA_CR_GRP0PRI(x) (((x)&0x03)<<8)
4355 +#define MCF_EDMA_CR_GRP1PRI(x) (((x)&0x03)<<10)
4356 +#define MCF_EDMA_CR_GRP2PRI(x) (((x)&0x03)<<12)
4357 +#define MCF_EDMA_CR_GRP3PRI(x) (((x)&0x03)<<14)
4358 +#define MCF_EDMA_CR_ECX (0x00010000)
4359 +#define MCF_EDMA_CR_CX (0x00020000)
4360 +
4361 +/* Bit definitions and macros for ES */
4362 +#define MCF_EDMA_ES_DBE (0x00000001)
4363 +#define MCF_EDMA_ES_SBE (0x00000002)
4364 +#define MCF_EDMA_ES_SGE (0x00000004)
4365 +#define MCF_EDMA_ES_NCE (0x00000008)
4366 +#define MCF_EDMA_ES_DOE (0x00000010)
4367 +#define MCF_EDMA_ES_DAE (0x00000020)
4368 +#define MCF_EDMA_ES_SOE (0x00000040)
4369 +#define MCF_EDMA_ES_SAE (0x00000080)
4370 +#define MCF_EDMA_ES_ERRCHN(x) (((x)&0x0000003F)<<8)
4371 +#define MCF_EDMA_ES_CPE (0x00004000)
4372 +#define MCF_EDMA_ES_GPE (0x00008000)
4373 +#define MCF_EDMA_ES_ECX (0x00010000)
4374 +#define MCF_EDMA_ES_VLD (0x80000000)
4375 +
4376 +/* Bit definitions and macros for ERQ: 0~63 bits */
4377 +#define MCF_EDMA_ERQ_ERQH(x) (0x01<<x) /*32~63*/
4378 +#define MCF_EDMA_ERQ_ERQL(x) (0x01<<x) /*0~31*/
4379 +
4380 +/* Bit definitions and macros for EEI: 0~63 bits */
4381 +#define MCF_EDMA_EEI_EEIH(x) (0x01<<x) /*32~63*/
4382 +#define MCF_EDMA_EEI_EEIL(x) (0x01<<x) /*0~31*/
4383 +
4384 +/* Bit definitions and macros for SERQ */
4385 +#define MCF_EDMA_SERQ_SERQ(x) (((x)&0x3F))
4386 +#define MCF_EDMA_SERQ_SAER (0x40)
4387 +#define MCF_EDMA_SERQ_NOP (0x80)
4388 +
4389 +/* Bit definitions and macros for CERQ */
4390 +#define MCF_EDMA_CERQ_CERQ(x) (((x)&0x3F))
4391 +#define MCF_EDMA_CERQ_CAER (0x40)
4392 +#define MCF_EDMA_CERQ_NOP (0x80)
4393 +
4394 +/* Bit definitions and macros for SEEI */
4395 +#define MCF_EDMA_SEEI_SEEI(x) (((x)&0x3F))
4396 +#define MCF_EDMA_SEEI_SAEE (0x40)
4397 +#define MCF_EDMA_SEEI_NOP (0x80)
4398 +
4399 +/* Bit definitions and macros for CEEI */
4400 +#define MCF_EDMA_CEEI_CEEI(x) (((x)&0x3F))
4401 +#define MCF_EDMA_CEEI_CAEE (0x40)
4402 +#define MCF_EDMA_CEEI_NOP (0x80)
4403 +
4404 +/* Bit definitions and macros for CINT */
4405 +#define MCF_EDMA_CINT_CINT(x) (((x)&0x3F))
4406 +#define MCF_EDMA_CINT_CAIR (0x40)
4407 +#define MCF_EDMA_CINT_NOP (0x80)
4408 +
4409 +/* Bit definitions and macros for CERR */
4410 +#define MCF_EDMA_CERR_CERR(x) (((x)&0x3F))
4411 +#define MCF_EDMA_CERR_CAER (0x40)
4412 +#define MCF_EDMA_CERR_NOP (0x80)
4413 +
4414 +/* Bit definitions and macros for SSRT */
4415 +#define MCF_EDMA_SSRT_SSRT(x) (((x)&0x3F))
4416 +#define MCF_EDMA_SSRT_SAST (0x40)
4417 +#define MCF_EDMA_SSRT_NOP (0x80)
4418 +
4419 +/* Bit definitions and macros for CDNE */
4420 +#define MCF_EDMA_CDNE_CDNE(x) (((x)&0x3F))
4421 +#define MCF_EDMA_CDNE_CADN (0x40)
4422 +#define MCF_EDMA_CDNE_NOP (0x80)
4423 +
4424 +/* Bit definitions and macros for INTR: 0~63 bits */
4425 +#define MCF_EDMA_INTR_INTH(x) (0x01<<x) /*32~63*/
4426 +#define MCF_EDMA_INTR_INTL(x) (0x01<<x) /*0~31*/
4427 +
4428 +/* Bit definitions and macros for ERR: 0~63 bits */
4429 +#define MCF_EDMA_ERR_ERRH(x) (0x01<<x) /*32~63*/
4430 +#define MCF_EDMA_ERR_ERRL(x) (0x01<<x) /*0~31*/
4431 +
4432 +/* Bit defineitions and macros for HRSH/HRSL */
4433 +#define MCF_EDMA_HRS_HRSH(x) (0x01<<x) /*32~63*/
4434 +#define MCF_EDMA_HRS_HRSL(x) (0x01<<x) /*0~31*/
4435 +
4436 +/* Bit definitions and macros for DCHPRI group */
4437 +#define MCF_EDMA_DCHPRI_CHPRI(x) (((x)&0x0F))
4438 +#define MCF_EDMA_DCHPRI_GRPPRI(x) (((x)&0x03) << 4)
4439 +#define MCF_EDMA_DCHPRI_DPA (0x40)
4440 +#define MCF_EDMA_DCHPRI_ECP (0x80)
4441 +
4442 +/* Bit definitions and macros for TCD_SADDR group */
4443 +#define MCF_EDMA_TCD_SADDR_SADDR(x) (x)
4444 +
4445 +/* Bit definitions and macros for TCD_ATTR group */
4446 +#define MCF_EDMA_TCD_ATTR_DSIZE(x) (((x)&0x0007))
4447 +#define MCF_EDMA_TCD_ATTR_DMOD(x) (((x)&0x001F)<<3)
4448 +#define MCF_EDMA_TCD_ATTR_SSIZE(x) (((x)&0x0007)<<8)
4449 +#define MCF_EDMA_TCD_ATTR_SMOD(x) (((x)&0x001F)<<11)
4450 +#define MCF_EDMA_TCD_ATTR_SSIZE_8BIT (0x0000)
4451 +#define MCF_EDMA_TCD_ATTR_SSIZE_16BIT (0x0100)
4452 +#define MCF_EDMA_TCD_ATTR_SSIZE_32BIT (0x0200)
4453 +#define MCF_EDMA_TCD_ATTR_SSIZE_16BYTE (0x0400)
4454 +#define MCF_EDMA_TCD_ATTR_DSIZE_8BIT (0x0000)
4455 +#define MCF_EDMA_TCD_ATTR_DSIZE_16BIT (0x0001)
4456 +#define MCF_EDMA_TCD_ATTR_DSIZE_32BIT (0x0002)
4457 +#define MCF_EDMA_TCD_ATTR_DSIZE_16BYTE (0x0004)
4458 +
4459 +/* Bit definitions and macros for TCD_SOFF group */
4460 +#define MCF_EDMA_TCD_SOFF_SOFF(x) (x)
4461 +
4462 +/* Bit definitions and macros for TCD_NBYTES group */
4463 +#define MCF_EDMA_TCD_NBYTES_NBYTES(x) (x)
4464 +#define MCF_EDMA_TCD_NBYTES_SMLOE (0x80000000)
4465 +#define MCF_EDMA_TCD_NBYTES_DMLOE (0x40000000)
4466 +#define MCF_EDMA_TCD_NBYTES_MLOFF(x) (((x)&0xFFFFF)<<20)
4467 +#define MCF_EDMA_TCD_NBYTES_9BITS ((x)&0x1FF)
4468 +
4469 +/* Bit definitions and macros for TCD_SLAST group */
4470 +#define MCF_EDMA_TCD_SLAST_SLAST(x) (x)
4471 +
4472 +/* Bit definitions and macros for TCD_DADDR group */
4473 +#define MCF_EDMA_TCD_DADDR_DADDR(x) (x)
4474 +
4475 +/* Bit definitions and macros for TCD_CITER_ELINK group */
4476 +#define MCF_EDMA_TCD_CITER_ELINK_CITER(x) (((x)&0x01FF))
4477 +#define MCF_EDMA_TCD_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
4478 +#define MCF_EDMA_TCD_CITER_ELINK_E_LINK (0x8000)
4479 +
4480 +/* Bit definitions and macros for TCD_CITER group */
4481 +#define MCF_EDMA_TCD_CITER_CITER(x) (((x)&0x7FFF))
4482 +#define MCF_EDMA_TCD_CITER_E_LINK (0x8000)
4483 +
4484 +/* Bit definitions and macros for TCD_DOFF group */
4485 +#define MCF_EDMA_TCD_DOFF_DOFF(x) (x)
4486 +
4487 +/* Bit definitions and macros for TCD_DLAST_SGA group */
4488 +#define MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (x)
4489 +
4490 +/* Bit definitions and macros for TCD_BITER_ELINK group */
4491 +#define MCF_EDMA_TCD_BITER_ELINK_BITER(x) (((x)&0x01FF))
4492 +#define MCF_EDMA_TCD_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
4493 +#define MCF_EDMA_TCD_BITER_ELINK_E_LINK (0x8000)
4494 +
4495 +/* Bit definitions and macros for TCD_BITER group */
4496 +#define MCF_EDMA_TCD_BITER_BITER(x) (((x)&0x7FFF))
4497 +#define MCF_EDMA_TCD_BITER_E_LINK (0x8000)
4498 +
4499 +/* Bit definitions and macros for TCD_CSR group */
4500 +#define MCF_EDMA_TCD_CSR_START (0x0001)
4501 +#define MCF_EDMA_TCD_CSR_INT_MAJOR (0x0002)
4502 +#define MCF_EDMA_TCD_CSR_INT_HALF (0x0004)
4503 +#define MCF_EDMA_TCD_CSR_D_REQ (0x0008)
4504 +#define MCF_EDMA_TCD_CSR_E_SG (0x0010)
4505 +#define MCF_EDMA_TCD_CSR_E_LINK (0x0020)
4506 +#define MCF_EDMA_TCD_CSR_ACTIVE (0x0040)
4507 +#define MCF_EDMA_TCD_CSR_DONE (0x0080)
4508 +#define MCF_EDMA_TCD_CSR_LINKCH(x) (((x)&0x003F)<<8)
4509 +#define MCF_EDMA_TCD_CSR_BWC(x) (((x)&0x0003)<<14)
4510 +#define MCF_EDMA_TCD_CSR_BWC_NO_STALL (0x0000)
4511 +#define MCF_EDMA_TCD_CSR_BWC_4CYC_STALL (0x8000)
4512 +#define MCF_EDMA_TCD_CSR_BWC_8CYC_STALL (0xC000)
4513 +
4514 +/* Bit definitions and macros for TCD0_CSR */
4515 +#define MCF_EDMA_TCD0_CSR_START (0x0001)
4516 +#define MCF_EDMA_TCD0_CSR_INT_MAJOR (0x0002)
4517 +#define MCF_EDMA_TCD0_CSR_INT_HALF (0x0004)
4518 +#define MCF_EDMA_TCD0_CSR_D_REQ (0x0008)
4519 +#define MCF_EDMA_TCD0_CSR_E_SG (0x0010)
4520 +#define MCF_EDMA_TCD0_CSR_E_LINK (0x0020)
4521 +#define MCF_EDMA_TCD0_CSR_ACTIVE (0x0040)
4522 +#define MCF_EDMA_TCD0_CSR_DONE (0x0080)
4523 +#define MCF_EDMA_TCD0_CSR_LINKCH(x) (((x)&0x003F)<<8)
4524 +#define MCF_EDMA_TCD0_CSR_BWC(x) (((x)&0x0003)<<14)
4525 +#define MCF_EDMA_TCD0_CSR_BWC_NO_STALL (0x0000)
4526 +#define MCF_EDMA_TCD0_CSR_BWC_4CYC_STALL (0x8000)
4527 +#define MCF_EDMA_TCD0_CSR_BWC_8CYC_STALL (0xC000)
4528 +
4529 +#endif /* __MCF5441X_EDMA_H__ */
4530 --- /dev/null
4531 +++ b/arch/m68k/include/asm/mcf5441x_eport.h
4532 @@ -0,0 +1,94 @@
4533 +/*
4534 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
4535 + *
4536 + * This program is free software; you can redistribute it and/or modify it
4537 + * under the terms of the GNU General Public License as published by the
4538 + * Free Software Foundation; either version 2 of the License, or (at your
4539 + * option) any later version.
4540 + */
4541 +
4542 +#ifndef __MCF5441X_EPORT_H__
4543 +#define __MCF5441X_EPORT_H__
4544 +
4545 +/*********************************************************************
4546 +*
4547 +* Edge Port Module (EPORT)
4548 +*
4549 +*********************************************************************/
4550 +
4551 +/* Register read/write macros */
4552 +#define MCF_EPORT_EPPAR MCF_REG16(0xFC090000)
4553 +#define MCF_EPORT_EPDDR MCF_REG08(0xFC094002)
4554 +#define MCF_EPORT_EPIER MCF_REG08(0xFC090003)
4555 +#define MCF_EPORT_EPDR MCF_REG08(0xFC090004)
4556 +#define MCF_EPORT_EPPDR MCF_REG08(0xFC090005)
4557 +#define MCF_EPORT_EPFR MCF_REG08(0xFC090006)
4558 +
4559 +/* Bit definitions and macros for EPPAR */
4560 +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
4561 +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
4562 +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
4563 +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
4564 +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
4565 +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
4566 +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
4567 +#define MCF_EPORT_EPPAR_LEVEL (0)
4568 +#define MCF_EPORT_EPPAR_RISING (1)
4569 +#define MCF_EPORT_EPPAR_FALLING (2)
4570 +#define MCF_EPORT_EPPAR_BOTH (3)
4571 +#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000)
4572 +#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
4573 +#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
4574 +#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
4575 +#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000)
4576 +#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
4577 +#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
4578 +#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
4579 +#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000)
4580 +#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400)
4581 +#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800)
4582 +#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00)
4583 +#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000)
4584 +#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100)
4585 +#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200)
4586 +#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300)
4587 +#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000)
4588 +#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040)
4589 +#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080)
4590 +#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0)
4591 +#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000)
4592 +#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010)
4593 +#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020)
4594 +#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030)
4595 +#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000)
4596 +#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004)
4597 +#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008)
4598 +#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C)
4599 +#define MCF_EPORT_EPPAR_EPPA0_LEVEL (0x0000)
4600 +#define MCF_EPORT_EPPAR_EPPA0_RISING (0x0001)
4601 +#define MCF_EPORT_EPPAR_EPPA0_FALLING (0x0002)
4602 +#define MCF_EPORT_EPPAR_EPPA0_BOTH (0x0003)
4603 +
4604 +/* Bit definitions and macros for EPIER */
4605 +#define MCF_EPORT_EPIER_EPIE0 (0x01)
4606 +#define MCF_EPORT_EPIER_EPIE1 (0x02)
4607 +#define MCF_EPORT_EPIER_EPIE2 (0x04)
4608 +#define MCF_EPORT_EPIER_EPIE3 (0x08)
4609 +#define MCF_EPORT_EPIER_EPIE4 (0x10)
4610 +#define MCF_EPORT_EPIER_EPIE5 (0x20)
4611 +#define MCF_EPORT_EPIER_EPIE6 (0x40)
4612 +#define MCF_EPORT_EPIER_EPIE7 (0x80)
4613 +
4614 +/* Bit definitions and macros for EPFR */
4615 +#define MCF_EPORT_EPFR_EPF0 (0x01)
4616 +#define MCF_EPORT_EPFR_EPF1 (0x02)
4617 +#define MCF_EPORT_EPFR_EPF2 (0x04)
4618 +#define MCF_EPORT_EPFR_EPF3 (0x08)
4619 +#define MCF_EPORT_EPFR_EPF4 (0x10)
4620 +#define MCF_EPORT_EPFR_EPF5 (0x20)
4621 +#define MCF_EPORT_EPFR_EPF6 (0x40)
4622 +#define MCF_EPORT_EPFR_EPF7 (0x80)
4623 +
4624 +/********************************************************************/
4625 +
4626 +#endif /* __MCF5441X_EPORT_H__ */
4627 --- /dev/null
4628 +++ b/arch/m68k/include/asm/mcf5441x_fbcs.h
4629 @@ -0,0 +1,204 @@
4630 +/*
4631 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
4632 + *
4633 + * This program is free software; you can redistribute it and/or modify it
4634 + * under the terms of the GNU General Public License as published by the
4635 + * Free Software Foundation; either version 2 of the License, or (at your
4636 + * option) any later version.
4637 + */
4638 +
4639 +#ifndef __MCF5441X_FBCS_H__
4640 +#define __MCF5441X_FBCS_H__
4641 +
4642 +/*********************************************************************
4643 +*
4644 +* FlexBus Chip Selects (FBCS)
4645 +*
4646 +*********************************************************************/
4647 +
4648 +/* Register read/write macros */
4649 +#define MCF_FBCS_CSAR0 MCF_REG32(0xFC008000) /* Chip-select Addr Register */
4650 +#define MCF_FBCS_CSMR0 MCF_REG32(0xFC008004) /* Chip-select Mask Register */
4651 +#define MCF_FBCS_CSCR0 MCF_REG32(0xFC008008) /* Chip-select Cntl Register */
4652 +#define MCF_FBCS_CSAR1 MCF_REG32(0xFC00800C) /* Chip-select Addr Register */
4653 +#define MCF_FBCS_CSMR1 MCF_REG32(0xFC008010) /* Chip-select Mask Register */
4654 +#define MCF_FBCS_CSCR1 MCF_REG32(0xFC008014) /* Chip-select Cntl Register */
4655 +#define MCF_FBCS_CSAR2 MCF_REG32(0xFC008018) /* Chip-select Addr Register */
4656 +#define MCF_FBCS_CSMR2 MCF_REG32(0xFC00801C) /* Chip-select Mask Register */
4657 +#define MCF_FBCS_CSCR2 MCF_REG32(0xFC008020) /* Chip-select Cntl Register */
4658 +#define MCF_FBCS_CSAR3 MCF_REG32(0xFC008024) /* Chip-select Addr Register */
4659 +#define MCF_FBCS_CSMR3 MCF_REG32(0xFC008028) /* Chip-select Mask Register */
4660 +#define MCF_FBCS_CSCR3 MCF_REG32(0xFC00802C) /* Chip-select Cntl Register */
4661 +
4662 +/* Parameterized register read/write macros for multiple registers */
4663 +/* Chip-select Addr Register */
4664 +#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C))
4665 +/* Chip-select Mask Register */
4666 +#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C))
4667 +/* Chip-select Cntl Register */
4668 +#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C))
4669 +
4670 +/* Bit definitions and macros for CSAR group */
4671 +#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
4672 +
4673 +/* Bit definitions and macros for CSAR0 */
4674 +#define MCF_FBCS_CSAR0_BA(x) ((x)&0xFFFF0000)
4675 +
4676 +/* Bit definitions and macros for CSMR group */
4677 +#define MCF_FBCS_CSMR_V (0x00000001) /* Valid bit */
4678 +#define MCF_FBCS_CSMR_WP (0x00000100) /* Write protect */
4679 +#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */
4680 +#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
4681 +#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
4682 +#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
4683 +#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
4684 +#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
4685 +#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000)
4686 +#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000)
4687 +#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000)
4688 +#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000)
4689 +#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000)
4690 +#define MCF_FBCS_CSMR_BAM_8M (0x007F0000)
4691 +#define MCF_FBCS_CSMR_BAM_4M (0x003F0000)
4692 +#define MCF_FBCS_CSMR_BAM_2M (0x001F0000)
4693 +#define MCF_FBCS_CSMR_BAM_1M (0x000F0000)
4694 +#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000)
4695 +#define MCF_FBCS_CSMR_BAM_512K (0x00070000)
4696 +#define MCF_FBCS_CSMR_BAM_256K (0x00030000)
4697 +#define MCF_FBCS_CSMR_BAM_128K (0x00010000)
4698 +#define MCF_FBCS_CSMR_BAM_64K (0x00000000)
4699 +
4700 +/* Bit definitions and macros for CSMR0 */
4701 +#define MCF_FBCS_CSMR0_V (0x00000001) /* Valid bit */
4702 +#define MCF_FBCS_CSMR0_WP (0x00000100) /* Write protect */
4703 +#define MCF_FBCS_CSMR0_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */
4704 +#define MCF_FBCS_CSMR0_BAM_4G (0xFFFF0000)
4705 +#define MCF_FBCS_CSMR0_BAM_2G (0x7FFF0000)
4706 +#define MCF_FBCS_CSMR0_BAM_1G (0x3FFF0000)
4707 +#define MCF_FBCS_CSMR0_BAM_1024M (0x3FFF0000)
4708 +#define MCF_FBCS_CSMR0_BAM_512M (0x1FFF0000)
4709 +#define MCF_FBCS_CSMR0_BAM_256M (0x0FFF0000)
4710 +#define MCF_FBCS_CSMR0_BAM_128M (0x07FF0000)
4711 +#define MCF_FBCS_CSMR0_BAM_64M (0x03FF0000)
4712 +#define MCF_FBCS_CSMR0_BAM_32M (0x01FF0000)
4713 +#define MCF_FBCS_CSMR0_BAM_16M (0x00FF0000)
4714 +#define MCF_FBCS_CSMR0_BAM_8M (0x007F0000)
4715 +#define MCF_FBCS_CSMR0_BAM_4M (0x003F0000)
4716 +#define MCF_FBCS_CSMR0_BAM_2M (0x001F0000)
4717 +#define MCF_FBCS_CSMR0_BAM_1M (0x000F0000)
4718 +#define MCF_FBCS_CSMR0_BAM_1024K (0x000F0000)
4719 +#define MCF_FBCS_CSMR0_BAM_512K (0x00070000)
4720 +#define MCF_FBCS_CSMR0_BAM_256K (0x00030000)
4721 +#define MCF_FBCS_CSMR0_BAM_128K (0x00010000)
4722 +#define MCF_FBCS_CSMR0_BAM_64K (0x00000000)
4723 +
4724 +/* Bit definitions and macros for CSCR group */
4725 +#define MCF_FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */
4726 +#define MCF_FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */
4727 +#define MCF_FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */
4728 +#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */
4729 +#define MCF_FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */
4730 +#define MCF_FBCS_CSCR_BLS (0x00000200) /* Byte-lane shift */
4731 +#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
4732 +/* Write address hold or deselect */
4733 +#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16)
4734 +/* Read address hold or deselect */
4735 +#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18)
4736 +#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
4737 +/* Secondary wait state enable */
4738 +#define MCF_FBCS_CSCR_SWSEN (0x00800000)
4739 +/* Secondary wait states */
4740 +#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26)
4741 +#define MCF_FBCS_CSCR_PS_8 (0x00000040)
4742 +#define MCF_FBCS_CSCR_PS_16 (0x00000080)
4743 +#define MCF_FBCS_CSCR_PS_32 (0x00000000)
4744 +
4745 +/* Bit definitions and macros for CSCR0 */
4746 +#define MCF_FBCS_CSCR0_BSTW (0x00000008) /* Burst-write enable */
4747 +#define MCF_FBCS_CSCR0_BSTR (0x00000010) /* Burst-read enable */
4748 +#define MCF_FBCS_CSCR0_BEM (0x00000020) /* Byte-enable mode */
4749 +#define MCF_FBCS_CSCR0_PS(x) (((x)&0x00000003)<<6) /* Port size */
4750 +#define MCF_FBCS_CSCR0_AA (0x00000100) /* Auto-acknowledge */
4751 +#define MCF_FBCS_CSCR0_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
4752 +/* Write address hold or deselect */
4753 +#define MCF_FBCS_CSCR0_WRAH(x) (((x)&0x00000003)<<16)
4754 +/* Read address hold or deselect */
4755 +#define MCF_FBCS_CSCR0_RDAH(x) (((x)&0x00000003)<<18)
4756 +#define MCF_FBCS_CSCR0_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
4757 +/* Secondary wait state enable */
4758 +#define MCF_FBCS_CSCR0_SWSEN (0x00800000)
4759 +/* Secondary wait states */
4760 +#define MCF_FBCS_CSCR0_SWS(x) (((x)&0x0000003F)<<26)
4761 +#define MCF_FBCS_CSCR0_PS_8 (0x00000040)
4762 +#define MCF_FBCS_CSCR0_PS_16 (0x00000080)
4763 +#define MCF_FBCS_CSCR0_PS_32 (0x00000000)
4764 +
4765 +/* Bit definitions and macros for CSMR1 */
4766 +#define MCF_FBCS_CSMR1_V (0x00000001) /* Valid bit */
4767 +#define MCF_FBCS_CSMR1_WP (0x00000100) /* Write protect */
4768 +#define MCF_FBCS_CSMR1_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
4769 +
4770 +/* Bit definitions and macros for CSCR1 */
4771 +#define MCF_FBCS_CSCR1_BSTW (0x00000008) /* Burst-write enable */
4772 +#define MCF_FBCS_CSCR1_BSTR (0x00000010) /* Burst-read enable */
4773 +#define MCF_FBCS_CSCR1_BEM (0x00000020) /* Byte-enable mode */
4774 +#define MCF_FBCS_CSCR1_PS(x) (((x)&0x00000003)<<6) /* Port size */
4775 +#define MCF_FBCS_CSCR1_AA (0x00000100) /* Auto-acknowledge */
4776 +#define MCF_FBCS_CSCR1_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
4777 +/* Write address hold or deselect */
4778 +#define MCF_FBCS_CSCR1_WRAH(x) (((x)&0x00000003)<<16)
4779 +/* Read address hold or deselect */
4780 +#define MCF_FBCS_CSCR1_RDAH(x) (((x)&0x00000003)<<18)
4781 +#define MCF_FBCS_CSCR1_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
4782 +/* Secondary wait state enable */
4783 +#define MCF_FBCS_CSCR1_SWSEN (0x00800000)
4784 +/* Secondary wait states */
4785 +#define MCF_FBCS_CSCR1_SWS(x) (((x)&0x0000003F)<<26)
4786 +
4787 +/* Bit definitions and macros for CSMR2 */
4788 +#define MCF_FBCS_CSMR2_V (0x00000001) /* Valid bit */
4789 +#define MCF_FBCS_CSMR2_WP (0x00000100) /* Write protect */
4790 +#define MCF_FBCS_CSMR2_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
4791 +
4792 +/* Bit definitions and macros for CSCR2 */
4793 +#define MCF_FBCS_CSCR2_BSTW (0x00000008) /* Burst-write enable */
4794 +#define MCF_FBCS_CSCR2_BSTR (0x00000010) /* Burst-read enable */
4795 +#define MCF_FBCS_CSCR2_BEM (0x00000020) /* Byte-enable mode */
4796 +#define MCF_FBCS_CSCR2_PS(x) (((x)&0x00000003)<<6) /* Port size */
4797 +#define MCF_FBCS_CSCR2_AA (0x00000100) /* Auto-acknowledge */
4798 +#define MCF_FBCS_CSCR2_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
4799 +/* Write address hold or deselect */
4800 +#define MCF_FBCS_CSCR2_WRAH(x) (((x)&0x00000003)<<16)
4801 +/* Read address hold or deselect */
4802 +#define MCF_FBCS_CSCR2_RDAH(x) (((x)&0x00000003)<<18)
4803 +#define MCF_FBCS_CSCR2_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
4804 +/* Secondary wait state enable */
4805 +#define MCF_FBCS_CSCR2_SWSEN (0x00800000)
4806 +/* Secondary wait states */
4807 +#define MCF_FBCS_CSCR2_SWS(x) (((x)&0x0000003F)<<26)
4808 +
4809 +/* Bit definitions and macros for CSMR3 */
4810 +#define MCF_FBCS_CSMR3_V (0x00000001) /* Valid bit */
4811 +#define MCF_FBCS_CSMR3_WP (0x00000100) /* Write protect */
4812 +#define MCF_FBCS_CSMR3_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
4813 +
4814 +/* Bit definitions and macros for CSCR3 */
4815 +#define MCF_FBCS_CSCR3_BSTW (0x00000008) /* Burst-write enable */
4816 +#define MCF_FBCS_CSCR3_BSTR (0x00000010) /* Burst-read enable */
4817 +#define MCF_FBCS_CSCR3_BEM (0x00000020) /* Byte-enable mode */
4818 +#define MCF_FBCS_CSCR3_PS(x) (((x)&0x00000003)<<6) /* Port size */
4819 +#define MCF_FBCS_CSCR3_AA (0x00000100) /* Auto-acknowledge */
4820 +#define MCF_FBCS_CSCR3_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
4821 +/* Write address hold or deselect */
4822 +#define MCF_FBCS_CSCR3_WRAH(x) (((x)&0x00000003)<<16)
4823 +/* Read address hold or deselect */
4824 +#define MCF_FBCS_CSCR3_RDAH(x) (((x)&0x00000003)<<18)
4825 +#define MCF_FBCS_CSCR3_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
4826 +/* Secondary wait state enable */
4827 +#define MCF_FBCS_CSCR3_SWSEN (0x00800000)
4828 +/* Secondary wait states */
4829 +#define MCF_FBCS_CSCR3_SWS(x) (((x)&0x0000003F)<<26)
4830 +
4831 +/********************************************************************/
4832 +
4833 +#endif /* __MCF5441X_FBCS_H__ */
4834 --- /dev/null
4835 +++ b/arch/m68k/include/asm/mcf5441x_flexcan.h
4836 @@ -0,0 +1,139 @@
4837 +/*
4838 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
4839 + *
4840 + * Author: Lanttor Guo <b18203@freescale.com>
4841 + *
4842 + * This is free software; you can redistribute it and/or modify it
4843 + * under the terms of the GNU General Public License as published by
4844 + * the Free Software Foundation; either version 2 of the License, or
4845 + * (at your option) any later version.
4846 + */
4847 +
4848 +#ifndef MCF5441X_FLEXCAN_H
4849 +#define MCF5441X_FLEXCAN_H
4850 +/*
4851 + * FlexCAN Module Configuration Register
4852 + */
4853 +#define CANMCR_MDIS (0x80000000)
4854 +#define CANMCR_FRZ (0x40000000)
4855 +#define CANMCR_FEN (0x20000000)
4856 +#define CANMCR_HALT (0x10000000)
4857 +#define CANMCR_SOFTRST (0x02000000)
4858 +#define CANMCR_NOTRDY (0x08000000)
4859 +#define CANMCR_FRZACK (0x01000000)
4860 +#define CANMCR_SUPV (0x00800000)
4861 +#define CANMCR_WARN_EN (0x00200000)
4862 +#define CANMCR_LPMACK (0x00100000)
4863 +#define CANMCR_DOZE (0x00040000)
4864 +#define CANMCR_SRXDIS (0x00020000)
4865 +#define CANMCR_BCC (0x00010000)
4866 +#define CANMCR_LPRIO_EN (0x00002000)
4867 +#define CANMCR_AEN (0x00001000)
4868 +#define CANMCR_IDAM_VAL(x) ((x & 0x3) << 8)
4869 +#define CANMCR_MAXMB (0x0F)
4870 +/*
4871 + * FlexCAN Control Register
4872 + */
4873 +#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24)
4874 +#define CANCTRL_RJW(x) (((x)&0x03)<<22)
4875 +#define CANCTRL_PSEG1(x) (((x)&0x07)<<19)
4876 +#define CANCTRL_PSEG2(x) (((x)&0x07)<<16)
4877 +#define CANCTRL_BOFFMSK (0x00008000)
4878 +#define CANCTRL_ERRMSK (0x00004000)
4879 +#define CANCTRL_CLKSRC (0x00002000)
4880 +#define CANCTRL_LPB (0x00001000)
4881 +#define CANCTRL_TWRN_MSK (0x00000800)
4882 +#define CANCTRL_RWRN_MSK (0x00000400)
4883 +#define CANCTRL_SAMP(x) (((x)&0x01)<<7)
4884 +#define CANCTRL_BOFFREC (0x00000040)
4885 +#define CANCTRL_TSYNC (0x00000020)
4886 +#define CANCTRL_LBUF (0x00000010)
4887 +#define CANCTRL_LOM (0x00000008)
4888 +#define CANCTRL_PROPSEG(x) ((x)&0x07)
4889 +
4890 +/*
4891 + * FlexCAN Error Counter Register
4892 + */
4893 +#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8)
4894 +#define ERRCNT_TXECTR(x) ((x)&0xFF)
4895 +
4896 +/*
4897 + * FlexCAN Error and Status Register
4898 + */
4899 +#define ERRSTAT_TWRN_INT (0x00020000)
4900 +#define ERRSTAT_RWRN_INT (0x00010000)
4901 +#define ERRSTAT_BITERR(x) (((x)&0x03)<<14)
4902 +#define ERRSTAT_ACKERR (0x00002000)
4903 +#define ERRSTAT_CRCERR (0x00001000)
4904 +#define ERRSTAT_FRMERR (0x00000800)
4905 +#define ERRSTAT_STFERR (0x00000400)
4906 +#define ERRSTAT_TXWRN (0x00000200)
4907 +#define ERRSTAT_RXWRN (0x00000100)
4908 +#define ERRSTAT_IDLE (0x00000080)
4909 +#define ERRSTAT_TXRX (0x00000040)
4910 +#define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4)
4911 +#define ERRSTAT_BOFFINT (0x00000004)
4912 +#define ERRSTAT_ERRINT (0x00000002)
4913 +
4914 +/*
4915 + * Interrupt Mask Register
4916 + */
4917 +#define IMASK_BUF15M (0x8000)
4918 +#define IMASK_BUF14M (0x4000)
4919 +#define IMASK_BUF13M (0x2000)
4920 +#define IMASK_BUF12M (0x1000)
4921 +#define IMASK_BUF11M (0x0800)
4922 +#define IMASK_BUF10M (0x0400)
4923 +#define IMASK_BUF9M (0x0200)
4924 +#define IMASK_BUF8M (0x0100)
4925 +#define IMASK_BUF7M (0x0080)
4926 +#define IMASK_BUF6M (0x0040)
4927 +#define IMASK_BUF5M (0x0020)
4928 +#define IMASK_BUF4M (0x0010)
4929 +#define IMASK_BUF3M (0x0008)
4930 +#define IMASK_BUF2M (0x0004)
4931 +#define IMASK_BUF1M (0x0002)
4932 +#define IMASK_BUF0M (0x0001)
4933 +#define IMASK_BUFnM(x) (0x1<<(x))
4934 +#define IMASK_BUFF_ENABLE_ALL (0xFFFF)
4935 +#define IMASK_BUFF_DISABLE_ALL (0x0000)
4936 +
4937 +/*
4938 + * Interrupt Flag Register
4939 + */
4940 +#define IFLAG_BUF15M (0x8000)
4941 +#define IFLAG_BUF14M (0x4000)
4942 +#define IFLAG_BUF13M (0x2000)
4943 +#define IFLAG_BUF12M (0x1000)
4944 +#define IFLAG_BUF11M (0x0800)
4945 +#define IFLAG_BUF10M (0x0400)
4946 +#define IFLAG_BUF9M (0x0200)
4947 +#define IFLAG_BUF8M (0x0100)
4948 +#define IFLAG_BUF7M (0x0080)
4949 +#define IFLAG_BUF6M (0x0040)
4950 +#define IFLAG_BUF5M (0x0020)
4951 +#define IFLAG_BUF4M (0x0010)
4952 +#define IFLAG_BUF3M (0x0008)
4953 +#define IFLAG_BUF2M (0x0004)
4954 +#define IFLAG_BUF1M (0x0002)
4955 +#define IFLAG_BUF0M (0x0001)
4956 +#define IFLAG_BUFF_SET_ALL (0xFFFF)
4957 +#define IFLAG_BUFF_CLEAR_ALL (0x0000)
4958 +#define IFLAG_BUFnM(x) (0x1<<(x))
4959 +
4960 +/*
4961 + * Message Buffers
4962 + */
4963 +#define MB_CNT_CODE(x) (((x)&0x0F)<<24)
4964 +#define MB_CNT_SRR (0x00400000)
4965 +#define MB_CNT_IDE (0x00200000)
4966 +#define MB_CNT_RTR (0x00100000)
4967 +#define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF)
4968 +#define MB_PRIO(x) (((x)&0x7)<<29)
4969 +#define MB_ID_STD (0x07FF)
4970 +#define MB_ID_EXT (0x1FFFFFFF)
4971 +#define MB_CODE_MASK (0xF0FFFFFF)
4972 +#define CAN_MB 16
4973 +#define PDEV_MAX 2
4974 +
4975 +#endif
4976 --- /dev/null
4977 +++ b/arch/m68k/include/asm/mcf5441x_gpio.h
4978 @@ -0,0 +1,509 @@
4979 +/*
4980 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
4981 + *
4982 + * This program is free software; you can redistribute it and/or modify it
4983 + * under the terms of the GNU General Public License as published by the
4984 + * Free Software Foundation; either version 2 of the License, or (at your
4985 + * option) any later version.
4986 + */
4987 +
4988 +#ifndef __MCF5441X_GPIO_H__
4989 +#define __MCF5441X_GPIO_H__
4990 +
4991 +/*********************************************************************
4992 +*
4993 +* General Purpose I/O Module (GPIO)
4994 +*
4995 +*********************************************************************/
4996 +
4997 +#define MCF_GPIO_PODR_A MCF_REG08(0xEC094000)
4998 +#define MCF_GPIO_PODR_B MCF_REG08(0xEC094001)
4999 +#define MCF_GPIO_PODR_C MCF_REG08(0xEC094002)
5000 +#define MCF_GPIO_PODR_D MCF_REG08(0xEC094003)
5001 +#define MCF_GPIO_PODR_E MCF_REG08(0xEC094004)
5002 +#define MCF_GPIO_PODR_F MCF_REG08(0xEC094005)
5003 +#define MCF_GPIO_PODR_G MCF_REG08(0xEC094006)
5004 +#define MCF_GPIO_PODR_H MCF_REG08(0xEC094007)
5005 +#define MCF_GPIO_PODR_I MCF_REG08(0xEC094008)
5006 +#define MCF_GPIO_PODR_J MCF_REG08(0xEC094009)
5007 +#define MCF_GPIO_PODR_K MCF_REG08(0xEC09400A)
5008 +
5009 +#define MCF_GPIO_PDDR_A MCF_REG08(0xEC09400C)
5010 +#define MCF_GPIO_PDDR_B MCF_REG08(0xEC09400D)
5011 +#define MCF_GPIO_PDDR_C MCF_REG08(0xEC09400E)
5012 +#define MCF_GPIO_PDDR_D MCF_REG08(0xEC09400F)
5013 +#define MCF_GPIO_PDDR_E MCF_REG08(0xEC094010)
5014 +#define MCF_GPIO_PDDR_F MCF_REG08(0xEC094011)
5015 +#define MCF_GPIO_PDDR_G MCF_REG08(0xEC094012)
5016 +#define MCF_GPIO_PDDR_H MCF_REG08(0xEC094013)
5017 +#define MCF_GPIO_PDDR_I MCF_REG08(0xEC094014)
5018 +#define MCF_GPIO_PDDR_J MCF_REG08(0xEC094015)
5019 +#define MCF_GPIO_PDDR_K MCF_REG08(0xEC094016)
5020 +
5021 +#define MCF_GPIO_PPDSDR_A MCF_REG08(0xEC094018)
5022 +#define MCF_GPIO_PPDSDR_B MCF_REG08(0xEC094019)
5023 +#define MCF_GPIO_PPDSDR_C MCF_REG08(0xEC09401A)
5024 +#define MCF_GPIO_PPDSDR_D MCF_REG08(0xEC09401B)
5025 +#define MCF_GPIO_PPDSDR_E MCF_REG08(0xEC09401C)
5026 +#define MCF_GPIO_PPDSDR_F MCF_REG08(0xEC09401D)
5027 +#define MCF_GPIO_PPDSDR_G MCF_REG08(0xEC09401E)
5028 +#define MCF_GPIO_PPDSDR_H MCF_REG08(0xEC09401F)
5029 +#define MCF_GPIO_PPDSDR_I MCF_REG08(0xEC094020)
5030 +#define MCF_GPIO_PPDSDR_J MCF_REG08(0xEC094021)
5031 +#define MCF_GPIO_PPDSDR_K MCF_REG08(0xEC094022)
5032 +
5033 +#define MCF_GPIO_PCLRR_A MCF_REG08(0xEC094024)
5034 +#define MCF_GPIO_PCLRR_B MCF_REG08(0xEC094025)
5035 +#define MCF_GPIO_PCLRR_C MCF_REG08(0xEC094026)
5036 +#define MCF_GPIO_PCLRR_D MCF_REG08(0xEC094027)
5037 +#define MCF_GPIO_PCLRR_E MCF_REG08(0xEC094028)
5038 +#define MCF_GPIO_PCLRR_F MCF_REG08(0xEC094029)
5039 +#define MCF_GPIO_PCLRR_G MCF_REG08(0xEC09402A)
5040 +#define MCF_GPIO_PCLRR_H MCF_REG08(0xEC09402B)
5041 +#define MCF_GPIO_PCLRR_I MCF_REG08(0xEC09402C)
5042 +#define MCF_GPIO_PCLRR_J MCF_REG08(0xEC09402D)
5043 +#define MCF_GPIO_PCLRR_K MCF_REG08(0xEC09402E)
5044 +
5045 +#define MCF_GPIO_PCR_A MCF_REG16(0xEC094030)
5046 +#define MCF_GPIO_PCR_B MCF_REG16(0xEC094032)
5047 +#define MCF_GPIO_PCR_C MCF_REG16(0xEC094034)
5048 +#define MCF_GPIO_PCR_D MCF_REG16(0xEC094036)
5049 +#define MCF_GPIO_PCR_E MCF_REG16(0xEC094038)
5050 +#define MCF_GPIO_PCR_F MCF_REG16(0xEC09403A)
5051 +#define MCF_GPIO_PCR_G MCF_REG16(0xEC09403C)
5052 +
5053 +#define MCF_GPIO_PCR_H MCF_REG16(0xEC09403E)
5054 +#define MCF_GPIO_PCR_I MCF_REG16(0xEC094040)
5055 +#define MCF_GPIO_PCR_J MCF_REG16(0xEC094042)
5056 +#define MCF_GPIO_PCR_K MCF_REG16(0xEC094044)
5057 +
5058 +#define MCF_GPIO_PODR_G4_VAL (0x01 << 4)
5059 +#define MCF_GPIO_PODR_G4_MASK (0xff & ~MCF_GPIO_PODR_G4_VAL)
5060 +#define MCF_GPIO_PDDR_G4_OUTPUT (0x01 << 4)
5061 +#define MCF_GPIO_PDDR_G4_MASK (0xff & ~MCF_GPIO_PDDR_G4_OUTPUT)
5062 +
5063 +#define MCF_GPIO_PAR_FBCTL MCF_REG08(0xEC094048)
5064 +#define MCF_GPIO_PAR_BE MCF_REG08(0xEC094049)
5065 +#define MCF_GPIO_PAR_CS MCF_REG08(0xEC09404A)
5066 +#define MCF_GPIO_PAR_CANI2C MCF_REG08(0xEC09404B)
5067 +#define MCF_GPIO_PAR_IRQ0H MCF_REG08(0xEC09404C)
5068 +#define MCF_GPIO_PAR_IRQ0L MCF_REG08(0xEC09404D)
5069 +#define MCF_GPIO_PAR_DSPI0WH MCF_REG08(0xEC09404E)
5070 +#define MCF_GPIO_PAR_DSPI0WL MCF_REG08(0xEC09404F)
5071 +#define MCF_GPIO_PAR_TIMER MCF_REG08(0xEC094050)
5072 +#define MCF_GPIO_PAR_UART2 MCF_REG08(0xEC094051)
5073 +#define MCF_GPIO_PAR_UART1 MCF_REG08(0xEC094052)
5074 +#define MCF_GPIO_PAR_UART0 MCF_REG08(0xEC094053)
5075 +#define MCF_GPIO_PAR_ESDHCH MCF_REG08(0xEC094054)
5076 +#define MCF_GPIO_PAR_ESDHCL MCF_REG08(0xEC094055)
5077 +#define MCF_GPIO_PAR_SIMP0H MCF_REG08(0xEC094056)
5078 +#define MCF_GPIO_PAR_SIMP0L MCF_REG08(0xEC094057)
5079 +#define MCF_GPIO_PAR_SSI0H MCF_REG08(0xEC094058)
5080 +#define MCF_GPIO_PAR_SSI0L MCF_REG08(0xEC094059)
5081 +#define MCF_GPIO_PAR_DBGH1 MCF_REG08(0xEC09405A)
5082 +#define MCF_GPIO_PAR_DBGH0 MCF_REG08(0xEC09405B)
5083 +#define MCF_GPIO_PAR_DBGL MCF_REG08(0xEC09405C)
5084 +#define MCF_GPIO_PAR_FEC MCF_REG08(0xEC09405E)
5085 +#define MCF_GPIO_MSCR_SDRAMC MCF_REG08(0xEC094064)
5086 +#define MCF_GPIO_SRCR_FB1 MCF_REG08(0xEC094064)
5087 +#define MCF_GPIO_SRCR_FB2 MCF_REG08(0xEC094065)
5088 +#define MCF_GPIO_SRCR_FB3 MCF_REG08(0xEC094066)
5089 +#define MCF_GPIO_SRCR_FB4 MCF_REG08(0xEC094067)
5090 +#define MCF_GPIO_SRCR_DSPI0W MCF_REG08(0xEC094068)
5091 +#define MCF_GPIO_SRCR_CANI2C MCF_REG08(0xEC094069)
5092 +#define MCF_GPIO_SRCR_IRQ0 MCF_REG08(0xEC09406A)
5093 +#define MCF_GPIO_SRCR_TIMER MCF_REG08(0xEC09406B)
5094 +#define MCF_GPIO_SRCR_UART MCF_REG08(0xEC09406C)
5095 +#define MCF_GPIO_SRCR_FEC MCF_REG08(0xEC09406D)
5096 +#define MCF_GPIO_SRCR_SDHC MCF_REG08(0xEC09406E)
5097 +#define MCF_GPIO_SRCR_SIM0 MCF_REG08(0xEC09406F)
5098 +#define MCF_GPIO_SRCR_SSI0 MCF_REG08(0xEC094070)
5099 +
5100 +#define MCF_GPIO_PAR_FBCTL_ALE(x) (((x)&3)<<6)
5101 +#define MCF_GPIO_PAR_FBCTL_ALE_MASK (0x3F)
5102 +#define MCF_GPIO_PAR_FBCTL_ALE_FB_ALE (0xC0)
5103 +#define MCF_GPIO_PAR_FBCTL_ALE_FB_TS (0x80)
5104 +#define MCF_GPIO_PAR_FBCTL_ALE_GPIO (0x00)
5105 +#define MCF_GPIO_PAR_FBCTL_OE(x) (((x)&3)<<4)
5106 +#define MCF_GPIO_PAR_FBCTL_OE_MASK (0xCF)
5107 +#define MCF_GPIO_PAR_FBCTL_OE_FB_OE (0x30)
5108 +#define MCF_GPIO_PAR_FBCTL_OE_FB_TBST (0x20)
5109 +#define MCF_GPIO_PAR_FBCTL_OE_NFC_RE (0x20)
5110 +#define MCF_GPIO_PAR_FBCTL_OE_GPIO (0x00)
5111 +#define MCF_GPIO_PAR_FBCTL_FBCLK (0x08)
5112 +#define MCF_GPIO_PAR_FBCTL_RW (0x04)
5113 +#define MCF_GPIO_PAR_FBCTL_TA(x) ((x)&3)
5114 +#define MCF_GPIO_PAR_FBCTL_TA_MASK (0xFC)
5115 +#define MCF_GPIO_PAR_FBCTL_TA_TA (0x03)
5116 +#define MCF_GPIO_PAR_FBCTL_TA_NFC_RB (0x01)
5117 +#define MCF_GPIO_PAR_FBCTL_TA_GPIO (0x00)
5118 +
5119 +#define MCF_GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6)
5120 +#define MCF_GPIO_PAR_BE_BE3_MASK (0x3F)
5121 +#define MCF_GPIO_PAR_BE_BE3_BE3 (0xC0)
5122 +#define MCF_GPIO_PAR_BE_BE3_CS3 (0x80)
5123 +#define MCF_GPIO_PAR_BE_BE3_FB_A1 (0x40)
5124 +#define MCF_GPIO_PAR_BE_BE3_NFC_ALE (0x40)
5125 +#define MCF_GPIO_PAR_BE_BE3_GPIO (0x00)
5126 +#define MCF_GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4)
5127 +#define MCF_GPIO_PAR_BE_BE2_MASK (0xCF)
5128 +#define MCF_GPIO_PAR_BE_BE2_BE2 (0x30)
5129 +#define MCF_GPIO_PAR_BE_BE2_CS2 (0x20)
5130 +#define MCF_GPIO_PAR_BE_BE2_FB_A0 (0x10)
5131 +#define MCF_GPIO_PAR_BE_BE2_NFC_CLE (0x10)
5132 +#define MCF_GPIO_PAR_BE_BE2_GPIO (0x00)
5133 +#define MCF_GPIO_PAR_BE_BS1(x) (((x)&0x03)<<2)
5134 +#define MCF_GPIO_PAR_BE_BE1_MASK (0xF3)
5135 +#define MCF_GPIO_PAR_BE_BE1_BE1 (0x0C)
5136 +#define MCF_GPIO_PAR_BE_BE1_FB_TSZ1 (0x08)
5137 +#define MCF_GPIO_PAR_BE_BE1_GPIO (0x00)
5138 +#define MCF_GPIO_PAR_BE_BS0(x) ((x)&0x03)
5139 +#define MCF_GPIO_PAR_BE_BE0_MASK (0xFC)
5140 +#define MCF_GPIO_PAR_BE_BE0_BE0 (0x03)
5141 +#define MCF_GPIO_PAR_BE_BE0_FB_TSZ0 (0x02)
5142 +#define MCF_GPIO_PAR_BE_BE0_GPIO (0x00)
5143 +
5144 +#define MCF_GPIO_PAR_CS_CS5(x) (((x)&0x03)<<6)
5145 +#define MCF_GPIO_PAR_CS_CS5_MASK (0x3F)
5146 +#define MCF_GPIO_PAR_CS_CS5_CS5 (0xC0)
5147 +#define MCF_GPIO_PAR_CS_CS5_DACK1 (0x80)
5148 +#define MCF_GPIO_PAR_CS_CS5_GPIO (0x00)
5149 +#define MCF_GPIO_PAR_CS_CS4(x) (((x)&0x03)<<4)
5150 +#define MCF_GPIO_PAR_CS_CS4_MASK (0xCF)
5151 +#define MCF_GPIO_PAR_CS_CS4_CS4 (0x30)
5152 +#define MCF_GPIO_PAR_CS_CS4_DREQ1 (0x20)
5153 +#define MCF_GPIO_PAR_CS_CS4_GPIO (0x00)
5154 +#define MCF_GPIO_PAR_CS_CS1(x) (((x)&0x03)<<2)
5155 +#define MCF_GPIO_PAR_CS_CS1_MASK (0xF3)
5156 +#define MCF_GPIO_PAR_CS_CS1_CS1 (0x0C)
5157 +#define MCF_GPIO_PAR_CS_CS1_NFC_CE (0x04)
5158 +#define MCF_GPIO_PAR_CS_CS1_GPIO (0x00)
5159 +#define MCF_GPIO_PAR_CS_CS0_CS0 (0x01)
5160 +
5161 +#define MCF_GPIO_PAR_CANI2C_I2C0SCL(x) (((x)&0x03)<<6)
5162 +#define MCF_GPIO_PAR_CANI2C_I2C0SCL_MASK (0x3F)
5163 +#define MCF_GPIO_PAR_CANI2C_I2C0SCL_I2C0SCL (0xC0)
5164 +#define MCF_GPIO_PAR_CANI2C_I2C0SCL_U8TXD (0x80)
5165 +#define MCF_GPIO_PAR_CANI2C_I2C0SCL_CAN0TX (0x40)
5166 +#define MCF_GPIO_PAR_CANI2C_I2C0SCL_GPIO (0x00)
5167 +#define MCF_GPIO_PAR_CANI2C_I2C0SDA(x) (((x)&0x03)<<4)
5168 +#define MCF_GPIO_PAR_CANI2C_I2C0SDA_MASK (0xCF)
5169 +#define MCF_GPIO_PAR_CANI2C_I2C0SDA_I2C0SDA (0x30)
5170 +#define MCF_GPIO_PAR_CANI2C_I2C0SDA_U8RXD (0x20)
5171 +#define MCF_GPIO_PAR_CANI2C_I2C0SDA_CAN0RX (0x10)
5172 +#define MCF_GPIO_PAR_CANI2C_I2C0SDA_GPIO (0x00)
5173 +#define MCF_GPIO_PAR_CANI2C_CAN1TX(x) (((x)&0x03)<<2)
5174 +#define MCF_GPIO_PAR_CANI2C_CAN1TX_MASK (0xF3)
5175 +#define MCF_GPIO_PAR_CANI2C_CAN1TX_CAN1TX (0x0C)
5176 +#define MCF_GPIO_PAR_CANI2C_CAN1TX_U9TXD (0x08)
5177 +#define MCF_GPIO_PAR_CANI2C_CAN1TX_I2C1SCL (0x04)
5178 +#define MCF_GPIO_PAR_CANI2C_CAN1TX_GPIO (0x00)
5179 +#define MCF_GPIO_PAR_CANI2C_CAN1RX(x) ((x)&0x03)
5180 +#define MCF_GPIO_PAR_CANI2C_CAN1RX_MASK (0xFC)
5181 +#define MCF_GPIO_PAR_CANI2C_CAN1RX_CAN1RX (0x03)
5182 +#define MCF_GPIO_PAR_CANI2C_CAN1RX_U9RXD (0x02)
5183 +#define MCF_GPIO_PAR_CANI2C_CAN1RX_I2C1SDA (0x01)
5184 +#define MCF_GPIO_PAR_CANI2C_CAN1RX_GPIO (0x00)
5185 +
5186 +#define MCF_GPIO_PAR_IRQH_IRQ7 (0x10)
5187 +#define MCF_GPIO_PAR_IRQH_IRQ4(x) (((x)&0x03)<<2)
5188 +#define MCF_GPIO_PAR_IRQH_IRQ4_MASK (0xF3)
5189 +#define MCF_GPIO_PAR_IRQH_IRQ4_IRQ4 (0x0C)
5190 +#define MCF_GPIO_PAR_IRQH_IRQ4_DREQ0 (0x08)
5191 +#define MCF_GPIO_PAR_IRQH_IRQ4_GPIO (0x00)
5192 +#define MCF_GPIO_PAR_IRQH_IRQ1 (0x01)
5193 +
5194 +#define MCF_GPIO_PAR_IRQL_IRQ6(x) (((x)&0x03)<<6)
5195 +#define MCF_GPIO_PAR_IRQL_IRQ6_MASK (0x3F)
5196 +#define MCF_GPIO_PAR_IRQL_IRQ6_IRQ6 (0xC0)
5197 +#define MCF_GPIO_PAR_IRQL_IRQ6_USBCLKIN (0x40)
5198 +#define MCF_GPIO_PAR_IRQL_IRQ6_GPIO (0x00)
5199 +#define MCF_GPIO_PAR_IRQL_IRQ3(x) (((x)&0x03)<<4)
5200 +#define MCF_GPIO_PAR_IRQL_IRQ3_MASK (0xCF)
5201 +#define MCF_GPIO_PAR_IRQL_IRQ3_IRQ3 (0x30)
5202 +#define MCF_GPIO_PAR_IRQL_IRQ3_DSPI0_PCS3 (0x20)
5203 +#define MCF_GPIO_PAR_IRQL_IRQ3_USB1_VBUS_EN (0x10)
5204 +#define MCF_GPIO_PAR_IRQL_IRQ3_GPIO (0x00)
5205 +#define MCF_GPIO_PAR_IRQL_IRQ2(x) (((x)&0x03)<<2)
5206 +#define MCF_GPIO_PAR_IRQL_IRQ2_MASK (0xF3)
5207 +#define MCF_GPIO_PAR_IRQL_IRQ2_IRQ2 (0x0C)
5208 +#define MCF_GPIO_PAR_IRQL_IRQ2_DSPI0_PCS2 (0x08)
5209 +#define MCF_GPIO_PAR_IRQL_IRQ2_USB1_VBUS_OC (0x04)
5210 +#define MCF_GPIO_PAR_IRQL_IRQ2_GPIO (0x00)
5211 +
5212 +#define MCF_GPIO_PAR_DSPI0_SIN(x) (((x)&0x03)<<6)
5213 +#define MCF_GPIO_PAR_DSPI0_SIN_MASK (0x3F)
5214 +#define MCF_GPIO_PAR_DSPI0_SIN_DSPI0SIN (0xC0)
5215 +#define MCF_GPIO_PAR_DSPI0_SIN_SBF_DI (0xC0)
5216 +#define MCF_GPIO_PAR_DSPI0_SIN_U3RXD (0x80)
5217 +#define MCF_GPIO_PAR_DSPI0_SIN_SDHC_CMD (0x40)
5218 +#define MCF_GPIO_PAR_DSPI0_SIN_GPIO (0x00)
5219 +#define MCF_GPIO_PAR_DSPI0_SOUT(x) (((x)&0x03)<<4)
5220 +#define MCF_GPIO_PAR_DSPI0_SOUT_MASK (0xCF)
5221 +#define MCF_GPIO_PAR_DSPI0_SOUT_DSPI0SOUT (0x30)
5222 +#define MCF_GPIO_PAR_DSPI0_SOUT_SBF_DO (0x30)
5223 +#define MCF_GPIO_PAR_DSPI0_SOUT_U3TXD (0x20)
5224 +#define MCF_GPIO_PAR_DSPI0_SOUT_SDHC_DAT0 (0x10)
5225 +#define MCF_GPIO_PAR_DSPI0_SOUT_GPIO (0x00)
5226 +#define MCF_GPIO_PAR_DSPI0_SCK(x) (((x)&0x03)<<2)
5227 +#define MCF_GPIO_PAR_DSPI0_SCK_MASK (0xF3)
5228 +#define MCF_GPIO_PAR_DSPI0_SCK_DSPI0SCK (0x0C)
5229 +#define MCF_GPIO_PAR_DSPI0_SCK_SBF_CK (0x0C)
5230 +#define MCF_GPIO_PAR_DSPI0_SCK_I2C3SCL (0x08)
5231 +#define MCF_GPIO_PAR_DSPI0_SCK_SDHC_CLK (0x04)
5232 +#define MCF_GPIO_PAR_DSPI0_SCK_GPIO (0x00)
5233 +#define MCF_GPIO_PAR_DSPI0_PCS0(x) ((x)&0x03)
5234 +#define MCF_GPIO_PAR_DSPI0_PCS0_MASK (0xFC)
5235 +#define MCF_GPIO_PAR_DSPI0_PCS0_DSPI0PCS0 (0x03)
5236 +#define MCF_GPIO_PAR_DSPI0_PCS0_SS (0x03)
5237 +#define MCF_GPIO_PAR_DSPI0_PCS0_I2C3SDA (0x02)
5238 +#define MCF_GPIO_PAR_DSPI0_PCS0_SDHC_DAT3 (0x01)
5239 +#define MCF_GPIO_PAR_DSPI0_PCS0_GPIO (0x00)
5240 +
5241 +#define MCF_GPIO_PAR_DSPIOW_DSPI0PSC1 (0x80)
5242 +#define MCF_GPIO_PAR_DSPIOW_SBF_CS (0x80)
5243 +#define MCF_GPIO_PAR_DSPIOW_OWDAT (((x)&0x03)<<4)
5244 +#define MCF_GPIO_PAR_DSPIOW_OWDAT_MASK (0xCF)
5245 +#define MCF_GPIO_PAR_DSPIOW_OWDAT_OWDAT (0x30)
5246 +#define MCF_GPIO_PAR_DSPIOW_OWDAT_DACK0 (0x20)
5247 +#define MCF_GPIO_PAR_DSPIOW_OWDAT_GPIO (0x00)
5248 +
5249 +#define MCF_GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
5250 +#define MCF_GPIO_PAR_TIMER_T3IN_MASK (0x3F)
5251 +#define MCF_GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
5252 +#define MCF_GPIO_PAR_TIMER_T3IN_EXTA3 (0xC0)
5253 +#define MCF_GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
5254 +#define MCF_GPIO_PAR_TIMER_T3IN_USB0_VBUSEN (0x40)
5255 +#define MCF_GPIO_PAR_TIMER_T3IN_ULPI_DIR (0x40)
5256 +#define MCF_GPIO_PAR_TIMER_T3IN_GPIO (0x00)
5257 +#define MCF_GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
5258 +#define MCF_GPIO_PAR_TIMER_T2IN_MASK (0xCF)
5259 +#define MCF_GPIO_PAR_TIMER_T2IN_T2IN (0x30)
5260 +#define MCF_GPIO_PAR_TIMER_T2IN_EXTA2 (0x30)
5261 +#define MCF_GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
5262 +#define MCF_GPIO_PAR_TIMER_T2IN_SDHC_DAT2 (0x10)
5263 +#define MCF_GPIO_PAR_TIMER_T2IN_GPIO (0x00)
5264 +#define MCF_GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
5265 +#define MCF_GPIO_PAR_TIMER_T1IN_MASK (0xF3)
5266 +#define MCF_GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
5267 +#define MCF_GPIO_PAR_TIMER_T1IN_EXTA1 (0x0C)
5268 +#define MCF_GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
5269 +#define MCF_GPIO_PAR_TIMER_T1IN_SDHC_DAT1 (0x04)
5270 +#define MCF_GPIO_PAR_TIMER_T1IN_GPIO (0x00)
5271 +#define MCF_GPIO_PAR_TIMER_T0IN(x) ((x)&0x03)
5272 +#define MCF_GPIO_PAR_TIMER_T0IN_MASK (0xFC)
5273 +#define MCF_GPIO_PAR_TIMER_T0IN_T0IN (0x03)
5274 +#define MCF_GPIO_PAR_TIMER_T0IN_EXTA0 (0x03)
5275 +#define MCF_GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
5276 +#define MCF_GPIO_PAR_TIMER_T0IN_USBO_VBUSOC (0x01)
5277 +#define MCF_GPIO_PAR_TIMER_T0IN_ULPI_NXT (0x01)
5278 +#define MCF_GPIO_PAR_TIMER_T0IN_GPIO (0x00)
5279 +
5280 +#define MCF_GPIO_PAR_UART2_U2CTS(x) (((x)&0x03)<<6)
5281 +#define MCF_GPIO_PAR_UART2_U2CTS_MASK (0x3F)
5282 +#define MCF_GPIO_PAR_UART2_U2CTS_U2CTS (0xC0)
5283 +#define MCF_GPIO_PAR_UART2_U2CTS_U6TXD (0x80)
5284 +#define MCF_GPIO_PAR_UART2_U2CTS_SSI1_BCLK (0x40)
5285 +#define MCF_GPIO_PAR_UART2_U2CTS_GPIO (0x00)
5286 +#define MCF_GPIO_PAR_UART2_U2RTS(x) (((x)&0x03)<<4)
5287 +#define MCF_GPIO_PAR_UART2_U2RTS_MASK (0xCF)
5288 +#define MCF_GPIO_PAR_UART2_U2RTS_U2RTS (0x30)
5289 +#define MCF_GPIO_PAR_UART2_U2RTS_U6RXD (0x20)
5290 +#define MCF_GPIO_PAR_UART2_U2RTS_SSI1_FS (0x10)
5291 +#define MCF_GPIO_PAR_UART2_U2RTS_GPIO (0x00)
5292 +#define MCF_GPIO_PAR_UART2_U2RXD(x) (((x)&0x03)<<2)
5293 +#define MCF_GPIO_PAR_UART2_U2RXD_MASK (0xF3)
5294 +#define MCF_GPIO_PAR_UART2_U2RXD_U2RXD (0x0C)
5295 +#define MCF_GPIO_PAR_UART2_U2RXD_PWM_A3 (0x08)
5296 +#define MCF_GPIO_PAR_UART2_U2RXD_SSI1_RXD (0x04)
5297 +#define MCF_GPIO_PAR_UART2_U2RXD_GPIO (0x00)
5298 +#define MCF_GPIO_PAR_UART2_U2TXD(x) ((x)&0x03)
5299 +#define MCF_GPIO_PAR_UART2_U2TXD_MASK (0xFC)
5300 +#define MCF_GPIO_PAR_UART2_U2TXD_U2TXD (0x03)
5301 +#define MCF_GPIO_PAR_UART2_U2TXD_PWM_B3 (0x02)
5302 +#define MCF_GPIO_PAR_UART2_U2TXD_SSI1_TXD (0x01)
5303 +#define MCF_GPIO_PAR_UART2_U2TXD_GPIO (0x00)
5304 +
5305 +#define MCF_GPIO_PAR_UART1_U1CTS(x) (((x)&0x03)<<6)
5306 +#define MCF_GPIO_PAR_UART1_U1CTS_MASK (0x3F)
5307 +#define MCF_GPIO_PAR_UART1_U1CTS_U1CTS (0xC0)
5308 +#define MCF_GPIO_PAR_UART1_U1CTS_U5TXD (0x80)
5309 +#define MCF_GPIO_PAR_UART1_U1CTS_DSPI3_SCK (0x40)
5310 +#define MCF_GPIO_PAR_UART1_U1CTS_GPIO (0x00)
5311 +#define MCF_GPIO_PAR_UART1_U1RTS(x) (((x)&0x03)<<4)
5312 +#define MCF_GPIO_PAR_UART1_U1RTS_MASK (0xCF)
5313 +#define MCF_GPIO_PAR_UART1_U1RTS_U1RTS (0x30)
5314 +#define MCF_GPIO_PAR_UART1_U1RTS_U5RXD (0x20)
5315 +#define MCF_GPIO_PAR_UART1_U1RTS_DSPI3_PCS0 (0x10)
5316 +#define MCF_GPIO_PAR_UART1_U1RTS_GPIO (0x00)
5317 +#define MCF_GPIO_PAR_UART1_U1RXD(x) (((x)&0x03)<<2)
5318 +#define MCF_GPIO_PAR_UART1_U1RXD_MASK (0xF3)
5319 +#define MCF_GPIO_PAR_UART1_U1RXD_U1RXD (0x0C)
5320 +#define MCF_GPIO_PAR_UART1_U1RXD_I2C5SDA (0x08)
5321 +#define MCF_GPIO_PAR_UART1_U1RXD_DSPI3_SIN (0x04)
5322 +#define MCF_GPIO_PAR_UART1_U1RXD_GPIO (0x00)
5323 +#define MCF_GPIO_PAR_UART1_U1TXD(x) ((x)&0x03)
5324 +#define MCF_GPIO_PAR_UART1_U1TXD_MASK (0xFC)
5325 +#define MCF_GPIO_PAR_UART1_U1TXD_U1TXD (0x03)
5326 +#define MCF_GPIO_PAR_UART1_U1TXD_I2C5SCL (0x02)
5327 +#define MCF_GPIO_PAR_UART1_U1TXD_DSPI3_SOUT (0x01)
5328 +#define MCF_GPIO_PAR_UART1_U1TXD_GPIO (0x00)
5329 +
5330 +#define MCF_GPIO_PAR_UART0_U0CTS(x) (((x)&0x03)<<6)
5331 +#define MCF_GPIO_PAR_UART0_U0CTS_MASK (0x3F)
5332 +#define MCF_GPIO_PAR_UART0_U0CTS_U0CTS (0xC0)
5333 +#define MCF_GPIO_PAR_UART0_U0CTS_U4TXD (0x80)
5334 +#define MCF_GPIO_PAR_UART0_U0CTS_DSPI2_SCK (0x40)
5335 +#define MCF_GPIO_PAR_UART0_U0CTS_GPIO (0x00)
5336 +#define MCF_GPIO_PAR_UART0_U0RTS(x) (((x)&0x03)<<4)
5337 +#define MCF_GPIO_PAR_UART0_U0RTS_MASK (0xCF)
5338 +#define MCF_GPIO_PAR_UART0_U0RTS_U0RTS (0x30)
5339 +#define MCF_GPIO_PAR_UART0_U0RTS_U4RXD (0x20)
5340 +#define MCF_GPIO_PAR_UART0_U0RTS_DSPI2_PCS0 (0x10)
5341 +#define MCF_GPIO_PAR_UART0_U0RTS_GPIO (0x00)
5342 +#define MCF_GPIO_PAR_UART0_U0RXD(x) (((x)&0x03)<<2)
5343 +#define MCF_GPIO_PAR_UART0_U0RXD_MASK (0xF3)
5344 +#define MCF_GPIO_PAR_UART0_U0RXD_U0RXD (0x0C)
5345 +#define MCF_GPIO_PAR_UART0_U0RXD_I2C4SDA (0x08)
5346 +#define MCF_GPIO_PAR_UART0_U0RXD_DSPI2_SIN (0x04)
5347 +#define MCF_GPIO_PAR_UART0_U0RXD_GPIO (0x00)
5348 +#define MCF_GPIO_PAR_UART0_U0TXD(x) ((x)&0x03)
5349 +#define MCF_GPIO_PAR_UART0_U0TXD_MASK (0xFC)
5350 +#define MCF_GPIO_PAR_UART0_U0TXD_U0TXD (0x03)
5351 +#define MCF_GPIO_PAR_UART0_U0TXD_I2C4SCL (0x02)
5352 +#define MCF_GPIO_PAR_UART0_U0TXD_DSPI2_SOUT (0x01)
5353 +#define MCF_GPIO_PAR_UART0_U0TXD_GPIO (0x00)
5354 +
5355 +#define MCF_GPIO_PAR_SDHCH_DAT3(x) (((x)&0x03)<<6)
5356 +#define MCF_GPIO_PAR_SDHCH_DAT3_MASK (0x3F)
5357 +#define MCF_GPIO_PAR_SDHCH_DAT3_DAT3 (0xC0)
5358 +#define MCF_GPIO_PAR_SDHCH_DAT3_PWM_A1 (0x80)
5359 +#define MCF_GPIO_PAR_SDHCH_DAT3_DSPI1_PCS0 (0x40)
5360 +#define MCF_GPIO_PAR_SDHCH_DAT3_GPIO (0x00)
5361 +#define MCF_GPIO_PAR_SDHCH_DAT2(x) (((x)&0x03)<<4)
5362 +#define MCF_GPIO_PAR_SDHCH_DAT2_MASK (0xCF)
5363 +#define MCF_GPIO_PAR_SDHCH_DAT2_DAT2 (0x30)
5364 +#define MCF_GPIO_PAR_SDHCH_DAT2_PWM_B1 (0x20)
5365 +#define MCF_GPIO_PAR_SDHCH_DAT2_DSPI1_PCS2 (0x10)
5366 +#define MCF_GPIO_PAR_SDHCH_DAT2_GPIO (0x00)
5367 +#define MCF_GPIO_PAR_SDHCH_DAT1(x) (((x)&0x03)<<2)
5368 +#define MCF_GPIO_PAR_SDHCH_DAT1_MASK (0xF3)
5369 +#define MCF_GPIO_PAR_SDHCH_DAT1_DAT1 (0x0C)
5370 +#define MCF_GPIO_PAR_SDHCH_DAT1_PWM_A2 (0x08)
5371 +#define MCF_GPIO_PAR_SDHCH_DAT1_DSPI1_PCS1 (0x04)
5372 +#define MCF_GPIO_PAR_SDHCH_DAT1_GPIO (0x00)
5373 +#define MCF_GPIO_PAR_SDHCH_DAT0(x) ((x)&0x03)
5374 +#define MCF_GPIO_PAR_SDHCH_DAT0_MASK (0xFC)
5375 +#define MCF_GPIO_PAR_SDHCH_DAT0_DAT0 (0x03)
5376 +#define MCF_GPIO_PAR_SDHCH_DAT0_PWM_B2 (0x02)
5377 +#define MCF_GPIO_PAR_SDHCH_DAT0_DSPI1_SOUT (0x01)
5378 +#define MCF_GPIO_PAR_SDHCH_DAT0_GPIO (0x00)
5379 +
5380 +#define MCF_GPIO_PAR_SDHCL_CMD(x) (((x)&0x03)<<2)
5381 +#define MCF_GPIO_PAR_SDHCL_CMD_MASK (0xF3)
5382 +#define MCF_GPIO_PAR_SDHCL_CMD_CMD (0x0C)
5383 +#define MCF_GPIO_PAR_SDHCL_CMD_PWM_A0 (0x08)
5384 +#define MCF_GPIO_PAR_SDHCL_CMD_DSPI1_SIN (0x04)
5385 +#define MCF_GPIO_PAR_SDHCL_CMD_GPIO (0x00)
5386 +#define MCF_GPIO_PAR_SDHCL_CLK(x) ((x)&0x03)
5387 +#define MCF_GPIO_PAR_SDHCL_CLK_MASK (0xFC)
5388 +#define MCF_GPIO_PAR_SDHCL_CLK_CLK (0x03)
5389 +#define MCF_GPIO_PAR_SDHCL_CLK_PWM_B0 (0x02)
5390 +#define MCF_GPIO_PAR_SDHCL_CLK_DSPI1_SCK (0x01)
5391 +#define MCF_GPIO_PAR_SDHCL_CLK_GPIO (0x00)
5392 +
5393 +#define MCF_GPIO_PAR_SIMP0H_DAT(x) (((x)&0x03)<<6)
5394 +#define MCF_GPIO_PAR_SIMP0H_DAT_MASK (0x3F)
5395 +#define MCF_GPIO_PAR_SIMP0H_DAT_DAT (0xC0)
5396 +#define MCF_GPIO_PAR_SIMP0H_DAT_PWM_FAULT2 (0x80)
5397 +#define MCF_GPIO_PAR_SIMP0H_DAT_SDHC_DAT7 (0x40)
5398 +#define MCF_GPIO_PAR_SIMP0H_DAT_GPIO (0x00)
5399 +#define MCF_GPIO_PAR_SIMP0H_VEN(x) (((x)&0x03)<<4)
5400 +#define MCF_GPIO_PAR_SIMP0H_VEN_MASK (0xCF)
5401 +#define MCF_GPIO_PAR_SIMP0H_VEN_VEN (0x30)
5402 +#define MCF_GPIO_PAR_SIMP0H_VEN_PWM_FAULT0 (0x20)
5403 +#define MCF_GPIO_PAR_SIMP0H_VEN_GPIO (0x00)
5404 +#define MCF_GPIO_PAR_SIMP0H_RST(x) (((x)&0x03)<<2)
5405 +#define MCF_GPIO_PAR_SIMP0H_RST_MASK (0xF3)
5406 +#define MCF_GPIO_PAR_SIMP0H_RST_RST (0x0C)
5407 +#define MCF_GPIO_PAR_SIMP0H_RST_PWM_FORCE (0x08)
5408 +#define MCF_GPIO_PAR_SIMP0H_RST_SDHC_DAT6 (0x04)
5409 +#define MCF_GPIO_PAR_SIMP0H_RST_GPIO (0x00)
5410 +#define MCF_GPIO_PAR_SIMP0H_PD(x) ((x)&0x03)
5411 +#define MCF_GPIO_PAR_SIMP0H_PD_MASK (0xFC)
5412 +#define MCF_GPIO_PAR_SIMP0H_PD_PD (0x03)
5413 +#define MCF_GPIO_PAR_SIMP0H_PD_PWM_SYNC (0x02)
5414 +#define MCF_GPIO_PAR_SIMP0H_PD_SDHC_DAT5 (0x01)
5415 +#define MCF_GPIO_PAR_SIMP0H_PD_GPIO (0x00)
5416 +
5417 +#define MCF_GPIO_PAR_SIMP0L_CLK(x) ((x)&0x03)
5418 +#define MCF_GPIO_PAR_SIMP0L_CLK_MASK (0xFC)
5419 +#define MCF_GPIO_PAR_SIMP0L_CLK_CLK (0x03)
5420 +#define MCF_GPIO_PAR_SIMP0L_CLK_PWM_FAULT1 (0x02)
5421 +#define MCF_GPIO_PAR_SIMP0L_CLK_SDHC_DAT4 (0x01)
5422 +#define MCF_GPIO_PAR_SIMP0L_CLK_GPIO (0x00)
5423 +
5424 +#define MCF_GPIO_PAR_SSI0H_RXD(x) (((x)&0x03)<<6)
5425 +#define MCF_GPIO_PAR_SSI0H_RXD_MASK (0x3F)
5426 +#define MCF_GPIO_PAR_SSI0H_RXD_RXD (0xC0)
5427 +#define MCF_GPIO_PAR_SSI0H_RXD_I2C2SDA (0x80)
5428 +#define MCF_GPIO_PAR_SSI0H_RXD_SIM1_VEN (0x40)
5429 +#define MCF_GPIO_PAR_SSI0H_RXD_GPIO (0x00)
5430 +#define MCF_GPIO_PAR_SSI0H_TXD(x) (((x)&0x03)<<4)
5431 +#define MCF_GPIO_PAR_SSI0H_TXD_MASK (0xCF)
5432 +#define MCF_GPIO_PAR_SSI0H_TXD_TXD (0x30)
5433 +#define MCF_GPIO_PAR_SSI0H_TXD_I2C2SCL (0x20)
5434 +#define MCF_GPIO_PAR_SSI0H_TXD_SIM1_DAT (0x10)
5435 +#define MCF_GPIO_PAR_SSI0H_TXD_GPIO (0x00)
5436 +#define MCF_GPIO_PAR_SSI0H_FS(x) (((x)&0x03)<<2)
5437 +#define MCF_GPIO_PAR_SSI0H_FS_MASK (0xF3)
5438 +#define MCF_GPIO_PAR_SSI0H_FS_FS (0x0C)
5439 +#define MCF_GPIO_PAR_SSI0H_FS_U7TXD (0x08)
5440 +#define MCF_GPIO_PAR_SSI0H_FS_SIM1_RST (0x04)
5441 +#define MCF_GPIO_PAR_SSI0H_FS_GPIO (0x00)
5442 +#define MCF_GPIO_PAR_SSI0H_MCLK(x) ((x)&0x03)
5443 +#define MCF_GPIO_PAR_SSI0H_MCLK_MASK (0xFC)
5444 +#define MCF_GPIO_PAR_SSI0H_MCLK_MCLK (0x03)
5445 +#define MCF_GPIO_PAR_SSI0H_MCLK_SSI_CLKIN (0x02)
5446 +#define MCF_GPIO_PAR_SSI0H_MCLK_SIM1_CLK (0x01)
5447 +#define MCF_GPIO_PAR_SSI0H_MCLK_GPIO (0x00)
5448 +
5449 +#define MCF_GPIO_PAR_SSI0L_BCLK(x) ((x)&0x03)
5450 +#define MCF_GPIO_PAR_SSI0L_BCLK_MASK (0xFC)
5451 +#define MCF_GPIO_PAR_SSI0L_BCLK_BCLK (0x03)
5452 +#define MCF_GPIO_PAR_SSI0L_BCLK_U7RXD (0x02)
5453 +#define MCF_GPIO_PAR_SSI0L_BCLK_SIM1_PD (0x01)
5454 +#define MCF_GPIO_PAR_SSI0L_BCLK_GPIO (0x00)
5455 +
5456 +#define MCF_GPIO_PAR_DEBUGH1_DAT3 (0x40)
5457 +#define MCF_GPIO_PAR_DEBUGH1_DAT2 (0x10)
5458 +#define MCF_GPIO_PAR_DEBUGH1_DAT1 (0x04)
5459 +#define MCF_GPIO_PAR_DEBUGH1_DAT0 (0x01)
5460 +
5461 +#define MCF_GPIO_PAR_DEBUGH0_PST3 (0x40)
5462 +#define MCF_GPIO_PAR_DEBUGH0_PST2 (0x10)
5463 +#define MCF_GPIO_PAR_DEBUGH0_PST1 (0x04)
5464 +#define MCF_GPIO_PAR_DEBUGH0_PST0 (0x01)
5465 +
5466 +#define MCF_GPIO_PAR_DEBUGL_ALLPST (0x01)
5467 +
5468 +#define MCF_GPIO_PAR_FEC_FEC(x) ((x)&0x0F)
5469 +#define MCF_GPIO_PAR_FEC_FEC_MASK (0xF0)
5470 +#define MCF_GPIO_PAR_FEC_FEC_GPIO (0x0D)
5471 +#define MCF_GPIO_PAR_FEC_FEC_RMII1 (0x0C)
5472 +#define MCF_GPIO_PAR_FEC_FEC_RMII1FUL (0x0B)
5473 +#define MCF_GPIO_PAR_FEC_FEC_RMII_ULPI (0x0A)
5474 +#define MCF_GPIO_PAR_FEC_FEC_RMII0 (0x09)
5475 +#define MCF_GPIO_PAR_FEC_FEC_RMII0FUL_ULPI (0x08)
5476 +#define MCF_GPIO_PAR_FEC_FEC_RMII0FUL (0x07)
5477 +#define MCF_GPIO_PAR_FEC_FEC_RMII0_1FUL (0x06)
5478 +#define MCF_GPIO_PAR_FEC_FEC_RMII0FUL_1 (0x05) /* 0:Full 1: */
5479 +/* Both 0&1: MDC, MDIO, COL & TXER - GPIO */
5480 +#define MCF_GPIO_PAR_FEC_FEC_RMII0_1 (0x04)
5481 +#define MCF_GPIO_PAR_FEC_FEC_RMII0FUL_1FUL (0x03)
5482 +#define MCF_GPIO_PAR_FEC_FEC_MII (0x01) /* MDC & MDIO - GPIO */
5483 +#define MCF_GPIO_PAR_FEC_FEC_MIIFUL (0x00)
5484 +
5485 +/********************************************************************/
5486 +
5487 +#endif /* __MCF5441X_GPIO_H__ */
5488 --- /dev/null
5489 +++ b/arch/m68k/include/asm/mcf5441x_intc.h
5490 @@ -0,0 +1,727 @@
5491 +/*
5492 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5493 + *
5494 + * This program is free software; you can redistribute it and/or modify it
5495 + * under the terms of the GNU General Public License as published by the
5496 + * Free Software Foundation; either version 2 of the License, or (at your
5497 + * option) any later version.
5498 + */
5499 +
5500 +#ifndef __MCF5441X_INTC_H__
5501 +#define __MCF5441X_INTC_H__
5502 +
5503 +/*********************************************************************
5504 +*
5505 +* Interrupt Controller (INTC)
5506 +*
5507 +*********************************************************************/
5508 +
5509 +/* Register read/write macros */
5510 +#define MCF_INTC0_IPRH MCF_REG32(0xFC048000)
5511 +#define MCF_INTC0_IPRL MCF_REG32(0xFC048004)
5512 +#define MCF_INTC0_IMRH MCF_REG32(0xFC048008)
5513 +#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C)
5514 +#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010)
5515 +#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014)
5516 +#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A)
5517 +#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C)
5518 +#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D)
5519 +#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E)
5520 +#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F)
5521 +#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041)
5522 +#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042)
5523 +#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043)
5524 +#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044)
5525 +#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045)
5526 +#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046)
5527 +#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047)
5528 +#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048)
5529 +#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049)
5530 +#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A)
5531 +#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B)
5532 +#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C)
5533 +#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D)
5534 +#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E)
5535 +#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F)
5536 +#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050)
5537 +#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051)
5538 +#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052)
5539 +#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053)
5540 +#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054)
5541 +#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055)
5542 +#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056)
5543 +#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057)
5544 +#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058)
5545 +#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059)
5546 +#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A)
5547 +#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B)
5548 +#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C)
5549 +#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D)
5550 +#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E)
5551 +#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F)
5552 +#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060)
5553 +#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061)
5554 +#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062)
5555 +#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063)
5556 +#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064)
5557 +#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065)
5558 +#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066)
5559 +#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067)
5560 +#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068)
5561 +#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069)
5562 +#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A)
5563 +#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B)
5564 +#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C)
5565 +#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D)
5566 +#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E)
5567 +#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F)
5568 +#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070)
5569 +#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071)
5570 +#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072)
5571 +#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073)
5572 +#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074)
5573 +#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075)
5574 +#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076)
5575 +#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077)
5576 +#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078)
5577 +#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079)
5578 +#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A)
5579 +#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B)
5580 +#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C)
5581 +#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D)
5582 +#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E)
5583 +#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F)
5584 +#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0)
5585 +#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4)
5586 +#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8)
5587 +#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC)
5588 +#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0)
5589 +#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4)
5590 +#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8)
5591 +#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC)
5592 +#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000)
5593 +#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004)
5594 +#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008)
5595 +#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C)
5596 +#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010)
5597 +#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014)
5598 +#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A)
5599 +#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C)
5600 +#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D)
5601 +#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E)
5602 +#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F)
5603 +#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041)
5604 +#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042)
5605 +#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043)
5606 +#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044)
5607 +#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045)
5608 +#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046)
5609 +#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047)
5610 +#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048)
5611 +#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049)
5612 +#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A)
5613 +#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B)
5614 +#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C)
5615 +#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D)
5616 +#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E)
5617 +#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F)
5618 +#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050)
5619 +#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051)
5620 +#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052)
5621 +#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053)
5622 +#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054)
5623 +#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055)
5624 +#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056)
5625 +#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057)
5626 +#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058)
5627 +#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059)
5628 +#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A)
5629 +#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B)
5630 +#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C)
5631 +#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D)
5632 +#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E)
5633 +#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F)
5634 +#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060)
5635 +#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061)
5636 +#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062)
5637 +#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063)
5638 +#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064)
5639 +#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065)
5640 +#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066)
5641 +#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067)
5642 +#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068)
5643 +#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069)
5644 +#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A)
5645 +#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B)
5646 +#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C)
5647 +#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D)
5648 +#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E)
5649 +#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F)
5650 +#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070)
5651 +#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071)
5652 +#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072)
5653 +#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073)
5654 +#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074)
5655 +#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075)
5656 +#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076)
5657 +#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077)
5658 +#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078)
5659 +#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079)
5660 +#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A)
5661 +#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B)
5662 +#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C)
5663 +#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D)
5664 +#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E)
5665 +#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F)
5666 +#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0)
5667 +#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4)
5668 +#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8)
5669 +#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC)
5670 +#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0)
5671 +#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4)
5672 +#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8
5673 +#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC)
5674 +
5675 +#define MCF_INTC2_SIMR MCF_REG08(0xFC05001C)
5676 +#define MCF_INTC2_CIMR MCF_REG08(0xFC05001D)
5677 +#define MCF_INTC2_ICR31 MCF_REG08(0xFC05005F)
5678 +
5679 +/* Parameterized register read/write macros for multiple registers */
5680 +#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048041+((x-1)*0x001))
5681 +#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x-1)*0x004))
5682 +#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C041+((x-1)*0x001))
5683 +#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x-1)*0x004))
5684 +#define MCF_INTC2_ICR(x) MCF_REG08(0xFC050041+((x-1)*0x001))
5685 +
5686 +/* Parameterized register read/write macros for multiple modules */
5687 +#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000))
5688 +#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000))
5689 +#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000))
5690 +#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000))
5691 +#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000))
5692 +#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000))
5693 +#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000))
5694 +#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000))
5695 +#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000))
5696 +#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000))
5697 +#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000))
5698 +#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000))
5699 +#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000))
5700 +#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000))
5701 +#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000))
5702 +#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000))
5703 +#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000))
5704 +#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000))
5705 +#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000))
5706 +#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000))
5707 +#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000))
5708 +#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000))
5709 +#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000))
5710 +#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000))
5711 +#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000))
5712 +#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000))
5713 +#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000))
5714 +#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000))
5715 +#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000))
5716 +#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000))
5717 +#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000))
5718 +#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000))
5719 +#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000))
5720 +#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000))
5721 +#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000))
5722 +#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000))
5723 +#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000))
5724 +#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000))
5725 +#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000))
5726 +#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000))
5727 +#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000))
5728 +#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000))
5729 +#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000))
5730 +#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000))
5731 +#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000))
5732 +#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000))
5733 +#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000))
5734 +#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000))
5735 +#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000))
5736 +#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000))
5737 +#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000))
5738 +#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000))
5739 +#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000))
5740 +#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000))
5741 +#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000))
5742 +#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000))
5743 +#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000))
5744 +#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000))
5745 +#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000))
5746 +#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000))
5747 +#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000))
5748 +#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000))
5749 +#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000))
5750 +#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000))
5751 +#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000))
5752 +#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000))
5753 +#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000))
5754 +#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000))
5755 +#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000))
5756 +#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000))
5757 +#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000))
5758 +#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000))
5759 +#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000))
5760 +#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000))
5761 +#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000))
5762 +#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000))
5763 +#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000))
5764 +#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000))
5765 +#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000))
5766 +#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000))
5767 +#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000))
5768 +#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000))
5769 +
5770 +/* Bit definitions and macros for IPRH */
5771 +#define MCF_INTC_IPRH_INT32 (0x00000001)
5772 +#define MCF_INTC_IPRH_INT33 (0x00000002)
5773 +#define MCF_INTC_IPRH_INT34 (0x00000004)
5774 +#define MCF_INTC_IPRH_INT35 (0x00000008)
5775 +#define MCF_INTC_IPRH_INT36 (0x00000010)
5776 +#define MCF_INTC_IPRH_INT37 (0x00000020)
5777 +#define MCF_INTC_IPRH_INT38 (0x00000040)
5778 +#define MCF_INTC_IPRH_INT39 (0x00000080)
5779 +#define MCF_INTC_IPRH_INT40 (0x00000100)
5780 +#define MCF_INTC_IPRH_INT41 (0x00000200)
5781 +#define MCF_INTC_IPRH_INT42 (0x00000400)
5782 +#define MCF_INTC_IPRH_INT43 (0x00000800)
5783 +#define MCF_INTC_IPRH_INT44 (0x00001000)
5784 +#define MCF_INTC_IPRH_INT45 (0x00002000)
5785 +#define MCF_INTC_IPRH_INT46 (0x00004000)
5786 +#define MCF_INTC_IPRH_INT47 (0x00008000)
5787 +#define MCF_INTC_IPRH_INT48 (0x00010000)
5788 +#define MCF_INTC_IPRH_INT49 (0x00020000)
5789 +#define MCF_INTC_IPRH_INT50 (0x00040000)
5790 +#define MCF_INTC_IPRH_INT51 (0x00080000)
5791 +#define MCF_INTC_IPRH_INT52 (0x00100000)
5792 +#define MCF_INTC_IPRH_INT53 (0x00200000)
5793 +#define MCF_INTC_IPRH_INT54 (0x00400000)
5794 +#define MCF_INTC_IPRH_INT55 (0x00800000)
5795 +#define MCF_INTC_IPRH_INT56 (0x01000000)
5796 +#define MCF_INTC_IPRH_INT57 (0x02000000)
5797 +#define MCF_INTC_IPRH_INT58 (0x04000000)
5798 +#define MCF_INTC_IPRH_INT59 (0x08000000)
5799 +#define MCF_INTC_IPRH_INT60 (0x10000000)
5800 +#define MCF_INTC_IPRH_INT61 (0x20000000)
5801 +#define MCF_INTC_IPRH_INT62 (0x40000000)
5802 +#define MCF_INTC_IPRH_INT63 (0x80000000)
5803 +
5804 +/* Bit definitions and macros for IPRL */
5805 +#define MCF_INTC_IPRL_INT0 (0x00000001)
5806 +#define MCF_INTC_IPRL_INT1 (0x00000002)
5807 +#define MCF_INTC_IPRL_INT2 (0x00000004)
5808 +#define MCF_INTC_IPRL_INT3 (0x00000008)
5809 +#define MCF_INTC_IPRL_INT4 (0x00000010)
5810 +#define MCF_INTC_IPRL_INT5 (0x00000020)
5811 +#define MCF_INTC_IPRL_INT6 (0x00000040)
5812 +#define MCF_INTC_IPRL_INT7 (0x00000080)
5813 +#define MCF_INTC_IPRL_INT8 (0x00000100)
5814 +#define MCF_INTC_IPRL_INT9 (0x00000200)
5815 +#define MCF_INTC_IPRL_INT10 (0x00000400)
5816 +#define MCF_INTC_IPRL_INT11 (0x00000800)
5817 +#define MCF_INTC_IPRL_INT12 (0x00001000)
5818 +#define MCF_INTC_IPRL_INT13 (0x00002000)
5819 +#define MCF_INTC_IPRL_INT14 (0x00004000)
5820 +#define MCF_INTC_IPRL_INT15 (0x00008000)
5821 +#define MCF_INTC_IPRL_INT16 (0x00010000)
5822 +#define MCF_INTC_IPRL_INT17 (0x00020000)
5823 +#define MCF_INTC_IPRL_INT18 (0x00040000)
5824 +#define MCF_INTC_IPRL_INT19 (0x00080000)
5825 +#define MCF_INTC_IPRL_INT20 (0x00100000)
5826 +#define MCF_INTC_IPRL_INT21 (0x00200000)
5827 +#define MCF_INTC_IPRL_INT22 (0x00400000)
5828 +#define MCF_INTC_IPRL_INT23 (0x00800000)
5829 +#define MCF_INTC_IPRL_INT24 (0x01000000)
5830 +#define MCF_INTC_IPRL_INT25 (0x02000000)
5831 +#define MCF_INTC_IPRL_INT26 (0x04000000)
5832 +#define MCF_INTC_IPRL_INT27 (0x08000000)
5833 +#define MCF_INTC_IPRL_INT28 (0x10000000)
5834 +#define MCF_INTC_IPRL_INT29 (0x20000000)
5835 +#define MCF_INTC_IPRL_INT30 (0x40000000)
5836 +#define MCF_INTC_IPRL_INT31 (0x80000000)
5837 +
5838 +/* Bit definitions and macros for IMRH */
5839 +#define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
5840 +#define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
5841 +#define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
5842 +#define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
5843 +#define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
5844 +#define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
5845 +#define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
5846 +#define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
5847 +#define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
5848 +#define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
5849 +#define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
5850 +#define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
5851 +#define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
5852 +#define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
5853 +#define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
5854 +#define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
5855 +#define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
5856 +#define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
5857 +#define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
5858 +#define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
5859 +#define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
5860 +#define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
5861 +#define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
5862 +#define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
5863 +#define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
5864 +#define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
5865 +#define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
5866 +#define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
5867 +#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
5868 +#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
5869 +#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
5870 +#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
5871 +
5872 +/* Bit definitions and macros for IMRL */
5873 +#define MCF_INTC_IMRL_INT_MASK0 (0x00000001)
5874 +#define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
5875 +#define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
5876 +#define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
5877 +#define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
5878 +#define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
5879 +#define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
5880 +#define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
5881 +#define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
5882 +#define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
5883 +#define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
5884 +#define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
5885 +#define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
5886 +#define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
5887 +#define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
5888 +#define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
5889 +#define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
5890 +#define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
5891 +#define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
5892 +#define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
5893 +#define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
5894 +#define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
5895 +#define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
5896 +#define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
5897 +#define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
5898 +#define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
5899 +#define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
5900 +#define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
5901 +#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
5902 +#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
5903 +#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
5904 +#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
5905 +
5906 +/* Bit definitions and macros for INTFRCH */
5907 +#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
5908 +#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
5909 +#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
5910 +#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
5911 +#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
5912 +#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
5913 +#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
5914 +#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
5915 +#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
5916 +#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
5917 +#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
5918 +#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
5919 +#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000)
5920 +#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000)
5921 +#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000)
5922 +#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000)
5923 +#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000)
5924 +#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000)
5925 +#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000)
5926 +#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000)
5927 +#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000)
5928 +#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000)
5929 +#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000)
5930 +#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000)
5931 +#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000)
5932 +#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000)
5933 +#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000)
5934 +#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000)
5935 +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
5936 +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
5937 +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
5938 +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
5939 +
5940 +/* Bit definitions and macros for INTFRCL */
5941 +#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001)
5942 +#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002)
5943 +#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004)
5944 +#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008)
5945 +#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010)
5946 +#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020)
5947 +#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040)
5948 +#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080)
5949 +#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100)
5950 +#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200)
5951 +#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400)
5952 +#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800)
5953 +#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000)
5954 +#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000)
5955 +#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000)
5956 +#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000)
5957 +#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000)
5958 +#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000)
5959 +#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000)
5960 +#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000)
5961 +#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000)
5962 +#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000)
5963 +#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000)
5964 +#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000)
5965 +#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000)
5966 +#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000)
5967 +#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000)
5968 +#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000)
5969 +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
5970 +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
5971 +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
5972 +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
5973 +
5974 +/* Bit definitions and macros for ICONFIG */
5975 +#define MCF_INTC_ICONFIG_EMASK (0x0020)
5976 +#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200)
5977 +#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400)
5978 +#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800)
5979 +#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000)
5980 +#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000)
5981 +#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000)
5982 +#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000)
5983 +
5984 +/* Bit definitions and macros for SIMR */
5985 +#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F))
5986 +
5987 +/* Bit definitions and macros for CIMR */
5988 +#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F))
5989 +
5990 +/* Bit definitions and macros for CLMASK */
5991 +#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F))
5992 +
5993 +/* Bit definitions and macros for SLMASK */
5994 +#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F))
5995 +
5996 +/* Bit definitions and macros for ICR group */
5997 +#define MCF_INTC_ICR_IL(x) (((x)&0x07))
5998 +
5999 +/* Bit definitions and macros for ICR1 */
6000 +#define MCF_INTC_ICR1_IL(x) (((x)&0x07))
6001 +
6002 +/* Bit definitions and macros for ICR2 */
6003 +#define MCF_INTC_ICR2_IL(x) (((x)&0x07))
6004 +
6005 +/* Bit definitions and macros for ICR3 */
6006 +#define MCF_INTC_ICR3_IL(x) (((x)&0x07))
6007 +
6008 +/* Bit definitions and macros for ICR4 */
6009 +#define MCF_INTC_ICR4_IL(x) (((x)&0x07))
6010 +
6011 +/* Bit definitions and macros for ICR5 */
6012 +#define MCF_INTC_ICR5_IL(x) (((x)&0x07))
6013 +
6014 +/* Bit definitions and macros for ICR6 */
6015 +#define MCF_INTC_ICR6_IL(x) (((x)&0x07))
6016 +
6017 +/* Bit definitions and macros for ICR7 */
6018 +#define MCF_INTC_ICR7_IL(x) (((x)&0x07))
6019 +
6020 +/* Bit definitions and macros for ICR8 */
6021 +#define MCF_INTC_ICR8_IL(x) (((x)&0x07))
6022 +
6023 +/* Bit definitions and macros for ICR9 */
6024 +#define MCF_INTC_ICR9_IL(x) (((x)&0x07))
6025 +
6026 +/* Bit definitions and macros for ICR10 */
6027 +#define MCF_INTC_ICR10_IL(x) (((x)&0x07))
6028 +
6029 +/* Bit definitions and macros for ICR11 */
6030 +#define MCF_INTC_ICR11_IL(x) (((x)&0x07))
6031 +
6032 +/* Bit definitions and macros for ICR12 */
6033 +#define MCF_INTC_ICR12_IL(x) (((x)&0x07))
6034 +
6035 +/* Bit definitions and macros for ICR13 */
6036 +#define MCF_INTC_ICR13_IL(x) (((x)&0x07))
6037 +
6038 +/* Bit definitions and macros for ICR14 */
6039 +#define MCF_INTC_ICR14_IL(x) (((x)&0x07))
6040 +
6041 +/* Bit definitions and macros for ICR15 */
6042 +#define MCF_INTC_ICR15_IL(x) (((x)&0x07))
6043 +
6044 +/* Bit definitions and macros for ICR16 */
6045 +#define MCF_INTC_ICR16_IL(x) (((x)&0x07))
6046 +
6047 +/* Bit definitions and macros for ICR17 */
6048 +#define MCF_INTC_ICR17_IL(x) (((x)&0x07))
6049 +
6050 +/* Bit definitions and macros for ICR18 */
6051 +#define MCF_INTC_ICR18_IL(x) (((x)&0x07))
6052 +
6053 +/* Bit definitions and macros for ICR19 */
6054 +#define MCF_INTC_ICR19_IL(x) (((x)&0x07))
6055 +
6056 +/* Bit definitions and macros for ICR20 */
6057 +#define MCF_INTC_ICR20_IL(x) (((x)&0x07))
6058 +
6059 +/* Bit definitions and macros for ICR21 */
6060 +#define MCF_INTC_ICR21_IL(x) (((x)&0x07))
6061 +
6062 +/* Bit definitions and macros for ICR22 */
6063 +#define MCF_INTC_ICR22_IL(x) (((x)&0x07))
6064 +
6065 +/* Bit definitions and macros for ICR23 */
6066 +#define MCF_INTC_ICR23_IL(x) (((x)&0x07))
6067 +
6068 +/* Bit definitions and macros for ICR24 */
6069 +#define MCF_INTC_ICR24_IL(x) (((x)&0x07))
6070 +
6071 +/* Bit definitions and macros for ICR25 */
6072 +#define MCF_INTC_ICR25_IL(x) (((x)&0x07))
6073 +
6074 +/* Bit definitions and macros for ICR26 */
6075 +#define MCF_INTC_ICR26_IL(x) (((x)&0x07))
6076 +
6077 +/* Bit definitions and macros for ICR27 */
6078 +#define MCF_INTC_ICR27_IL(x) (((x)&0x07))
6079 +
6080 +/* Bit definitions and macros for ICR28 */
6081 +#define MCF_INTC_ICR28_IL(x) (((x)&0x07))
6082 +
6083 +/* Bit definitions and macros for ICR29 */
6084 +#define MCF_INTC_ICR29_IL(x) (((x)&0x07))
6085 +
6086 +/* Bit definitions and macros for ICR30 */
6087 +#define MCF_INTC_ICR30_IL(x) (((x)&0x07))
6088 +
6089 +/* Bit definitions and macros for ICR31 */
6090 +#define MCF_INTC_ICR31_IL(x) (((x)&0x07))
6091 +
6092 +/* Bit definitions and macros for ICR32 */
6093 +#define MCF_INTC_ICR32_IL(x) (((x)&0x07))
6094 +
6095 +/* Bit definitions and macros for ICR33 */
6096 +#define MCF_INTC_ICR33_IL(x) (((x)&0x07))
6097 +
6098 +/* Bit definitions and macros for ICR34 */
6099 +#define MCF_INTC_ICR34_IL(x) (((x)&0x07))
6100 +
6101 +/* Bit definitions and macros for ICR35 */
6102 +#define MCF_INTC_ICR35_IL(x) (((x)&0x07))
6103 +
6104 +/* Bit definitions and macros for ICR36 */
6105 +#define MCF_INTC_ICR36_IL(x) (((x)&0x07))
6106 +
6107 +/* Bit definitions and macros for ICR37 */
6108 +#define MCF_INTC_ICR37_IL(x) (((x)&0x07))
6109 +
6110 +/* Bit definitions and macros for ICR38 */
6111 +#define MCF_INTC_ICR38_IL(x) (((x)&0x07))
6112 +
6113 +/* Bit definitions and macros for ICR39 */
6114 +#define MCF_INTC_ICR39_IL(x) (((x)&0x07))
6115 +
6116 +/* Bit definitions and macros for ICR40 */
6117 +#define MCF_INTC_ICR40_IL(x) (((x)&0x07))
6118 +
6119 +/* Bit definitions and macros for ICR41 */
6120 +#define MCF_INTC_ICR41_IL(x) (((x)&0x07))
6121 +
6122 +/* Bit definitions and macros for ICR42 */
6123 +#define MCF_INTC_ICR42_IL(x) (((x)&0x07))
6124 +
6125 +/* Bit definitions and macros for ICR43 */
6126 +#define MCF_INTC_ICR43_IL(x) (((x)&0x07))
6127 +
6128 +/* Bit definitions and macros for ICR44 */
6129 +#define MCF_INTC_ICR44_IL(x) (((x)&0x07))
6130 +
6131 +/* Bit definitions and macros for ICR45 */
6132 +#define MCF_INTC_ICR45_IL(x) (((x)&0x07))
6133 +
6134 +/* Bit definitions and macros for ICR46 */
6135 +#define MCF_INTC_ICR46_IL(x) (((x)&0x07))
6136 +
6137 +/* Bit definitions and macros for ICR47 */
6138 +#define MCF_INTC_ICR47_IL(x) (((x)&0x07))
6139 +
6140 +/* Bit definitions and macros for ICR48 */
6141 +#define MCF_INTC_ICR48_IL(x) (((x)&0x07))
6142 +
6143 +/* Bit definitions and macros for ICR49 */
6144 +#define MCF_INTC_ICR49_IL(x) (((x)&0x07))
6145 +
6146 +/* Bit definitions and macros for ICR50 */
6147 +#define MCF_INTC_ICR50_IL(x) (((x)&0x07))
6148 +
6149 +/* Bit definitions and macros for ICR51 */
6150 +#define MCF_INTC_ICR51_IL(x) (((x)&0x07))
6151 +
6152 +/* Bit definitions and macros for ICR52 */
6153 +#define MCF_INTC_ICR52_IL(x) (((x)&0x07))
6154 +
6155 +/* Bit definitions and macros for ICR53 */
6156 +#define MCF_INTC_ICR53_IL(x) (((x)&0x07))
6157 +
6158 +/* Bit definitions and macros for ICR54 */
6159 +#define MCF_INTC_ICR54_IL(x) (((x)&0x07))
6160 +
6161 +/* Bit definitions and macros for ICR55 */
6162 +#define MCF_INTC_ICR55_IL(x) (((x)&0x07))
6163 +
6164 +/* Bit definitions and macros for ICR56 */
6165 +#define MCF_INTC_ICR56_IL(x) (((x)&0x07))
6166 +
6167 +/* Bit definitions and macros for ICR57 */
6168 +#define MCF_INTC_ICR57_IL(x) (((x)&0x07))
6169 +
6170 +/* Bit definitions and macros for ICR58 */
6171 +#define MCF_INTC_ICR58_IL(x) (((x)&0x07))
6172 +
6173 +/* Bit definitions and macros for ICR59 */
6174 +#define MCF_INTC_ICR59_IL(x) (((x)&0x07))
6175 +
6176 +/* Bit definitions and macros for ICR60 */
6177 +#define MCF_INTC_ICR60_IL(x) (((x)&0x07))
6178 +
6179 +/* Bit definitions and macros for ICR61 */
6180 +#define MCF_INTC_ICR61_IL(x) (((x)&0x07))
6181 +
6182 +/* Bit definitions and macros for ICR62 */
6183 +#define MCF_INTC_ICR62_IL(x) (((x)&0x07))
6184 +
6185 +/* Bit definitions and macros for ICR63 */
6186 +#define MCF_INTC_ICR63_IL(x) (((x)&0x07))
6187 +
6188 +/* Bit definitions and macros for SWIACK */
6189 +#define MCF_INTC_SWIACK_VECTOR(x) (x)
6190 +
6191 +/* Bit definitions and macros for LIACK group */
6192 +#define MCF_INTC_LIACK_VECTOR(x) (x)
6193 +
6194 +/* Bit definitions and macros for L1IACK */
6195 +#define MCF_INTC_L1IACK_VECTOR(x) (x)
6196 +
6197 +/* Bit definitions and macros for L2IACK */
6198 +#define MCF_INTC_L2IACK_VECTOR(x) (x)
6199 +
6200 +/* Bit definitions and macros for L3IACK */
6201 +#define MCF_INTC_L3IACK_VECTOR(x) (x)
6202 +
6203 +/* Bit definitions and macros for L4IACK */
6204 +#define MCF_INTC_L4IACK_VECTOR(x) (x)
6205 +
6206 +/* Bit definitions and macros for L5IACK */
6207 +#define MCF_INTC_L5IACK_VECTOR(x) (x)
6208 +
6209 +/* Bit definitions and macros for L6IACK */
6210 +#define MCF_INTC_L6IACK_VECTOR(x) (x)
6211 +
6212 +/* Bit definitions and macros for L7IACK */
6213 +#define MCF_INTC_L7IACK_VECTOR(x) (x)
6214 +
6215 +/********************************************************************/
6216 +
6217 +#endif /* __MCF5441X_INTC_H__ */
6218 --- /dev/null
6219 +++ b/arch/m68k/include/asm/mcf5441x_pm.h
6220 @@ -0,0 +1,33 @@
6221 +/*
6222 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6223 + *
6224 + * This program is free software; you can redistribute it and/or modify it
6225 + * under the terms of the GNU General Public License as published by the
6226 + * Free Software Foundation; either version 2 of the License, or (at your
6227 + * option) any later version.
6228 + */
6229 +
6230 +#ifndef __MCF5441X_PM_H__
6231 +#define __MCF5441X_PM_H__
6232 +
6233 +/*********************************************************************
6234 +*
6235 +* Power Management Module Register Definition
6236 +*
6237 +*********************************************************************/
6238 +
6239 +#define MCF_PM_WCR MCF_REG08(0xFC040013)
6240 +#define MCF_PM_PPMSR0 MCF_REG08(0xFC04002C)
6241 +#define MCF_PM_PPMCR0 MCF_REG08(0xFC04002D)
6242 +#define MCF_PM_PPMSR1 MCF_REG08(0xFC04002E)
6243 +#define MCF_PM_PPMCR1 MCF_REG08(0xFC04002F)
6244 +#define MCF_PM_PPMHR0 MCF_REG32(0xFC040030)
6245 +#define MCF_PM_PPMLR0 MCF_REG32(0xFC040034)
6246 +#define MCF_PM_PPMHR1 MCF_REG32(0xFC040038)
6247 +#define MCF_PM_PPMLR1 MCF_REG32(0xFC04003C)
6248 +#define MCF_PM_LPCR MCF_REG08(0xEC090007)
6249 +#define MCF_PM_MISCCR MCF_REG16(0xEC09000E)
6250 +#define MCF_PM_CDHR MCF_REG16(0xEC090010)
6251 +#define MCF_PM_CDLR MCF_REG16(0xEC090012)
6252 +
6253 +#endif
6254 --- /dev/null
6255 +++ b/arch/m68k/include/asm/mcf5441x_rtc.h
6256 @@ -0,0 +1,127 @@
6257 +/*
6258 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6259 + *
6260 + * Lanttor.Guo@freescale.com
6261 + *
6262 + * Description:
6263 + * This file is the register definition of m5441x RTC module
6264 + *
6265 + * This is free software; you can redistribute it and/or modify
6266 + * it under the terms of the GNU General Public License as published by
6267 + * the Free Software Foundation; either version 2 of the License, or
6268 + * (at your option) any later version.
6269 + *
6270 + */
6271 +
6272 +#ifndef __MCF5441X_RTC_H__
6273 +#define __MCF5441X_RTC_H__
6274 +
6275 +/*********************************************************************
6276 +*
6277 +* Real-time Clock (RTC)
6278 +*
6279 +*********************************************************************/
6280 +#ifndef MCFINT_VECBASE
6281 +#define MCFINT_VECBASE 64
6282 +#endif
6283 +
6284 +#define MCFSIM_ICR_RTC (0xFC050040 + 26)
6285 +
6286 +/* Register read/write macros */
6287 +#define MCF_RTC_YEARMON 0xFC0A8000
6288 +#define MCF_RTC_DAYS 0xFC0A8002
6289 +#define MCF_RTC_HOURMIN 0xFC0A8004
6290 +#define MCF_RTC_SECONDS 0xFC0A8006
6291 +#define MCF_RTC_ALRM_YRMON 0xFC0A8008
6292 +#define MCF_RTC_ALRM_DAYS 0xFC0A800A
6293 +#define MCF_RTC_ALRM_HM 0xFC0A800C
6294 +#define MCF_RTC_ALRM_SEC 0xFC0A800E
6295 +#define MCF_RTC_CR 0xFC0A8010
6296 +#define MCF_RTC_SR 0xFC0A8012
6297 +#define MCF_RTC_ISR 0xFC0A8014
6298 +#define MCF_RTC_IER 0xFC0A8016
6299 +#define MCF_RTC_COUNT_DN 0xFC0A8018
6300 +#define MCF_RTC_CFG_DATA 0xFC0A8020
6301 +#define MCF_RTC_DST_HOUR 0xFC0A8022
6302 +#define MCF_RTC_DST_MON 0xFC0A8024
6303 +#define MCF_RTC_DST_DAY 0xFC0A8026
6304 +#define MCF_RTC_COMPEN 0xFC0A8028
6305 +#define MCF_RTC_UP_CNTRH 0xFC0A8032
6306 +#define MCF_RTC_UP_CNTRL 0xFC0A8034
6307 +
6308 +#define MCF_RTC_STANDBY_RAM_START 0xFC0A8040
6309 +#define MCF_RTC_STANDBY_RAM_END 0xFC0A8040
6310 +
6311 +/* Bit definitions and macros for MCF_RTC_YEARMON */
6312 +
6313 +#define MCF_RTC_YEARMON_YEAR_RD(x) (((x) & 0xFF00) >> 8)
6314 +#define MCF_RTC_YEARMON_MON_RD(x) ((x) & 0x00FF)
6315 +#define MCF_RTC_YEARMON_YEAR_SET(x) (((x) & 0x00FF) << 8)
6316 +#define MCF_RTC_YEARMON_MON_SET(x) ((x) & 0x000F)
6317 +
6318 +/* Bit definitions and macros for MCF_RTC_DAYS */
6319 +#define MCF_RTC_DAYS_DAYWEEK_RD(x) (((x) & 0xFF00) >> 8)
6320 +#define MCF_RTC_DAYS_DAY_RD(x) ((x) & 0x00FF)
6321 +#define MCF_RTC_DAYS_DAYWEEK_SET(x) (((x) & 0x0007) << 8)
6322 +#define MCF_RTC_DAYS_DAY_SET(x) ((x) & 0x001F)
6323 +
6324 +/* Bit definitions and macros for MCF_RTC_HOURMIN */
6325 +#define MCF_RTC_HOURMIN_HOURS_RD(x) (((x) & 0xFF00) >> 8)
6326 +#define MCF_RTC_HOURMIN_MINUTES_RD(x) ((x) & 0x00FF)
6327 +#define MCF_RTC_HOURMIN_HOURS_SET(x) (((x) & 0x001F) << 8)
6328 +#define MCF_RTC_HOURMIN_MINUTES_SET(x) ((x) & 0x003F)
6329 +
6330 +/* Bit definitions and macros for MCF_RTC_SECONDS */
6331 +#define MCF_RTC_SECONDS_SECONDS_RD(x) ((x) & 0x00FF)
6332 +#define MCF_RTC_SECONDS_SECONDS_SET(x) (((x) & 0x003F) << 0)
6333 +
6334 +/* Bit definitions and macros for MCF_RTC_CR */
6335 +#define MCF_RTC_CR_WP 0x0002
6336 +
6337 +/* Bit definitions and macros for MCF_RTC_ISR */
6338 +#define MCF_RTC_ISR_STW 0x0002
6339 +#define MCF_RTC_ISR_ALM 0x0004
6340 +#define MCF_RTC_ISR_DAY 0x0008
6341 +#define MCF_RTC_ISR_HR 0x0010
6342 +#define MCF_RTC_ISR_MIN 0x0020
6343 +#define MCF_RTC_ISR_1HZ 0x0040
6344 +#define MCF_RTC_ISR_2HZ 0x0080
6345 +#define MCF_RTC_ISR_SAM0 0x0100
6346 +#define MCF_RTC_ISR_SAM1 0x0200
6347 +#define MCF_RTC_ISR_SAM2 0x0400
6348 +#define MCF_RTC_ISR_SAM3 0x0800
6349 +#define MCF_RTC_ISR_SAM4 0x1000
6350 +#define MCF_RTC_ISR_SAM5 0x2000
6351 +#define MCF_RTC_ISR_SAM6 0x4000
6352 +#define MCF_RTC_ISR_SAM7 0x8000
6353 +
6354 +/* Bit definitions and macros for MCF_RTC_IER */
6355 +#define MCF_RTC_IER_STW 0x0002
6356 +#define MCF_RTC_IER_ALM 0x0004
6357 +#define MCF_RTC_IER_DAY 0x0008
6358 +#define MCF_RTC_IER_HR 0x0010
6359 +#define MCF_RTC_IER_MIN 0x0020
6360 +#define MCF_RTC_IER_1HZ 0x0040
6361 +#define MCF_RTC_IER_2HZ 0x0080
6362 +#define MCF_RTC_IER_SAM0 0x0100
6363 +#define MCF_RTC_IER_SAM1 0x0200
6364 +#define MCF_RTC_IER_SAM2 0x0400
6365 +#define MCF_RTC_IER_SAM3 0x0800
6366 +#define MCF_RTC_IER_SAM4 0x1000
6367 +#define MCF_RTC_IER_SAM5 0x2000
6368 +#define MCF_RTC_IER_SAM6 0x4000
6369 +#define MCF_RTC_IER_SAM7 0x8000
6370 +
6371 +/* Bit definitions and macros for MCF_RTC_CFG_DATA */
6372 +#define MCF_RTC_CFG_DATA_OSCBYP 0x0010
6373 +#define MCF_RTC_CFG_DATA_OSCEN 0x0008
6374 +
6375 +/* Bit definitions and macros for MCF_RTC_SR */
6376 +#define MCF_RTC_SR_INVALID 0x0001
6377 +#define MCF_RTC_SR_WPE 0x0010
6378 +
6379 +/* Interrupt source */
6380 +#define MCFINT_RTC (64+64+26)
6381 +/*********************************************************************/
6382 +
6383 +#endif
6384 --- /dev/null
6385 +++ b/arch/m68k/include/asm/mcf5441x_scm.h
6386 @@ -0,0 +1,33 @@
6387 +/*
6388 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6389 + *
6390 + * This is free software; you can redistribute it and/or modify
6391 + * it under the terms of the GNU General Public License as published by
6392 + * the Free Software Foundation; either version 2 of the License, or
6393 + * (at your option) any later version.
6394 + *
6395 + */
6396 +#ifndef __MCF5441X_SCM_H__
6397 +#define __MCF5441X_SCM_H__
6398 +
6399 +/*********************************************************************
6400 +*
6401 +* System Control Module (SCM)
6402 +*
6403 +*********************************************************************/
6404 +
6405 +/* Core Watchdog(CW) Register read/write macros */
6406 +#define MCF_SCM_CWCR MCF_REG16(0xFC040016) /* CW Control Register */
6407 +#define MCF_SCM_CWSR MCF_REG08(0xFC04001B) /* CW Service Register */
6408 +
6409 +/* CW Bit definitions and macros for SWCR */
6410 +#define MCF_SCM_CWCR_RO (0x8000) /* CWCR is read-only */
6411 +#define MCF_SCM_CWCR_CWRWR (0x0100) /* CW run when halted */
6412 +#define MCF_SCM_CWCR_CWE (0x0080) /* CW timer enable */
6413 +#define MCF_SCM_CWCR_CWRI(x) (((x) & 0x03) << 5) /* CW reset/interrupt */
6414 +#define MCF_SCM_CWCR_CWT(x) (((x) & 0x1F) << 0) /* CW time-out period */
6415 +
6416 +#define MCF_GPT_MAX_TIMEOUT 17
6417 +/********************************************************************/
6418 +
6419 +#endif /* __MCF5441X_SCM_H__ */
6420 --- /dev/null
6421 +++ b/arch/m68k/include/asm/mcf5441x_sdramc.h
6422 @@ -0,0 +1,141 @@
6423 +/*
6424 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6425 + *
6426 + * This program is free software; you can redistribute it and/or modify it
6427 + * under the terms of the GNU General Public License as published by the
6428 + * Free Software Foundation; either version 2 of the License, or (at your
6429 + * option) any later version.
6430 + */
6431 +
6432 +#ifndef __MCF5441X_SDRAMC_H__
6433 +#define __MCF5441X_SDRAMC_H__
6434 +
6435 +/*********************************************************************
6436 +*
6437 +* SDRAM Controller (SDRAMC)
6438 +*
6439 +*********************************************************************/
6440 +
6441 +/* Register read/write macros */
6442 +/* SDRAM Mode/Extended Mode Register */
6443 +#define MCF_SDRAMC_SDMR (*(vuint32 *)(0xFC0B8000))
6444 +/* SDRAM Control Register */
6445 +#define MCF_SDRAMC_SDCR (*(vuint32 *)(0xFC0B8004))
6446 +/* SDRAM Configuration Register 1 */
6447 +#define MCF_SDRAMC_SDCFG1 (*(vuint32 *)(0xFC0B8008))
6448 +/* SDRAM Configuration Register 2 */
6449 +#define MCF_SDRAMC_SDCFG2 (*(vuint32 *)(0xFC0B800C))
6450 +/* SDRAM Chip Select Register */
6451 +#define MCF_SDRAMC_SDCS0 (*(vuint32 *)(0xFC0B8110))
6452 +/* SDRAM Chip Select Register */
6453 +#define MCF_SDRAMC_SDCS1 (*(vuint32 *)(0xFC0B8114))
6454 +
6455 +/* Parameterized register read/write macros for multiple registers */
6456 +/* SDRAM Chip Select Register */
6457 +#define MCF_SDRAMC_SDCS(x) (*(vuint32 *)(0xFC0B8110+((x)*0x004)))
6458 +
6459 +/* Bit definitions and macros for SDMR */
6460 +#define MCF_SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
6461 +#define MCF_SDRAMC_SDMR_CMD (0x00010000) /* Command */
6462 +#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
6463 +#define MCF_SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
6464 +#define MCF_SDRAMC_SDMR_BK_LMR (0x00000000)
6465 +#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000)
6466 +
6467 +/* Bit definitions and macros for SDCR */
6468 +#define MCF_SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
6469 +#define MCF_SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
6470 +#define MCF_SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
6471 +#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
6472 +#define MCF_SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
6473 +/* Periodic Refresh Counter */
6474 +#define MCF_SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16)
6475 +#define MCF_SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
6476 +/* Internal Address Mux Select */
6477 +#define MCF_SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24)
6478 +#define MCF_SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
6479 +#define MCF_SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
6480 +#define MCF_SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
6481 +/* Clock Enable */
6482 +#define MCF_SDRAMC_SDCR_CKE (0x40000000)
6483 +/* SDRAM Mode Register Programming Enable */
6484 +#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
6485 +#define MCF_SDRAMC_SDCR_DQS_OE_BOTH (0x00000C00)
6486 +
6487 +/* Bit definitions and macros for SDCFG1 */
6488 +/* Write Latency */
6489 +#define MCF_SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4)
6490 +/* Refresh to active delay */
6491 +#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8)
6492 +/* Precharge to active delay */
6493 +#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12)
6494 +/* Active to read/write delay */
6495 +#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16)
6496 +/* Read CAS Latency */
6497 +#define MCF_SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20)
6498 +/* Single write to read/write/precharge delay */
6499 +#define MCF_SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24)
6500 +/* Single read to read/write/precharge delay */
6501 +#define MCF_SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28)
6502 +
6503 +/* Bit definitions and macros for SDCFG2 */
6504 +/* Burst Length */
6505 +#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16)
6506 +/* Burst read to write delay */
6507 +#define MCF_SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20)
6508 +/* Burst write to read/write/precharge delay */
6509 +#define MCF_SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24)
6510 +/* Burst read to read/precharge delay */
6511 +#define MCF_SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28)
6512 +
6513 +/* Bit definitions and macros for SDCS group */
6514 +/* Chip-Select Size */
6515 +#define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F))
6516 +/* Chip-Select Base Address */
6517 +#define MCF_SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20)
6518 +#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
6519 +#define MCF_SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
6520 +#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
6521 +#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
6522 +#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
6523 +#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
6524 +#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
6525 +#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
6526 +#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
6527 +#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
6528 +#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
6529 +#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
6530 +#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
6531 +#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
6532 +#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
6533 +
6534 +/* Bit definitions and macros for SDCS0 */
6535 +/* Chip-Select Size */
6536 +#define MCF_SDRAMC_SDCS0_CSSZ(x) (((x)&0x0000001F))
6537 +/* Chip-Select Base Address */
6538 +#define MCF_SDRAMC_SDCS0_CSBA(x) (((x)&0x00000FFF)<<20)
6539 +#define MCF_SDRAMC_SDCS0_BA(x) ((x)&0xFFF00000)
6540 +#define MCF_SDRAMC_SDCS0_CSSZ_DISABLE (0x00000000)
6541 +#define MCF_SDRAMC_SDCS0_CSSZ_1MBYTE (0x00000013)
6542 +#define MCF_SDRAMC_SDCS0_CSSZ_2MBYTE (0x00000014)
6543 +#define MCF_SDRAMC_SDCS0_CSSZ_4MBYTE (0x00000015)
6544 +#define MCF_SDRAMC_SDCS0_CSSZ_8MBYTE (0x00000016)
6545 +#define MCF_SDRAMC_SDCS0_CSSZ_16MBYTE (0x00000017)
6546 +#define MCF_SDRAMC_SDCS0_CSSZ_32MBYTE (0x00000018)
6547 +#define MCF_SDRAMC_SDCS0_CSSZ_64MBYTE (0x00000019)
6548 +#define MCF_SDRAMC_SDCS0_CSSZ_128MBYTE (0x0000001A)
6549 +#define MCF_SDRAMC_SDCS0_CSSZ_256MBYTE (0x0000001B)
6550 +#define MCF_SDRAMC_SDCS0_CSSZ_512MBYTE (0x0000001C)
6551 +#define MCF_SDRAMC_SDCS0_CSSZ_1GBYTE (0x0000001D)
6552 +#define MCF_SDRAMC_SDCS0_CSSZ_2GBYTE (0x0000001E)
6553 +#define MCF_SDRAMC_SDCS0_CSSZ_4GBYTE (0x0000001F)
6554 +
6555 +/* Bit definitions and macros for SDCS1 */
6556 +/* Chip-Select Size */
6557 +#define MCF_SDRAMC_SDCS1_CSSZ(x) (((x)&0x0000001F))
6558 +/* Chip-Select Base Address */
6559 +#define MCF_SDRAMC_SDCS1_CSBA(x) (((x)&0x00000FFF)<<20)
6560 +
6561 +/********************************************************************/
6562 +
6563 +#endif /* __MCF5441X_SDRAMC_H__ */
6564 --- /dev/null
6565 +++ b/arch/m68k/include/asm/mcf5441x_xbs.h
6566 @@ -0,0 +1,77 @@
6567 +/*
6568 + * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
6569 + *
6570 + * This program is free software; you can redistribute it and/or modify it
6571 + * under the terms of the GNU General Public License as published by the
6572 + * Free Software Foundation; either version 2 of the License, or (at your
6573 + * option) any later version.
6574 + */
6575 +
6576 +#ifndef __MCF5441X_XBS_H__
6577 +#define __MCF5441X_XBS_H__
6578 +
6579 +/*
6580 + * Crossbar Switch (XBS)
6581 + */
6582 +
6583 +/* Register read/write macros */
6584 +#define MCF_XBS_PRS0 MCF_REG32(0xFC004000) /* DRAM */
6585 +#define MCF_XBS_CRS0 MCF_REG32(0xFC004010)
6586 +#define MCF_XBS_PRS1 MCF_REG32(0xFC004100) /* Flexbus Priority */
6587 +#define MCF_XBS_CRS1 MCF_REG32(0xFC004110) /* Flexbus Control */
6588 +#define MCF_XBS_PRS2 MCF_REG32(0xFC004200) /* SDRam Priority */
6589 +#define MCF_XBS_CRS2 MCF_REG32(0xFC004210) /* SDRam Control */
6590 +#define MCF_XBS_PRS3 MCF_REG32(0xFC004300) /* ATA Priority */
6591 +#define MCF_XBS_CRS4 MCF_REG32(0xFC004410) /* SRAM Control */
6592 +#define MCF_XBS_PRS6 MCF_REG32(0xFC004600) /* Slave6 Priority */
6593 +#define MCF_XBS_CRS6 MCF_REG32(0xFC004610) /* Slave6 Control */
6594 +#define MCF_XBS_PRS7 MCF_REG32(0xFC004700) /* Other Priority */
6595 +#define MCF_XBS_CRS7 MCF_REG32(0xFC004710) /* Other Control */
6596 +
6597 +/* Priorities */
6598 +#define MCF_XBS_PRI_1 0 /* Level 1 (highest) */
6599 +#define MCF_XBS_PRI_2 1 /* Level 2 */
6600 +#define MCF_XBS_PRI_3 2 /* Level 3 */
6601 +#define MCF_XBS_PRI_4 3 /* Level 4 */
6602 +#define MCF_XBS_PRI_5 4 /* Level 5 */
6603 +#define MCF_XBS_PRI_6 5 /* Level 6 */
6604 +#define MCF_XBS_PRI_7 6 /* Level 7 (lowest) */
6605 +#define MCF_XBS_PRI_MASK 7 /* Mask (Not a valid level) */
6606 +
6607 +/* Priority Register (PRSn) Defs */
6608 +#define MCF_XBS_PRS_MACRO(m, p) ((p)<<((m)<<2))
6609 +#define MCF_XBS_PRS_M0(p) MCF_XBS_PRS_MACRO(0, p) /* Coldfire Core */
6610 +#define MCF_XBS_PRS_M1(p) MCF_XBS_PRS_MACRO(1, p) /* eDMA */
6611 +#define MCF_XBS_PRS_M2(p) MCF_XBS_PRS_MACRO(2, p) /* FEC0 */
6612 +#define MCF_XBS_PRS_M3(p) MCF_XBS_PRS_MACRO(3, p) /* FEC1 */
6613 +#define MCF_XBS_PRS_M4(p) MCF_XBS_PRS_MACRO(4, p) /* Master 4 */
6614 +#define MCF_XBS_PRS_M5(p) MCF_XBS_PRS_MACRO(5, p) /* PCI */
6615 +#define MCF_XBS_PRS_M6(p) MCF_XBS_PRS_MACRO(6, p) /* USB OTG */
6616 +#define MCF_XBS_PRS_M7(p) MCF_XBS_PRS_MACRO(7, p) /* Serial Boot */
6617 +
6618 +/* Control Register (CRSn) Defs */
6619 +#define MCF_XBS_CRS_RO 0x80000000 /* Read Only */
6620 +#define MCF_XBS_CRS_ARB 0x00000100 /* Arbitration Mode */
6621 +#define MCF_XBS_CRS_PCTL 0x00000030 /* Parking Control */
6622 +#define MCF_XBS_CRS_PARK 0x00000007 /* Park Location */
6623 +
6624 +/* MCF_XBS_CRS_ARB Defs */
6625 +#define MCF_ABS_CRS_ARB_FIXED 0x00000000 /* Fixed priority */
6626 +#define MCF_ABS_CRS_ARB_ROUND 0x00000100 /* Round Robin priority */
6627 +
6628 +/* MCF_XBS_CRS_PCTL Defs */
6629 +#define MCF_ABS_CRS_PCTL_PARK 0x00000000 /* Park on the defined PARK */
6630 +#define MCF_ABS_CRS_PCTL_LAST 0x00000010 /* Park on the last master */
6631 +#define MCF_ABS_CRS_PCTL_NONE 0x00000020 /* Don't park */
6632 +
6633 +/* MCF_XBS_CRS_PARK Defs */
6634 +#define MCF_ABS_CRS_PARK_M0 0x00000000 /* Park on Coldfire Core */
6635 +#define MCF_ABS_CRS_PARK_M1 0x00000001 /* Park on eDMA */
6636 +#define MCF_ABS_CRS_PARK_M2 0x00000002 /* Park on FEC0 */
6637 +#define MCF_ABS_CRS_PARK_M3 0x00000003 /* Park on FEC1 */
6638 +#define MCF_ABS_CRS_PARK_M4 0x00000004 /* Park on Reserved */
6639 +#define MCF_ABS_CRS_PARK_M5 0x00000005 /* Park on PCI */
6640 +#define MCF_ABS_CRS_PARK_M6 0x00000006 /* Park on USB OTG */
6641 +#define MCF_ABS_CRS_PARK_M7 0x00000007 /* Park on Serial Boot */
6642 +
6643 +#endif /* __MCF5441X_XBS_H__ */
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