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[openwrt/openwrt.git] / target / linux / coldfire / patches / 002-MCF54451-and-MCF54455-support-in-Linux-2.6.38.patch
1 From f46a96f02d74535e928710eaebffe6c8b201b76a Mon Sep 17 00:00:00 2001
2 From: Alison Wang <b18965@freescale.com>
3 Date: Thu, 4 Aug 2011 09:59:37 +0800
4 Subject: [PATCH 02/52] MCF54451 and MCF54455 support in Linux 2.6.38
5
6 Add MCF54451 and MCF54455 support in Linux 2.6.38.
7
8 Signed-off-by: Alison Wang <b18965@freescale.com>
9 ---
10 arch/m68k/coldfire/m5445x/Makefile | 20 +
11 arch/m68k/coldfire/m5445x/config.c | 599 ++++++++++
12 arch/m68k/coldfire/m5445x/devices.c | 527 +++++++++
13 arch/m68k/configs/m54451evb_defconfig | 1412 +++++++++++++++++++++++
14 arch/m68k/configs/m54455evb_defconfig | 1597 +++++++++++++++++++++++++++
15 arch/m68k/include/asm/cf_5445x_cacheflush.h | 534 +++++++++
16 arch/m68k/include/asm/mcf5445x_ccm.h | 206 ++++
17 arch/m68k/include/asm/mcf5445x_dspi.h | 665 +++++++++++
18 arch/m68k/include/asm/mcf5445x_dtim.h | 96 ++
19 arch/m68k/include/asm/mcf5445x_edma.h | 1472 ++++++++++++++++++++++++
20 arch/m68k/include/asm/mcf5445x_eport.h | 117 ++
21 arch/m68k/include/asm/mcf5445x_fbcs.h | 200 ++++
22 arch/m68k/include/asm/mcf5445x_gpio.h | 1411 +++++++++++++++++++++++
23 arch/m68k/include/asm/mcf5445x_intc.h | 724 ++++++++++++
24 arch/m68k/include/asm/mcf5445x_pci.h | 238 ++++
25 arch/m68k/include/asm/mcf5445x_pciarb.h | 40 +
26 arch/m68k/include/asm/mcf5445x_rtc.h | 114 ++
27 arch/m68k/include/asm/mcf5445x_scm.h | 48 +
28 arch/m68k/include/asm/mcf5445x_sdramc.h | 142 +++
29 arch/m68k/include/asm/mcf5445x_ssi.h | 187 ++++
30 arch/m68k/include/asm/mcf5445x_xbs.h | 81 ++
31 21 files changed, 10430 insertions(+), 0 deletions(-)
32 create mode 100644 arch/m68k/coldfire/m5445x/Makefile
33 create mode 100644 arch/m68k/coldfire/m5445x/config.c
34 create mode 100644 arch/m68k/coldfire/m5445x/devices.c
35 create mode 100644 arch/m68k/configs/m54451evb_defconfig
36 create mode 100644 arch/m68k/configs/m54455evb_defconfig
37 create mode 100644 arch/m68k/include/asm/cf_5445x_cacheflush.h
38 create mode 100644 arch/m68k/include/asm/mcf5445x_ccm.h
39 create mode 100644 arch/m68k/include/asm/mcf5445x_dspi.h
40 create mode 100644 arch/m68k/include/asm/mcf5445x_dtim.h
41 create mode 100644 arch/m68k/include/asm/mcf5445x_edma.h
42 create mode 100644 arch/m68k/include/asm/mcf5445x_eport.h
43 create mode 100644 arch/m68k/include/asm/mcf5445x_fbcs.h
44 create mode 100644 arch/m68k/include/asm/mcf5445x_gpio.h
45 create mode 100644 arch/m68k/include/asm/mcf5445x_intc.h
46 create mode 100644 arch/m68k/include/asm/mcf5445x_pci.h
47 create mode 100644 arch/m68k/include/asm/mcf5445x_pciarb.h
48 create mode 100644 arch/m68k/include/asm/mcf5445x_rtc.h
49 create mode 100644 arch/m68k/include/asm/mcf5445x_scm.h
50 create mode 100644 arch/m68k/include/asm/mcf5445x_sdramc.h
51 create mode 100644 arch/m68k/include/asm/mcf5445x_ssi.h
52 create mode 100644 arch/m68k/include/asm/mcf5445x_xbs.h
53
54 --- /dev/null
55 +++ b/arch/m68k/coldfire/m5445x/Makefile
56 @@ -0,0 +1,20 @@
57 +#
58 +# Makefile for Linux arch/m68k/coldfire/m5445x source directory
59 +#
60 +
61 +obj-$(CONFIG_M5445X) += devices.o config.o
62 +
63 +ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_FSL_USB2)),)
64 + obj-y += usb.o
65 +endif
66 +ifneq ($(strip $(CONFIG_USB_GADGET_FSL_USB2) $(CONFIG_USB_EHCI_HCD)),)
67 + obj-y += usb_dr.o
68 +endif
69 +ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_FSL_USB2)),)
70 + obj-y += xcvr.o
71 +endif
72 +
73 +obj-$(CONFIG_PCI) += pci.o mcf5445x-pci.o
74 +ifneq ($(CONFIG_FEC),)
75 +obj-y += fec.o
76 +endif
77 --- /dev/null
78 +++ b/arch/m68k/coldfire/m5445x/config.c
79 @@ -0,0 +1,599 @@
80 +/*
81 + * linux/arch/m68k/coldfire/config_m5445x.c
82 + *
83 + * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
84 + * Author:
85 + * Kurt Mahan kmahan@freescale.com
86 + * Matt Waddel Matt.Waddel@freescale.com
87 + * Jason Jin Jason.Jin@freescale.com
88 + * Shrek Wu B16972@freescale.com
89 + *
90 + * This program is free software; you can redistribute it and/or modify
91 + * it under the terms of the GNU General Public License as published by
92 + * the Free Software Foundation; either version 2 of the License, or
93 + * (at your option) any later version.
94 + */
95 +
96 +#include <linux/module.h>
97 +#include <linux/init.h>
98 +#include <linux/string.h>
99 +#include <linux/kernel.h>
100 +#include <linux/console.h>
101 +#include <linux/bootmem.h>
102 +#include <linux/mm.h>
103 +#include <linux/sched.h>
104 +#include <linux/clockchips.h>
105 +#include <linux/delay.h>
106 +#include <asm/bootinfo.h>
107 +#include <asm/machdep.h>
108 +#include <asm/coldfire.h>
109 +#include <asm/cfcache.h>
110 +#include <asm/cacheflush.h>
111 +#include <asm/io.h>
112 +#include <asm/cfmmu.h>
113 +#include <asm/setup.h>
114 +#include <asm/irq.h>
115 +#include <asm/traps.h>
116 +#include <asm/movs.h>
117 +#include <asm/movs.h>
118 +#include <asm/page.h>
119 +#include <asm/pgalloc.h>
120 +#include <asm/cf-sram.h>
121 +
122 +#include <asm/mcfsim.h>
123 +
124 +#define UBOOT_EXTRA_CLOCKS
125 +#include <asm/bootinfo.h>
126 +
127 +#include <asm/mcf5445x_intc.h>
128 +#include <asm/mcf5445x_sdramc.h>
129 +#include <asm/mcf5445x_fbcs.h>
130 +#include <asm/mcf5445x_dtim.h>
131 +#include <asm/mcf5445x_xbs.h>
132 +
133 +extern int get_irq_list(struct seq_file *p, void *v);
134 +extern char _text, _end;
135 +extern char _etext, _edata, __init_begin, __init_end;
136 +extern struct console mcfrs_console;
137 +extern char m68k_command_line[CL_SIZE];
138 +extern unsigned long availmem;
139 +extern unsigned long shadow_cacr;
140 +EXPORT_SYMBOL(shadow_cacr);
141 +extern struct mem_info m68k_ramdisk;
142 +
143 +static int irq_enable[NR_IRQS];
144 +unsigned long num_pages;
145 +
146 +/* cf dma physical addresses */
147 +unsigned long cf_dma_base;
148 +EXPORT_SYMBOL(cf_dma_base);
149 +unsigned long cf_dma_end;
150 +EXPORT_SYMBOL(cf_dma_end);
151 +unsigned long cf_dma_size;
152 +EXPORT_SYMBOL(cf_dma_size);
153 +
154 +/* ethernet mac addresses from uboot */
155 +unsigned char uboot_enet0[6];
156 +unsigned char uboot_enet1[6];
157 +
158 +void coldfire_sort_memrec(void)
159 +{
160 + int i, j;
161 +
162 + /* Sort the m68k_memory records by address */
163 + for (i = 0; i < m68k_num_memory; ++i) {
164 + for (j = i + 1; j < m68k_num_memory; ++j) {
165 + if (m68k_memory[i].addr > m68k_memory[j].addr) {
166 + struct mem_info tmp;
167 + tmp = m68k_memory[i];
168 + m68k_memory[i] = m68k_memory[j];
169 + m68k_memory[j] = tmp;
170 + }
171 + }
172 + }
173 + /* Trim off discontiguous bits */
174 + for (i = 1; i < m68k_num_memory; ++i) {
175 + if ((m68k_memory[i-1].addr + m68k_memory[i-1].size) !=
176 + m68k_memory[i].addr) {
177 + printk(KERN_DEBUG "m68k_parse_bootinfo: "
178 + "addr gap between 0x%lx & 0x%lx\n",
179 + m68k_memory[i-1].addr+m68k_memory[i-1].size,
180 + m68k_memory[i].addr);
181 + m68k_num_memory = i;
182 + break;
183 + }
184 + }
185 +}
186 +
187 +/*
188 + * UBoot Handler
189 + */
190 +int __init uboot_commandline(char *bootargs)
191 +{
192 + int len = 0, cmd_line_len;
193 + static struct uboot_record uboot_info;
194 + u32 offset = PAGE_OFFSET_RAW - PHYS_OFFSET;
195 +
196 + extern unsigned long uboot_info_stk;
197 +
198 + /* validate address */
199 + if ((uboot_info_stk < PAGE_OFFSET_RAW) ||
200 + (uboot_info_stk >= (PAGE_OFFSET_RAW + CONFIG_SDRAM_SIZE)))
201 + return 0;
202 +
203 + /* Add offset to get post-remapped kernel memory location */
204 + uboot_info.bdi = (struct bd_info *)
205 + ((*(u32 *)(uboot_info_stk)) + offset);
206 + uboot_info.initrd_start = (*(u32 *)(uboot_info_stk+4)) + offset;
207 + uboot_info.initrd_end = (*(u32 *)(uboot_info_stk+8)) + offset;
208 + uboot_info.cmd_line_start = (*(u32 *)(uboot_info_stk+12)) + offset;
209 + uboot_info.cmd_line_stop = (*(u32 *)(uboot_info_stk+16)) + offset;
210 +
211 +#if defined(CONFIG_BLK_DEV_INITRD)
212 + m68k_ramdisk.addr = uboot_info.initrd_start;
213 + m68k_ramdisk.size = (uboot_info.initrd_end - uboot_info.initrd_start) ?
214 + (uboot_info.initrd_end - uboot_info.initrd_start + 1) : 0;
215 +#endif
216 +
217 + /* copy over mac addresses */
218 + memcpy(uboot_enet0, uboot_info.bdi->bi_enet0addr, 6);
219 + memcpy(uboot_enet1, uboot_info.bdi->bi_enet1addr, 6);
220 +
221 + /* copy command line */
222 + cmd_line_len = uboot_info.cmd_line_stop - uboot_info.cmd_line_start;
223 + if ((cmd_line_len > 0) && (cmd_line_len < CL_SIZE-1))
224 + len = (int)strncpy(bootargs, (char *)uboot_info.cmd_line_start,\
225 + cmd_line_len);
226 +
227 + return len;
228 +}
229 +
230 +#if defined(CONFIG_M54451)
231 +#define DEFAULT_COMMAND_LINE \
232 + "debug root=/dev/nfs rw \
233 + nfsroot=172.27.155.1:/tftpboot/redstripe/rootfs/ \
234 + ip=172.27.155.51:172.27.155.1"
235 +#elif defined(CONFIG_M54455)
236 +#define MTD_DEFAULT_COMMAND_LINE \
237 + "root=/dev/mtdblock1 rw rootfstype=jffs2 \
238 + ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
239 +#define DEFAULT_COMMAND_LINE \
240 + "debug root=/dev/nfs rw \
241 + nfsroot=172.27.155.1:/tftpboot/redstripe/rootfs/ \
242 + ip=172.27.155.55:172.27.155.1"
243 +#endif
244 +
245 +
246 +/*
247 + * Early Coldfire Initialization.
248 + */
249 +asmlinkage void __init cf_early_init(void)
250 +{
251 + SET_VBR((void *)MCF_RAMBAR1);
252 +
253 + /* Mask all interrupts */
254 + MCF_INTC0_IMRL = 0xFFFFFFFF;
255 + MCF_INTC0_IMRH = 0xFFFFFFFF;
256 + MCF_INTC1_IMRL = 0xFFFFFFFF;
257 + MCF_INTC1_IMRH = 0xFFFFFFFF;
258 +
259 +#if defined(CONFIG_NOR_FLASH_BASE)
260 + MCF_FBCS_CSAR(1) = CONFIG_NOR_FLASH_BASE;
261 +#else
262 + MCF_FBCS_CSAR(1) = 0x00000000;
263 +#endif
264 +
265 +#if CONFIG_SDRAM_SIZE > (256*1024*1024)
266 + /* Init optional SDRAM chip select */
267 + MCF_SDRAMC_SDCS(1) = (256*1024*1024) | 0x1B;
268 +#endif
269 +
270 + MCF_XBS_CRS2 = 0x100;
271 + /* Setup SDRAM crossbar(XBS) priorities */
272 + MCF_XBS_PRS2 = (MCF_XBS_PRS_M0(MCF_XBS_PRI_2) | /*CPU*/
273 + MCF_XBS_PRS_M1(MCF_XBS_PRI_3) | /*eDMA*/
274 + MCF_XBS_PRS_M2(MCF_XBS_PRI_1) | /*FEC0*/
275 + MCF_XBS_PRS_M3(MCF_XBS_PRI_5) | /*FEC1*/
276 + MCF_XBS_PRS_M5(MCF_XBS_PRI_6) | /*PCI*/
277 + MCF_XBS_PRS_M6(MCF_XBS_PRI_4) | /*USB*/
278 + MCF_XBS_PRS_M7(MCF_XBS_PRI_7)); /*SBF*/
279 +
280 + m68k_machtype = MACH_CFMMU;
281 + m68k_fputype = FPU_CFV4E;
282 + m68k_mmutype = MMU_CFV4E;
283 + m68k_cputype = CPU_CFV4E;
284 +
285 + /* initialize PHYSRAM */
286 + m68k_num_memory = 0;
287 + m68k_memory[m68k_num_memory].addr = CONFIG_SDRAM_BASE; /* phys */
288 + m68k_memory[m68k_num_memory++].size = CONFIG_SDRAM_SIZE;
289 +
290 + if (!uboot_commandline(m68k_command_line)) {
291 +#if defined(CONFIG_BOOTPARAM)
292 + strncpy(m68k_command_line, CONFIG_BOOTPARAM_STRING, CL_SIZE-1);
293 +#else
294 + strcpy(m68k_command_line, DEFAULT_COMMAND_LINE);
295 +#endif
296 + }
297 +
298 + /* Invalidate caches via CACR */
299 + flush_bcache();
300 + cacr_set(CACHE_DISABLE_MODE);
301 +
302 + /* Turn on caches via CACR, enable EUSP */
303 + cacr_set(CACHE_INITIAL_MODE);
304 +}
305 +
306 +/* Assembler routines */
307 +asmlinkage void buserr(void);
308 +asmlinkage void trap(void);
309 +asmlinkage void system_call(void);
310 +asmlinkage void inthandler(void);
311 +
312 +void __init coldfire_trap_init(void)
313 +{
314 + int i = 0;
315 + e_vector *vectors;
316 +
317 + vectors = (e_vector *)MCF_RAMBAR1;
318 + /*
319 + * There is a common trap handler and common interrupt
320 + * handler that handle almost every vector. We treat
321 + * the system call and bus error special, they get their
322 + * own first level handlers.
323 + */
324 + for (i = 3; (i <= 23); i++)
325 + vectors[i] = trap;
326 + for (i = 33; (i <= 63); i++)
327 + vectors[i] = trap;
328 + for (i = 24; (i <= 31); i++)
329 + vectors[i] = inthandler;
330 + for (i = 64; (i < 255); i++)
331 + vectors[i] = inthandler;
332 +
333 + vectors[255] = 0;
334 + vectors[2] = buserr;
335 + vectors[32] = system_call;
336 +}
337 +
338 +void settimericr(unsigned int timer, unsigned int level)
339 +{
340 + volatile unsigned char *icrp;
341 + unsigned int icr = 0;
342 + unsigned char irq = 0;
343 +
344 + if (timer <= 3) {
345 + switch (timer) {
346 + case 0:
347 + irq = 32;
348 + icr = MCFSIM_ICR_TIMER0;
349 + break;
350 + case 1:
351 + irq = 33;
352 + icr = MCFSIM_ICR_TIMER1;
353 + break;
354 + case 2:
355 + irq = 34;
356 + icr = MCFSIM_ICR_TIMER2;
357 + break;
358 + case 3:
359 + irq = 35;
360 + icr = MCFSIM_ICR_TIMER3;
361 + break;
362 + }
363 +
364 + icrp = (volatile unsigned char *) (icr);
365 + *icrp = level;
366 + coldfire_enable_irq0(irq);
367 + }
368 +}
369 +
370 +void coldfire_sched_clk_init(void);
371 +
372 +void coldfire_tick(void)
373 +{
374 + /* Reset the ColdFire timer */
375 + __raw_writeb(MCF_DTIM_DTER_CAP | MCF_DTIM_DTER_REF, MCF_DTIM0_DTER);
376 +}
377 +
378 +void __init coldfire_sched_init(irq_handler_t handler)
379 +{
380 + unsigned int mcf_timerlevel = 5;
381 + unsigned int mcf_timervector = 64+32;
382 +
383 + __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM0_DTMR);
384 + __raw_writel(((MCF_BUSCLK / 16) / HZ), MCF_DTIM0_DTRR);
385 + __raw_writew(MCF_DTIM_DTMR_ORRI | MCF_DTIM_DTMR_CLK_DIV16 |
386 + MCF_DTIM_DTMR_FRR | MCF_DTIM_DTMR_RST_EN, \
387 + MCF_DTIM0_DTMR);
388 +
389 + request_irq(mcf_timervector, handler, IRQF_DISABLED, \
390 + "timer", (void *)MCF_DTIM0_DTMR);
391 +
392 + settimericr(0, mcf_timerlevel);
393 +
394 + /* initialize the fast clock */
395 + coldfire_sched_clk_init();
396 +}
397 +
398 +int timerirqpending(int timer)
399 +{
400 + unsigned int imr = 0;
401 + unsigned ret = 0;
402 +
403 + switch (timer) {
404 + case 1:
405 + imr = 0x1;
406 + break;
407 + case 2:
408 + imr = 0x2;
409 + break;
410 + default:
411 + break;
412 + }
413 +
414 + ret = getiprh() & imr;
415 + return ret;
416 +}
417 +
418 +unsigned long coldfire_gettimeoffset(void)
419 +{
420 + volatile unsigned long trr, tcn, offset;
421 +
422 + tcn = __raw_readw(MCF_DTIM0_DTCN);
423 + trr = __raw_readl(MCF_DTIM0_DTRR);
424 + offset = (tcn * (1000000 / HZ)) / trr;
425 +
426 + /* Check if we just wrapped the counters and maybe missed a tick */
427 + if ((offset < (1000000 / HZ / 2)) && timerirqpending(1))
428 + offset += 1000000 / HZ;
429 + return offset;
430 +}
431 +
432 +/* sched_clock support */
433 +
434 +static unsigned long long sched_clk_val;
435 +
436 +static irqreturn_t coldfire_sched_clk_irq(int irq, void *dev)
437 +{
438 + __raw_writeb(MCF_DTIM_DTER_CAP | MCF_DTIM_DTER_REF, MCF_DTIM3_DTER);
439 + sched_clk_val += 0x100000000LL;
440 +
441 + return IRQ_HANDLED;
442 +}
443 +
444 +/*
445 + * Setup DTIM3 as the 5445x sched_clock() implementation. The
446 + * input frequency to the clock is the internal bus clock (MCF_BUSCLK)
447 + * which is the system clock (MCF_CLK) / 2.
448 + *
449 + * On a system running at 266Mhz:
450 + * MCF_CLK = 266Mhz (266000000)
451 + * MCF_BUSCLK = 133Mhz (133000000)
452 + * DTIM3 Tick = 133Mhz (133000000)
453 + * Tick Resolution = 7.5ns (round to 8ns/Tick)
454 + *
455 + * On a system running at 240Mhz:
456 + * MCF_CLK = 240Mhz (240000000)
457 + * MCF_BUSCLK = 120Mhz (120000000)
458 + * DTIM3 Tick = 120Mhz (120000000)
459 + * Tick Resolution = 8.4ns (round to 8ns/Tick)
460 + */
461 +void __init coldfire_sched_clk_init(void)
462 +{
463 + unsigned int mcf_timerlevel = 5;
464 + unsigned int mcf_timervector = 64+32+3; /* DTIM3 */
465 +
466 + printk(KERN_INFO "Initializing DTIM3 for sched_clock\n");
467 + __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM3_DTMR);
468 + __raw_writel(0xffffffff, MCF_DTIM3_DTRR);
469 + __raw_writew(MCF_DTIM_DTMR_ORRI | MCF_DTIM_DTMR_CLK_DIV1 | \
470 + MCF_DTIM_DTMR_RST_EN, MCF_DTIM3_DTMR);
471 +
472 + sched_clk_val = 0;
473 + request_irq(mcf_timervector, coldfire_sched_clk_irq, IRQF_DISABLED, \
474 + "timer", (void *)MCF_DTIM3_DTMR);
475 +
476 + settimericr(3, mcf_timerlevel);
477 +}
478 +
479 +#ifndef CONFIG_GENERIC_CLOCKEVENTS
480 +/* get highres timer */
481 +unsigned long long sched_clock(void)
482 +{
483 + unsigned long long ret = 0;
484 + ret = sched_clk_val | (unsigned long long)(MCF_REG32(MCF_DTIM3_DTCN));
485 + ret = ret << 3;
486 + return ret;
487 +}
488 +
489 +#else /*CONFIG_GENERIC_CLOCKEVENTS*/
490 +
491 +static unsigned long long sched_dtim_clk_val;
492 +
493 +unsigned long long sched_clock(void)
494 +{
495 + unsigned long flags;
496 + unsigned long long tcn, cycles;
497 +
498 + local_irq_save(flags);
499 + tcn = ((unsigned long long)(MCF_REG32(MCF_DTIM2_DTCN)));
500 + cycles = sched_dtim_clk_val;
501 + local_irq_restore(flags);
502 + return cycles + tcn;
503 +}
504 +
505 +unsigned long long sys_dtim2_read(void)
506 +{
507 + unsigned long flags;
508 + unsigned long long tcn, cycles;
509 +
510 + local_irq_save(flags);
511 + tcn = ((unsigned long long)(MCF_REG32(MCF_DTIM2_DTCN)));
512 + cycles = sched_dtim_clk_val;
513 + local_irq_restore(flags);
514 +
515 + return cycles + tcn;
516 +}
517 +
518 +static irqreturn_t coldfire_dtim_clk_irq(int irq, void *dev)
519 +{
520 + struct clock_event_device *evt = (struct clock_event_device *)dev;
521 +
522 + __raw_writeb(MCF_DTIM_DTER_CAP | MCF_DTIM_DTER_REF, MCF_DTIM2_DTER);
523 + sched_dtim_clk_val += (MCF_BUSCLK / 16) / HZ;
524 + evt->event_handler(evt);
525 + return IRQ_HANDLED;
526 +}
527 +
528 +void sys_dtim2_init(struct clock_event_device *evt)
529 +{
530 + unsigned int mcf_timerlevel = 5;
531 + unsigned int mcf_timervector = 64+32+2; /* DTIM2 */
532 +
533 + printk(KERN_INFO "Initializing DTIM2 for sched_clock\n");
534 + __raw_writew(MCF_DTIM_DTMR_RST_RST, MCF_DTIM2_DTMR);
535 + __raw_writel(((MCF_BUSCLK / 16) / HZ)-1, MCF_DTIM2_DTRR);
536 + __raw_writew(MCF_DTIM_DTMR_ORRI | MCF_DTIM_DTMR_CLK_DIV16 |
537 + MCF_DTIM_DTMR_FRR | MCF_DTIM_DTMR_RST_EN, \
538 + MCF_DTIM2_DTMR);
539 +
540 + request_irq(mcf_timervector, coldfire_dtim_clk_irq, IRQF_DISABLED, \
541 + "timer2", (void *)evt);
542 +
543 + settimericr(3, mcf_timerlevel);
544 + return;
545 +}
546 +
547 +#endif
548 +
549 +void coldfire_reboot(void)
550 +{
551 + /* disable interrupts and do a software reset */
552 + asm("movew #0x2700, %%sr\n\t"
553 + "moveb #0x40, %%d0\n\t"
554 + "moveb %%d0, 0xfc0a0000\n\t"
555 + : : : "%d0");
556 +
557 + mdelay(10);
558 +
559 + asm("moveb #0xc0, %%d0\n\t"
560 + "moveb %%d0, 0xfc0a0000\n\t"
561 + : : : "%d0");
562 +}
563 +
564 +static void coldfire_get_model(char *model)
565 +{
566 + sprintf(model, "Version 4 ColdFire");
567 +}
568 +
569 +/*
570 + * Setup the nodes and the boot memory.
571 + *
572 + * memory_start and memory_end are VIRTUAL addresses
573 + */
574 +static void __init
575 +coldfire_bootmem_alloc(unsigned long memory_start, unsigned long memory_end)
576 +{
577 + unsigned long base_pfn;
578 +
579 + /* compute total pages in system */
580 + num_pages = PAGE_ALIGN(memory_end - PAGE_OFFSET) >> PAGE_SHIFT;
581 +
582 + /* align start/end to page boundries */
583 + memory_start = PAGE_ALIGN(memory_start);
584 + memory_end = memory_end & PAGE_MASK;
585 +
586 + /* page numbers */
587 + base_pfn = __pa(PAGE_OFFSET) >> PAGE_SHIFT;
588 + min_low_pfn = __pa(memory_start) >> PAGE_SHIFT;
589 + max_low_pfn = __pa(memory_end) >> PAGE_SHIFT;
590 +
591 + high_memory = (void *)memory_end;
592 + availmem = memory_start;
593 +
594 + /* setup bootmem data */
595 + m68k_setup_node(0);
596 + availmem += init_bootmem_node(NODE_DATA(0), min_low_pfn,
597 + base_pfn, max_low_pfn);
598 + availmem = PAGE_ALIGN(availmem);
599 +
600 + printk(KERN_INFO "** availmem=0x%lx pa(am)=0x%lx\n",
601 + availmem, __pa(availmem));
602 + printk(KERN_INFO "** mstart=0x%lx mend=0x%lx\n",
603 + memory_start, memory_end);
604 + printk(KERN_INFO "bpfn=0x%lx minpfn=0x%lx maxpfn=0x%lx\n",
605 + base_pfn, min_low_pfn, max_low_pfn);
606 +
607 + /* turn over physram */
608 + free_bootmem(__pa(availmem), memory_end - availmem);
609 +
610 + /* configure physical dma area */
611 + cf_dma_base = __pa(PAGE_ALIGN(memory_start));
612 + cf_dma_size = CONFIG_DMA_SIZE;
613 + cf_dma_end = CONFIG_SDRAM_BASE + cf_dma_size - 1;
614 +
615 + printk(KERN_INFO "dma: phys base=0x%lx phys end=0x%lx virt base=0x%x\n",
616 + cf_dma_base, cf_dma_end, CONFIG_DMA_BASE);
617 +
618 + printk(KERN_INFO "mdma=0x%x pa(mdma)=0x%lx\n",
619 + MAX_DMA_ADDRESS, __pa(MAX_DMA_ADDRESS));
620 +}
621 +
622 +/*
623 + * Architecture setup for Coldfire
624 + */
625 +void __init config_coldfire(void)
626 +{
627 + unsigned long endmem, startmem;
628 +
629 + /*
630 + * Calculate endmem from m68k_memory[0] assuming that a single
631 + * chunk of ram is being configured.
632 + */
633 + startmem = ((((int) &_end) + (PAGE_SIZE - 1)) & PAGE_MASK);
634 + endmem = PAGE_OFFSET + m68k_memory[0].size;
635 +
636 + /* set virt to node shift to be the high nibble byte */
637 + m68k_virt_to_node_shift = 28;
638 +
639 + printk(KERN_INFO "starting up linux startmem 0x%lx, endmem 0x%lx, \
640 + size %luMB\n", startmem, endmem, (endmem - startmem) >> 20);
641 +
642 + memset(irq_enable, 0, sizeof(irq_enable));
643 +
644 + /*
645 + * Setup coldfire mach-specific handlers
646 + */
647 + mach_max_dma_address = 0xffffffff;
648 + mach_sched_init = coldfire_sched_init;
649 + mach_tick = coldfire_tick;
650 + mach_gettimeoffset = coldfire_gettimeoffset;
651 + mach_reset = coldfire_reboot;
652 + mach_get_model = coldfire_get_model;
653 +
654 + coldfire_bootmem_alloc(startmem, endmem-1);
655 +
656 +#if defined(CONFIG_DUMMY_CONSOLE) || defined(CONFIG_FRAMEBUFFER_CONSOLE)
657 + conswitchp = &dummy_con;
658 +#endif
659 +
660 +#if defined(CONFIG_SERIAL_COLDFIRE)
661 + /*
662 + * This causes trouble when it is re-registered later.
663 + * Currently this is fixed by conditionally commenting
664 + * out the register_console in mcf_serial.c
665 + */
666 +/*JKM -- moved earlier*/
667 + register_console(&mcfrs_console);
668 +#endif
669 +}
670 +
671 +#ifdef CONFIG_SRAM
672 +static int __init setup_sram_pool(void)
673 +{
674 + declare_sram_pool((void *)CONFIG_SRAM_BASE, CONFIG_SRAM_SIZE);
675 + return 0;
676 +}
677 +postcore_initcall(setup_sram_pool);
678 +#endif
679 --- /dev/null
680 +++ b/arch/m68k/coldfire/m5445x/devices.c
681 @@ -0,0 +1,527 @@
682 +/*
683 + * arch/m68k/coldfire/mcf5445x-devices.c
684 + *
685 + * Coldfire M5445x Platform Device Configuration
686 + *
687 + * Based on the Freescale MXC devices.c
688 + *
689 + * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
690 + * Kurt Mahan <kmahan@freescale.com>
691 + * Jason Jin Jason.Jin@freescale.com
692 + * Shrek Wu B16972@freescale.com
693 + *
694 + */
695 +#include <linux/module.h>
696 +#include <linux/kernel.h>
697 +#include <linux/init.h>
698 +#include <linux/platform_device.h>
699 +#include <linux/fsl_devices.h>
700 +#include <linux/spi/spi.h>
701 +
702 +#include <linux/interrupt.h>
703 +#include <linux/init.h>
704 +#ifdef CONFIG_MMC_SPI
705 +#include <linux/mmc/host.h>
706 +#include <linux/spi/mmc_spi.h>
707 +#endif
708 +
709 +#include <asm/coldfire.h>
710 +#include <asm/mcfsim.h>
711 +#include <asm/mcfuart.h>
712 +#include <asm/mcfqspi.h>
713 +#include <asm/mcfdspi.h>
714 +#include <asm/cf_io.h>
715 +
716 +/* ATA Interrupt */
717 +#define IRQ_ATA (64 + 64 + 54)
718 +
719 +/* ATA Base */
720 +void __iomem *io_ata_map;
721 +unsigned long io_ata_mapsize = 16 * 1024 * 1024;
722 +#define BASE_IO_ATA ((unsigned int)(io_ata_map))
723 +#define BASE_IO_ATA_PHY 0x90000000
724 +#define IO_ATA_MAP_OFFSET (BASE_IO_ATA-BASE_IO_ATA_PHY)
725 +
726 +/* conversion function between virtual address and physical address */
727 +unsigned int io_ata_virt2phys(void *x)
728 +{
729 + return (unsigned int)x - IO_ATA_MAP_OFFSET;
730 +}
731 +
732 +void *io_ata_phys2virt(unsigned int x)
733 +{
734 + return (void *)(x + IO_ATA_MAP_OFFSET);
735 +}
736 +
737 +#define ATA_IER MCF_REG08(BASE_IO_ATA+0x2c) /* int enable reg */
738 +#define ATA_ICR MCF_REG08(BASE_IO_ATA+0x30) /* int clear reg */
739 +
740 +/* DSPI */
741 +#define M5445X_DSPI_MCR 0xfc05c000 /* base */
742 +
743 +#define M5445X_DSPI_IRQ_SOURCE (31)
744 +#define M5445X_DSPI_IRQ_VECTOR (64 + M5445X_DSPI_IRQ_SOURCE)
745 +
746 +#define M5445X_AUDIO_IRQ_SOURCE (49) /* SSI interrupt */
747 +#define M5445X_AUDIO_IRQ_VECTOR (128+M5445X_AUDIO_IRQ_SOURCE)
748 +#define M5445X_AUDIO_IRQ_LEVEL (4)
749 +
750 +/* number of supported SPI selects */
751 +#define SPI_NUM_CHIPSELECTS 8
752 +
753 +#define M5445X_SPI_PAR_VAL (MCF_GPIO_PAR_DSPI_SCK | \
754 + MCF_GPIO_PAR_DSPI_SOUT | \
755 + MCF_GPIO_PAR_DSPI_SIN | \
756 + MCF_GPIO_PAR_DSPI_PCS5_PCS5 | \
757 + MCF_GPIO_PAR_DSPI_PCS1_PCS1 | \
758 + MCF_GPIO_PAR_DSPI_PCS0_PCS0)
759 +
760 +#ifdef CONFIG_SPI
761 +/*
762 + * DSPI
763 + */
764 +
765 +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
766 +static struct coldfire_dspi_chip spidev_chip_info = {
767 + .bits_per_word = 8,
768 +};
769 +#endif
770 +
771 +#if defined(CONFIG_SND_COLDFIRE) || defined(CONFIG_SND_COLDFIRE_MODULE)
772 +static struct coldfire_dspi_chip codec_spi_chip_info = {
773 + .mode = SPI_MODE_0,
774 + .bits_per_word = 16,
775 + .void_write_data = 0,
776 + .dbr = 0,
777 + .pbr = 2,
778 + .br = 8,
779 + .pcssck = 1,
780 + .pasc = 1,
781 + .pdt = 1,
782 + .cssck = 0,
783 + .asc = 1,
784 + .dt = 1,
785 +};
786 +#endif
787 +
788 +#if defined(CONFIG_MMC_SPI)
789 +int mmc_spi_init(struct device *mmc_spi_device,
790 + irqreturn_t mmc_spi_irq_handler(int irq, void *private),
791 + void *irq_privatedata)
792 +{
793 +#if 0
794 + MCF_GPIO_PAR_IRQ = MCF_GPIO_PAR_IRQ | MCF_GPIO_PAR_IRQ_IRQ4_GPIO;
795 + /* Set trailing edge for PCI interrupts */
796 + MCF_EPORT_EPPAR &= ~MCF_EPORT_EPPAR_EPPA4(3);
797 + MCF_EPORT_EPPAR |= MCF_EPORT_EPPAR_EPPA4_LEVEL;
798 + /* Turn on irq line in eport */
799 + MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE4;
800 +#endif
801 + MCF_EPORT_EPPAR &= ~MCF_EPORT_EPPAR_EPPA7(3);
802 + MCF_EPORT_EPPAR |= MCF_EPORT_EPPAR_EPPA7_BOTH;
803 + MCF_EPORT_EPIER = MCF_EPORT_EPIER | MCF_EPORT_EPIER_EPIE7;
804 +#if defined(CONFIG_M54451_SD_HW_DETECT)
805 + MCF_INTC0_ICR7 = 2;
806 + if (request_irq(64 + 7, mmc_spi_irq_handler,
807 + IRQF_DISABLED, "mmc_spi_irq", irq_privatedata)) {
808 + printk(KERN_INFO "Cannot allocate "
809 + "eport_irq_lines[%d] IRQ\n", 7);
810 + return -EBUSY;
811 + }
812 + printk(KERN_INFO " extern irq7 as sd card detect\n");
813 +#endif
814 + return 0;
815 +}
816 +
817 +static struct coldfire_dspi_chip dspi_sd_chip_info = {
818 + .mode = SPI_MODE_0,
819 + .bits_per_word = 8,
820 + .void_write_data = 0xff,
821 + .dbr = 0,
822 + .pbr = 1,
823 + .br = 1,
824 + .pcssck = 2,
825 + .pasc = 2,
826 + .pdt = 2,
827 + .cssck = 5,
828 + .asc = 5,
829 + .dt = 5,
830 +};
831 +
832 +static struct mmc_spi_platform_data mcf54451_mmc_pdata = {
833 + .ocr_mask = MMC_VDD_33_34,
834 + .init = mmc_spi_init,
835 +};
836 +#endif
837 +
838 +#if defined(CONFIG_VOIP_FXS) || defined(CONFIG_VOIP_FXS_MODULE)
839 +static struct coldfire_dspi_chip fxs_chip_info = {
840 + .mode = SPI_MODE_3,
841 + .bits_per_word = 8,
842 + .void_write_data = 0,
843 + .dbr = 0,
844 + .pbr = 1,
845 + .br = 1,
846 + .pcssck = 0,
847 + .pasc = 0,
848 + .pdt = 0,
849 + .cssck = 0,
850 + .asc = 0,
851 + .dt = 0,
852 +};
853 +#endif
854 +
855 +#if defined(CONFIG_VOIP_FXO) || defined(CONFIG_VOIP_FXO_MODULE)
856 +static struct coldfire_dspi_chip fxo_chip_info = {
857 + .mode = SPI_MODE_3,
858 + .bits_per_word = 8,
859 + .void_write_data = 0,
860 + .dbr = 0,
861 + .pbr = 1,
862 + .br = 1,
863 + .pcssck = 0,
864 + .pasc = 0,
865 + .pdt = 0,
866 + .cssck = 0,
867 + .asc = 0,
868 + .dt = 0,
869 +};
870 +#endif
871 +
872 +static struct spi_board_info spi_board_info[] = {
873 +#if defined(CONFIG_SND_COLDFIRE) || defined(CONFIG_SND_COLDFIRE_MODULE)
874 + {
875 + .modalias = "mcf_codec_spi",
876 + .max_speed_hz = 300000,
877 + .bus_num = 1,
878 + .chip_select = 5,
879 + .irq = M5445X_AUDIO_IRQ_VECTOR,
880 + .platform_data = NULL,
881 + .controller_data = &codec_spi_chip_info
882 + },
883 +#endif
884 +
885 +#if defined(CONFIG_VOIP_FXS) || defined(CONFIG_VOIP_FXS_MODULE)
886 + {
887 + .modalias = "spi_fxs",
888 + .max_speed_hz = 10000000, /* max spi clock in HZ */
889 + .bus_num = 1,
890 + .chip_select = 2,
891 + .controller_data = &fxs_chip_info
892 + },
893 +#endif
894 +
895 +#if defined(CONFIG_VOIP_FXO) || defined(CONFIG_VOIP_FXO_MODULE)
896 + {
897 + .modalias = "spi_fxo",
898 + .max_speed_hz = 10000000, /* max spi clock in HZ */
899 + .bus_num = 1,
900 + .chip_select = 3,
901 + .controller_data = &fxo_chip_info
902 + },
903 +#endif
904 +
905 +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
906 + {
907 + .modalias = "spidev",
908 + .max_speed_hz = 16000000, /* max clk (SCK) speed in HZ */
909 + .bus_num = 1,
910 + .chip_select = 0, /* CS0 */
911 + .controller_data = &spidev_chip_info,
912 + },
913 +#endif
914 +
915 +#if defined(CONFIG_MMC_SPI)
916 + {
917 + .modalias = "mmc_spi",
918 + .max_speed_hz = 25000000,
919 + .bus_num = 1,
920 + .chip_select = 0,
921 + .platform_data = &mcf54451_mmc_pdata,
922 + .controller_data = &dspi_sd_chip_info,
923 + },
924 +#endif
925 +};
926 +
927 +
928 +static struct coldfire_spi_master coldfire_master_info = {
929 + .bus_num = 1,
930 + .num_chipselect = SPI_NUM_CHIPSELECTS,
931 + .irq_list = 0, /* not used */
932 + .irq_source = M5445X_DSPI_IRQ_SOURCE,
933 + .irq_vector = M5445X_DSPI_IRQ_VECTOR,
934 + .irq_mask = (1 << M5445X_DSPI_IRQ_SOURCE),
935 + .irq_lp = 0x2, /* irq level */
936 + .par_val = M5445X_SPI_PAR_VAL,
937 + .cs_control = NULL,
938 +};
939 +
940 +static struct resource coldfire_spi_resources[] = {
941 + [0] = {
942 + .name = "spi-par",
943 + .start = (u32)&MCF_GPIO_PAR_DSPI, /* PAR_DSPI */
944 + .end = (u32)&MCF_GPIO_PAR_DSPI, /* PAR_DSPI */
945 + .flags = IORESOURCE_MEM
946 + },
947 +
948 + [1] = {
949 + .name = "spi-module",
950 + .start = M5445X_DSPI_MCR, /* DSPI MCR Base */
951 + .end = M5445X_DSPI_MCR + 0xc0, /* DSPI mem map end */
952 + .flags = IORESOURCE_MEM
953 + },
954 +
955 + [2] = {
956 + .name = "spi-int-level",
957 + .start = (u32)&MCF_INTC0_ICR31, /* ICR start */
958 + .end = (u32)&MCF_INTC0_ICR31, /* ICR end */
959 + .flags = IORESOURCE_MEM
960 + },
961 +
962 + [3] = {
963 + .name = "spi-int-mask",
964 + .start = (u32)&MCF_INTC0_IMRL, /* IMRL */
965 + .end = (u32)&MCF_INTC0_IMRL, /* IMRL */
966 + .flags = IORESOURCE_MEM
967 + }
968 +};
969 +
970 +static struct platform_device coldfire_spi = {
971 + .name = "spi_coldfire",
972 + .id = -1,
973 + .resource = coldfire_spi_resources,
974 + .num_resources = ARRAY_SIZE(coldfire_spi_resources),
975 + .dev = {
976 + .platform_data = &coldfire_master_info,
977 + }
978 +};
979 +
980 +/**
981 + * m5445x_spi_init - Initialize SPI
982 + */
983 +static int __init m5445x_spi_init(void)
984 +{
985 + int retval;
986 +
987 + /* register device */
988 + retval = platform_device_register(&coldfire_spi);
989 + if (retval < 0)
990 + goto out;
991 +
992 + /* register board info */
993 + if (ARRAY_SIZE(spi_board_info))
994 + retval = spi_register_board_info(spi_board_info,
995 + ARRAY_SIZE(spi_board_info));
996 +
997 +out:
998 + return retval;
999 +}
1000 +#endif
1001 +
1002 +/*
1003 + * On-chip PATA
1004 + */
1005 +#if defined(CONFIG_PATA_FSL) || defined(CONFIG_PATA_FSL_MODULE)
1006 +static int ata_init(struct platform_device *pdev)
1007 +{
1008 + /* clear ints */
1009 + ATA_IER = 0x00;
1010 + ATA_ICR = 0xff;
1011 +
1012 + /* setup shared pins */
1013 + MCF_GPIO_PAR_FEC = (MCF_GPIO_PAR_FEC & MCF_GPIO_PAR_FEC_FEC1_MASK) |
1014 + MCF_GPIO_PAR_FEC_FEC1_ATA;
1015 +
1016 + MCF_GPIO_PAR_FECI2C = (MCF_GPIO_PAR_FECI2C &
1017 + (MCF_GPIO_PAR_FECI2C_MDC1_MASK &
1018 + MCF_GPIO_PAR_FECI2C_MDIO1_MASK)) |
1019 + MCF_GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
1020 + MCF_GPIO_PAR_FECI2C_MDIO1_ATA_DIOW;
1021 +
1022 + MCF_GPIO_PAR_ATA = MCF_GPIO_PAR_ATA_BUFEN |
1023 + MCF_GPIO_PAR_ATA_CS1 |
1024 + MCF_GPIO_PAR_ATA_CS0 |
1025 + MCF_GPIO_PAR_ATA_DA2 |
1026 + MCF_GPIO_PAR_ATA_DA1 |
1027 + MCF_GPIO_PAR_ATA_DA0 |
1028 + MCF_GPIO_PAR_ATA_RESET_RESET |
1029 + MCF_GPIO_PAR_ATA_DMARQ_DMARQ |
1030 + MCF_GPIO_PAR_ATA_IORDY_IORDY;
1031 +
1032 + MCF_GPIO_PAR_PCI = (MCF_GPIO_PAR_PCI &
1033 + (MCF_GPIO_PAR_PCI_GNT3_MASK &
1034 + MCF_GPIO_PAR_PCI_REQ3_MASK)) |
1035 + MCF_GPIO_PAR_PCI_GNT3_ATA_DMACK |
1036 + MCF_GPIO_PAR_PCI_REQ3_ATA_INTRQ;
1037 +
1038 + return 0;
1039 +}
1040 +
1041 +static void ata_exit(void)
1042 +{
1043 + printk(KERN_INFO "** ata_exit\n");
1044 +}
1045 +
1046 +static int ata_get_clk_rate(void)
1047 +{
1048 + return MCF_BUSCLK;
1049 +}
1050 +
1051 +
1052 +static struct fsl_ata_platform_data ata_data = {
1053 + .init = ata_init,
1054 + .exit = ata_exit,
1055 + .get_clk_rate = ata_get_clk_rate,
1056 +};
1057 +
1058 +static struct resource pata_fsl_resources[] = {
1059 + [0] = { /* I/O */
1060 + .flags = IORESOURCE_MEM,
1061 + },
1062 + [2] = { /* IRQ */
1063 + .start = IRQ_ATA,
1064 + .end = IRQ_ATA,
1065 + .flags = IORESOURCE_IRQ,
1066 + },
1067 +};
1068 +
1069 +static struct platform_device pata_fsl_device = {
1070 + .name = "pata_fsl",
1071 + .id = -1,
1072 + .num_resources = ARRAY_SIZE(pata_fsl_resources),
1073 + .resource = pata_fsl_resources,
1074 + .dev = {
1075 + .platform_data = &ata_data,
1076 + .coherent_dma_mask = ~0, /* $$$ REVISIT */
1077 + },
1078 +};
1079 +
1080 +static inline void mcf5445x_init_pata(void)
1081 +{
1082 + io_ata_map = ioremap(BASE_IO_ATA_PHY, io_ata_mapsize);
1083 + if (!io_ata_map) {
1084 + printk(KERN_ERR "IO ATA map failed by ioremap!\n");
1085 + return;
1086 + }
1087 + printk(KERN_INFO "BASE_IO_ATA value is 0x%x\n", BASE_IO_ATA);
1088 +
1089 + pata_fsl_resources[0].start = BASE_IO_ATA;
1090 + pata_fsl_resources[0].end = BASE_IO_ATA + 0x000000d8;
1091 +
1092 + (void)platform_device_register(&pata_fsl_device);
1093 +}
1094 +#endif
1095 +
1096 +/*
1097 + * I2C
1098 + */
1099 +#if defined(CONFIG_I2C)
1100 +static struct resource coldfire_i2c_resources[] = {
1101 + { /* I/O */
1102 + .start = 0xFC058000,
1103 + .end = 0xFC058010,
1104 + .flags = IORESOURCE_MEM,
1105 + },
1106 + { /* IRQ */
1107 + .start = (64 + 30),
1108 + .end = (64 + 30),
1109 + .flags = IORESOURCE_IRQ,
1110 + },
1111 +};
1112 +
1113 +static struct platform_device coldfire_i2c_device = {
1114 + .name = "mcf-i2c",
1115 + .id = 0, /*bus number*/
1116 + .num_resources = ARRAY_SIZE(coldfire_i2c_resources),
1117 + .resource = coldfire_i2c_resources,
1118 +};
1119 +
1120 +static void mcf5445x_init_i2c(void)
1121 +{
1122 + platform_device_register(&coldfire_i2c_device);
1123 +}
1124 +#endif
1125 +
1126 +static int __init mcf5445x_init_devices(void)
1127 +{
1128 + printk(KERN_INFO "mcf5445x_init_devices: %s.\n", __func__);
1129 +#ifdef CONFIG_SPI
1130 + m5445x_spi_init();
1131 +#endif
1132 +
1133 +#if defined(CONFIG_PATA_FSL) || defined(CONFIG_PATA_FSL_MODULE)
1134 + mcf5445x_init_pata();
1135 +#endif
1136 +
1137 +#if defined(CONFIG_I2C)
1138 + mcf5445x_init_i2c();
1139 +#endif
1140 + return 0;
1141 +}
1142 +arch_initcall(mcf5445x_init_devices);
1143 +
1144 +/***************************************************************************/
1145 +static struct mcf_platform_uart m5445x_uart_platform[] = {
1146 + {
1147 + .mapbase = MCFUART_BASE1,
1148 + .irq = MCFINT_VECBASE + MCFINT_UART0,
1149 + },
1150 +#ifdef CONFIG_M54455
1151 + {
1152 + .mapbase = MCFUART_BASE2,
1153 + .irq = MCFINT_VECBASE + MCFINT_UART1,
1154 + },
1155 +#endif
1156 + { },
1157 +};
1158 +
1159 +static struct platform_device m5445x_uart = {
1160 + .name = "mcfuart",
1161 + .id = 0,
1162 + .dev.platform_data = m5445x_uart_platform,
1163 +};
1164 +
1165 +#if defined(CONFIG_RTC_MCF) || defined(CONFIG_RTC_MCF_MODULE)
1166 +static struct platform_device rtc_device = {
1167 + .name = "mcf-rtc",
1168 + .id = -1,
1169 +};
1170 +#endif
1171 +
1172 +static struct platform_device *m5445x_devices[] __initdata = {
1173 + &m5445x_uart,
1174 +#if defined(CONFIG_RTC_MCF) || defined(CONFIG_RTC_MCF_MODULE)
1175 + &rtc_device,
1176 +#endif
1177 +};
1178 +
1179 +
1180 +static void m5445x_uart_init_line(int line, int irq)
1181 +{
1182 + if (line == 0)
1183 + MCF_GPIO_PAR_UART = (0 | 0x000F);
1184 + else if (line == 1)
1185 + MCF_GPIO_PAR_UART |= (0 | 0x0FF0);
1186 +}
1187 +
1188 +void m5445x_uarts_init(void)
1189 +{
1190 + const int nrlines = ARRAY_SIZE(m5445x_uart_platform);
1191 + int line;
1192 +
1193 + for (line = 0; (line < nrlines); line++)
1194 + m5445x_uart_init_line(line, m5445x_uart_platform[line].irq);
1195 +}
1196 +/****************************************************************************/
1197 +/***************************************************************************/
1198 +
1199 +static int __init init_BSP(void)
1200 +{
1201 + m5445x_uarts_init();
1202 + platform_add_devices(m5445x_devices, ARRAY_SIZE(m5445x_devices));
1203 + return 0;
1204 +}
1205 +
1206 +arch_initcall(init_BSP);
1207 +
1208 +
1209 --- /dev/null
1210 +++ b/arch/m68k/configs/m54451evb_defconfig
1211 @@ -0,0 +1,1412 @@
1212 +#
1213 +# Automatically generated make config: don't edit
1214 +# Linux kernel version: 2.6.29
1215 +# Tue Aug 24 16:14:20 2010
1216 +#
1217 +CONFIG_M68K=y
1218 +CONFIG_MMU=y
1219 +CONFIG_GENERIC_TIME=y
1220 +CONFIG_GENERIC_CLOCKEVENTS=y
1221 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
1222 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
1223 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
1224 +CONFIG_GENERIC_HWEIGHT=y
1225 +CONFIG_GENERIC_CALIBRATE_DELAY=y
1226 +# CONFIG_TIME_LOW_RES is not set
1227 +CONFIG_GENERIC_IOMAP=y
1228 +# CONFIG_NO_IOPORT is not set
1229 +# CONFIG_NO_DMA is not set
1230 +CONFIG_HZ=100
1231 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
1232 +
1233 +#
1234 +# General setup
1235 +#
1236 +CONFIG_EXPERIMENTAL=y
1237 +CONFIG_BROKEN_ON_SMP=y
1238 +CONFIG_INIT_ENV_ARG_LIMIT=32
1239 +CONFIG_LOCALVERSION=""
1240 +# CONFIG_LOCALVERSION_AUTO is not set
1241 +CONFIG_SWAP=y
1242 +CONFIG_SYSVIPC=y
1243 +CONFIG_SYSVIPC_SYSCTL=y
1244 +# CONFIG_POSIX_MQUEUE is not set
1245 +# CONFIG_BSD_PROCESS_ACCT is not set
1246 +# CONFIG_TASKSTATS is not set
1247 +# CONFIG_AUDIT is not set
1248 +
1249 +#
1250 +# RCU Subsystem
1251 +#
1252 +CONFIG_CLASSIC_RCU=y
1253 +# CONFIG_TREE_RCU is not set
1254 +# CONFIG_PREEMPT_RCU is not set
1255 +# CONFIG_TREE_RCU_TRACE is not set
1256 +# CONFIG_PREEMPT_RCU_TRACE is not set
1257 +CONFIG_IKCONFIG=y
1258 +CONFIG_IKCONFIG_PROC=y
1259 +CONFIG_LOG_BUF_SHIFT=17
1260 +CONFIG_GROUP_SCHED=y
1261 +CONFIG_FAIR_GROUP_SCHED=y
1262 +# CONFIG_RT_GROUP_SCHED is not set
1263 +CONFIG_USER_SCHED=y
1264 +# CONFIG_CGROUP_SCHED is not set
1265 +# CONFIG_CGROUPS is not set
1266 +CONFIG_SYSFS_DEPRECATED=y
1267 +CONFIG_SYSFS_DEPRECATED_V2=y
1268 +# CONFIG_RELAY is not set
1269 +CONFIG_NAMESPACES=y
1270 +# CONFIG_UTS_NS is not set
1271 +# CONFIG_IPC_NS is not set
1272 +# CONFIG_USER_NS is not set
1273 +# CONFIG_PID_NS is not set
1274 +# CONFIG_NET_NS is not set
1275 +CONFIG_BLK_DEV_INITRD=y
1276 +CONFIG_INITRAMFS_SOURCE=""
1277 +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
1278 +CONFIG_SYSCTL=y
1279 +CONFIG_ANON_INODES=y
1280 +CONFIG_EMBEDDED=y
1281 +CONFIG_UID16=y
1282 +CONFIG_SYSCTL_SYSCALL=y
1283 +CONFIG_KALLSYMS=y
1284 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
1285 +CONFIG_HOTPLUG=y
1286 +CONFIG_PRINTK=y
1287 +CONFIG_BUG=y
1288 +CONFIG_ELF_CORE=y
1289 +CONFIG_BASE_FULL=y
1290 +CONFIG_FUTEX=y
1291 +CONFIG_EPOLL=y
1292 +CONFIG_SIGNALFD=y
1293 +CONFIG_TIMERFD=y
1294 +CONFIG_EVENTFD=y
1295 +CONFIG_SHMEM=y
1296 +CONFIG_AIO=y
1297 +CONFIG_VM_EVENT_COUNTERS=y
1298 +CONFIG_COMPAT_BRK=y
1299 +CONFIG_SLAB=y
1300 +# CONFIG_SLUB is not set
1301 +# CONFIG_SLOB is not set
1302 +# CONFIG_PROFILING is not set
1303 +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
1304 +CONFIG_SLABINFO=y
1305 +CONFIG_RT_MUTEXES=y
1306 +CONFIG_BASE_SMALL=0
1307 +CONFIG_MODULES=y
1308 +# CONFIG_MODULE_FORCE_LOAD is not set
1309 +CONFIG_MODULE_UNLOAD=y
1310 +CONFIG_MODULE_FORCE_UNLOAD=y
1311 +# CONFIG_MODVERSIONS is not set
1312 +# CONFIG_MODULE_SRCVERSION_ALL is not set
1313 +CONFIG_BLOCK=y
1314 +CONFIG_LBD=y
1315 +# CONFIG_BLK_DEV_IO_TRACE is not set
1316 +# CONFIG_BLK_DEV_BSG is not set
1317 +# CONFIG_BLK_DEV_INTEGRITY is not set
1318 +
1319 +#
1320 +# IO Schedulers
1321 +#
1322 +CONFIG_IOSCHED_NOOP=y
1323 +CONFIG_IOSCHED_AS=y
1324 +CONFIG_IOSCHED_DEADLINE=y
1325 +CONFIG_IOSCHED_CFQ=y
1326 +# CONFIG_DEFAULT_AS is not set
1327 +# CONFIG_DEFAULT_DEADLINE is not set
1328 +CONFIG_DEFAULT_CFQ=y
1329 +# CONFIG_DEFAULT_NOOP is not set
1330 +CONFIG_DEFAULT_IOSCHED="cfq"
1331 +# CONFIG_FREEZER is not set
1332 +
1333 +#
1334 +# Platform dependent setup
1335 +#
1336 +CONFIG_COLDFIRE=y
1337 +CONFIG_CFV4E=y
1338 +# CONFIG_FPU is not set
1339 +# CONFIG_AMIGA is not set
1340 +# CONFIG_ATARI is not set
1341 +# CONFIG_MAC is not set
1342 +# CONFIG_APOLLO is not set
1343 +# CONFIG_VME is not set
1344 +# CONFIG_HP300 is not set
1345 +# CONFIG_SUN3X is not set
1346 +# CONFIG_Q40 is not set
1347 +# CONFIG_SUN3 is not set
1348 +
1349 +#
1350 +# Processor type
1351 +#
1352 +# CONFIG_M68020 is not set
1353 +# CONFIG_M68030 is not set
1354 +# CONFIG_M68040 is not set
1355 +# CONFIG_M68060 is not set
1356 +CONFIG_M5445X=y
1357 +CONFIG_M54451=y
1358 +# CONFIG_M54455 is not set
1359 +CONFIG_M54451EVB=y
1360 +# CONFIG_M54455EVB is not set
1361 +CONFIG_HAVE_FSL_USB_DR=y
1362 +# CONFIG_M547X_8X is not set
1363 +# CONFIG_M5441X is not set
1364 +CONFIG_MCFCLK=240000000
1365 +# CONFIG_MCF_USER_HALT is not set
1366 +CONFIG_MMU_CFV4E=y
1367 +CONFIG_SDRAM_BASE=0x40000000
1368 +CONFIG_SDRAM_SIZE=0x08000000
1369 +CONFIG_NOR_FLASH_BASE=0x00000000
1370 +CONFIG_DMA_BASE=0xef000000
1371 +CONFIG_DMA_SIZE=0x1000000
1372 +CONFIG_SRAM=y
1373 +CONFIG_SRAM_BASE=0x8ff00000
1374 +CONFIG_SRAM_SIZE=0x8000
1375 +CONFIG_SRAM_ALLOC_GRANULARITY=0x200
1376 +CONFIG_VDSO=y
1377 +# CONFIG_M68KFPU_EMU is not set
1378 +CONFIG_ADVANCED=y
1379 +# CONFIG_RMW_INSNS is not set
1380 +CONFIG_SINGLE_MEMORY_CHUNK=y
1381 +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
1382 +CONFIG_SELECT_MEMORY_MODEL=y
1383 +CONFIG_FLATMEM_MANUAL=y
1384 +# CONFIG_DISCONTIGMEM_MANUAL is not set
1385 +# CONFIG_SPARSEMEM_MANUAL is not set
1386 +CONFIG_FLATMEM=y
1387 +CONFIG_FLAT_NODE_MEM_MAP=y
1388 +CONFIG_NEED_MULTIPLE_NODES=y
1389 +CONFIG_PAGEFLAGS_EXTENDED=y
1390 +CONFIG_SPLIT_PTLOCK_CPUS=4
1391 +# CONFIG_PHYS_ADDR_T_64BIT is not set
1392 +CONFIG_ZONE_DMA_FLAG=1
1393 +CONFIG_BOUNCE=y
1394 +CONFIG_VIRT_TO_BUS=y
1395 +CONFIG_UNEVICTABLE_LRU=y
1396 +
1397 +#
1398 +# General setup
1399 +#
1400 +CONFIG_BINFMT_ELF=y
1401 +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
1402 +CONFIG_HAVE_AOUT=y
1403 +# CONFIG_BINFMT_AOUT is not set
1404 +# CONFIG_BINFMT_MISC is not set
1405 +CONFIG_PROC_HARDWARE=y
1406 +CONFIG_ZONE_DMA=y
1407 +# CONFIG_ARCH_SUPPORTS_MSI is not set
1408 +
1409 +#
1410 +# Power management options
1411 +#
1412 +CONFIG_PM=y
1413 +CONFIG_NET=y
1414 +
1415 +#
1416 +# Networking options
1417 +#
1418 +CONFIG_COMPAT_NET_DEV_OPS=y
1419 +CONFIG_PACKET=y
1420 +# CONFIG_PACKET_MMAP is not set
1421 +CONFIG_UNIX=y
1422 +CONFIG_XFRM=y
1423 +# CONFIG_XFRM_USER is not set
1424 +# CONFIG_XFRM_SUB_POLICY is not set
1425 +# CONFIG_XFRM_MIGRATE is not set
1426 +# CONFIG_XFRM_STATISTICS is not set
1427 +CONFIG_NET_KEY=y
1428 +# CONFIG_NET_KEY_MIGRATE is not set
1429 +CONFIG_INET=y
1430 +# CONFIG_IP_MULTICAST is not set
1431 +CONFIG_IP_ADVANCED_ROUTER=y
1432 +CONFIG_ASK_IP_FIB_HASH=y
1433 +# CONFIG_IP_FIB_TRIE is not set
1434 +CONFIG_IP_FIB_HASH=y
1435 +# CONFIG_IP_MULTIPLE_TABLES is not set
1436 +# CONFIG_IP_ROUTE_MULTIPATH is not set
1437 +# CONFIG_IP_ROUTE_VERBOSE is not set
1438 +CONFIG_IP_PNP=y
1439 +# CONFIG_IP_PNP_DHCP is not set
1440 +# CONFIG_IP_PNP_BOOTP is not set
1441 +# CONFIG_IP_PNP_RARP is not set
1442 +# CONFIG_NET_IPIP is not set
1443 +# CONFIG_NET_IPGRE is not set
1444 +# CONFIG_ARPD is not set
1445 +# CONFIG_SYN_COOKIES is not set
1446 +CONFIG_INET_AH=y
1447 +CONFIG_INET_ESP=y
1448 +# CONFIG_INET_IPCOMP is not set
1449 +# CONFIG_INET_XFRM_TUNNEL is not set
1450 +# CONFIG_INET_TUNNEL is not set
1451 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
1452 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
1453 +# CONFIG_INET_XFRM_MODE_BEET is not set
1454 +# CONFIG_INET_LRO is not set
1455 +CONFIG_INET_DIAG=y
1456 +CONFIG_INET_TCP_DIAG=y
1457 +# CONFIG_TCP_CONG_ADVANCED is not set
1458 +CONFIG_TCP_CONG_CUBIC=y
1459 +CONFIG_DEFAULT_TCP_CONG="cubic"
1460 +# CONFIG_TCP_MD5SIG is not set
1461 +# CONFIG_IPV6 is not set
1462 +# CONFIG_NETWORK_SECMARK is not set
1463 +# CONFIG_NETFILTER is not set
1464 +# CONFIG_IP_DCCP is not set
1465 +# CONFIG_IP_SCTP is not set
1466 +# CONFIG_TIPC is not set
1467 +# CONFIG_ATM is not set
1468 +# CONFIG_BRIDGE is not set
1469 +# CONFIG_NET_DSA is not set
1470 +# CONFIG_VLAN_8021Q is not set
1471 +# CONFIG_DECNET is not set
1472 +# CONFIG_LLC2 is not set
1473 +# CONFIG_IPX is not set
1474 +# CONFIG_ATALK is not set
1475 +# CONFIG_X25 is not set
1476 +# CONFIG_LAPB is not set
1477 +# CONFIG_ECONET is not set
1478 +# CONFIG_WAN_ROUTER is not set
1479 +# CONFIG_NET_SCHED is not set
1480 +# CONFIG_DCB is not set
1481 +
1482 +#
1483 +# Network testing
1484 +#
1485 +# CONFIG_NET_PKTGEN is not set
1486 +# CONFIG_HAMRADIO is not set
1487 +# CONFIG_CAN is not set
1488 +# CONFIG_IRDA is not set
1489 +# CONFIG_BT is not set
1490 +# CONFIG_AF_RXRPC is not set
1491 +# CONFIG_PHONET is not set
1492 +CONFIG_WIRELESS=y
1493 +# CONFIG_CFG80211 is not set
1494 +CONFIG_WIRELESS_OLD_REGULATORY=y
1495 +# CONFIG_WIRELESS_EXT is not set
1496 +# CONFIG_LIB80211 is not set
1497 +# CONFIG_MAC80211 is not set
1498 +# CONFIG_WIMAX is not set
1499 +# CONFIG_RFKILL is not set
1500 +# CONFIG_NET_9P is not set
1501 +# CONFIG_KLIPS is not set
1502 +
1503 +#
1504 +# Device Drivers
1505 +#
1506 +
1507 +#
1508 +# Generic Driver Options
1509 +#
1510 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
1511 +# CONFIG_STANDALONE is not set
1512 +CONFIG_PREVENT_FIRMWARE_BUILD=y
1513 +CONFIG_FW_LOADER=y
1514 +CONFIG_FIRMWARE_IN_KERNEL=y
1515 +CONFIG_EXTRA_FIRMWARE=""
1516 +# CONFIG_SYS_HYPERVISOR is not set
1517 +# CONFIG_CONNECTOR is not set
1518 +CONFIG_MTD=y
1519 +# CONFIG_MTD_DEBUG is not set
1520 +CONFIG_MTD_CONCAT=y
1521 +CONFIG_MTD_PARTITIONS=y
1522 +# CONFIG_MTD_TESTS is not set
1523 +# CONFIG_MTD_REDBOOT_PARTS is not set
1524 +CONFIG_MTD_CMDLINE_PARTS=y
1525 +# CONFIG_MTD_AR7_PARTS is not set
1526 +
1527 +#
1528 +# User Modules And Translation Layers
1529 +#
1530 +CONFIG_MTD_CHAR=y
1531 +CONFIG_MTD_BLKDEVS=y
1532 +CONFIG_MTD_BLOCK=y
1533 +# CONFIG_FTL is not set
1534 +# CONFIG_NFTL is not set
1535 +# CONFIG_INFTL is not set
1536 +# CONFIG_RFD_FTL is not set
1537 +# CONFIG_SSFDC is not set
1538 +# CONFIG_MTD_OOPS is not set
1539 +
1540 +#
1541 +# RAM/ROM/Flash chip drivers
1542 +#
1543 +CONFIG_MTD_CFI=y
1544 +# CONFIG_MTD_JEDECPROBE is not set
1545 +CONFIG_MTD_GEN_PROBE=y
1546 +CONFIG_MTD_CFI_ADV_OPTIONS=y
1547 +CONFIG_MTD_CFI_NOSWAP=y
1548 +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
1549 +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
1550 +CONFIG_MTD_CFI_GEOMETRY=y
1551 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
1552 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
1553 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
1554 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
1555 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
1556 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
1557 +CONFIG_MTD_CFI_I1=y
1558 +CONFIG_MTD_CFI_I2=y
1559 +# CONFIG_MTD_CFI_I4 is not set
1560 +# CONFIG_MTD_CFI_I8 is not set
1561 +# CONFIG_MTD_OTP is not set
1562 +CONFIG_MTD_CFI_INTELEXT=y
1563 +CONFIG_MTD_CFI_AMDSTD=y
1564 +CONFIG_MTD_CFI_STAA=y
1565 +CONFIG_MTD_CFI_UTIL=y
1566 +CONFIG_MTD_RAM=y
1567 +# CONFIG_MTD_ROM is not set
1568 +# CONFIG_MTD_ABSENT is not set
1569 +
1570 +#
1571 +# Mapping drivers for chip access
1572 +#
1573 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
1574 +CONFIG_MTD_PHYSMAP=y
1575 +CONFIG_MTD_PHYSMAP_COMPAT=y
1576 +CONFIG_MTD_PHYSMAP_START=0x0
1577 +CONFIG_MTD_PHYSMAP_LEN=0x01000000
1578 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2
1579 +# CONFIG_MTD_PLATRAM is not set
1580 +
1581 +#
1582 +# Self-contained MTD device drivers
1583 +#
1584 +# CONFIG_MTD_DATAFLASH is not set
1585 +# CONFIG_MTD_M25P80 is not set
1586 +# CONFIG_MTD_SLRAM is not set
1587 +# CONFIG_MTD_PHRAM is not set
1588 +# CONFIG_MTD_MTDRAM is not set
1589 +# CONFIG_MTD_BLOCK2MTD is not set
1590 +
1591 +#
1592 +# Disk-On-Chip Device Drivers
1593 +#
1594 +# CONFIG_MTD_DOC2000 is not set
1595 +# CONFIG_MTD_DOC2001 is not set
1596 +# CONFIG_MTD_DOC2001PLUS is not set
1597 +# CONFIG_MTD_NAND is not set
1598 +# CONFIG_MTD_ONENAND is not set
1599 +
1600 +#
1601 +# LPDDR flash memory drivers
1602 +#
1603 +# CONFIG_MTD_LPDDR is not set
1604 +
1605 +#
1606 +# UBI - Unsorted block images
1607 +#
1608 +# CONFIG_MTD_UBI is not set
1609 +# CONFIG_PARPORT is not set
1610 +CONFIG_BLK_DEV=y
1611 +# CONFIG_BLK_DEV_COW_COMMON is not set
1612 +CONFIG_BLK_DEV_LOOP=y
1613 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
1614 +# CONFIG_BLK_DEV_NBD is not set
1615 +# CONFIG_BLK_DEV_UB is not set
1616 +CONFIG_BLK_DEV_RAM=y
1617 +CONFIG_BLK_DEV_RAM_COUNT=16
1618 +CONFIG_BLK_DEV_RAM_SIZE=64000
1619 +# CONFIG_BLK_DEV_XIP is not set
1620 +# CONFIG_CDROM_PKTCDVD is not set
1621 +# CONFIG_ATA_OVER_ETH is not set
1622 +# CONFIG_BLK_DEV_HD is not set
1623 +CONFIG_MISC_DEVICES=y
1624 +# CONFIG_ICS932S401 is not set
1625 +# CONFIG_ENCLOSURE_SERVICES is not set
1626 +# CONFIG_C2PORT is not set
1627 +
1628 +#
1629 +# EEPROM support
1630 +#
1631 +# CONFIG_EEPROM_AT24 is not set
1632 +# CONFIG_EEPROM_AT25 is not set
1633 +# CONFIG_EEPROM_LEGACY is not set
1634 +# CONFIG_EEPROM_93CX6 is not set
1635 +CONFIG_HAVE_IDE=y
1636 +# CONFIG_IDE is not set
1637 +
1638 +#
1639 +# SCSI device support
1640 +#
1641 +# CONFIG_RAID_ATTRS is not set
1642 +CONFIG_SCSI=y
1643 +CONFIG_SCSI_DMA=y
1644 +# CONFIG_SCSI_TGT is not set
1645 +# CONFIG_SCSI_NETLINK is not set
1646 +CONFIG_SCSI_PROC_FS=y
1647 +
1648 +#
1649 +# SCSI support type (disk, tape, CD-ROM)
1650 +#
1651 +CONFIG_BLK_DEV_SD=y
1652 +# CONFIG_CHR_DEV_ST is not set
1653 +# CONFIG_CHR_DEV_OSST is not set
1654 +# CONFIG_BLK_DEV_SR is not set
1655 +# CONFIG_CHR_DEV_SG is not set
1656 +# CONFIG_CHR_DEV_SCH is not set
1657 +
1658 +#
1659 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
1660 +#
1661 +CONFIG_SCSI_MULTI_LUN=y
1662 +# CONFIG_SCSI_CONSTANTS is not set
1663 +# CONFIG_SCSI_LOGGING is not set
1664 +# CONFIG_SCSI_SCAN_ASYNC is not set
1665 +CONFIG_SCSI_WAIT_SCAN=m
1666 +
1667 +#
1668 +# SCSI Transports
1669 +#
1670 +# CONFIG_SCSI_SPI_ATTRS is not set
1671 +# CONFIG_SCSI_FC_ATTRS is not set
1672 +# CONFIG_SCSI_ISCSI_ATTRS is not set
1673 +# CONFIG_SCSI_SAS_LIBSAS is not set
1674 +# CONFIG_SCSI_SRP_ATTRS is not set
1675 +CONFIG_SCSI_LOWLEVEL=y
1676 +# CONFIG_ISCSI_TCP is not set
1677 +# CONFIG_LIBFC is not set
1678 +# CONFIG_SCSI_DEBUG is not set
1679 +# CONFIG_SCSI_DH is not set
1680 +# CONFIG_ATA is not set
1681 +# CONFIG_MD is not set
1682 +CONFIG_NETDEVICES=y
1683 +# CONFIG_DUMMY is not set
1684 +# CONFIG_BONDING is not set
1685 +# CONFIG_MACVLAN is not set
1686 +# CONFIG_EQUALIZER is not set
1687 +# CONFIG_TUN is not set
1688 +# CONFIG_VETH is not set
1689 +CONFIG_PHYLIB=y
1690 +
1691 +#
1692 +# MII PHY device drivers
1693 +#
1694 +# CONFIG_MARVELL_PHY is not set
1695 +# CONFIG_DAVICOM_PHY is not set
1696 +# CONFIG_QSEMI_PHY is not set
1697 +# CONFIG_LXT_PHY is not set
1698 +# CONFIG_CICADA_PHY is not set
1699 +# CONFIG_VITESSE_PHY is not set
1700 +# CONFIG_SMSC_PHY is not set
1701 +# CONFIG_BROADCOM_PHY is not set
1702 +# CONFIG_BROADCOM5222_PHY is not set
1703 +# CONFIG_ICPLUS_PHY is not set
1704 +# CONFIG_REALTEK_PHY is not set
1705 +# CONFIG_NATIONAL_PHY is not set
1706 +# CONFIG_NATIONAL8364x_PHY is not set
1707 +# CONFIG_NATIONAL8384x_PHY is not set
1708 +CONFIG_MicrelKSZ8041_PHY=y
1709 +# CONFIG_STE10XP is not set
1710 +# CONFIG_LSI_ET1011C_PHY is not set
1711 +# CONFIG_FIXED_PHY is not set
1712 +# CONFIG_MDIO_BITBANG is not set
1713 +CONFIG_NET_ETHERNET=y
1714 +CONFIG_MII=y
1715 +# CONFIG_ENC28J60 is not set
1716 +# CONFIG_DNET is not set
1717 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
1718 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
1719 +# CONFIG_IBM_NEW_EMAC_TAH is not set
1720 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
1721 +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
1722 +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
1723 +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
1724 +# CONFIG_B44 is not set
1725 +CONFIG_FEC=y
1726 +# CONFIG_NETDEV_1000 is not set
1727 +# CONFIG_NETDEV_10000 is not set
1728 +
1729 +#
1730 +# Wireless LAN
1731 +#
1732 +# CONFIG_WLAN_PRE80211 is not set
1733 +# CONFIG_WLAN_80211 is not set
1734 +# CONFIG_IWLWIFI_LEDS is not set
1735 +
1736 +#
1737 +# Enable WiMAX (Networking options) to see the WiMAX drivers
1738 +#
1739 +
1740 +#
1741 +# USB Network Adapters
1742 +#
1743 +# CONFIG_USB_CATC is not set
1744 +# CONFIG_USB_KAWETH is not set
1745 +CONFIG_USB_PEGASUS=m
1746 +CONFIG_USB_RTL8150=m
1747 +CONFIG_USB_USBNET=m
1748 +CONFIG_USB_NET_AX8817X=m
1749 +CONFIG_USB_NET_CDCETHER=m
1750 +# CONFIG_USB_NET_DM9601 is not set
1751 +# CONFIG_USB_NET_SMSC95XX is not set
1752 +# CONFIG_USB_NET_GL620A is not set
1753 +# CONFIG_USB_NET_NET1080 is not set
1754 +# CONFIG_USB_NET_PLUSB is not set
1755 +# CONFIG_USB_NET_MCS7830 is not set
1756 +# CONFIG_USB_NET_RNDIS_HOST is not set
1757 +# CONFIG_USB_NET_CDC_SUBSET is not set
1758 +# CONFIG_USB_NET_ZAURUS is not set
1759 +# CONFIG_WAN is not set
1760 +# CONFIG_PPP is not set
1761 +# CONFIG_SLIP is not set
1762 +# CONFIG_NETCONSOLE is not set
1763 +# CONFIG_NETPOLL is not set
1764 +# CONFIG_NET_POLL_CONTROLLER is not set
1765 +# CONFIG_ISDN is not set
1766 +# CONFIG_PHONE is not set
1767 +
1768 +#
1769 +# Input device support
1770 +#
1771 +CONFIG_INPUT=y
1772 +# CONFIG_INPUT_FF_MEMLESS is not set
1773 +# CONFIG_INPUT_POLLDEV is not set
1774 +
1775 +#
1776 +# Userland interfaces
1777 +#
1778 +CONFIG_INPUT_MOUSEDEV=y
1779 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
1780 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
1781 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
1782 +# CONFIG_INPUT_JOYDEV is not set
1783 +CONFIG_INPUT_EVDEV=y
1784 +# CONFIG_INPUT_EVBUG is not set
1785 +
1786 +#
1787 +# Input Device Drivers
1788 +#
1789 +CONFIG_INPUT_KEYBOARD=y
1790 +# CONFIG_KEYBOARD_ATKBD is not set
1791 +# CONFIG_KEYBOARD_SUNKBD is not set
1792 +# CONFIG_KEYBOARD_LKKBD is not set
1793 +# CONFIG_KEYBOARD_XTKBD is not set
1794 +# CONFIG_KEYBOARD_NEWTON is not set
1795 +# CONFIG_KEYBOARD_STOWAWAY is not set
1796 +# CONFIG_INPUT_MOUSE is not set
1797 +# CONFIG_INPUT_JOYSTICK is not set
1798 +# CONFIG_INPUT_TABLET is not set
1799 +# CONFIG_INPUT_TOUCHSCREEN is not set
1800 +# CONFIG_INPUT_MISC is not set
1801 +
1802 +#
1803 +# Hardware I/O ports
1804 +#
1805 +CONFIG_SERIO=y
1806 +CONFIG_SERIO_SERPORT=y
1807 +# CONFIG_SERIO_LIBPS2 is not set
1808 +# CONFIG_SERIO_RAW is not set
1809 +# CONFIG_GAMEPORT is not set
1810 +
1811 +#
1812 +# Character devices
1813 +#
1814 +CONFIG_VT=y
1815 +CONFIG_CONSOLE_TRANSLATIONS=y
1816 +CONFIG_VT_CONSOLE=y
1817 +CONFIG_HW_CONSOLE=y
1818 +# CONFIG_VT_HW_CONSOLE_BINDING is not set
1819 +CONFIG_DEVKMEM=y
1820 +CONFIG_DEVSRAM=m
1821 +# CONFIG_SERIAL_NONSTANDARD is not set
1822 +
1823 +#
1824 +# Serial drivers
1825 +#
1826 +# CONFIG_SERIAL_8250 is not set
1827 +
1828 +#
1829 +# Non-8250 serial port support
1830 +#
1831 +CONFIG_SERIAL_CORE=y
1832 +CONFIG_SERIAL_CORE_CONSOLE=y
1833 +# CONFIG_SERIAL_COLDFIRE_IRDA is not set
1834 +# CONFIG_SERIAL_COLDFIRE_EDMA is not set
1835 +CONFIG_SERIAL_MCF=y
1836 +CONFIG_SERIAL_MCF_BAUDRATE=115200
1837 +CONFIG_SERIAL_MCF_CONSOLE=y
1838 +CONFIG_UNIX98_PTYS=y
1839 +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
1840 +# CONFIG_LEGACY_PTYS is not set
1841 +# CONFIG_IPMI_HANDLER is not set
1842 +# CONFIG_HW_RANDOM is not set
1843 +# CONFIG_R3964 is not set
1844 +# CONFIG_RAW_DRIVER is not set
1845 +# CONFIG_TCG_TPM is not set
1846 +CONFIG_I2C=y
1847 +CONFIG_I2C_BOARDINFO=y
1848 +CONFIG_I2C_CHARDEV=y
1849 +CONFIG_I2C_HELPER_AUTO=y
1850 +
1851 +#
1852 +# I2C Hardware Bus support
1853 +#
1854 +
1855 +#
1856 +# I2C system bus drivers (mostly embedded / system-on-chip)
1857 +#
1858 +CONFIG_I2C_MCF=y
1859 +# CONFIG_I2C_OCORES is not set
1860 +# CONFIG_I2C_SIMTEC is not set
1861 +
1862 +#
1863 +# External I2C/SMBus adapter drivers
1864 +#
1865 +# CONFIG_I2C_PARPORT_LIGHT is not set
1866 +# CONFIG_I2C_TAOS_EVM is not set
1867 +# CONFIG_I2C_TINY_USB is not set
1868 +
1869 +#
1870 +# Other I2C/SMBus bus drivers
1871 +#
1872 +# CONFIG_I2C_PCA_PLATFORM is not set
1873 +# CONFIG_I2C_STUB is not set
1874 +
1875 +#
1876 +# Miscellaneous I2C Chip support
1877 +#
1878 +# CONFIG_DS1682 is not set
1879 +# CONFIG_SENSORS_PCF8574 is not set
1880 +# CONFIG_PCF8575 is not set
1881 +# CONFIG_SENSORS_PCA9539 is not set
1882 +# CONFIG_SENSORS_PCF8591 is not set
1883 +# CONFIG_SENSORS_MAX6875 is not set
1884 +# CONFIG_SENSORS_TSL2550 is not set
1885 +# CONFIG_I2C_DEBUG_CORE is not set
1886 +# CONFIG_I2C_DEBUG_ALGO is not set
1887 +# CONFIG_I2C_DEBUG_BUS is not set
1888 +# CONFIG_I2C_DEBUG_CHIP is not set
1889 +CONFIG_SPI=y
1890 +CONFIG_SPI_MASTER=y
1891 +
1892 +#
1893 +# SPI Master Controller Drivers
1894 +#
1895 +# CONFIG_SPI_BITBANG is not set
1896 +CONFIG_SPI_DSPI=y
1897 +CONFIG_SPI_COLDFIRE_DSPI_EDMA=y
1898 +# CONFIG_VOIP_FXS is not set
1899 +# CONFIG_VOIP_FXO is not set
1900 +
1901 +#
1902 +# SPI Protocol Masters
1903 +#
1904 +# CONFIG_SPI_SPIDEV is not set
1905 +# CONFIG_SPI_TLE62X0 is not set
1906 +# CONFIG_W1 is not set
1907 +# CONFIG_POWER_SUPPLY is not set
1908 +# CONFIG_HWMON is not set
1909 +# CONFIG_THERMAL is not set
1910 +# CONFIG_THERMAL_HWMON is not set
1911 +CONFIG_WATCHDOG=y
1912 +# CONFIG_WATCHDOG_NOWAYOUT is not set
1913 +
1914 +#
1915 +# Watchdog Device Drivers
1916 +#
1917 +# CONFIG_SOFT_WATCHDOG is not set
1918 +CONFIG_COLDFIRE_WATCHDOG=y
1919 +
1920 +#
1921 +# USB-based Watchdog Cards
1922 +#
1923 +# CONFIG_USBPCWATCHDOG is not set
1924 +CONFIG_SSB_POSSIBLE=y
1925 +
1926 +#
1927 +# Sonics Silicon Backplane
1928 +#
1929 +# CONFIG_SSB is not set
1930 +
1931 +#
1932 +# Multifunction device drivers
1933 +#
1934 +# CONFIG_MFD_CORE is not set
1935 +# CONFIG_MFD_SM501 is not set
1936 +# CONFIG_HTC_PASIC3 is not set
1937 +# CONFIG_MFD_TMIO is not set
1938 +# CONFIG_PMIC_DA903X is not set
1939 +# CONFIG_MFD_WM8400 is not set
1940 +# CONFIG_MFD_WM8350_I2C is not set
1941 +# CONFIG_MFD_PCF50633 is not set
1942 +# CONFIG_REGULATOR is not set
1943 +
1944 +#
1945 +# Multimedia devices
1946 +#
1947 +
1948 +#
1949 +# Multimedia core support
1950 +#
1951 +# CONFIG_VIDEO_DEV is not set
1952 +# CONFIG_DVB_CORE is not set
1953 +# CONFIG_VIDEO_MEDIA is not set
1954 +
1955 +#
1956 +# Multimedia drivers
1957 +#
1958 +CONFIG_DAB=y
1959 +# CONFIG_USB_DABUSB is not set
1960 +
1961 +#
1962 +# Graphics support
1963 +#
1964 +# CONFIG_VGASTATE is not set
1965 +CONFIG_VIDEO_OUTPUT_CONTROL=m
1966 +# CONFIG_FB is not set
1967 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1968 +
1969 +#
1970 +# Display device support
1971 +#
1972 +# CONFIG_DISPLAY_SUPPORT is not set
1973 +
1974 +#
1975 +# Console display driver support
1976 +#
1977 +CONFIG_DUMMY_CONSOLE=y
1978 +CONFIG_SOUND=y
1979 +CONFIG_SOUND_OSS_CORE=y
1980 +CONFIG_SND=y
1981 +CONFIG_SND_TIMER=y
1982 +CONFIG_SND_PCM=y
1983 +# CONFIG_SND_SEQUENCER is not set
1984 +CONFIG_SND_OSSEMUL=y
1985 +# CONFIG_SND_MIXER_OSS is not set
1986 +CONFIG_SND_PCM_OSS=y
1987 +CONFIG_SND_PCM_OSS_PLUGINS=y
1988 +# CONFIG_SND_HRTIMER is not set
1989 +# CONFIG_SND_DYNAMIC_MINORS is not set
1990 +CONFIG_SND_SUPPORT_OLD_API=y
1991 +CONFIG_SND_VERBOSE_PROCFS=y
1992 +# CONFIG_SND_VERBOSE_PRINTK is not set
1993 +# CONFIG_SND_DEBUG is not set
1994 +CONFIG_SND_DRIVERS=y
1995 +# CONFIG_SND_DUMMY is not set
1996 +# CONFIG_SND_MTPAV is not set
1997 +# CONFIG_SND_SERIAL_U16550 is not set
1998 +# CONFIG_SND_MPU401 is not set
1999 +
2000 +#
2001 +# ALSA for Coldfire
2002 +#
2003 +CONFIG_SND_COLDFIRE=y
2004 +CONFIG_SND_SPI=y
2005 +CONFIG_SND_USB=y
2006 +# CONFIG_SND_USB_AUDIO is not set
2007 +# CONFIG_SND_USB_CAIAQ is not set
2008 +# CONFIG_SND_SOC is not set
2009 +# CONFIG_SOUND_PRIME is not set
2010 +CONFIG_HID_SUPPORT=y
2011 +CONFIG_HID=y
2012 +# CONFIG_HID_DEBUG is not set
2013 +# CONFIG_HIDRAW is not set
2014 +
2015 +#
2016 +# USB Input Devices
2017 +#
2018 +CONFIG_USB_HID=y
2019 +# CONFIG_HID_PID is not set
2020 +# CONFIG_USB_HIDDEV is not set
2021 +
2022 +#
2023 +# Special HID drivers
2024 +#
2025 +CONFIG_HID_COMPAT=y
2026 +# CONFIG_HID_A4TECH is not set
2027 +# CONFIG_HID_APPLE is not set
2028 +# CONFIG_HID_BELKIN is not set
2029 +# CONFIG_HID_CHERRY is not set
2030 +# CONFIG_HID_CHICONY is not set
2031 +# CONFIG_HID_CYPRESS is not set
2032 +# CONFIG_HID_EZKEY is not set
2033 +# CONFIG_HID_GYRATION is not set
2034 +# CONFIG_HID_LOGITECH is not set
2035 +# CONFIG_HID_MICROSOFT is not set
2036 +# CONFIG_HID_MONTEREY is not set
2037 +# CONFIG_HID_NTRIG is not set
2038 +# CONFIG_HID_PANTHERLORD is not set
2039 +# CONFIG_HID_PETALYNX is not set
2040 +# CONFIG_HID_SAMSUNG is not set
2041 +# CONFIG_HID_SONY is not set
2042 +# CONFIG_HID_SUNPLUS is not set
2043 +# CONFIG_GREENASIA_FF is not set
2044 +# CONFIG_HID_TOPSEED is not set
2045 +# CONFIG_THRUSTMASTER_FF is not set
2046 +# CONFIG_ZEROPLUS_FF is not set
2047 +CONFIG_USB_SUPPORT=y
2048 +CONFIG_USB_ARCH_HAS_HCD=y
2049 +# CONFIG_USB_ARCH_HAS_OHCI is not set
2050 +CONFIG_USB_ARCH_HAS_EHCI=y
2051 +CONFIG_USB=y
2052 +# CONFIG_USB_DEBUG is not set
2053 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
2054 +
2055 +#
2056 +# Miscellaneous USB options
2057 +#
2058 +CONFIG_USB_DEVICEFS=y
2059 +# CONFIG_USB_DEVICE_CLASS is not set
2060 +# CONFIG_USB_DYNAMIC_MINORS is not set
2061 +CONFIG_USB_SUSPEND=y
2062 +CONFIG_USB_OTG=y
2063 +# CONFIG_USB_OTG_WHITELIST is not set
2064 +# CONFIG_USB_OTG_BLACKLIST_HUB is not set
2065 +# CONFIG_USB_MON is not set
2066 +# CONFIG_USB_WUSB is not set
2067 +# CONFIG_USB_WUSB_CBAF is not set
2068 +
2069 +#
2070 +# USB Host Controller Drivers
2071 +#
2072 +# CONFIG_USB_C67X00_HCD is not set
2073 +CONFIG_USB_EHCI_HCD=m
2074 +CONFIG_USB_EHCI_ROOT_HUB_TT=y
2075 +# CONFIG_USB_EHCI_TT_NEWSCHED is not set
2076 +CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
2077 +CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
2078 +CONFIG_USB_EHCI_FSL=y
2079 +# CONFIG_USB_OXU210HP_HCD is not set
2080 +# CONFIG_USB_ISP116X_HCD is not set
2081 +# CONFIG_USB_SL811_HCD is not set
2082 +# CONFIG_USB_R8A66597_HCD is not set
2083 +# CONFIG_USB_HWA_HCD is not set
2084 +CONFIG_USB_M5445X_ULPI=y
2085 +# CONFIG_USB_M5445X_FSLS is not set
2086 +# CONFIG_USB_M5441X_ULPI is not set
2087 +# CONFIG_USB_M5441X_FSLS is not set
2088 +# CONFIG_USB_GADGET_MUSB_HDRC is not set
2089 +
2090 +#
2091 +# USB Device Class drivers
2092 +#
2093 +# CONFIG_USB_ACM is not set
2094 +# CONFIG_USB_PRINTER is not set
2095 +# CONFIG_USB_WDM is not set
2096 +# CONFIG_USB_TMC is not set
2097 +
2098 +#
2099 +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
2100 +#
2101 +
2102 +#
2103 +# see USB_STORAGE Help for more information
2104 +#
2105 +CONFIG_USB_STORAGE=y
2106 +# CONFIG_USB_STORAGE_DEBUG is not set
2107 +# CONFIG_USB_STORAGE_DATAFAB is not set
2108 +# CONFIG_USB_STORAGE_FREECOM is not set
2109 +# CONFIG_USB_STORAGE_ISD200 is not set
2110 +# CONFIG_USB_STORAGE_USBAT is not set
2111 +# CONFIG_USB_STORAGE_SDDR09 is not set
2112 +# CONFIG_USB_STORAGE_SDDR55 is not set
2113 +# CONFIG_USB_STORAGE_JUMPSHOT is not set
2114 +# CONFIG_USB_STORAGE_ALAUDA is not set
2115 +# CONFIG_USB_STORAGE_ONETOUCH is not set
2116 +# CONFIG_USB_STORAGE_KARMA is not set
2117 +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
2118 +# CONFIG_USB_LIBUSUAL is not set
2119 +
2120 +#
2121 +# USB Imaging devices
2122 +#
2123 +# CONFIG_USB_MDC800 is not set
2124 +# CONFIG_USB_MICROTEK is not set
2125 +
2126 +#
2127 +# USB port drivers
2128 +#
2129 +# CONFIG_USB_SERIAL is not set
2130 +
2131 +#
2132 +# USB Miscellaneous drivers
2133 +#
2134 +# CONFIG_USB_EMI62 is not set
2135 +# CONFIG_USB_EMI26 is not set
2136 +# CONFIG_USB_ADUTUX is not set
2137 +# CONFIG_USB_SEVSEG is not set
2138 +# CONFIG_USB_RIO500 is not set
2139 +# CONFIG_USB_LEGOTOWER is not set
2140 +# CONFIG_USB_LCD is not set
2141 +# CONFIG_USB_BERRY_CHARGE is not set
2142 +# CONFIG_USB_LED is not set
2143 +# CONFIG_USB_CYPRESS_CY7C63 is not set
2144 +# CONFIG_USB_CYTHERM is not set
2145 +# CONFIG_USB_PHIDGET is not set
2146 +# CONFIG_USB_IDMOUSE is not set
2147 +# CONFIG_USB_FTDI_ELAN is not set
2148 +# CONFIG_USB_APPLEDISPLAY is not set
2149 +# CONFIG_USB_SISUSBVGA is not set
2150 +# CONFIG_USB_LD is not set
2151 +# CONFIG_USB_TRANCEVIBRATOR is not set
2152 +# CONFIG_USB_IOWARRIOR is not set
2153 +# CONFIG_USB_TEST is not set
2154 +# CONFIG_USB_ISIGHTFW is not set
2155 +# CONFIG_USB_VST is not set
2156 +CONFIG_USB_GADGET=m
2157 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
2158 +CONFIG_USB_GADGET_VBUS_DRAW=2
2159 +CONFIG_USB_GADGET_SELECTED=y
2160 +# CONFIG_USB_GADGET_AT91 is not set
2161 +# CONFIG_USB_GADGET_ATMEL_USBA is not set
2162 +CONFIG_USB_GADGET_FSL_USB2=y
2163 +CONFIG_USB_FSL_USB2=m
2164 +# CONFIG_USB_GADGET_LH7A40X is not set
2165 +# CONFIG_USB_GADGET_OMAP is not set
2166 +# CONFIG_USB_GADGET_PXA25X is not set
2167 +# CONFIG_USB_GADGET_PXA27X is not set
2168 +# CONFIG_USB_GADGET_S3C2410 is not set
2169 +# CONFIG_USB_GADGET_IMX is not set
2170 +# CONFIG_USB_GADGET_M66592 is not set
2171 +# CONFIG_USB_GADGET_AMD5536UDC is not set
2172 +# CONFIG_USB_GADGET_FSL_QE is not set
2173 +# CONFIG_USB_GADGET_CI13XXX is not set
2174 +# CONFIG_USB_GADGET_NET2280 is not set
2175 +# CONFIG_USB_GADGET_GOKU is not set
2176 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
2177 +CONFIG_USB_GADGET_DUALSPEED=y
2178 +# CONFIG_USB_ZERO is not set
2179 +CONFIG_USB_ETH=m
2180 +CONFIG_USB_ETH_RNDIS=y
2181 +# CONFIG_USB_GADGETFS is not set
2182 +CONFIG_USB_FILE_STORAGE=m
2183 +# CONFIG_USB_FILE_STORAGE_TEST is not set
2184 +# CONFIG_USB_G_SERIAL is not set
2185 +# CONFIG_USB_MIDI_GADGET is not set
2186 +# CONFIG_USB_G_PRINTER is not set
2187 +# CONFIG_USB_CDC_COMPOSITE is not set
2188 +
2189 +#
2190 +# OTG and related infrastructure
2191 +#
2192 +CONFIG_MMC=y
2193 +# CONFIG_MMC_DEBUG is not set
2194 +# CONFIG_MMC_UNSAFE_RESUME is not set
2195 +
2196 +#
2197 +# MMC/SD/SDIO Card Drivers
2198 +#
2199 +CONFIG_MMC_BLOCK=y
2200 +CONFIG_MMC_BLOCK_BOUNCE=y
2201 +CONFIG_SDIO_UART=y
2202 +# CONFIG_MMC_TEST is not set
2203 +
2204 +#
2205 +# MMC/SD/SDIO Host Controller Drivers
2206 +#
2207 +# CONFIG_MMC_SDHCI is not set
2208 +CONFIG_MMC_SPI=y
2209 +CONFIG_M54451_SD_HW_DETECT=y
2210 +# CONFIG_MEMSTICK is not set
2211 +# CONFIG_NEW_LEDS is not set
2212 +# CONFIG_ACCESSIBILITY is not set
2213 +CONFIG_RTC_LIB=y
2214 +CONFIG_RTC_CLASS=y
2215 +CONFIG_RTC_HCTOSYS=y
2216 +CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
2217 +# CONFIG_RTC_DEBUG is not set
2218 +
2219 +#
2220 +# RTC interfaces
2221 +#
2222 +CONFIG_RTC_INTF_SYSFS=y
2223 +CONFIG_RTC_INTF_PROC=y
2224 +CONFIG_RTC_INTF_DEV=y
2225 +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
2226 +# CONFIG_RTC_DRV_TEST is not set
2227 +
2228 +#
2229 +# I2C RTC drivers
2230 +#
2231 +# CONFIG_RTC_DRV_DS1307 is not set
2232 +# CONFIG_RTC_DRV_DS1374 is not set
2233 +# CONFIG_RTC_DRV_DS1672 is not set
2234 +# CONFIG_RTC_DRV_MAX6900 is not set
2235 +# CONFIG_RTC_DRV_RS5C372 is not set
2236 +# CONFIG_RTC_DRV_ISL1208 is not set
2237 +# CONFIG_RTC_DRV_X1205 is not set
2238 +# CONFIG_RTC_DRV_PCF8563 is not set
2239 +# CONFIG_RTC_DRV_PCF8583 is not set
2240 +# CONFIG_RTC_DRV_M41T80 is not set
2241 +# CONFIG_RTC_DRV_S35390A is not set
2242 +# CONFIG_RTC_DRV_FM3130 is not set
2243 +# CONFIG_RTC_DRV_RX8581 is not set
2244 +
2245 +#
2246 +# SPI RTC drivers
2247 +#
2248 +# CONFIG_RTC_DRV_M41T94 is not set
2249 +# CONFIG_RTC_DRV_DS1305 is not set
2250 +# CONFIG_RTC_DRV_DS1390 is not set
2251 +# CONFIG_RTC_DRV_MAX6902 is not set
2252 +# CONFIG_RTC_DRV_R9701 is not set
2253 +# CONFIG_RTC_DRV_RS5C348 is not set
2254 +# CONFIG_RTC_DRV_DS3234 is not set
2255 +
2256 +#
2257 +# Platform RTC drivers
2258 +#
2259 +# CONFIG_RTC_DRV_DS1286 is not set
2260 +# CONFIG_RTC_DRV_DS1511 is not set
2261 +# CONFIG_RTC_DRV_DS1553 is not set
2262 +# CONFIG_RTC_DRV_DS1742 is not set
2263 +# CONFIG_RTC_DRV_STK17TA8 is not set
2264 +# CONFIG_RTC_DRV_M48T86 is not set
2265 +# CONFIG_RTC_DRV_M48T35 is not set
2266 +# CONFIG_RTC_DRV_M48T59 is not set
2267 +# CONFIG_RTC_DRV_BQ4802 is not set
2268 +# CONFIG_RTC_DRV_V3020 is not set
2269 +
2270 +#
2271 +# on-CPU RTC drivers
2272 +#
2273 +CONFIG_RTC_MCF=y
2274 +# CONFIG_RTC_M5441X is not set
2275 +CONFIG_DMADEVICES=y
2276 +
2277 +#
2278 +# DMA Devices
2279 +#
2280 +CONFIG_COLDFIRE_EDMA=y
2281 +CONFIG_COLDFIRE_EDMA_TEST=m
2282 +# CONFIG_UIO is not set
2283 +# CONFIG_STAGING is not set
2284 +
2285 +#
2286 +# Character devices
2287 +#
2288 +CONFIG_TICK_ONESHOT=y
2289 +CONFIG_NO_HZ=y
2290 +CONFIG_HIGH_RES_TIMERS=y
2291 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
2292 +
2293 +#
2294 +# File systems
2295 +#
2296 +CONFIG_EXT2_FS=y
2297 +# CONFIG_EXT2_FS_XATTR is not set
2298 +# CONFIG_EXT2_FS_XIP is not set
2299 +CONFIG_EXT3_FS=y
2300 +CONFIG_EXT3_FS_XATTR=y
2301 +# CONFIG_EXT3_FS_POSIX_ACL is not set
2302 +# CONFIG_EXT3_FS_SECURITY is not set
2303 +# CONFIG_EXT4_FS is not set
2304 +CONFIG_JBD=y
2305 +CONFIG_FS_MBCACHE=y
2306 +# CONFIG_REISERFS_FS is not set
2307 +# CONFIG_JFS_FS is not set
2308 +# CONFIG_FS_POSIX_ACL is not set
2309 +CONFIG_FILE_LOCKING=y
2310 +# CONFIG_XFS_FS is not set
2311 +# CONFIG_GFS2_FS is not set
2312 +# CONFIG_OCFS2_FS is not set
2313 +# CONFIG_BTRFS_FS is not set
2314 +CONFIG_DNOTIFY=y
2315 +CONFIG_INOTIFY=y
2316 +CONFIG_INOTIFY_USER=y
2317 +# CONFIG_QUOTA is not set
2318 +# CONFIG_AUTOFS_FS is not set
2319 +# CONFIG_AUTOFS4_FS is not set
2320 +# CONFIG_FUSE_FS is not set
2321 +
2322 +#
2323 +# CD-ROM/DVD Filesystems
2324 +#
2325 +CONFIG_ISO9660_FS=y
2326 +# CONFIG_JOLIET is not set
2327 +# CONFIG_ZISOFS is not set
2328 +# CONFIG_UDF_FS is not set
2329 +
2330 +#
2331 +# DOS/FAT/NT Filesystems
2332 +#
2333 +CONFIG_FAT_FS=y
2334 +CONFIG_MSDOS_FS=y
2335 +CONFIG_VFAT_FS=y
2336 +CONFIG_FAT_DEFAULT_CODEPAGE=437
2337 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
2338 +CONFIG_NTFS_FS=y
2339 +# CONFIG_NTFS_DEBUG is not set
2340 +CONFIG_NTFS_RW=y
2341 +
2342 +#
2343 +# Pseudo filesystems
2344 +#
2345 +CONFIG_PROC_FS=y
2346 +# CONFIG_PROC_KCORE is not set
2347 +CONFIG_PROC_SYSCTL=y
2348 +CONFIG_PROC_PAGE_MONITOR=y
2349 +CONFIG_SYSFS=y
2350 +CONFIG_TMPFS=y
2351 +# CONFIG_TMPFS_POSIX_ACL is not set
2352 +# CONFIG_HUGETLB_PAGE is not set
2353 +# CONFIG_CONFIGFS_FS is not set
2354 +CONFIG_MISC_FILESYSTEMS=y
2355 +# CONFIG_ADFS_FS is not set
2356 +# CONFIG_AFFS_FS is not set
2357 +# CONFIG_HFS_FS is not set
2358 +# CONFIG_HFSPLUS_FS is not set
2359 +# CONFIG_BEFS_FS is not set
2360 +# CONFIG_BFS_FS is not set
2361 +# CONFIG_EFS_FS is not set
2362 +CONFIG_JFFS2_FS=y
2363 +CONFIG_JFFS2_FS_DEBUG=0
2364 +CONFIG_JFFS2_FS_WRITEBUFFER=y
2365 +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
2366 +# CONFIG_JFFS2_SUMMARY is not set
2367 +# CONFIG_JFFS2_FS_XATTR is not set
2368 +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
2369 +CONFIG_JFFS2_ZLIB=y
2370 +# CONFIG_JFFS2_LZO is not set
2371 +CONFIG_JFFS2_RTIME=y
2372 +# CONFIG_JFFS2_RUBIN is not set
2373 +# CONFIG_CRAMFS is not set
2374 +# CONFIG_SQUASHFS is not set
2375 +# CONFIG_VXFS_FS is not set
2376 +CONFIG_MINIX_FS=y
2377 +# CONFIG_OMFS_FS is not set
2378 +# CONFIG_HPFS_FS is not set
2379 +# CONFIG_QNX4FS_FS is not set
2380 +# CONFIG_ROMFS_FS is not set
2381 +# CONFIG_SYSV_FS is not set
2382 +# CONFIG_UFS_FS is not set
2383 +CONFIG_NETWORK_FILESYSTEMS=y
2384 +CONFIG_NFS_FS=y
2385 +CONFIG_NFS_V3=y
2386 +# CONFIG_NFS_V3_ACL is not set
2387 +# CONFIG_NFS_V4 is not set
2388 +CONFIG_ROOT_NFS=y
2389 +# CONFIG_NFSD is not set
2390 +CONFIG_LOCKD=y
2391 +CONFIG_LOCKD_V4=y
2392 +CONFIG_NFS_COMMON=y
2393 +CONFIG_SUNRPC=y
2394 +# CONFIG_SUNRPC_REGISTER_V4 is not set
2395 +# CONFIG_RPCSEC_GSS_KRB5 is not set
2396 +# CONFIG_RPCSEC_GSS_SPKM3 is not set
2397 +# CONFIG_SMB_FS is not set
2398 +# CONFIG_CIFS is not set
2399 +# CONFIG_NCP_FS is not set
2400 +# CONFIG_CODA_FS is not set
2401 +# CONFIG_AFS_FS is not set
2402 +
2403 +#
2404 +# Partition Types
2405 +#
2406 +CONFIG_PARTITION_ADVANCED=y
2407 +# CONFIG_ACORN_PARTITION is not set
2408 +# CONFIG_OSF_PARTITION is not set
2409 +# CONFIG_AMIGA_PARTITION is not set
2410 +# CONFIG_ATARI_PARTITION is not set
2411 +# CONFIG_MAC_PARTITION is not set
2412 +CONFIG_MSDOS_PARTITION=y
2413 +# CONFIG_BSD_DISKLABEL is not set
2414 +# CONFIG_MINIX_SUBPARTITION is not set
2415 +# CONFIG_SOLARIS_X86_PARTITION is not set
2416 +# CONFIG_UNIXWARE_DISKLABEL is not set
2417 +# CONFIG_LDM_PARTITION is not set
2418 +# CONFIG_SGI_PARTITION is not set
2419 +# CONFIG_ULTRIX_PARTITION is not set
2420 +# CONFIG_SUN_PARTITION is not set
2421 +# CONFIG_KARMA_PARTITION is not set
2422 +# CONFIG_EFI_PARTITION is not set
2423 +# CONFIG_SYSV68_PARTITION is not set
2424 +CONFIG_NLS=y
2425 +CONFIG_NLS_DEFAULT="iso8859-1"
2426 +CONFIG_NLS_CODEPAGE_437=y
2427 +# CONFIG_NLS_CODEPAGE_737 is not set
2428 +# CONFIG_NLS_CODEPAGE_775 is not set
2429 +# CONFIG_NLS_CODEPAGE_850 is not set
2430 +# CONFIG_NLS_CODEPAGE_852 is not set
2431 +# CONFIG_NLS_CODEPAGE_855 is not set
2432 +# CONFIG_NLS_CODEPAGE_857 is not set
2433 +# CONFIG_NLS_CODEPAGE_860 is not set
2434 +# CONFIG_NLS_CODEPAGE_861 is not set
2435 +# CONFIG_NLS_CODEPAGE_862 is not set
2436 +# CONFIG_NLS_CODEPAGE_863 is not set
2437 +# CONFIG_NLS_CODEPAGE_864 is not set
2438 +# CONFIG_NLS_CODEPAGE_865 is not set
2439 +# CONFIG_NLS_CODEPAGE_866 is not set
2440 +# CONFIG_NLS_CODEPAGE_869 is not set
2441 +# CONFIG_NLS_CODEPAGE_936 is not set
2442 +# CONFIG_NLS_CODEPAGE_950 is not set
2443 +# CONFIG_NLS_CODEPAGE_932 is not set
2444 +# CONFIG_NLS_CODEPAGE_949 is not set
2445 +# CONFIG_NLS_CODEPAGE_874 is not set
2446 +# CONFIG_NLS_ISO8859_8 is not set
2447 +# CONFIG_NLS_CODEPAGE_1250 is not set
2448 +# CONFIG_NLS_CODEPAGE_1251 is not set
2449 +# CONFIG_NLS_ASCII is not set
2450 +CONFIG_NLS_ISO8859_1=y
2451 +# CONFIG_NLS_ISO8859_2 is not set
2452 +# CONFIG_NLS_ISO8859_3 is not set
2453 +# CONFIG_NLS_ISO8859_4 is not set
2454 +# CONFIG_NLS_ISO8859_5 is not set
2455 +# CONFIG_NLS_ISO8859_6 is not set
2456 +# CONFIG_NLS_ISO8859_7 is not set
2457 +# CONFIG_NLS_ISO8859_9 is not set
2458 +# CONFIG_NLS_ISO8859_13 is not set
2459 +# CONFIG_NLS_ISO8859_14 is not set
2460 +# CONFIG_NLS_ISO8859_15 is not set
2461 +# CONFIG_NLS_KOI8_R is not set
2462 +# CONFIG_NLS_KOI8_U is not set
2463 +CONFIG_NLS_UTF8=y
2464 +# CONFIG_DLM is not set
2465 +
2466 +#
2467 +# Kernel hacking
2468 +#
2469 +# CONFIG_PRINTK_TIME is not set
2470 +CONFIG_ENABLE_WARN_DEPRECATED=y
2471 +# CONFIG_ENABLE_MUST_CHECK is not set
2472 +CONFIG_FRAME_WARN=1024
2473 +# CONFIG_MAGIC_SYSRQ is not set
2474 +# CONFIG_UNUSED_SYMBOLS is not set
2475 +# CONFIG_DEBUG_FS is not set
2476 +# CONFIG_HEADERS_CHECK is not set
2477 +# CONFIG_DEBUG_KERNEL is not set
2478 +# CONFIG_DEBUG_BUGVERBOSE is not set
2479 +# CONFIG_DEBUG_MEMORY_INIT is not set
2480 +# CONFIG_RCU_CPU_STALL_DETECTOR is not set
2481 +# CONFIG_SYSCTL_SYSCALL_CHECK is not set
2482 +
2483 +#
2484 +# Tracers
2485 +#
2486 +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
2487 +# CONFIG_SAMPLES is not set
2488 +# CONFIG_BOOTPARAM is not set
2489 +
2490 +#
2491 +# Security options
2492 +#
2493 +# CONFIG_KEYS is not set
2494 +# CONFIG_SECURITY is not set
2495 +# CONFIG_SECURITYFS is not set
2496 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
2497 +CONFIG_CRYPTO=y
2498 +
2499 +#
2500 +# Crypto core or helper
2501 +#
2502 +# CONFIG_CRYPTO_FIPS is not set
2503 +CONFIG_CRYPTO_ALGAPI=y
2504 +CONFIG_CRYPTO_ALGAPI2=y
2505 +CONFIG_CRYPTO_AEAD=y
2506 +CONFIG_CRYPTO_AEAD2=y
2507 +CONFIG_CRYPTO_BLKCIPHER=y
2508 +CONFIG_CRYPTO_BLKCIPHER2=y
2509 +CONFIG_CRYPTO_HASH=y
2510 +CONFIG_CRYPTO_HASH2=y
2511 +CONFIG_CRYPTO_RNG2=y
2512 +CONFIG_CRYPTO_MANAGER=y
2513 +CONFIG_CRYPTO_MANAGER2=y
2514 +# CONFIG_CRYPTO_GF128MUL is not set
2515 +# CONFIG_CRYPTO_NULL is not set
2516 +# CONFIG_CRYPTO_CRYPTD is not set
2517 +CONFIG_CRYPTO_AUTHENC=y
2518 +CONFIG_CRYPTO_TEST=m
2519 +
2520 +#
2521 +# Authenticated Encryption with Associated Data
2522 +#
2523 +# CONFIG_CRYPTO_CCM is not set
2524 +# CONFIG_CRYPTO_GCM is not set
2525 +# CONFIG_CRYPTO_SEQIV is not set
2526 +
2527 +#
2528 +# Block modes
2529 +#
2530 +CONFIG_CRYPTO_CBC=y
2531 +# CONFIG_CRYPTO_CTR is not set
2532 +# CONFIG_CRYPTO_CTS is not set
2533 +CONFIG_CRYPTO_ECB=y
2534 +# CONFIG_CRYPTO_LRW is not set
2535 +CONFIG_CRYPTO_PCBC=m
2536 +# CONFIG_CRYPTO_XTS is not set
2537 +
2538 +#
2539 +# Hash modes
2540 +#
2541 +CONFIG_CRYPTO_HMAC=y
2542 +# CONFIG_CRYPTO_XCBC is not set
2543 +
2544 +#
2545 +# Digest
2546 +#
2547 +CONFIG_CRYPTO_CRC32C=y
2548 +# CONFIG_CRYPTO_MD4 is not set
2549 +CONFIG_CRYPTO_MD5=y
2550 +# CONFIG_CRYPTO_MICHAEL_MIC is not set
2551 +# CONFIG_CRYPTO_RMD128 is not set
2552 +# CONFIG_CRYPTO_RMD160 is not set
2553 +# CONFIG_CRYPTO_RMD256 is not set
2554 +# CONFIG_CRYPTO_RMD320 is not set
2555 +CONFIG_CRYPTO_SHA1=y
2556 +# CONFIG_CRYPTO_SHA256 is not set
2557 +# CONFIG_CRYPTO_SHA512 is not set
2558 +# CONFIG_CRYPTO_TGR192 is not set
2559 +# CONFIG_CRYPTO_WP512 is not set
2560 +
2561 +#
2562 +# Ciphers
2563 +#
2564 +CONFIG_CRYPTO_AES=y
2565 +# CONFIG_CRYPTO_ANUBIS is not set
2566 +CONFIG_CRYPTO_ARC4=y
2567 +# CONFIG_CRYPTO_BLOWFISH is not set
2568 +# CONFIG_CRYPTO_CAMELLIA is not set
2569 +# CONFIG_CRYPTO_CAST5 is not set
2570 +# CONFIG_CRYPTO_CAST6 is not set
2571 +CONFIG_CRYPTO_DES=y
2572 +# CONFIG_CRYPTO_FCRYPT is not set
2573 +# CONFIG_CRYPTO_KHAZAD is not set
2574 +# CONFIG_CRYPTO_SALSA20 is not set
2575 +# CONFIG_CRYPTO_SEED is not set
2576 +# CONFIG_CRYPTO_SERPENT is not set
2577 +# CONFIG_CRYPTO_TEA is not set
2578 +# CONFIG_CRYPTO_TWOFISH is not set
2579 +
2580 +#
2581 +# Compression
2582 +#
2583 +# CONFIG_CRYPTO_DEFLATE is not set
2584 +# CONFIG_CRYPTO_LZO is not set
2585 +
2586 +#
2587 +# Random Number Generation
2588 +#
2589 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
2590 +
2591 +#
2592 +# OCF Configuration
2593 +#
2594 +
2595 +#
2596 +# Talitos Driver
2597 +#
2598 +CONFIG_CRYPTO_HW=y
2599 +CONFIG_CRYPTO_DEV_MCFCAU=y
2600 +CONFIG_CRYPTO_DEV_MCFCAU_DES=y
2601 +CONFIG_CRYPTO_DEV_MCFCAU_AES=y
2602 +CONFIG_CRYPTO_DEV_MCFCAU_MD5=y
2603 +CONFIG_CRYPTO_DEV_MCFCAU_SHA1=y
2604 +
2605 +#
2606 +# Library routines
2607 +#
2608 +CONFIG_BITREVERSE=y
2609 +CONFIG_GENERIC_FIND_LAST_BIT=y
2610 +CONFIG_CRC_CCITT=y
2611 +CONFIG_CRC16=y
2612 +# CONFIG_CRC_T10DIF is not set
2613 +CONFIG_CRC_ITU_T=y
2614 +CONFIG_CRC32=y
2615 +CONFIG_CRC7=y
2616 +CONFIG_LIBCRC32C=y
2617 +CONFIG_ZLIB_INFLATE=y
2618 +CONFIG_ZLIB_DEFLATE=y
2619 +CONFIG_GENERIC_ALLOCATOR=y
2620 +CONFIG_PLIST=y
2621 +CONFIG_HAS_IOMEM=y
2622 +CONFIG_HAS_IOPORT=y
2623 +CONFIG_HAS_DMA=y
2624 --- /dev/null
2625 +++ b/arch/m68k/configs/m54455evb_defconfig
2626 @@ -0,0 +1,1597 @@
2627 +#
2628 +# Automatically generated make config: don't edit
2629 +# Linux kernel version: 2.6.29
2630 +# Tue Aug 24 16:16:14 2010
2631 +#
2632 +CONFIG_M68K=y
2633 +CONFIG_MMU=y
2634 +CONFIG_GENERIC_TIME=y
2635 +CONFIG_GENERIC_CLOCKEVENTS=y
2636 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
2637 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
2638 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
2639 +CONFIG_GENERIC_HWEIGHT=y
2640 +CONFIG_GENERIC_CALIBRATE_DELAY=y
2641 +# CONFIG_TIME_LOW_RES is not set
2642 +CONFIG_GENERIC_IOMAP=y
2643 +# CONFIG_NO_IOPORT is not set
2644 +# CONFIG_NO_DMA is not set
2645 +CONFIG_HZ=100
2646 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
2647 +
2648 +#
2649 +# General setup
2650 +#
2651 +CONFIG_EXPERIMENTAL=y
2652 +CONFIG_BROKEN_ON_SMP=y
2653 +CONFIG_INIT_ENV_ARG_LIMIT=32
2654 +CONFIG_LOCALVERSION=""
2655 +# CONFIG_LOCALVERSION_AUTO is not set
2656 +CONFIG_SWAP=y
2657 +CONFIG_SYSVIPC=y
2658 +CONFIG_SYSVIPC_SYSCTL=y
2659 +# CONFIG_POSIX_MQUEUE is not set
2660 +# CONFIG_BSD_PROCESS_ACCT is not set
2661 +# CONFIG_TASKSTATS is not set
2662 +# CONFIG_AUDIT is not set
2663 +
2664 +#
2665 +# RCU Subsystem
2666 +#
2667 +CONFIG_CLASSIC_RCU=y
2668 +# CONFIG_TREE_RCU is not set
2669 +# CONFIG_PREEMPT_RCU is not set
2670 +# CONFIG_TREE_RCU_TRACE is not set
2671 +# CONFIG_PREEMPT_RCU_TRACE is not set
2672 +CONFIG_IKCONFIG=y
2673 +CONFIG_IKCONFIG_PROC=y
2674 +CONFIG_LOG_BUF_SHIFT=17
2675 +CONFIG_GROUP_SCHED=y
2676 +CONFIG_FAIR_GROUP_SCHED=y
2677 +# CONFIG_RT_GROUP_SCHED is not set
2678 +CONFIG_USER_SCHED=y
2679 +# CONFIG_CGROUP_SCHED is not set
2680 +# CONFIG_CGROUPS is not set
2681 +CONFIG_SYSFS_DEPRECATED=y
2682 +CONFIG_SYSFS_DEPRECATED_V2=y
2683 +# CONFIG_RELAY is not set
2684 +CONFIG_NAMESPACES=y
2685 +# CONFIG_UTS_NS is not set
2686 +# CONFIG_IPC_NS is not set
2687 +# CONFIG_USER_NS is not set
2688 +# CONFIG_PID_NS is not set
2689 +# CONFIG_NET_NS is not set
2690 +CONFIG_BLK_DEV_INITRD=y
2691 +CONFIG_INITRAMFS_SOURCE=""
2692 +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
2693 +CONFIG_SYSCTL=y
2694 +CONFIG_ANON_INODES=y
2695 +CONFIG_EMBEDDED=y
2696 +CONFIG_UID16=y
2697 +CONFIG_SYSCTL_SYSCALL=y
2698 +CONFIG_KALLSYMS=y
2699 +# CONFIG_KALLSYMS_EXTRA_PASS is not set
2700 +CONFIG_HOTPLUG=y
2701 +CONFIG_PRINTK=y
2702 +CONFIG_BUG=y
2703 +CONFIG_ELF_CORE=y
2704 +CONFIG_BASE_FULL=y
2705 +CONFIG_FUTEX=y
2706 +CONFIG_EPOLL=y
2707 +CONFIG_SIGNALFD=y
2708 +CONFIG_TIMERFD=y
2709 +CONFIG_EVENTFD=y
2710 +CONFIG_SHMEM=y
2711 +CONFIG_AIO=y
2712 +CONFIG_VM_EVENT_COUNTERS=y
2713 +CONFIG_PCI_QUIRKS=y
2714 +CONFIG_COMPAT_BRK=y
2715 +CONFIG_SLAB=y
2716 +# CONFIG_SLUB is not set
2717 +# CONFIG_SLOB is not set
2718 +# CONFIG_PROFILING is not set
2719 +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
2720 +CONFIG_SLABINFO=y
2721 +CONFIG_RT_MUTEXES=y
2722 +CONFIG_BASE_SMALL=0
2723 +CONFIG_MODULES=y
2724 +# CONFIG_MODULE_FORCE_LOAD is not set
2725 +CONFIG_MODULE_UNLOAD=y
2726 +CONFIG_MODULE_FORCE_UNLOAD=y
2727 +# CONFIG_MODVERSIONS is not set
2728 +# CONFIG_MODULE_SRCVERSION_ALL is not set
2729 +CONFIG_BLOCK=y
2730 +CONFIG_LBD=y
2731 +# CONFIG_BLK_DEV_IO_TRACE is not set
2732 +# CONFIG_BLK_DEV_BSG is not set
2733 +# CONFIG_BLK_DEV_INTEGRITY is not set
2734 +
2735 +#
2736 +# IO Schedulers
2737 +#
2738 +CONFIG_IOSCHED_NOOP=y
2739 +CONFIG_IOSCHED_AS=y
2740 +CONFIG_IOSCHED_DEADLINE=y
2741 +CONFIG_IOSCHED_CFQ=y
2742 +# CONFIG_DEFAULT_AS is not set
2743 +# CONFIG_DEFAULT_DEADLINE is not set
2744 +CONFIG_DEFAULT_CFQ=y
2745 +# CONFIG_DEFAULT_NOOP is not set
2746 +CONFIG_DEFAULT_IOSCHED="cfq"
2747 +# CONFIG_FREEZER is not set
2748 +
2749 +#
2750 +# Platform dependent setup
2751 +#
2752 +CONFIG_COLDFIRE=y
2753 +CONFIG_CFV4E=y
2754 +# CONFIG_FPU is not set
2755 +# CONFIG_AMIGA is not set
2756 +# CONFIG_ATARI is not set
2757 +CONFIG_PCI=y
2758 +# CONFIG_MAC is not set
2759 +# CONFIG_APOLLO is not set
2760 +# CONFIG_VME is not set
2761 +# CONFIG_HP300 is not set
2762 +# CONFIG_SUN3X is not set
2763 +# CONFIG_Q40 is not set
2764 +# CONFIG_SUN3 is not set
2765 +
2766 +#
2767 +# Processor type
2768 +#
2769 +# CONFIG_M68020 is not set
2770 +# CONFIG_M68030 is not set
2771 +# CONFIG_M68040 is not set
2772 +# CONFIG_M68060 is not set
2773 +CONFIG_M5445X=y
2774 +# CONFIG_M54451 is not set
2775 +CONFIG_M54455=y
2776 +# CONFIG_M54451EVB is not set
2777 +CONFIG_M54455EVB=y
2778 +CONFIG_HAVE_FSL_USB_DR=y
2779 +# CONFIG_M547X_8X is not set
2780 +# CONFIG_M5441X is not set
2781 +CONFIG_MCFCLK=266666666
2782 +# CONFIG_MCF_USER_HALT is not set
2783 +CONFIG_MMU_CFV4E=y
2784 +CONFIG_SDRAM_BASE=0x40000000
2785 +CONFIG_SDRAM_SIZE=0x10000000
2786 +CONFIG_NOR_FLASH_BASE=0x00000000
2787 +CONFIG_DMA_BASE=0xef000000
2788 +CONFIG_DMA_SIZE=0x1000000
2789 +CONFIG_SRAM=y
2790 +CONFIG_SRAM_BASE=0x8ff00000
2791 +CONFIG_SRAM_SIZE=0x8000
2792 +CONFIG_SRAM_ALLOC_GRANULARITY=0x200
2793 +CONFIG_VDSO=y
2794 +# CONFIG_M68KFPU_EMU is not set
2795 +CONFIG_ADVANCED=y
2796 +# CONFIG_RMW_INSNS is not set
2797 +CONFIG_SINGLE_MEMORY_CHUNK=y
2798 +# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
2799 +CONFIG_SELECT_MEMORY_MODEL=y
2800 +CONFIG_FLATMEM_MANUAL=y
2801 +# CONFIG_DISCONTIGMEM_MANUAL is not set
2802 +# CONFIG_SPARSEMEM_MANUAL is not set
2803 +CONFIG_FLATMEM=y
2804 +CONFIG_FLAT_NODE_MEM_MAP=y
2805 +CONFIG_NEED_MULTIPLE_NODES=y
2806 +CONFIG_PAGEFLAGS_EXTENDED=y
2807 +CONFIG_SPLIT_PTLOCK_CPUS=4
2808 +# CONFIG_PHYS_ADDR_T_64BIT is not set
2809 +CONFIG_ZONE_DMA_FLAG=1
2810 +CONFIG_BOUNCE=y
2811 +CONFIG_VIRT_TO_BUS=y
2812 +CONFIG_UNEVICTABLE_LRU=y
2813 +
2814 +#
2815 +# General setup
2816 +#
2817 +CONFIG_BINFMT_ELF=y
2818 +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
2819 +CONFIG_HAVE_AOUT=y
2820 +# CONFIG_BINFMT_AOUT is not set
2821 +# CONFIG_BINFMT_MISC is not set
2822 +CONFIG_PROC_HARDWARE=y
2823 +CONFIG_ZONE_DMA=y
2824 +# CONFIG_ARCH_SUPPORTS_MSI is not set
2825 +CONFIG_PCI_LEGACY=y
2826 +# CONFIG_PCI_STUB is not set
2827 +
2828 +#
2829 +# Power management options
2830 +#
2831 +CONFIG_PM=y
2832 +CONFIG_NET=y
2833 +
2834 +#
2835 +# Networking options
2836 +#
2837 +CONFIG_COMPAT_NET_DEV_OPS=y
2838 +CONFIG_PACKET=y
2839 +# CONFIG_PACKET_MMAP is not set
2840 +CONFIG_UNIX=y
2841 +CONFIG_XFRM=y
2842 +# CONFIG_XFRM_USER is not set
2843 +# CONFIG_XFRM_SUB_POLICY is not set
2844 +# CONFIG_XFRM_MIGRATE is not set
2845 +# CONFIG_XFRM_STATISTICS is not set
2846 +CONFIG_NET_KEY=y
2847 +# CONFIG_NET_KEY_MIGRATE is not set
2848 +CONFIG_INET=y
2849 +# CONFIG_IP_MULTICAST is not set
2850 +CONFIG_IP_ADVANCED_ROUTER=y
2851 +CONFIG_ASK_IP_FIB_HASH=y
2852 +# CONFIG_IP_FIB_TRIE is not set
2853 +CONFIG_IP_FIB_HASH=y
2854 +# CONFIG_IP_MULTIPLE_TABLES is not set
2855 +# CONFIG_IP_ROUTE_MULTIPATH is not set
2856 +# CONFIG_IP_ROUTE_VERBOSE is not set
2857 +CONFIG_IP_PNP=y
2858 +# CONFIG_IP_PNP_DHCP is not set
2859 +# CONFIG_IP_PNP_BOOTP is not set
2860 +# CONFIG_IP_PNP_RARP is not set
2861 +# CONFIG_NET_IPIP is not set
2862 +# CONFIG_NET_IPGRE is not set
2863 +# CONFIG_ARPD is not set
2864 +# CONFIG_SYN_COOKIES is not set
2865 +CONFIG_INET_AH=y
2866 +CONFIG_INET_ESP=y
2867 +# CONFIG_INET_IPCOMP is not set
2868 +# CONFIG_INET_XFRM_TUNNEL is not set
2869 +# CONFIG_INET_TUNNEL is not set
2870 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
2871 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
2872 +# CONFIG_INET_XFRM_MODE_BEET is not set
2873 +# CONFIG_INET_LRO is not set
2874 +CONFIG_INET_DIAG=y
2875 +CONFIG_INET_TCP_DIAG=y
2876 +# CONFIG_TCP_CONG_ADVANCED is not set
2877 +CONFIG_TCP_CONG_CUBIC=y
2878 +CONFIG_DEFAULT_TCP_CONG="cubic"
2879 +# CONFIG_TCP_MD5SIG is not set
2880 +# CONFIG_IPV6 is not set
2881 +# CONFIG_NETWORK_SECMARK is not set
2882 +# CONFIG_NETFILTER is not set
2883 +# CONFIG_IP_DCCP is not set
2884 +# CONFIG_IP_SCTP is not set
2885 +# CONFIG_TIPC is not set
2886 +# CONFIG_ATM is not set
2887 +# CONFIG_BRIDGE is not set
2888 +# CONFIG_NET_DSA is not set
2889 +# CONFIG_VLAN_8021Q is not set
2890 +# CONFIG_DECNET is not set
2891 +# CONFIG_LLC2 is not set
2892 +# CONFIG_IPX is not set
2893 +# CONFIG_ATALK is not set
2894 +# CONFIG_X25 is not set
2895 +# CONFIG_LAPB is not set
2896 +# CONFIG_ECONET is not set
2897 +# CONFIG_WAN_ROUTER is not set
2898 +# CONFIG_NET_SCHED is not set
2899 +# CONFIG_DCB is not set
2900 +
2901 +#
2902 +# Network testing
2903 +#
2904 +# CONFIG_NET_PKTGEN is not set
2905 +# CONFIG_HAMRADIO is not set
2906 +# CONFIG_CAN is not set
2907 +# CONFIG_IRDA is not set
2908 +# CONFIG_BT is not set
2909 +# CONFIG_AF_RXRPC is not set
2910 +# CONFIG_PHONET is not set
2911 +CONFIG_WIRELESS=y
2912 +# CONFIG_CFG80211 is not set
2913 +CONFIG_WIRELESS_OLD_REGULATORY=y
2914 +# CONFIG_WIRELESS_EXT is not set
2915 +# CONFIG_LIB80211 is not set
2916 +# CONFIG_MAC80211 is not set
2917 +# CONFIG_WIMAX is not set
2918 +# CONFIG_RFKILL is not set
2919 +# CONFIG_NET_9P is not set
2920 +# CONFIG_KLIPS is not set
2921 +
2922 +#
2923 +# Device Drivers
2924 +#
2925 +
2926 +#
2927 +# Generic Driver Options
2928 +#
2929 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
2930 +# CONFIG_STANDALONE is not set
2931 +CONFIG_PREVENT_FIRMWARE_BUILD=y
2932 +CONFIG_FW_LOADER=y
2933 +CONFIG_FIRMWARE_IN_KERNEL=y
2934 +CONFIG_EXTRA_FIRMWARE=""
2935 +# CONFIG_SYS_HYPERVISOR is not set
2936 +# CONFIG_CONNECTOR is not set
2937 +CONFIG_MTD=y
2938 +# CONFIG_MTD_DEBUG is not set
2939 +# CONFIG_MTD_CONCAT is not set
2940 +CONFIG_MTD_PARTITIONS=y
2941 +# CONFIG_MTD_TESTS is not set
2942 +# CONFIG_MTD_REDBOOT_PARTS is not set
2943 +CONFIG_MTD_CMDLINE_PARTS=y
2944 +# CONFIG_MTD_AR7_PARTS is not set
2945 +
2946 +#
2947 +# User Modules And Translation Layers
2948 +#
2949 +CONFIG_MTD_CHAR=y
2950 +CONFIG_MTD_BLKDEVS=y
2951 +CONFIG_MTD_BLOCK=y
2952 +# CONFIG_FTL is not set
2953 +# CONFIG_NFTL is not set
2954 +# CONFIG_INFTL is not set
2955 +# CONFIG_RFD_FTL is not set
2956 +# CONFIG_SSFDC is not set
2957 +# CONFIG_MTD_OOPS is not set
2958 +
2959 +#
2960 +# RAM/ROM/Flash chip drivers
2961 +#
2962 +CONFIG_MTD_CFI=y
2963 +# CONFIG_MTD_JEDECPROBE is not set
2964 +CONFIG_MTD_GEN_PROBE=y
2965 +# CONFIG_MTD_CFI_ADV_OPTIONS is not set
2966 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
2967 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
2968 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
2969 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
2970 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
2971 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
2972 +CONFIG_MTD_CFI_I1=y
2973 +CONFIG_MTD_CFI_I2=y
2974 +# CONFIG_MTD_CFI_I4 is not set
2975 +# CONFIG_MTD_CFI_I8 is not set
2976 +CONFIG_MTD_CFI_INTELEXT=y
2977 +CONFIG_MTD_CFI_AMDSTD=y
2978 +# CONFIG_MTD_CFI_STAA is not set
2979 +CONFIG_MTD_CFI_UTIL=y
2980 +# CONFIG_MTD_RAM is not set
2981 +# CONFIG_MTD_ROM is not set
2982 +# CONFIG_MTD_ABSENT is not set
2983 +
2984 +#
2985 +# Mapping drivers for chip access
2986 +#
2987 +# CONFIG_MTD_COMPLEX_MAPPINGS is not set
2988 +CONFIG_MTD_PHYSMAP=y
2989 +CONFIG_MTD_PHYSMAP_COMPAT=y
2990 +CONFIG_MTD_PHYSMAP_START=0x0
2991 +CONFIG_MTD_PHYSMAP_LEN=0x01000000
2992 +CONFIG_MTD_PHYSMAP_BANKWIDTH=1
2993 +# CONFIG_MTD_INTEL_VR_NOR is not set
2994 +# CONFIG_MTD_PLATRAM is not set
2995 +
2996 +#
2997 +# Self-contained MTD device drivers
2998 +#
2999 +# CONFIG_MTD_PMC551 is not set
3000 +# CONFIG_MTD_DATAFLASH is not set
3001 +# CONFIG_MTD_M25P80 is not set
3002 +# CONFIG_MTD_SLRAM is not set
3003 +# CONFIG_MTD_PHRAM is not set
3004 +# CONFIG_MTD_MTDRAM is not set
3005 +# CONFIG_MTD_BLOCK2MTD is not set
3006 +
3007 +#
3008 +# Disk-On-Chip Device Drivers
3009 +#
3010 +# CONFIG_MTD_DOC2000 is not set
3011 +# CONFIG_MTD_DOC2001 is not set
3012 +# CONFIG_MTD_DOC2001PLUS is not set
3013 +# CONFIG_MTD_NAND is not set
3014 +# CONFIG_MTD_ONENAND is not set
3015 +
3016 +#
3017 +# LPDDR flash memory drivers
3018 +#
3019 +# CONFIG_MTD_LPDDR is not set
3020 +
3021 +#
3022 +# UBI - Unsorted block images
3023 +#
3024 +# CONFIG_MTD_UBI is not set
3025 +# CONFIG_PARPORT is not set
3026 +CONFIG_BLK_DEV=y
3027 +# CONFIG_BLK_CPQ_DA is not set
3028 +# CONFIG_BLK_CPQ_CISS_DA is not set
3029 +# CONFIG_BLK_DEV_DAC960 is not set
3030 +# CONFIG_BLK_DEV_UMEM is not set
3031 +# CONFIG_BLK_DEV_COW_COMMON is not set
3032 +CONFIG_BLK_DEV_LOOP=y
3033 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set
3034 +# CONFIG_BLK_DEV_NBD is not set
3035 +# CONFIG_BLK_DEV_SX8 is not set
3036 +# CONFIG_BLK_DEV_UB is not set
3037 +CONFIG_BLK_DEV_RAM=y
3038 +CONFIG_BLK_DEV_RAM_COUNT=16
3039 +CONFIG_BLK_DEV_RAM_SIZE=64000
3040 +# CONFIG_BLK_DEV_XIP is not set
3041 +# CONFIG_CDROM_PKTCDVD is not set
3042 +# CONFIG_ATA_OVER_ETH is not set
3043 +# CONFIG_BLK_DEV_HD is not set
3044 +CONFIG_MISC_DEVICES=y
3045 +# CONFIG_PHANTOM is not set
3046 +# CONFIG_SGI_IOC4 is not set
3047 +# CONFIG_TIFM_CORE is not set
3048 +# CONFIG_ICS932S401 is not set
3049 +# CONFIG_ENCLOSURE_SERVICES is not set
3050 +# CONFIG_HP_ILO is not set
3051 +# CONFIG_C2PORT is not set
3052 +
3053 +#
3054 +# EEPROM support
3055 +#
3056 +# CONFIG_EEPROM_AT24 is not set
3057 +# CONFIG_EEPROM_AT25 is not set
3058 +# CONFIG_EEPROM_LEGACY is not set
3059 +# CONFIG_EEPROM_93CX6 is not set
3060 +CONFIG_HAVE_IDE=y
3061 +# CONFIG_IDE is not set
3062 +
3063 +#
3064 +# SCSI device support
3065 +#
3066 +# CONFIG_RAID_ATTRS is not set
3067 +CONFIG_SCSI=y
3068 +CONFIG_SCSI_DMA=y
3069 +# CONFIG_SCSI_TGT is not set
3070 +# CONFIG_SCSI_NETLINK is not set
3071 +CONFIG_SCSI_PROC_FS=y
3072 +
3073 +#
3074 +# SCSI support type (disk, tape, CD-ROM)
3075 +#
3076 +CONFIG_BLK_DEV_SD=y
3077 +# CONFIG_CHR_DEV_ST is not set
3078 +# CONFIG_CHR_DEV_OSST is not set
3079 +# CONFIG_BLK_DEV_SR is not set
3080 +CONFIG_CHR_DEV_SG=y
3081 +# CONFIG_CHR_DEV_SCH is not set
3082 +
3083 +#
3084 +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
3085 +#
3086 +CONFIG_SCSI_MULTI_LUN=y
3087 +# CONFIG_SCSI_CONSTANTS is not set
3088 +# CONFIG_SCSI_LOGGING is not set
3089 +# CONFIG_SCSI_SCAN_ASYNC is not set
3090 +CONFIG_SCSI_WAIT_SCAN=m
3091 +
3092 +#
3093 +# SCSI Transports
3094 +#
3095 +# CONFIG_SCSI_SPI_ATTRS is not set
3096 +# CONFIG_SCSI_FC_ATTRS is not set
3097 +# CONFIG_SCSI_ISCSI_ATTRS is not set
3098 +# CONFIG_SCSI_SAS_LIBSAS is not set
3099 +# CONFIG_SCSI_SRP_ATTRS is not set
3100 +CONFIG_SCSI_LOWLEVEL=y
3101 +# CONFIG_ISCSI_TCP is not set
3102 +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
3103 +# CONFIG_SCSI_3W_9XXX is not set
3104 +# CONFIG_SCSI_ACARD is not set
3105 +# CONFIG_SCSI_AACRAID is not set
3106 +# CONFIG_SCSI_AIC7XXX is not set
3107 +# CONFIG_SCSI_AIC7XXX_OLD is not set
3108 +# CONFIG_SCSI_AIC79XX is not set
3109 +# CONFIG_SCSI_AIC94XX is not set
3110 +# CONFIG_SCSI_DPT_I2O is not set
3111 +# CONFIG_SCSI_ADVANSYS is not set
3112 +# CONFIG_SCSI_ARCMSR is not set
3113 +# CONFIG_MEGARAID_NEWGEN is not set
3114 +# CONFIG_MEGARAID_LEGACY is not set
3115 +# CONFIG_MEGARAID_SAS is not set
3116 +# CONFIG_SCSI_HPTIOP is not set
3117 +# CONFIG_LIBFC is not set
3118 +# CONFIG_FCOE is not set
3119 +# CONFIG_SCSI_DMX3191D is not set
3120 +# CONFIG_SCSI_FUTURE_DOMAIN is not set
3121 +# CONFIG_SCSI_IPS is not set
3122 +# CONFIG_SCSI_INITIO is not set
3123 +# CONFIG_SCSI_INIA100 is not set
3124 +# CONFIG_SCSI_MVSAS is not set
3125 +# CONFIG_SCSI_STEX is not set
3126 +# CONFIG_SCSI_SYM53C8XX_2 is not set
3127 +# CONFIG_SCSI_IPR is not set
3128 +# CONFIG_SCSI_QLOGIC_1280 is not set
3129 +# CONFIG_SCSI_QLA_FC is not set
3130 +# CONFIG_SCSI_QLA_ISCSI is not set
3131 +# CONFIG_SCSI_LPFC is not set
3132 +# CONFIG_SCSI_DC395x is not set
3133 +# CONFIG_SCSI_DC390T is not set
3134 +# CONFIG_SCSI_NSP32 is not set
3135 +# CONFIG_SCSI_DEBUG is not set
3136 +# CONFIG_SCSI_SRP is not set
3137 +# CONFIG_SCSI_DH is not set
3138 +CONFIG_ATA=y
3139 +# CONFIG_ATA_NONSTANDARD is not set
3140 +CONFIG_SATA_PMP=y
3141 +# CONFIG_SATA_AHCI is not set
3142 +# CONFIG_SATA_SIL24 is not set
3143 +CONFIG_ATA_SFF=y
3144 +# CONFIG_SATA_SVW is not set
3145 +# CONFIG_ATA_PIIX is not set
3146 +# CONFIG_SATA_MV is not set
3147 +# CONFIG_SATA_NV is not set
3148 +# CONFIG_PDC_ADMA is not set
3149 +# CONFIG_SATA_QSTOR is not set
3150 +# CONFIG_SATA_PROMISE is not set
3151 +# CONFIG_SATA_SX4 is not set
3152 +# CONFIG_SATA_SIL is not set
3153 +# CONFIG_SATA_SIS is not set
3154 +# CONFIG_SATA_ULI is not set
3155 +# CONFIG_SATA_VIA is not set
3156 +# CONFIG_SATA_VITESSE is not set
3157 +# CONFIG_SATA_INIC162X is not set
3158 +# CONFIG_PATA_ALI is not set
3159 +# CONFIG_PATA_AMD is not set
3160 +# CONFIG_PATA_ARTOP is not set
3161 +# CONFIG_PATA_ATIIXP is not set
3162 +# CONFIG_PATA_CMD640_PCI is not set
3163 +# CONFIG_PATA_CMD64X is not set
3164 +# CONFIG_PATA_CS5520 is not set
3165 +# CONFIG_PATA_CS5530 is not set
3166 +# CONFIG_PATA_CYPRESS is not set
3167 +# CONFIG_PATA_EFAR is not set
3168 +# CONFIG_ATA_GENERIC is not set
3169 +# CONFIG_PATA_HPT366 is not set
3170 +# CONFIG_PATA_HPT37X is not set
3171 +# CONFIG_PATA_HPT3X2N is not set
3172 +# CONFIG_PATA_HPT3X3 is not set
3173 +# CONFIG_PATA_IT821X is not set
3174 +# CONFIG_PATA_IT8213 is not set
3175 +# CONFIG_PATA_JMICRON is not set
3176 +# CONFIG_PATA_TRIFLEX is not set
3177 +# CONFIG_PATA_MARVELL is not set
3178 +# CONFIG_PATA_MPIIX is not set
3179 +# CONFIG_PATA_OLDPIIX is not set
3180 +# CONFIG_PATA_NETCELL is not set
3181 +# CONFIG_PATA_NINJA32 is not set
3182 +# CONFIG_PATA_NS87410 is not set
3183 +# CONFIG_PATA_NS87415 is not set
3184 +# CONFIG_PATA_OPTI is not set
3185 +# CONFIG_PATA_OPTIDMA is not set
3186 +# CONFIG_PATA_PDC_OLD is not set
3187 +# CONFIG_PATA_RADISYS is not set
3188 +# CONFIG_PATA_RZ1000 is not set
3189 +# CONFIG_PATA_SC1200 is not set
3190 +# CONFIG_PATA_SERVERWORKS is not set
3191 +# CONFIG_PATA_PDC2027X is not set
3192 +# CONFIG_PATA_SIL680 is not set
3193 +# CONFIG_PATA_SIS is not set
3194 +# CONFIG_PATA_VIA is not set
3195 +# CONFIG_PATA_WINBOND is not set
3196 +# CONFIG_PATA_PLATFORM is not set
3197 +# CONFIG_PATA_SCH is not set
3198 +CONFIG_PATA_FSL=y
3199 +CONFIG_FSL_PATA_USE_DMA=y
3200 +# CONFIG_MD is not set
3201 +# CONFIG_FUSION is not set
3202 +
3203 +#
3204 +# IEEE 1394 (FireWire) support
3205 +#
3206 +
3207 +#
3208 +# Enable only one of the two stacks, unless you know what you are doing
3209 +#
3210 +# CONFIG_FIREWIRE is not set
3211 +# CONFIG_IEEE1394 is not set
3212 +# CONFIG_I2O is not set
3213 +CONFIG_NETDEVICES=y
3214 +# CONFIG_DUMMY is not set
3215 +# CONFIG_BONDING is not set
3216 +# CONFIG_MACVLAN is not set
3217 +# CONFIG_EQUALIZER is not set
3218 +# CONFIG_TUN is not set
3219 +# CONFIG_VETH is not set
3220 +# CONFIG_ARCNET is not set
3221 +CONFIG_PHYLIB=y
3222 +
3223 +#
3224 +# MII PHY device drivers
3225 +#
3226 +# CONFIG_MARVELL_PHY is not set
3227 +# CONFIG_DAVICOM_PHY is not set
3228 +# CONFIG_QSEMI_PHY is not set
3229 +# CONFIG_LXT_PHY is not set
3230 +# CONFIG_CICADA_PHY is not set
3231 +# CONFIG_VITESSE_PHY is not set
3232 +# CONFIG_SMSC_PHY is not set
3233 +# CONFIG_BROADCOM_PHY is not set
3234 +# CONFIG_BROADCOM5222_PHY is not set
3235 +# CONFIG_ICPLUS_PHY is not set
3236 +# CONFIG_REALTEK_PHY is not set
3237 +# CONFIG_NATIONAL_PHY is not set
3238 +# CONFIG_NATIONAL8364x_PHY is not set
3239 +CONFIG_NATIONAL8384x_PHY=y
3240 +# CONFIG_MicrelKSZ8041_PHY is not set
3241 +# CONFIG_STE10XP is not set
3242 +# CONFIG_LSI_ET1011C_PHY is not set
3243 +# CONFIG_FIXED_PHY is not set
3244 +# CONFIG_MDIO_BITBANG is not set
3245 +CONFIG_NET_ETHERNET=y
3246 +CONFIG_MII=y
3247 +# CONFIG_HAPPYMEAL is not set
3248 +# CONFIG_SUNGEM is not set
3249 +# CONFIG_CASSINI is not set
3250 +# CONFIG_NET_VENDOR_3COM is not set
3251 +# CONFIG_ENC28J60 is not set
3252 +# CONFIG_DNET is not set
3253 +# CONFIG_NET_TULIP is not set
3254 +# CONFIG_HP100 is not set
3255 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
3256 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
3257 +# CONFIG_IBM_NEW_EMAC_TAH is not set
3258 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
3259 +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
3260 +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
3261 +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
3262 +CONFIG_NET_PCI=y
3263 +# CONFIG_PCNET32 is not set
3264 +# CONFIG_AMD8111_ETH is not set
3265 +# CONFIG_ADAPTEC_STARFIRE is not set
3266 +# CONFIG_B44 is not set
3267 +# CONFIG_FORCEDETH is not set
3268 +CONFIG_E100=y
3269 +# CONFIG_FEALNX is not set
3270 +# CONFIG_NATSEMI is not set
3271 +# CONFIG_NE2K_PCI is not set
3272 +# CONFIG_8139CP is not set
3273 +CONFIG_8139TOO=y
3274 +# CONFIG_8139TOO_PIO is not set
3275 +# CONFIG_8139TOO_TUNE_TWISTER is not set
3276 +# CONFIG_8139TOO_8129 is not set
3277 +# CONFIG_8139_OLD_RX_RESET is not set
3278 +# CONFIG_R6040 is not set
3279 +# CONFIG_SIS900 is not set
3280 +# CONFIG_EPIC100 is not set
3281 +# CONFIG_SMSC9420 is not set
3282 +# CONFIG_SUNDANCE is not set
3283 +# CONFIG_TLAN is not set
3284 +# CONFIG_VIA_RHINE is not set
3285 +# CONFIG_SC92031 is not set
3286 +CONFIG_FEC=y
3287 +# CONFIG_FEC2 is not set
3288 +# CONFIG_ATL2 is not set
3289 +CONFIG_NETDEV_1000=y
3290 +# CONFIG_ACENIC is not set
3291 +# CONFIG_DL2K is not set
3292 +CONFIG_E1000=y
3293 +# CONFIG_E1000E is not set
3294 +# CONFIG_IP1000 is not set
3295 +# CONFIG_IGB is not set
3296 +# CONFIG_NS83820 is not set
3297 +# CONFIG_HAMACHI is not set
3298 +# CONFIG_YELLOWFIN is not set
3299 +# CONFIG_R8169 is not set
3300 +# CONFIG_SIS190 is not set
3301 +# CONFIG_SKGE is not set
3302 +# CONFIG_SKY2 is not set
3303 +# CONFIG_VIA_VELOCITY is not set
3304 +# CONFIG_TIGON3 is not set
3305 +# CONFIG_BNX2 is not set
3306 +# CONFIG_QLA3XXX is not set
3307 +# CONFIG_ATL1 is not set
3308 +# CONFIG_ATL1E is not set
3309 +# CONFIG_ATL1C is not set
3310 +# CONFIG_JME is not set
3311 +# CONFIG_NETDEV_10000 is not set
3312 +# CONFIG_TR is not set
3313 +
3314 +#
3315 +# Wireless LAN
3316 +#
3317 +# CONFIG_WLAN_PRE80211 is not set
3318 +# CONFIG_WLAN_80211 is not set
3319 +# CONFIG_IWLWIFI_LEDS is not set
3320 +
3321 +#
3322 +# Enable WiMAX (Networking options) to see the WiMAX drivers
3323 +#
3324 +
3325 +#
3326 +# USB Network Adapters
3327 +#
3328 +# CONFIG_USB_CATC is not set
3329 +# CONFIG_USB_KAWETH is not set
3330 +# CONFIG_USB_PEGASUS is not set
3331 +CONFIG_USB_RTL8150=y
3332 +# CONFIG_USB_USBNET is not set
3333 +# CONFIG_WAN is not set
3334 +# CONFIG_FDDI is not set
3335 +# CONFIG_HIPPI is not set
3336 +# CONFIG_PPP is not set
3337 +# CONFIG_SLIP is not set
3338 +# CONFIG_NET_FC is not set
3339 +# CONFIG_NETCONSOLE is not set
3340 +# CONFIG_NETPOLL is not set
3341 +# CONFIG_NET_POLL_CONTROLLER is not set
3342 +# CONFIG_ISDN is not set
3343 +# CONFIG_PHONE is not set
3344 +
3345 +#
3346 +# Input device support
3347 +#
3348 +CONFIG_INPUT=y
3349 +# CONFIG_INPUT_FF_MEMLESS is not set
3350 +# CONFIG_INPUT_POLLDEV is not set
3351 +
3352 +#
3353 +# Userland interfaces
3354 +#
3355 +CONFIG_INPUT_MOUSEDEV=y
3356 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
3357 +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
3358 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
3359 +# CONFIG_INPUT_JOYDEV is not set
3360 +CONFIG_INPUT_EVDEV=y
3361 +# CONFIG_INPUT_EVBUG is not set
3362 +
3363 +#
3364 +# Input Device Drivers
3365 +#
3366 +CONFIG_INPUT_KEYBOARD=y
3367 +# CONFIG_KEYBOARD_ATKBD is not set
3368 +# CONFIG_KEYBOARD_SUNKBD is not set
3369 +# CONFIG_KEYBOARD_LKKBD is not set
3370 +# CONFIG_KEYBOARD_XTKBD is not set
3371 +# CONFIG_KEYBOARD_NEWTON is not set
3372 +# CONFIG_KEYBOARD_STOWAWAY is not set
3373 +# CONFIG_INPUT_MOUSE is not set
3374 +# CONFIG_INPUT_JOYSTICK is not set
3375 +# CONFIG_INPUT_TABLET is not set
3376 +# CONFIG_INPUT_TOUCHSCREEN is not set
3377 +# CONFIG_INPUT_MISC is not set
3378 +
3379 +#
3380 +# Hardware I/O ports
3381 +#
3382 +CONFIG_SERIO=y
3383 +CONFIG_SERIO_SERPORT=y
3384 +# CONFIG_SERIO_PCIPS2 is not set
3385 +# CONFIG_SERIO_LIBPS2 is not set
3386 +# CONFIG_SERIO_RAW is not set
3387 +# CONFIG_GAMEPORT is not set
3388 +
3389 +#
3390 +# Character devices
3391 +#
3392 +CONFIG_VT=y
3393 +CONFIG_CONSOLE_TRANSLATIONS=y
3394 +CONFIG_VT_CONSOLE=y
3395 +CONFIG_HW_CONSOLE=y
3396 +# CONFIG_VT_HW_CONSOLE_BINDING is not set
3397 +CONFIG_DEVKMEM=y
3398 +CONFIG_DEVSRAM=m
3399 +# CONFIG_SERIAL_NONSTANDARD is not set
3400 +# CONFIG_NOZOMI is not set
3401 +
3402 +#
3403 +# Serial drivers
3404 +#
3405 +# CONFIG_SERIAL_8250 is not set
3406 +
3407 +#
3408 +# Non-8250 serial port support
3409 +#
3410 +CONFIG_SERIAL_CORE=y
3411 +CONFIG_SERIAL_CORE_CONSOLE=y
3412 +# CONFIG_SERIAL_COLDFIRE_IRDA is not set
3413 +# CONFIG_SERIAL_COLDFIRE_EDMA is not set
3414 +CONFIG_SERIAL_MCF=y
3415 +CONFIG_SERIAL_MCF_BAUDRATE=115200
3416 +CONFIG_SERIAL_MCF_CONSOLE=y
3417 +# CONFIG_SERIAL_JSM is not set
3418 +CONFIG_UNIX98_PTYS=y
3419 +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
3420 +# CONFIG_LEGACY_PTYS is not set
3421 +# CONFIG_IPMI_HANDLER is not set
3422 +# CONFIG_HW_RANDOM is not set
3423 +# CONFIG_GEN_RTC is not set
3424 +# CONFIG_R3964 is not set
3425 +# CONFIG_APPLICOM is not set
3426 +# CONFIG_RAW_DRIVER is not set
3427 +# CONFIG_TCG_TPM is not set
3428 +CONFIG_I2C=y
3429 +CONFIG_I2C_BOARDINFO=y
3430 +CONFIG_I2C_CHARDEV=y
3431 +CONFIG_I2C_HELPER_AUTO=y
3432 +
3433 +#
3434 +# I2C Hardware Bus support
3435 +#
3436 +
3437 +#
3438 +# PC SMBus host controller drivers
3439 +#
3440 +# CONFIG_I2C_ALI1535 is not set
3441 +# CONFIG_I2C_ALI1563 is not set
3442 +# CONFIG_I2C_ALI15X3 is not set
3443 +# CONFIG_I2C_AMD756 is not set
3444 +# CONFIG_I2C_AMD8111 is not set
3445 +# CONFIG_I2C_I801 is not set
3446 +# CONFIG_I2C_ISCH is not set
3447 +# CONFIG_I2C_PIIX4 is not set
3448 +# CONFIG_I2C_NFORCE2 is not set
3449 +# CONFIG_I2C_SIS5595 is not set
3450 +# CONFIG_I2C_SIS630 is not set
3451 +# CONFIG_I2C_SIS96X is not set
3452 +# CONFIG_I2C_VIA is not set
3453 +# CONFIG_I2C_VIAPRO is not set
3454 +
3455 +#
3456 +# I2C system bus drivers (mostly embedded / system-on-chip)
3457 +#
3458 +CONFIG_I2C_MCF=y
3459 +# CONFIG_I2C_OCORES is not set
3460 +# CONFIG_I2C_SIMTEC is not set
3461 +
3462 +#
3463 +# External I2C/SMBus adapter drivers
3464 +#
3465 +# CONFIG_I2C_PARPORT_LIGHT is not set
3466 +# CONFIG_I2C_TAOS_EVM is not set
3467 +# CONFIG_I2C_TINY_USB is not set
3468 +
3469 +#
3470 +# Graphics adapter I2C/DDC channel drivers
3471 +#
3472 +# CONFIG_I2C_VOODOO3 is not set
3473 +
3474 +#
3475 +# Other I2C/SMBus bus drivers
3476 +#
3477 +# CONFIG_I2C_PCA_PLATFORM is not set
3478 +# CONFIG_I2C_STUB is not set
3479 +
3480 +#
3481 +# Miscellaneous I2C Chip support
3482 +#
3483 +# CONFIG_DS1682 is not set
3484 +# CONFIG_SENSORS_PCF8574 is not set
3485 +# CONFIG_PCF8575 is not set
3486 +# CONFIG_SENSORS_PCA9539 is not set
3487 +# CONFIG_SENSORS_PCF8591 is not set
3488 +# CONFIG_SENSORS_MAX6875 is not set
3489 +# CONFIG_SENSORS_TSL2550 is not set
3490 +# CONFIG_I2C_DEBUG_CORE is not set
3491 +# CONFIG_I2C_DEBUG_ALGO is not set
3492 +# CONFIG_I2C_DEBUG_BUS is not set
3493 +# CONFIG_I2C_DEBUG_CHIP is not set
3494 +CONFIG_SPI=y
3495 +CONFIG_SPI_MASTER=y
3496 +
3497 +#
3498 +# SPI Master Controller Drivers
3499 +#
3500 +# CONFIG_SPI_BITBANG is not set
3501 +CONFIG_SPI_DSPI=y
3502 +CONFIG_SPI_COLDFIRE_DSPI_EDMA=y
3503 +# CONFIG_VOIP_FXS is not set
3504 +# CONFIG_VOIP_FXO is not set
3505 +
3506 +#
3507 +# SPI Protocol Masters
3508 +#
3509 +# CONFIG_SPI_SPIDEV is not set
3510 +# CONFIG_SPI_TLE62X0 is not set
3511 +# CONFIG_W1 is not set
3512 +# CONFIG_POWER_SUPPLY is not set
3513 +# CONFIG_HWMON is not set
3514 +# CONFIG_THERMAL is not set
3515 +# CONFIG_THERMAL_HWMON is not set
3516 +CONFIG_WATCHDOG=y
3517 +# CONFIG_WATCHDOG_NOWAYOUT is not set
3518 +
3519 +#
3520 +# Watchdog Device Drivers
3521 +#
3522 +# CONFIG_SOFT_WATCHDOG is not set
3523 +# CONFIG_ALIM7101_WDT is not set
3524 +CONFIG_COLDFIRE_WATCHDOG=y
3525 +
3526 +#
3527 +# PCI-based Watchdog Cards
3528 +#
3529 +# CONFIG_PCIPCWATCHDOG is not set
3530 +# CONFIG_WDTPCI is not set
3531 +
3532 +#
3533 +# USB-based Watchdog Cards
3534 +#
3535 +# CONFIG_USBPCWATCHDOG is not set
3536 +CONFIG_SSB_POSSIBLE=y
3537 +
3538 +#
3539 +# Sonics Silicon Backplane
3540 +#
3541 +# CONFIG_SSB is not set
3542 +
3543 +#
3544 +# Multifunction device drivers
3545 +#
3546 +# CONFIG_MFD_CORE is not set
3547 +# CONFIG_MFD_SM501 is not set
3548 +# CONFIG_HTC_PASIC3 is not set
3549 +# CONFIG_MFD_TMIO is not set
3550 +# CONFIG_PMIC_DA903X is not set
3551 +# CONFIG_MFD_WM8400 is not set
3552 +# CONFIG_MFD_WM8350_I2C is not set
3553 +# CONFIG_MFD_PCF50633 is not set
3554 +# CONFIG_REGULATOR is not set
3555 +
3556 +#
3557 +# Multimedia devices
3558 +#
3559 +
3560 +#
3561 +# Multimedia core support
3562 +#
3563 +# CONFIG_VIDEO_DEV is not set
3564 +# CONFIG_DVB_CORE is not set
3565 +# CONFIG_VIDEO_MEDIA is not set
3566 +
3567 +#
3568 +# Multimedia drivers
3569 +#
3570 +CONFIG_DAB=y
3571 +# CONFIG_USB_DABUSB is not set
3572 +
3573 +#
3574 +# Graphics support
3575 +#
3576 +# CONFIG_DRM is not set
3577 +# CONFIG_VGASTATE is not set
3578 +CONFIG_VIDEO_OUTPUT_CONTROL=m
3579 +# CONFIG_FB is not set
3580 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
3581 +
3582 +#
3583 +# Display device support
3584 +#
3585 +# CONFIG_DISPLAY_SUPPORT is not set
3586 +
3587 +#
3588 +# Console display driver support
3589 +#
3590 +CONFIG_DUMMY_CONSOLE=y
3591 +CONFIG_SOUND=y
3592 +CONFIG_SOUND_OSS_CORE=y
3593 +CONFIG_SND=y
3594 +CONFIG_SND_TIMER=y
3595 +CONFIG_SND_PCM=y
3596 +# CONFIG_SND_SEQUENCER is not set
3597 +CONFIG_SND_OSSEMUL=y
3598 +# CONFIG_SND_MIXER_OSS is not set
3599 +CONFIG_SND_PCM_OSS=y
3600 +CONFIG_SND_PCM_OSS_PLUGINS=y
3601 +# CONFIG_SND_HRTIMER is not set
3602 +# CONFIG_SND_DYNAMIC_MINORS is not set
3603 +CONFIG_SND_SUPPORT_OLD_API=y
3604 +CONFIG_SND_VERBOSE_PROCFS=y
3605 +# CONFIG_SND_VERBOSE_PRINTK is not set
3606 +# CONFIG_SND_DEBUG is not set
3607 +CONFIG_SND_DRIVERS=y
3608 +# CONFIG_SND_DUMMY is not set
3609 +# CONFIG_SND_MTPAV is not set
3610 +# CONFIG_SND_SERIAL_U16550 is not set
3611 +# CONFIG_SND_MPU401 is not set
3612 +CONFIG_SND_PCI=y
3613 +# CONFIG_SND_AD1889 is not set
3614 +# CONFIG_SND_ALS300 is not set
3615 +# CONFIG_SND_ALI5451 is not set
3616 +# CONFIG_SND_ATIIXP is not set
3617 +# CONFIG_SND_ATIIXP_MODEM is not set
3618 +# CONFIG_SND_AU8810 is not set
3619 +# CONFIG_SND_AU8820 is not set
3620 +# CONFIG_SND_AU8830 is not set
3621 +# CONFIG_SND_AW2 is not set
3622 +# CONFIG_SND_AZT3328 is not set
3623 +# CONFIG_SND_BT87X is not set
3624 +# CONFIG_SND_CA0106 is not set
3625 +# CONFIG_SND_CMIPCI is not set
3626 +# CONFIG_SND_OXYGEN is not set
3627 +# CONFIG_SND_CS4281 is not set
3628 +# CONFIG_SND_CS46XX is not set
3629 +# CONFIG_SND_DARLA20 is not set
3630 +# CONFIG_SND_GINA20 is not set
3631 +# CONFIG_SND_LAYLA20 is not set
3632 +# CONFIG_SND_DARLA24 is not set
3633 +# CONFIG_SND_GINA24 is not set
3634 +# CONFIG_SND_LAYLA24 is not set
3635 +# CONFIG_SND_MONA is not set
3636 +# CONFIG_SND_MIA is not set
3637 +# CONFIG_SND_ECHO3G is not set
3638 +# CONFIG_SND_INDIGO is not set
3639 +# CONFIG_SND_INDIGOIO is not set
3640 +# CONFIG_SND_INDIGODJ is not set
3641 +# CONFIG_SND_EMU10K1 is not set
3642 +# CONFIG_SND_EMU10K1X is not set
3643 +# CONFIG_SND_ENS1370 is not set
3644 +# CONFIG_SND_ENS1371 is not set
3645 +# CONFIG_SND_ES1938 is not set
3646 +# CONFIG_SND_ES1968 is not set
3647 +# CONFIG_SND_FM801 is not set
3648 +# CONFIG_SND_HDA_INTEL is not set
3649 +# CONFIG_SND_HDSP is not set
3650 +# CONFIG_SND_HDSPM is not set
3651 +# CONFIG_SND_HIFIER is not set
3652 +# CONFIG_SND_ICE1712 is not set
3653 +# CONFIG_SND_ICE1724 is not set
3654 +# CONFIG_SND_INTEL8X0 is not set
3655 +# CONFIG_SND_INTEL8X0M is not set
3656 +# CONFIG_SND_KORG1212 is not set
3657 +# CONFIG_SND_MAESTRO3 is not set
3658 +# CONFIG_SND_MIXART is not set
3659 +# CONFIG_SND_NM256 is not set
3660 +# CONFIG_SND_PCXHR is not set
3661 +# CONFIG_SND_RIPTIDE is not set
3662 +# CONFIG_SND_RME32 is not set
3663 +# CONFIG_SND_RME96 is not set
3664 +# CONFIG_SND_RME9652 is not set
3665 +# CONFIG_SND_SONICVIBES is not set
3666 +# CONFIG_SND_TRIDENT is not set
3667 +# CONFIG_SND_VIA82XX is not set
3668 +# CONFIG_SND_VIA82XX_MODEM is not set
3669 +# CONFIG_SND_VIRTUOSO is not set
3670 +# CONFIG_SND_VX222 is not set
3671 +# CONFIG_SND_YMFPCI is not set
3672 +
3673 +#
3674 +# ALSA for Coldfire
3675 +#
3676 +CONFIG_SND_COLDFIRE=y
3677 +CONFIG_SND_SPI=y
3678 +CONFIG_SND_USB=y
3679 +# CONFIG_SND_USB_AUDIO is not set
3680 +# CONFIG_SND_USB_CAIAQ is not set
3681 +# CONFIG_SND_SOC is not set
3682 +# CONFIG_SOUND_PRIME is not set
3683 +CONFIG_HID_SUPPORT=y
3684 +CONFIG_HID=y
3685 +CONFIG_HID_DEBUG=y
3686 +# CONFIG_HIDRAW is not set
3687 +
3688 +#
3689 +# USB Input Devices
3690 +#
3691 +CONFIG_USB_HID=y
3692 +# CONFIG_HID_PID is not set
3693 +# CONFIG_USB_HIDDEV is not set
3694 +
3695 +#
3696 +# Special HID drivers
3697 +#
3698 +CONFIG_HID_COMPAT=y
3699 +# CONFIG_HID_A4TECH is not set
3700 +# CONFIG_HID_APPLE is not set
3701 +# CONFIG_HID_BELKIN is not set
3702 +# CONFIG_HID_CHERRY is not set
3703 +# CONFIG_HID_CHICONY is not set
3704 +# CONFIG_HID_CYPRESS is not set
3705 +# CONFIG_HID_EZKEY is not set
3706 +# CONFIG_HID_GYRATION is not set
3707 +# CONFIG_HID_LOGITECH is not set
3708 +# CONFIG_HID_MICROSOFT is not set
3709 +# CONFIG_HID_MONTEREY is not set
3710 +# CONFIG_HID_NTRIG is not set
3711 +# CONFIG_HID_PANTHERLORD is not set
3712 +# CONFIG_HID_PETALYNX is not set
3713 +# CONFIG_HID_SAMSUNG is not set
3714 +# CONFIG_HID_SONY is not set
3715 +# CONFIG_HID_SUNPLUS is not set
3716 +# CONFIG_GREENASIA_FF is not set
3717 +# CONFIG_HID_TOPSEED is not set
3718 +# CONFIG_THRUSTMASTER_FF is not set
3719 +# CONFIG_ZEROPLUS_FF is not set
3720 +CONFIG_USB_SUPPORT=y
3721 +CONFIG_USB_ARCH_HAS_HCD=y
3722 +CONFIG_USB_ARCH_HAS_OHCI=y
3723 +CONFIG_USB_ARCH_HAS_EHCI=y
3724 +CONFIG_USB=y
3725 +# CONFIG_USB_DEBUG is not set
3726 +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
3727 +
3728 +#
3729 +# Miscellaneous USB options
3730 +#
3731 +CONFIG_USB_DEVICEFS=y
3732 +# CONFIG_USB_DEVICE_CLASS is not set
3733 +# CONFIG_USB_DYNAMIC_MINORS is not set
3734 +CONFIG_USB_SUSPEND=y
3735 +CONFIG_USB_OTG=y
3736 +# CONFIG_USB_OTG_WHITELIST is not set
3737 +# CONFIG_USB_OTG_BLACKLIST_HUB is not set
3738 +# CONFIG_USB_MON is not set
3739 +# CONFIG_USB_WUSB is not set
3740 +# CONFIG_USB_WUSB_CBAF is not set
3741 +
3742 +#
3743 +# USB Host Controller Drivers
3744 +#
3745 +# CONFIG_USB_C67X00_HCD is not set
3746 +CONFIG_USB_EHCI_HCD=m
3747 +CONFIG_USB_EHCI_ROOT_HUB_TT=y
3748 +# CONFIG_USB_EHCI_TT_NEWSCHED is not set
3749 +CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
3750 +CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
3751 +CONFIG_USB_EHCI_FSL=y
3752 +# CONFIG_USB_OXU210HP_HCD is not set
3753 +# CONFIG_USB_ISP116X_HCD is not set
3754 +# CONFIG_USB_ISP1760_HCD is not set
3755 +# CONFIG_USB_OHCI_HCD is not set
3756 +# CONFIG_USB_UHCI_HCD is not set
3757 +# CONFIG_USB_SL811_HCD is not set
3758 +# CONFIG_USB_R8A66597_HCD is not set
3759 +# CONFIG_USB_WHCI_HCD is not set
3760 +# CONFIG_USB_HWA_HCD is not set
3761 +CONFIG_USB_M5445X_ULPI=y
3762 +# CONFIG_USB_M5445X_FSLS is not set
3763 +# CONFIG_USB_M5441X_ULPI is not set
3764 +# CONFIG_USB_M5441X_FSLS is not set
3765 +# CONFIG_USB_GADGET_MUSB_HDRC is not set
3766 +
3767 +#
3768 +# USB Device Class drivers
3769 +#
3770 +# CONFIG_USB_ACM is not set
3771 +# CONFIG_USB_PRINTER is not set
3772 +# CONFIG_USB_WDM is not set
3773 +# CONFIG_USB_TMC is not set
3774 +
3775 +#
3776 +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
3777 +#
3778 +
3779 +#
3780 +# see USB_STORAGE Help for more information
3781 +#
3782 +CONFIG_USB_STORAGE=y
3783 +# CONFIG_USB_STORAGE_DEBUG is not set
3784 +# CONFIG_USB_STORAGE_DATAFAB is not set
3785 +# CONFIG_USB_STORAGE_FREECOM is not set
3786 +# CONFIG_USB_STORAGE_ISD200 is not set
3787 +# CONFIG_USB_STORAGE_USBAT is not set
3788 +# CONFIG_USB_STORAGE_SDDR09 is not set
3789 +# CONFIG_USB_STORAGE_SDDR55 is not set
3790 +# CONFIG_USB_STORAGE_JUMPSHOT is not set
3791 +# CONFIG_USB_STORAGE_ALAUDA is not set
3792 +# CONFIG_USB_STORAGE_ONETOUCH is not set
3793 +# CONFIG_USB_STORAGE_KARMA is not set
3794 +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
3795 +# CONFIG_USB_LIBUSUAL is not set
3796 +
3797 +#
3798 +# USB Imaging devices
3799 +#
3800 +# CONFIG_USB_MDC800 is not set
3801 +# CONFIG_USB_MICROTEK is not set
3802 +
3803 +#
3804 +# USB port drivers
3805 +#
3806 +# CONFIG_USB_SERIAL is not set
3807 +
3808 +#
3809 +# USB Miscellaneous drivers
3810 +#
3811 +# CONFIG_USB_EMI62 is not set
3812 +# CONFIG_USB_EMI26 is not set
3813 +# CONFIG_USB_ADUTUX is not set
3814 +# CONFIG_USB_SEVSEG is not set
3815 +# CONFIG_USB_RIO500 is not set
3816 +# CONFIG_USB_LEGOTOWER is not set
3817 +# CONFIG_USB_LCD is not set
3818 +# CONFIG_USB_BERRY_CHARGE is not set
3819 +# CONFIG_USB_LED is not set
3820 +# CONFIG_USB_CYPRESS_CY7C63 is not set
3821 +# CONFIG_USB_CYTHERM is not set
3822 +# CONFIG_USB_PHIDGET is not set
3823 +# CONFIG_USB_IDMOUSE is not set
3824 +# CONFIG_USB_FTDI_ELAN is not set
3825 +# CONFIG_USB_APPLEDISPLAY is not set
3826 +# CONFIG_USB_SISUSBVGA is not set
3827 +# CONFIG_USB_LD is not set
3828 +# CONFIG_USB_TRANCEVIBRATOR is not set
3829 +# CONFIG_USB_IOWARRIOR is not set
3830 +# CONFIG_USB_TEST is not set
3831 +# CONFIG_USB_ISIGHTFW is not set
3832 +# CONFIG_USB_VST is not set
3833 +CONFIG_USB_GADGET=m
3834 +# CONFIG_USB_GADGET_DEBUG_FILES is not set
3835 +CONFIG_USB_GADGET_VBUS_DRAW=2
3836 +CONFIG_USB_GADGET_SELECTED=y
3837 +# CONFIG_USB_GADGET_AT91 is not set
3838 +# CONFIG_USB_GADGET_ATMEL_USBA is not set
3839 +CONFIG_USB_GADGET_FSL_USB2=y
3840 +CONFIG_USB_FSL_USB2=m
3841 +# CONFIG_USB_GADGET_LH7A40X is not set
3842 +# CONFIG_USB_GADGET_OMAP is not set
3843 +# CONFIG_USB_GADGET_PXA25X is not set
3844 +# CONFIG_USB_GADGET_PXA27X is not set
3845 +# CONFIG_USB_GADGET_S3C2410 is not set
3846 +# CONFIG_USB_GADGET_IMX is not set
3847 +# CONFIG_USB_GADGET_M66592 is not set
3848 +# CONFIG_USB_GADGET_AMD5536UDC is not set
3849 +# CONFIG_USB_GADGET_FSL_QE is not set
3850 +# CONFIG_USB_GADGET_CI13XXX is not set
3851 +# CONFIG_USB_GADGET_NET2280 is not set
3852 +# CONFIG_USB_GADGET_GOKU is not set
3853 +# CONFIG_USB_GADGET_DUMMY_HCD is not set
3854 +CONFIG_USB_GADGET_DUALSPEED=y
3855 +# CONFIG_USB_ZERO is not set
3856 +CONFIG_USB_ETH=m
3857 +CONFIG_USB_ETH_RNDIS=y
3858 +# CONFIG_USB_GADGETFS is not set
3859 +CONFIG_USB_FILE_STORAGE=m
3860 +# CONFIG_USB_FILE_STORAGE_TEST is not set
3861 +# CONFIG_USB_G_SERIAL is not set
3862 +# CONFIG_USB_MIDI_GADGET is not set
3863 +# CONFIG_USB_G_PRINTER is not set
3864 +# CONFIG_USB_CDC_COMPOSITE is not set
3865 +
3866 +#
3867 +# OTG and related infrastructure
3868 +#
3869 +# CONFIG_UWB is not set
3870 +# CONFIG_MMC is not set
3871 +# CONFIG_MEMSTICK is not set
3872 +# CONFIG_NEW_LEDS is not set
3873 +# CONFIG_ACCESSIBILITY is not set
3874 +# CONFIG_INFINIBAND is not set
3875 +# CONFIG_RTC_CLASS is not set
3876 +CONFIG_DMADEVICES=y
3877 +
3878 +#
3879 +# DMA Devices
3880 +#
3881 +CONFIG_COLDFIRE_EDMA=y
3882 +CONFIG_COLDFIRE_EDMA_TEST=m
3883 +# CONFIG_UIO is not set
3884 +# CONFIG_STAGING is not set
3885 +
3886 +#
3887 +# Character devices
3888 +#
3889 +CONFIG_TICK_ONESHOT=y
3890 +CONFIG_NO_HZ=y
3891 +CONFIG_HIGH_RES_TIMERS=y
3892 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
3893 +
3894 +#
3895 +# File systems
3896 +#
3897 +CONFIG_EXT2_FS=y
3898 +# CONFIG_EXT2_FS_XATTR is not set
3899 +# CONFIG_EXT2_FS_XIP is not set
3900 +CONFIG_EXT3_FS=y
3901 +CONFIG_EXT3_FS_XATTR=y
3902 +# CONFIG_EXT3_FS_POSIX_ACL is not set
3903 +# CONFIG_EXT3_FS_SECURITY is not set
3904 +# CONFIG_EXT4_FS is not set
3905 +CONFIG_JBD=y
3906 +CONFIG_FS_MBCACHE=y
3907 +# CONFIG_REISERFS_FS is not set
3908 +# CONFIG_JFS_FS is not set
3909 +# CONFIG_FS_POSIX_ACL is not set
3910 +CONFIG_FILE_LOCKING=y
3911 +# CONFIG_XFS_FS is not set
3912 +# CONFIG_GFS2_FS is not set
3913 +# CONFIG_OCFS2_FS is not set
3914 +# CONFIG_BTRFS_FS is not set
3915 +CONFIG_DNOTIFY=y
3916 +CONFIG_INOTIFY=y
3917 +CONFIG_INOTIFY_USER=y
3918 +# CONFIG_QUOTA is not set
3919 +# CONFIG_AUTOFS_FS is not set
3920 +# CONFIG_AUTOFS4_FS is not set
3921 +# CONFIG_FUSE_FS is not set
3922 +
3923 +#
3924 +# CD-ROM/DVD Filesystems
3925 +#
3926 +# CONFIG_ISO9660_FS is not set
3927 +# CONFIG_UDF_FS is not set
3928 +
3929 +#
3930 +# DOS/FAT/NT Filesystems
3931 +#
3932 +CONFIG_FAT_FS=y
3933 +CONFIG_MSDOS_FS=y
3934 +CONFIG_VFAT_FS=y
3935 +CONFIG_FAT_DEFAULT_CODEPAGE=437
3936 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
3937 +CONFIG_NTFS_FS=y
3938 +# CONFIG_NTFS_DEBUG is not set
3939 +CONFIG_NTFS_RW=y
3940 +
3941 +#
3942 +# Pseudo filesystems
3943 +#
3944 +CONFIG_PROC_FS=y
3945 +# CONFIG_PROC_KCORE is not set
3946 +CONFIG_PROC_SYSCTL=y
3947 +CONFIG_PROC_PAGE_MONITOR=y
3948 +CONFIG_SYSFS=y
3949 +CONFIG_TMPFS=y
3950 +# CONFIG_TMPFS_POSIX_ACL is not set
3951 +# CONFIG_HUGETLB_PAGE is not set
3952 +# CONFIG_CONFIGFS_FS is not set
3953 +CONFIG_MISC_FILESYSTEMS=y
3954 +# CONFIG_ADFS_FS is not set
3955 +# CONFIG_AFFS_FS is not set
3956 +# CONFIG_HFS_FS is not set
3957 +# CONFIG_HFSPLUS_FS is not set
3958 +# CONFIG_BEFS_FS is not set
3959 +# CONFIG_BFS_FS is not set
3960 +# CONFIG_EFS_FS is not set
3961 +CONFIG_JFFS2_FS=y
3962 +CONFIG_JFFS2_FS_DEBUG=0
3963 +CONFIG_JFFS2_FS_WRITEBUFFER=y
3964 +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
3965 +# CONFIG_JFFS2_SUMMARY is not set
3966 +# CONFIG_JFFS2_FS_XATTR is not set
3967 +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
3968 +CONFIG_JFFS2_ZLIB=y
3969 +# CONFIG_JFFS2_LZO is not set
3970 +CONFIG_JFFS2_RTIME=y
3971 +# CONFIG_JFFS2_RUBIN is not set
3972 +# CONFIG_CRAMFS is not set
3973 +# CONFIG_SQUASHFS is not set
3974 +# CONFIG_VXFS_FS is not set
3975 +CONFIG_MINIX_FS=y
3976 +# CONFIG_OMFS_FS is not set
3977 +# CONFIG_HPFS_FS is not set
3978 +# CONFIG_QNX4FS_FS is not set
3979 +# CONFIG_ROMFS_FS is not set
3980 +# CONFIG_SYSV_FS is not set
3981 +# CONFIG_UFS_FS is not set
3982 +CONFIG_NETWORK_FILESYSTEMS=y
3983 +CONFIG_NFS_FS=y
3984 +CONFIG_NFS_V3=y
3985 +# CONFIG_NFS_V3_ACL is not set
3986 +# CONFIG_NFS_V4 is not set
3987 +CONFIG_ROOT_NFS=y
3988 +# CONFIG_NFSD is not set
3989 +CONFIG_LOCKD=y
3990 +CONFIG_LOCKD_V4=y
3991 +CONFIG_NFS_COMMON=y
3992 +CONFIG_SUNRPC=y
3993 +# CONFIG_SUNRPC_REGISTER_V4 is not set
3994 +# CONFIG_RPCSEC_GSS_KRB5 is not set
3995 +# CONFIG_RPCSEC_GSS_SPKM3 is not set
3996 +# CONFIG_SMB_FS is not set
3997 +# CONFIG_CIFS is not set
3998 +# CONFIG_NCP_FS is not set
3999 +# CONFIG_CODA_FS is not set
4000 +# CONFIG_AFS_FS is not set
4001 +
4002 +#
4003 +# Partition Types
4004 +#
4005 +CONFIG_PARTITION_ADVANCED=y
4006 +# CONFIG_ACORN_PARTITION is not set
4007 +# CONFIG_OSF_PARTITION is not set
4008 +# CONFIG_AMIGA_PARTITION is not set
4009 +# CONFIG_ATARI_PARTITION is not set
4010 +# CONFIG_MAC_PARTITION is not set
4011 +CONFIG_MSDOS_PARTITION=y
4012 +# CONFIG_BSD_DISKLABEL is not set
4013 +# CONFIG_MINIX_SUBPARTITION is not set
4014 +# CONFIG_SOLARIS_X86_PARTITION is not set
4015 +# CONFIG_UNIXWARE_DISKLABEL is not set
4016 +# CONFIG_LDM_PARTITION is not set
4017 +# CONFIG_SGI_PARTITION is not set
4018 +# CONFIG_ULTRIX_PARTITION is not set
4019 +# CONFIG_SUN_PARTITION is not set
4020 +# CONFIG_KARMA_PARTITION is not set
4021 +# CONFIG_EFI_PARTITION is not set
4022 +# CONFIG_SYSV68_PARTITION is not set
4023 +CONFIG_NLS=y
4024 +CONFIG_NLS_DEFAULT="iso8859-1"
4025 +CONFIG_NLS_CODEPAGE_437=y
4026 +# CONFIG_NLS_CODEPAGE_737 is not set
4027 +# CONFIG_NLS_CODEPAGE_775 is not set
4028 +# CONFIG_NLS_CODEPAGE_850 is not set
4029 +# CONFIG_NLS_CODEPAGE_852 is not set
4030 +# CONFIG_NLS_CODEPAGE_855 is not set
4031 +# CONFIG_NLS_CODEPAGE_857 is not set
4032 +# CONFIG_NLS_CODEPAGE_860 is not set
4033 +# CONFIG_NLS_CODEPAGE_861 is not set
4034 +# CONFIG_NLS_CODEPAGE_862 is not set
4035 +# CONFIG_NLS_CODEPAGE_863 is not set
4036 +# CONFIG_NLS_CODEPAGE_864 is not set
4037 +# CONFIG_NLS_CODEPAGE_865 is not set
4038 +# CONFIG_NLS_CODEPAGE_866 is not set
4039 +# CONFIG_NLS_CODEPAGE_869 is not set
4040 +# CONFIG_NLS_CODEPAGE_936 is not set
4041 +# CONFIG_NLS_CODEPAGE_950 is not set
4042 +# CONFIG_NLS_CODEPAGE_932 is not set
4043 +# CONFIG_NLS_CODEPAGE_949 is not set
4044 +# CONFIG_NLS_CODEPAGE_874 is not set
4045 +# CONFIG_NLS_ISO8859_8 is not set
4046 +# CONFIG_NLS_CODEPAGE_1250 is not set
4047 +# CONFIG_NLS_CODEPAGE_1251 is not set
4048 +# CONFIG_NLS_ASCII is not set
4049 +CONFIG_NLS_ISO8859_1=y
4050 +# CONFIG_NLS_ISO8859_2 is not set
4051 +# CONFIG_NLS_ISO8859_3 is not set
4052 +# CONFIG_NLS_ISO8859_4 is not set
4053 +# CONFIG_NLS_ISO8859_5 is not set
4054 +# CONFIG_NLS_ISO8859_6 is not set
4055 +# CONFIG_NLS_ISO8859_7 is not set
4056 +# CONFIG_NLS_ISO8859_9 is not set
4057 +# CONFIG_NLS_ISO8859_13 is not set
4058 +# CONFIG_NLS_ISO8859_14 is not set
4059 +# CONFIG_NLS_ISO8859_15 is not set
4060 +# CONFIG_NLS_KOI8_R is not set
4061 +# CONFIG_NLS_KOI8_U is not set
4062 +CONFIG_NLS_UTF8=y
4063 +# CONFIG_DLM is not set
4064 +
4065 +#
4066 +# Kernel hacking
4067 +#
4068 +# CONFIG_PRINTK_TIME is not set
4069 +CONFIG_ENABLE_WARN_DEPRECATED=y
4070 +# CONFIG_ENABLE_MUST_CHECK is not set
4071 +CONFIG_FRAME_WARN=1024
4072 +# CONFIG_MAGIC_SYSRQ is not set
4073 +# CONFIG_UNUSED_SYMBOLS is not set
4074 +# CONFIG_DEBUG_FS is not set
4075 +# CONFIG_HEADERS_CHECK is not set
4076 +# CONFIG_DEBUG_KERNEL is not set
4077 +# CONFIG_DEBUG_BUGVERBOSE is not set
4078 +# CONFIG_DEBUG_MEMORY_INIT is not set
4079 +# CONFIG_RCU_CPU_STALL_DETECTOR is not set
4080 +# CONFIG_SYSCTL_SYSCALL_CHECK is not set
4081 +
4082 +#
4083 +# Tracers
4084 +#
4085 +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
4086 +# CONFIG_SAMPLES is not set
4087 +# CONFIG_BOOTPARAM is not set
4088 +
4089 +#
4090 +# Security options
4091 +#
4092 +# CONFIG_KEYS is not set
4093 +# CONFIG_SECURITY is not set
4094 +# CONFIG_SECURITYFS is not set
4095 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
4096 +CONFIG_CRYPTO=y
4097 +
4098 +#
4099 +# Crypto core or helper
4100 +#
4101 +# CONFIG_CRYPTO_FIPS is not set
4102 +CONFIG_CRYPTO_ALGAPI=y
4103 +CONFIG_CRYPTO_ALGAPI2=y
4104 +CONFIG_CRYPTO_AEAD=y
4105 +CONFIG_CRYPTO_AEAD2=y
4106 +CONFIG_CRYPTO_BLKCIPHER=y
4107 +CONFIG_CRYPTO_BLKCIPHER2=y
4108 +CONFIG_CRYPTO_HASH=y
4109 +CONFIG_CRYPTO_HASH2=y
4110 +CONFIG_CRYPTO_RNG2=y
4111 +CONFIG_CRYPTO_MANAGER=y
4112 +CONFIG_CRYPTO_MANAGER2=y
4113 +# CONFIG_CRYPTO_GF128MUL is not set
4114 +# CONFIG_CRYPTO_NULL is not set
4115 +# CONFIG_CRYPTO_CRYPTD is not set
4116 +CONFIG_CRYPTO_AUTHENC=y
4117 +CONFIG_CRYPTO_TEST=m
4118 +
4119 +#
4120 +# Authenticated Encryption with Associated Data
4121 +#
4122 +# CONFIG_CRYPTO_CCM is not set
4123 +# CONFIG_CRYPTO_GCM is not set
4124 +# CONFIG_CRYPTO_SEQIV is not set
4125 +
4126 +#
4127 +# Block modes
4128 +#
4129 +CONFIG_CRYPTO_CBC=y
4130 +# CONFIG_CRYPTO_CTR is not set
4131 +# CONFIG_CRYPTO_CTS is not set
4132 +CONFIG_CRYPTO_ECB=y
4133 +# CONFIG_CRYPTO_LRW is not set
4134 +CONFIG_CRYPTO_PCBC=m
4135 +# CONFIG_CRYPTO_XTS is not set
4136 +
4137 +#
4138 +# Hash modes
4139 +#
4140 +CONFIG_CRYPTO_HMAC=y
4141 +# CONFIG_CRYPTO_XCBC is not set
4142 +
4143 +#
4144 +# Digest
4145 +#
4146 +CONFIG_CRYPTO_CRC32C=y
4147 +# CONFIG_CRYPTO_MD4 is not set
4148 +CONFIG_CRYPTO_MD5=y
4149 +# CONFIG_CRYPTO_MICHAEL_MIC is not set
4150 +# CONFIG_CRYPTO_RMD128 is not set
4151 +# CONFIG_CRYPTO_RMD160 is not set
4152 +# CONFIG_CRYPTO_RMD256 is not set
4153 +# CONFIG_CRYPTO_RMD320 is not set
4154 +CONFIG_CRYPTO_SHA1=y
4155 +# CONFIG_CRYPTO_SHA256 is not set
4156 +# CONFIG_CRYPTO_SHA512 is not set
4157 +# CONFIG_CRYPTO_TGR192 is not set
4158 +# CONFIG_CRYPTO_WP512 is not set
4159 +
4160 +#
4161 +# Ciphers
4162 +#
4163 +CONFIG_CRYPTO_AES=y
4164 +# CONFIG_CRYPTO_ANUBIS is not set
4165 +CONFIG_CRYPTO_ARC4=y
4166 +# CONFIG_CRYPTO_BLOWFISH is not set
4167 +# CONFIG_CRYPTO_CAMELLIA is not set
4168 +# CONFIG_CRYPTO_CAST5 is not set
4169 +# CONFIG_CRYPTO_CAST6 is not set
4170 +CONFIG_CRYPTO_DES=y
4171 +# CONFIG_CRYPTO_FCRYPT is not set
4172 +# CONFIG_CRYPTO_KHAZAD is not set
4173 +# CONFIG_CRYPTO_SALSA20 is not set
4174 +# CONFIG_CRYPTO_SEED is not set
4175 +# CONFIG_CRYPTO_SERPENT is not set
4176 +# CONFIG_CRYPTO_TEA is not set
4177 +# CONFIG_CRYPTO_TWOFISH is not set
4178 +
4179 +#
4180 +# Compression
4181 +#
4182 +# CONFIG_CRYPTO_DEFLATE is not set
4183 +# CONFIG_CRYPTO_LZO is not set
4184 +
4185 +#
4186 +# Random Number Generation
4187 +#
4188 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
4189 +
4190 +#
4191 +# OCF Configuration
4192 +#
4193 +
4194 +#
4195 +# Talitos Driver
4196 +#
4197 +CONFIG_CRYPTO_HW=y
4198 +CONFIG_CRYPTO_DEV_MCFCAU=y
4199 +CONFIG_CRYPTO_DEV_MCFCAU_DES=y
4200 +CONFIG_CRYPTO_DEV_MCFCAU_AES=y
4201 +CONFIG_CRYPTO_DEV_MCFCAU_MD5=y
4202 +CONFIG_CRYPTO_DEV_MCFCAU_SHA1=y
4203 +# CONFIG_CRYPTO_DEV_HIFN_795X is not set
4204 +
4205 +#
4206 +# Library routines
4207 +#
4208 +CONFIG_BITREVERSE=y
4209 +CONFIG_GENERIC_FIND_LAST_BIT=y
4210 +CONFIG_CRC_CCITT=y
4211 +CONFIG_CRC16=y
4212 +# CONFIG_CRC_T10DIF is not set
4213 +# CONFIG_CRC_ITU_T is not set
4214 +CONFIG_CRC32=y
4215 +# CONFIG_CRC7 is not set
4216 +CONFIG_LIBCRC32C=y
4217 +CONFIG_ZLIB_INFLATE=y
4218 +CONFIG_ZLIB_DEFLATE=y
4219 +CONFIG_GENERIC_ALLOCATOR=y
4220 +CONFIG_PLIST=y
4221 +CONFIG_HAS_IOMEM=y
4222 +CONFIG_HAS_IOPORT=y
4223 +CONFIG_HAS_DMA=y
4224 --- /dev/null
4225 +++ b/arch/m68k/include/asm/cf_5445x_cacheflush.h
4226 @@ -0,0 +1,534 @@
4227 +/*
4228 + * include/asm-m68k/cf_5445x_cacheflush.h - Coldfire 5445x Cache
4229 + *
4230 + * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
4231 + *
4232 + * Kurt Mahan kmahan@freescale.com
4233 + *
4234 + * Based on include/asm-m68k/cacheflush.h
4235 + *
4236 + * This program is free software; you can redistribute it and/or modify it
4237 + * under the terms of the GNU General Public License as published by the
4238 + * Free Software Foundation; either version 2 of the License, or (at your
4239 + * option) any later version.
4240 + */
4241 +#ifndef M68K_CF_5445x_CACHEFLUSH_H
4242 +#define M68K_CF_5445x_CACHEFLUSH_H
4243 +
4244 +#include <asm/cfcache.h>
4245 +
4246 +/*
4247 + * Coldfire Cache Model
4248 + *
4249 + * The Coldfire processors use a Harvard architecture cache configured
4250 + * as four-way set associative. The cache does not implement bus snooping
4251 + * so cache coherency with other masters must be maintained in software.
4252 + *
4253 + * The cache is managed via the CPUSHL instruction in conjunction with
4254 + * bits set in the CACR (cache control register). Currently the code
4255 + * uses the CPUSHL enhancement which adds the ability to
4256 + * invalidate/clear/push a cacheline by physical address. This feature
4257 + * is designated in the Hardware Configuration Register [D1-CPES].
4258 + *
4259 + * CACR Bits:
4260 + * DPI[28] cpushl invalidate disable for d-cache
4261 + * IDPI[12] cpushl invalidate disable for i-cache
4262 + * SPA[14] cpushl search by physical address
4263 + * IVO[20] cpushl invalidate only
4264 + *
4265 + * Random Terminology:
4266 + * * invalidate = reset the cache line's valid bit
4267 + * * push = generate a line-sized store of the data if its contents are
4268 + * marked as modifed (the modified flag is cleared after
4269 + * the store)
4270 + * * clear = push + invalidate
4271 + */
4272 +
4273 +/**
4274 + * flush_icache - Flush all of the instruction cache
4275 + */
4276 +static inline void flush_icache(void)
4277 +{
4278 + asm volatile("nop\n"
4279 + "moveq%.l #0,%%d0\n"
4280 + "moveq%.l #0,%%d1\n"
4281 + "move%.l %%d0,%%a0\n"
4282 + "1:\n"
4283 + "cpushl %%ic,(%%a0)\n"
4284 + "add%.l #0x0010,%%a0\n"
4285 + "addq%.l #1,%%d1\n"
4286 + "cmpi%.l %0,%%d1\n"
4287 + "bne 1b\n"
4288 + "moveq%.l #0,%%d1\n"
4289 + "addq%.l #1,%%d0\n"
4290 + "move%.l %%d0,%%a0\n"
4291 + "cmpi%.l #4,%%d0\n"
4292 + "bne 1b\n"
4293 + : : "i" (CACHE_SETS)
4294 + : "a0", "d0", "d1");
4295 +}
4296 +
4297 +/**
4298 + * flush_dcache - Flush all of the data cache
4299 + */
4300 +static inline void flush_dcache(void)
4301 +{
4302 + asm volatile("nop\n"
4303 + "moveq%.l #0,%%d0\n"
4304 + "moveq%.l #0,%%d1\n"
4305 + "move%.l %%d0,%%a0\n"
4306 + "1:\n"
4307 + "cpushl %%dc,(%%a0)\n"
4308 + "add%.l #0x0010,%%a0\n"
4309 + "addq%.l #1,%%d1\n"
4310 + "cmpi%.l %0,%%d1\n"
4311 + "bne 1b\n"
4312 + "moveq%.l #0,%%d1\n"
4313 + "addq%.l #1,%%d0\n"
4314 + "move%.l %%d0,%%a0\n"
4315 + "cmpi%.l #4,%%d0\n"
4316 + "bne 1b\n"
4317 + : : "i" (CACHE_SETS)
4318 + : "a0", "d0", "d1");
4319 +}
4320 +
4321 +/**
4322 + * flush_bcache - Flush all of both caches
4323 + */
4324 +static inline void flush_bcache(void)
4325 +{
4326 + asm volatile("nop\n"
4327 + "moveq%.l #0,%%d0\n"
4328 + "moveq%.l #0,%%d1\n"
4329 + "move%.l %%d0,%%a0\n"
4330 + "1:\n"
4331 + "cpushl %%bc,(%%a0)\n"
4332 + "add%.l #0x0010,%%a0\n"
4333 + "addq%.l #1,%%d1\n"
4334 + "cmpi%.l %0,%%d1\n"
4335 + "bne 1b\n"
4336 + "moveq%.l #0,%%d1\n"
4337 + "addq%.l #1,%%d0\n"
4338 + "move%.l %%d0,%%a0\n"
4339 + "cmpi%.l #4,%%d0\n"
4340 + "bne 1b\n"
4341 + : : "i" (CACHE_SETS)
4342 + : "a0", "d0", "d1");
4343 +}
4344 +
4345 +/**
4346 + * cf_cache_clear - invalidate cache
4347 + * @paddr: starting physical address
4348 + * @len: number of bytes
4349 + *
4350 + * Invalidate cache lines starting at paddr for len bytes.
4351 + * Those lines are not pushed.
4352 + */
4353 +static inline void cf_cache_clear(unsigned long paddr, int len)
4354 +{
4355 + /* number of lines */
4356 + len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
4357 + if (len == 0)
4358 + return;
4359 +
4360 + /* align on set boundary */
4361 + paddr &= 0xfffffff0;
4362 +
4363 + asm volatile("nop\n"
4364 + "move%.l %2,%%d0\n"
4365 + "or%.l %3,%%d0\n"
4366 + "movec %%d0,%%cacr\n"
4367 + "move%.l %0,%%a0\n"
4368 + "move%.l %1,%%d0\n"
4369 + "1:\n"
4370 + "cpushl %%bc,(%%a0)\n"
4371 + "lea 0x10(%%a0),%%a0\n"
4372 + "subq%.l #1,%%d0\n"
4373 + "bne%.b 1b\n"
4374 + "movec %2,%%cacr\n"
4375 + : : "a" (paddr), "r" (len),
4376 + "r" (shadow_cacr),
4377 + "i" (CF_CACR_SPA+CF_CACR_IVO)
4378 + : "a0", "d0");
4379 +}
4380 +
4381 +/**
4382 + * cf_cache_push - Push dirty cache out with no invalidate
4383 + * @paddr: starting physical address
4384 + * @len: number of bytes
4385 + *
4386 + * Push the any dirty lines starting at paddr for len bytes.
4387 + * Those lines are not invalidated.
4388 + */
4389 +static inline void cf_cache_push(unsigned long paddr, int len)
4390 +{
4391 + /* number of lines */
4392 + len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
4393 + if (len == 0)
4394 + return;
4395 +
4396 + /* align on set boundary */
4397 + paddr &= 0xfffffff0;
4398 +
4399 + asm volatile("nop\n"
4400 + "move%.l %2,%%d0\n"
4401 + "or%.l %3,%%d0\n"
4402 + "movec %%d0,%%cacr\n"
4403 + "move%.l %0,%%a0\n"
4404 + "move%.l %1,%%d0\n"
4405 + "1:\n"
4406 + "cpushl %%bc,(%%a0)\n"
4407 + "lea 0x10(%%a0),%%a0\n"
4408 + "subq%.l #1,%%d0\n"
4409 + "bne.b 1b\n"
4410 + "movec %2,%%cacr\n"
4411 + : : "a" (paddr), "r" (len),
4412 + "r" (shadow_cacr),
4413 + "i" (CF_CACR_SPA+CF_CACR_DPI+CF_CACR_IDPI)
4414 + : "a0", "d0");
4415 +}
4416 +
4417 +/**
4418 + * cf_cache_flush - Push dirty cache out and invalidate
4419 + * @paddr: starting physical address
4420 + * @len: number of bytes
4421 + *
4422 + * Push the any dirty lines starting at paddr for len bytes and
4423 + * invalidate those lines.
4424 + */
4425 +static inline void cf_cache_flush(unsigned long paddr, int len)
4426 +{
4427 + /* number of lines */
4428 + len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
4429 + if (len == 0)
4430 + return;
4431 +
4432 + /* align on set boundary */
4433 + paddr &= 0xfffffff0;
4434 +
4435 + asm volatile("nop\n"
4436 + "move%.l %2,%%d0\n"
4437 + "or%.l %3,%%d0\n"
4438 + "movec %%d0,%%cacr\n"
4439 + "move%.l %0,%%a0\n"
4440 + "move%.l %1,%%d0\n"
4441 + "1:\n"
4442 + "cpushl %%bc,(%%a0)\n"
4443 + "lea 0x10(%%a0),%%a0\n"
4444 + "subq%.l #1,%%d0\n"
4445 + "bne.b 1b\n"
4446 + "movec %2,%%cacr\n"
4447 + : : "a" (paddr), "r" (len),
4448 + "r" (shadow_cacr),
4449 + "i" (CF_CACR_SPA)
4450 + : "a0", "d0");
4451 +}
4452 +
4453 +/**
4454 + * cf_cache_flush_range - Push dirty data/inst cache in range out and invalidate
4455 + * @vstart - starting virtual address
4456 + * @vend: ending virtual address
4457 + *
4458 + * Push the any dirty data/instr lines starting at paddr for len bytes and
4459 + * invalidate those lines.
4460 + */
4461 +static inline void cf_cache_flush_range(unsigned long vstart,
4462 + unsigned long vend)
4463 +{
4464 + int len;
4465 +
4466 + /* align on set boundary */
4467 + vstart &= 0xfffffff0;
4468 + vend = PAGE_ALIGN((vend + (CACHE_LINE_SIZE-1))) & 0xfffffff0;
4469 + len = vend - vstart;
4470 + if (len == 0)
4471 + return;
4472 + vstart = __pa(vstart);
4473 + vend = vstart + len;
4474 +
4475 + asm volatile("nop\n"
4476 + "move%.l %2,%%d0\n"
4477 + "or%.l %3,%%d0\n"
4478 + "movec %%d0,%%cacr\n"
4479 + "move%.l %0,%%a0\n"
4480 + "move%.l %1,%%a1\n"
4481 + "1:\n"
4482 + "cpushl %%bc,(%%a0)\n"
4483 + "lea 0x10(%%a0),%%a0\n"
4484 + "cmpa%.l %%a0,%%a1\n"
4485 + "bne.b 1b\n"
4486 + "movec %2,%%cacr\n"
4487 + : /* no return */
4488 + : "a" (vstart), "a" (vend),
4489 + "r" (shadow_cacr),
4490 + "i" (CF_CACR_SPA)
4491 + : "a0", "a1", "d0");
4492 +}
4493 +
4494 +/**
4495 + * cf_dcache_flush_range - Push dirty data cache in range out and invalidate
4496 + * @vstart - starting virtual address
4497 + * @vend: ending virtual address
4498 + *
4499 + * Push/Clear the virtual range *vstart* -> *vend* using the enhanced
4500 + * cpushl instruction to search by physical address.
4501 + *
4502 + * Assumes CACR[IVO] is 0
4503 + * CACR[DDPI] is 0
4504 + *
4505 + * Sets CACR[SPA] to 1 for the duration of this routine
4506 + */
4507 +static inline void cf_dcache_flush_range(unsigned long vstart,
4508 + unsigned long vend)
4509 +{
4510 + /* align on set boundary */
4511 + vstart &= 0xfffffff0;
4512 + vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
4513 +
4514 + asm volatile("nop\n"
4515 + "move%.l %2,%%d0\n"
4516 + "or%.l %3,%%d0\n"
4517 + "movec %%d0,%%cacr\n"
4518 + "move%.l %0,%%a0\n"
4519 + "move%.l %1,%%a1\n"
4520 + "1:\n"
4521 + "cpushl %%dc,(%%a0)\n"
4522 + "lea 0x10(%%a0),%%a0\n"
4523 + "cmpa%.l %%a0,%%a1\n"
4524 + "bne.b 1b\n"
4525 + "movec %2,%%cacr\n"
4526 + : /* no return */
4527 + : "a" (__pa(vstart)), "a" (__pa(vend)),
4528 + "r" (shadow_cacr),
4529 + "i" (CF_CACR_SPA)
4530 + : "a0", "a1", "d0");
4531 +}
4532 +
4533 +/**
4534 + * cf_dcache_inv_range - Invalidate data cache in range
4535 + * @vstart - starting virtual address
4536 + * @vend: ending virtual address
4537 + *
4538 + * Invalidate the virtual range *vstart* -> *vend* using the enhanced
4539 + * cpushl instruction to search by physical address.
4540 + *
4541 + * Assumes CACR[DDPI] is 0
4542 + *
4543 + * Sets CACR[SPA] and CACR[IVO] to 1 for the duration of this routine
4544 + */
4545 +static inline void cf_dcache_inv_range(unsigned long vstart,
4546 + unsigned long vend)
4547 +{
4548 + /* align on set boundary */
4549 + vstart &= 0xfffffff0;
4550 + vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
4551 +
4552 + asm volatile("nop\n"
4553 + "move%.l %2,%%d0\n"
4554 + "or%.l %3,%%d0\n"
4555 + "movec %%d0,%%cacr\n"
4556 + "move%.l %0,%%a0\n"
4557 + "move%.l %1,%%a1\n"
4558 + "1:\n"
4559 + "cpushl %%dc,(%%a0)\n"
4560 + "lea 0x10(%%a0),%%a0\n"
4561 + "cmpa%.l %%a0,%%a1\n"
4562 + "bne.b 1b\n"
4563 + "movec %2,%%cacr\n"
4564 + : /* no return */
4565 + : "a" (__pa(vstart)), "a" (__pa(vend)),
4566 + "r" (shadow_cacr),
4567 + "i" (CF_CACR_SPA | CF_CACR_IVO)
4568 + : "a0", "a1", "d0");
4569 +}
4570 +
4571 +/**
4572 + * cf_dcache_push_range - Push data cache in range
4573 + * @vstart - starting virtual address
4574 + * @vend: ending virtual address
4575 + *
4576 + * Push the virtual range *vstart* -> *vend* using the enhanced
4577 + * cpushl instruction to search by physical address.
4578 + *
4579 + * Assumes CACR[IVO] is 0
4580 + *
4581 + * Sets CACR[SPA] and CACR[DDPI] to 1 for the duration of this routine
4582 + */
4583 +static inline void cf_dcache_push_range(unsigned long vstart,
4584 + unsigned long vend)
4585 +{
4586 + /* align on set boundary */
4587 + vstart &= 0xfffffff0;
4588 + vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
4589 +
4590 + asm volatile("nop\n"
4591 + "move%.l %2,%%d0\n"
4592 + "or%.l %3,%%d0\n"
4593 + "movec %%d0,%%cacr\n"
4594 + "move%.l %0,%%a0\n"
4595 + "move%.l %1,%%a1\n"
4596 + "1:\n"
4597 + "cpushl %%dc,(%%a0)\n"
4598 + "lea 0x10(%%a0),%%a0\n"
4599 + "cmpa%.l %%a0,%%a1\n"
4600 + "bne.b 1b\n"
4601 + "movec %2,%%cacr\n"
4602 + : /* no return */
4603 + : "a" (__pa(vstart)), "a" (__pa(vend)),
4604 + "r" (shadow_cacr),
4605 + "i" (CF_CACR_SPA | CF_CACR_DPI)
4606 + : "a0", "a1", "d0");
4607 +}
4608 +
4609 +/**
4610 + * cf_icache_flush_range - Push dirty inst cache in range out and invalidate
4611 + * @vstart - starting virtual address
4612 + * @vend: ending virtual address
4613 + *
4614 + * Push the any dirty instr lines starting at paddr for len bytes and
4615 + * invalidate those lines. This should just be an invalidate since you
4616 + * shouldn't be able to have dirty instruction cache.
4617 + */
4618 +static inline void cf_icache_flush_range(unsigned long vstart,
4619 + unsigned long vend)
4620 +{
4621 + /* align on set boundary */
4622 + vstart &= 0xfffffff0;
4623 + vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
4624 +
4625 + asm volatile("nop\n"
4626 + "move%.l %2,%%d0\n"
4627 + "or%.l %3,%%d0\n"
4628 + "movec %%d0,%%cacr\n"
4629 + "move%.l %0,%%a0\n"
4630 + "move%.l %1,%%a1\n"
4631 + "1:\n"
4632 + "cpushl %%ic,(%%a0)\n"
4633 + "lea 0x10(%%a0),%%a0\n"
4634 + "cmpa%.l %%a0,%%a1\n"
4635 + "bne.b 1b\n"
4636 + "movec %2,%%cacr\n"
4637 + : /* no return */
4638 + : "a" (__pa(vstart)), "a" (__pa(vend)),
4639 + "r" (shadow_cacr),
4640 + "i" (CF_CACR_SPA)
4641 + : "a0", "a1", "d0");
4642 +}
4643 +
4644 +/**
4645 + * flush_cache_mm - Flush an mm_struct
4646 + * @mm: mm_struct to flush
4647 + */
4648 +static inline void flush_cache_mm(struct mm_struct *mm)
4649 +{
4650 + if (mm == current->mm)
4651 + flush_bcache();
4652 +}
4653 +
4654 +#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
4655 +
4656 +/**
4657 + * flush_cache_range - Flush a cache range
4658 + * @vma: vma struct
4659 + * @start: Starting address
4660 + * @end: Ending address
4661 + *
4662 + * flush_cache_range must be a macro to avoid a dependency on
4663 + * linux/mm.h which includes this file.
4664 + */
4665 +static inline void flush_cache_range(struct vm_area_struct *vma,
4666 + unsigned long start, unsigned long end)
4667 +{
4668 + if (vma->vm_mm == current->mm)
4669 + cf_cache_flush_range(start, end);
4670 +}
4671 +
4672 +/**
4673 + * flush_cache_page - Flush a page of the cache
4674 + * @vma: vma struct
4675 + * @vmaddr:
4676 + * @pfn: page numer
4677 + *
4678 + * flush_cache_page must be a macro to avoid a dependency on
4679 + * linux/mm.h which includes this file.
4680 + */
4681 +static inline void flush_cache_page(struct vm_area_struct *vma,
4682 + unsigned long vmaddr, unsigned long pfn)
4683 +{
4684 + if (vma->vm_mm == current->mm)
4685 + cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE);
4686 +}
4687 +
4688 +/**
4689 + * __flush_page_to_ram - Push a page out of the cache
4690 + * @vaddr: Virtual address at start of page
4691 + *
4692 + * Push the page at kernel virtual address *vaddr* and clear
4693 + * the icache.
4694 + */
4695 +static inline void __flush_page_to_ram(void *vaddr)
4696 +{
4697 + asm volatile("nop\n"
4698 + "move%.l %2,%%d0\n"
4699 + "or%.l %3,%%d0\n"
4700 + "movec %%d0,%%cacr\n"
4701 + "move%.l %0,%%d0\n"
4702 + "and%.l #0xfffffff0,%%d0\n"
4703 + "move%.l %%d0,%%a0\n"
4704 + "move%.l %1,%%d0\n"
4705 + "1:\n"
4706 + "cpushl %%bc,(%%a0)\n"
4707 + "lea 0x10(%%a0),%%a0\n"
4708 + "subq%.l #1,%%d0\n"
4709 + "bne.b 1b\n"
4710 + "movec %2,%%cacr\n"
4711 + : : "a" (__pa(vaddr)), "i" (PAGE_SIZE / CACHE_LINE_SIZE),
4712 + "r" (shadow_cacr), "i" (CF_CACR_SPA)
4713 + : "a0", "d0");
4714 +}
4715 +
4716 +/*
4717 + * Various defines for the kernel.
4718 + */
4719 +
4720 +extern void cache_clear(unsigned long paddr, int len);
4721 +extern void cache_push(unsigned long paddr, int len);
4722 +extern void flush_icache_range(unsigned long address, unsigned long endaddr);
4723 +
4724 +#define flush_cache_all() flush_bcache()
4725 +#define flush_cache_vmap(start, end) flush_bcache()
4726 +#define flush_cache_vunmap(start, end) flush_bcache()
4727 +
4728 +#define flush_dcache_range(vstart, vend) \
4729 + cf_dcache_flush_range(vstart, vend)
4730 +#define flush_dcache_page(page) \
4731 + __flush_page_to_ram(page_address(page))
4732 +#define flush_dcache_mmap_lock(mapping) do { } while (0)
4733 +#define flush_dcache_mmap_unlock(mapping) do { } while (0)
4734 +
4735 +#define flush_icache_page(vma, page) \
4736 + __flush_page_to_ram(page_address(page))
4737 +
4738 +/**
4739 + * copy_to_user_page - Copy memory to user page
4740 + */
4741 +static inline void copy_to_user_page(struct vm_area_struct *vma,
4742 + struct page *page, unsigned long vaddr,
4743 + void *dst, void *src, int len)
4744 +{
4745 + memcpy(dst, src, len);
4746 + cf_cache_flush(page_to_phys(page), PAGE_SIZE);
4747 +}
4748 +
4749 +/**
4750 + * copy_from_user_page - Copy memory from user page
4751 + */
4752 +static inline void copy_from_user_page(struct vm_area_struct *vma,
4753 + struct page *page, unsigned long vaddr,
4754 + void *dst, void *src, int len)
4755 +{
4756 + cf_cache_flush(page_to_phys(page), PAGE_SIZE);
4757 + memcpy(dst, src, len);
4758 +}
4759 +
4760 +#endif /* M68K_CF_5445x_CACHEFLUSH_H */
4761 --- /dev/null
4762 +++ b/arch/m68k/include/asm/mcf5445x_ccm.h
4763 @@ -0,0 +1,206 @@
4764 +/*
4765 + * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
4766 + *
4767 + * Matt Waddel Matt.Waddel@freescale.com
4768 + *
4769 + * This program is free software; you can redistribute it and/or modify it
4770 + * under the terms of the GNU General Public License as published by the
4771 + * Free Software Foundation; either version 2 of the License, or (at your
4772 + * option) any later version.
4773 + */
4774 +
4775 +#ifndef __MCF5445X_CCM_H__
4776 +#define __MCF5445X_CCM_H__
4777 +
4778 +/*********************************************************************
4779 +*
4780 +* Chip Configuration Module (CCM)
4781 +*
4782 +*********************************************************************/
4783 +
4784 +/* Register read/write macros */
4785 +/* Chip Configuration Register (Read-only) (256 or 360 TEPBGA) */
4786 +#define MCF_CCM_CCR MCF_REG16(0xFC0A0004)
4787 +/* Reset Configuration (Read-only) (256 or 360 TEPBGA) */
4788 +#define MCF_CCM_RCON MCF_REG16(0xFC0A0008)
4789 +/* Chip Identification Register (Read-only) */
4790 +#define MCF_CCM_CIR MCF_REG16(0xFC0A000A)
4791 +/* Miscellaneous Control Register */
4792 +#define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010)
4793 +#define MCF_CCM_CDR MCF_REG16(0xFC0A0012) /* Clock Divider Register */
4794 +/* USB On-the-Go Controller Status Register */
4795 +#define MCF_CCM_UOCSR MCF_REG16(0xFC0A0014)
4796 +/* Serial Boot Facility Status Register (Read Only) */
4797 +#define MCF_CCM_SBFSR MCF_REG16(0xFC0A0018)
4798 +/* Serial Boot Facility Control Register */
4799 +#define MCF_CCM_SBFCR MCF_REG16(0xFC0A0020)
4800 +
4801 +/* Bit definitions and macros for CCR_360 */
4802 +/* 2-Bit PLL clock mode */
4803 +#define MCF_CCM_CCR_360_PLLMULT2(x) (((x) & 0x0003))
4804 +/* PCI pad slew rate mode */
4805 +#define MCF_CCM_CCR_360_PCISLEW (0x0004)
4806 +#define MCF_CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */
4807 +#define MCF_CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */
4808 +/* Flexbus/PCI port size configuration */
4809 +#define MCF_CCM_CCR_360_FBCONFIG(x) (((x) & 0x0007) << 5)
4810 +/* 3-Bit PLL Clock Mode */
4811 +#define MCF_CCM_CCR_360_PLLMULT3(x) (((x) & 0x0007))
4812 +#define MCF_CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */
4813 +#define MCF_CCM_CCR_360_FBCONFIG_MASK (0x00E0)
4814 +#define MCF_CCM_CCR_360_PLLMULT2_MASK (0x0003)
4815 +#define MCF_CCM_CCR_360_PLLMULT3_MASK (0x0007)
4816 +#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000)
4817 +#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020)
4818 +#define MCF_CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040)
4819 +#define MCF_CCM_CCR_360_FBCONFIG_M_P_16 (0x0060)
4820 +#define MCF_CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080)
4821 +#define MCF_CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0)
4822 +#define MCF_CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0)
4823 +#define MCF_CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0)
4824 +#define MCF_CCM_CCR_360_PLLMULT2_12X (0x0000)
4825 +#define MCF_CCM_CCR_360_PLLMULT2_6X (0x0001)
4826 +#define MCF_CCM_CCR_360_PLLMULT2_16X (0x0002)
4827 +#define MCF_CCM_CCR_360_PLLMULT2_8X (0x0003)
4828 +#define MCF_CCM_CCR_360_PLLMULT3_20X (0x0000)
4829 +#define MCF_CCM_CCR_360_PLLMULT3_10X (0x0001)
4830 +#define MCF_CCM_CCR_360_PLLMULT3_24X (0x0002)
4831 +#define MCF_CCM_CCR_360_PLLMULT3_18X (0x0003)
4832 +#define MCF_CCM_CCR_360_PLLMULT3_12X (0x0004)
4833 +#define MCF_CCM_CCR_360_PLLMULT3_6X (0x0005)
4834 +#define MCF_CCM_CCR_360_PLLMULT3_16X (0x0006)
4835 +#define MCF_CCM_CCR_360_PLLMULT3_8X (0x0007)
4836 +
4837 +/* Bit definitions and macros for CCR_256 */
4838 +/* 3-Bit PLL clock mode */
4839 +#define MCF_CCM_CCR_256_PLLMULT3(x) (((x) & 0x0007))
4840 +/* Oscillator clock mode */
4841 +#define MCF_CCM_CCR_256_OSCMODE (0x0008)
4842 +#define MCF_CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */
4843 +/* Flexbus/PCI port size configuration */
4844 +#define MCF_CCM_CCR_256_FBCONFIG(x) (((x) & 0x0007) << 5)
4845 +#define MCF_CCM_CCR_256_FBCONFIG_MASK (0x00E0)
4846 +#define MCF_CCM_CCR_256_FBCONFIG_NM_32 (0x0000)
4847 +#define MCF_CCM_CCR_256_FBCONFIG_NM_8 (0x0020)
4848 +#define MCF_CCM_CCR_256_FBCONFIG_NM_16 (0x0040)
4849 +#define MCF_CCM_CCR_256_FBCONFIG_M_32 (0x0080)
4850 +#define MCF_CCM_CCR_256_FBCONFIG_M_8 (0x00A0)
4851 +#define MCF_CCM_CCR_256_FBCONFIG_M_16 (0x00C0)
4852 +#define MCF_CCM_CCR_256_PLLMULT3_MASK (0x0007)
4853 +#define MCF_CCM_CCR_256_PLLMULT3_20X (0x0000)
4854 +#define MCF_CCM_CCR_256_PLLMULT3_10X (0x0001)
4855 +#define MCF_CCM_CCR_256_PLLMULT3_24X (0x0002)
4856 +#define MCF_CCM_CCR_256_PLLMULT3_18X (0x0003)
4857 +#define MCF_CCM_CCR_256_PLLMULT3_12X (0x0004)
4858 +#define MCF_CCM_CCR_256_PLLMULT3_6X (0x0005)
4859 +#define MCF_CCM_CCR_256_PLLMULT3_16X (0x0006)
4860 +#define MCF_CCM_CCR_256_PLLMULT3_8X (0x0007)
4861 +
4862 +/* Bit definitions and macros for RCON_360 */
4863 +#define MCF_CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */
4864 +#define MCF_CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
4865 +#define MCF_CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */
4866 +#define MCF_CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */
4867 +/* Flexbus/PCI port size configuration */
4868 +#define MCF_CCM_RCON_360_FBCONFIG(x) (((x) & 0x0007) << 5)
4869 +
4870 +/* Bit definitions and macros for RCON_256 */
4871 +#define MCF_CCM_RCON_256_PLLMULT(x) (((x) & 0x0007)) /* PLL clock mode */
4872 +#define MCF_CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */
4873 +#define MCF_CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */
4874 +/* Flexbus/PCI port size configuration */
4875 +#define MCF_CCM_RCON_256_FBCONFIG(x) (((x) & 0x0007) << 5)
4876 +
4877 +/* Bit definitions and macros for CIR */
4878 +/* Part revision number */
4879 +#define MCF_CCM_CIR_PRN(x) (((x) & 0x003F))
4880 +/* Part identification number */
4881 +#define MCF_CCM_CIR_PIN(x) (((x) & 0x03FF) << 6)
4882 +#define MCF_CCM_CIR_PIN_MASK (0xFFC0)
4883 +#define MCF_CCM_CIR_PRN_MASK (0x003F)
4884 +#define MCF_CCM_CIR_PIN_MCF54450 (0x4F << 6)
4885 +#define MCF_CCM_CIR_PIN_MCF54451 (0x4D << 6)
4886 +#define MCF_CCM_CIR_PIN_MCF54452 (0x4B << 6)
4887 +#define MCF_CCM_CIR_PIN_MCF54453 (0x49 << 6)
4888 +#define MCF_CCM_CIR_PIN_MCF54454 (0x4A << 6)
4889 +#define MCF_CCM_CIR_PIN_MCF54455 (0x48 << 6)
4890 +
4891 +/* Bit definitions and macros for MISCCR */
4892 +/* USB clock source */
4893 +#define MCF_CCM_MISCCR_USBSRC (0x0001)
4894 +/* USB VBUS over-current sense polarity */
4895 +#define MCF_CCM_MISCCR_USBOC (0x0002)
4896 +/* USB transceiver pull-up enable */
4897 +#define MCF_CCM_MISCCR_USBPUE (0x0004)
4898 +/* SSI clock source */
4899 +#define MCF_CCM_MISCCR_SSI_SRC (0x0010)
4900 +/* Timer DMA mux selection */
4901 +#define MCF_CCM_MISCCR_TIM_DMA (0x0020)
4902 +/* SSI RXD/TXD pull select */
4903 +#define MCF_CCM_MISCCR_SSI_PUS (0x0040)
4904 +/* SSI RXD/TXD pull enable */
4905 +#define MCF_CCM_MISCCR_SSI_PUE (0x0080)
4906 +/* Bus monitor timing field */
4907 +#define MCF_CCM_MISCCR_BMT(x) (((x) & 0x0007) << 8)
4908 +/* Bus monitor external enable bit */
4909 +#define MCF_CCM_MISCCR_BME (0x0800)
4910 +/* Limp mode enable */
4911 +#define MCF_CCM_MISCCR_LIMP (0x1000)
4912 +#define MCF_CCM_MISCCR_BMT_65536 (0 << 8)
4913 +#define MCF_CCM_MISCCR_BMT_32768 (1 << 8)
4914 +#define MCF_CCM_MISCCR_BMT_16384 (2 << 8)
4915 +#define MCF_CCM_MISCCR_BMT_8192 (3 << 8)
4916 +#define MCF_CCM_MISCCR_BMT_4096 (4 << 8)
4917 +#define MCF_CCM_MISCCR_BMT_2048 (5 << 8)
4918 +#define MCF_CCM_MISCCR_BMT_1024 (6 << 8)
4919 +#define MCF_CCM_MISCCR_BMT_512 (7 << 8)
4920 +#define MCF_CCM_MISCCR_SSIPUE_UP (1 << 7)
4921 +#define MCF_CCM_MISCCR_SSIPUE_DOWN (0 << 7)
4922 +#define MCF_CCM_MISCCR_SSIPUS_UP (1 << 6)
4923 +#define MCF_CCM_MISCCR_SSIPUS_DOWN (0 << 6)
4924 +#define MCF_CCM_MISCCR_TIMDMA_TIM (1 << 5)
4925 +#define MCF_CCM_MISCCR_TIMDMA_SSI (0 << 5)
4926 +#define MCF_CCM_MISCCR_SSISRC_CLKIN (0 << 4)
4927 +#define MCF_CCM_MISCCR_SSISRC_PLL (1 << 4)
4928 +#define MCF_CCM_MISCCR_USBOC_ACTHI (0 << 1)
4929 +#define MCF_CCM_MISCCR_USBOC_ACTLO (1 << 1)
4930 +#define MCF_CCM_MISCCR_USBSRC_CLKIN (0)
4931 +#define MCF_CCM_MISCCR_USBSRC_PLL (1)
4932 +
4933 +/* Bit definitions and macros for CDR */
4934 +/* SSI oversampling clock divider */
4935 +#define MCF_CCM_CDR_SSIDIV(x) (((x) & 0x00FF))
4936 +/* Low power clock divider */
4937 +#define MCF_CCM_CDR_LPDIV(x) (((x) & 0x000F) << 8)
4938 +
4939 +/* Bit definitions and macros for UOCSR */
4940 +/* On-chip transceiver pull-down enable */
4941 +#define MCF_CCM_UOCSR_XPDE (0x0001)
4942 +/* USB OTG misc interrupt enable */
4943 +#define MCF_CCM_UOCSR_UOMIE (0x0002)
4944 +/* USB OTG controller wake-up event */
4945 +#define MCF_CCM_UOCSR_WKUP (0x0004)
4946 +/* VBUS power fault */
4947 +#define MCF_CCM_UOCSR_PWRFLT (0x0008)
4948 +/* Session end */
4949 +#define MCF_CCM_UOCSR_SEND (0x0010)
4950 +/* VBUS valid indicator */
4951 +#define MCF_CCM_UOCSR_VVLD (0x0020)
4952 +/* B-peripheral valid indicator */
4953 +#define MCF_CCM_UOCSR_BVLD (0x0040)
4954 +/* A-peripheral valid indicator */
4955 +#define MCF_CCM_UOCSR_AVLD (0x0080)
4956 +/* D+ pull-up for FS enabled (read-only) */
4957 +#define MCF_CCM_UOCSR_DPPU (0x0100)
4958 +/* VBUS discharge resistor enabled (read-only) */
4959 +#define MCF_CCM_UOCSR_DCR_VBUS (0x0200)
4960 +/* VBUS charge resistor enabled (read-only) */
4961 +#define MCF_CCM_UOCSR_CRG_VBUS (0x0400)
4962 +/* D- 15Kohm pull-down (read-only) */
4963 +#define MCF_CCM_UOCSR_DMPD (0x1000)
4964 +/* D+ 15Kohm pull-down (read-only) */
4965 +#define MCF_CCM_UOCSR_DPPD (0x2000)
4966 +
4967 +/********************************************************************/
4968 +
4969 +#endif /* __MCF5445X_CCM_H__ */
4970 --- /dev/null
4971 +++ b/arch/m68k/include/asm/mcf5445x_dspi.h
4972 @@ -0,0 +1,665 @@
4973 +/*
4974 + * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
4975 + *
4976 + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
4977 + *
4978 + * This program is free software; you can redistribute it and/or modify it
4979 + * under the terms of the GNU General Public License as published by the
4980 + * Free Software Foundation; either version 2 of the License, or (at your
4981 + * option) any later version.
4982 + */
4983 +
4984 +#ifndef __MCF5445X_DSPI_H__
4985 +#define __MCF5445X_DSPI_H__
4986 +
4987 +/*********************************************************************
4988 +*
4989 +* DMA Serial Peripheral Interface (DSPI)
4990 +*
4991 +*********************************************************************/
4992 +
4993 +/* Register read/write macros */
4994 +/* DSPI Module Configuration Register */
4995 +#define MCF_DSPI_DMCR MCF_REG32(0xFC05C000)
4996 +/* DSPI Transfer Count Register */
4997 +#define MCF_DSPI_DTCR MCF_REG32(0xFC05C008)
4998 +/* DSPI Clock and Transfer Attributes Register */
4999 +#define MCF_DSPI_DCTAR0 MCF_REG32(0xFC05C00C)
5000 +/* DSPI Clock and Transfer Attributes Register */
5001 +#define MCF_DSPI_DCTAR1 MCF_REG32(0xFC05C010)
5002 +/* DSPI Clock and Transfer Attributes Register */
5003 +#define MCF_DSPI_DCTAR2 MCF_REG32(0xFC05C014)
5004 +/* DSPI Clock and Transfer Attributes Register */
5005 +#define MCF_DSPI_DCTAR3 MCF_REG32(0xFC05C018)
5006 +/* DSPI Clock and Transfer Attributes Register */
5007 +#define MCF_DSPI_DCTAR4 MCF_REG32(0xFC05C01C)
5008 +/* DSPI Clock and Transfer Attributes Register */
5009 +#define MCF_DSPI_DCTAR5 MCF_REG32(0xFC05C020)
5010 +/* DSPI Clock and Transfer Attributes Register */
5011 +#define MCF_DSPI_DCTAR6 MCF_REG32(0xFC05C024)
5012 +/* DSPI Clock and Transfer Attributes Register */
5013 +#define MCF_DSPI_DCTAR7 MCF_REG32(0xFC05C028
5014 +/* DSPI Status Register */
5015 +#define MCF_DSPI_DSR MCF_REG32(0xFC05C02C)
5016 +/* DSPI DMA/Interrupt Request Select and Enable Register */
5017 +#define MCF_DSPI_DRSER MCF_REG32(0xFC05C030)
5018 +/* DSPI Transmit FIFO Register */
5019 +#define MCF_DSPI_DTFR MCF_REG32(0xFC05C034)
5020 +/* DSPI Receive FIFO Register */
5021 +#define MCF_DSPI_DRFR MCF_REG32(0xFC05C038)
5022 +/* DSPI Transmit FIFO Debugging Registers */
5023 +#define MCF_DSPI_DTFDR0 MCF_REG32(0xFC05C03C)
5024 +/* DSPI Transmit FIFO Debugging Registers */
5025 +#define MCF_DSPI_DTFDR1 MCF_REG32(0xFC05C040)
5026 +/* DSPI Transmit FIFO Debugging Registers */
5027 +#define MCF_DSPI_DTFDR2 MCF_REG32(0xFC05C044)
5028 +/* DSPI Transmit FIFO Debugging Registers */
5029 +#define MCF_DSPI_DTFDR3 MCF_REG32(0xFC05C048)
5030 +/* DSPI Receive FIFO Debugging Registers */
5031 +#define MCF_DSPI_DRFDR0 MCF_REG32(0xFC05C07C)
5032 +/* DSPI Receive FIFO Debugging Registers */
5033 +#define MCF_DSPI_DRFDR1 MCF_REG32(0xFC05C080)
5034 +/* DSPI Receive FIFO Debugging Registers */
5035 +#define MCF_DSPI_DRFDR2 MCF_REG32(0xFC05C084)
5036 +/* DSPI Receive FIFO Debugging Registers */
5037 +#define MCF_DSPI_DRFDR3 MCF_REG32(0xFC05C088)
5038 +
5039 +
5040 +/* Parameterized register read/write macros for multiple registers */
5041 +/* DSPI Clock and Transfer Attributes Register */
5042 +#define MCF_DSPI_DCTAR(x) MCF_REG32(0xFC05C00C+((x)*0x004))
5043 +/* DSPI Transmit FIFO Debugging Registers */
5044 +#define MCF_DSPI_DTFDR(x) MCF_REG32(0xFC05C03C+((x)*0x004))
5045 +/* DSPI Receive FIFO Debugging Registers */
5046 +#define MCF_DSPI_DRFDR(x) MCF_REG32(0xFC05C07C+((x)*0x004))
5047 +
5048 +/* Bit definitions and macros for DMCR */
5049 +/* Halt -- stops and starts DSPI transfers */
5050 +#define MCF_DSPI_DMCR_HALT (0x00000001)
5051 +/* Sample point selection */
5052 +#define MCF_DSPI_DMCR_SMPLPT(x) (((x)&0x00000003)<<8)
5053 +/* Clear receive FIFO */
5054 +#define MCF_DSPI_DMCR_CLRRXF (0x00000400)
5055 +/* Clear transmit FIFO */
5056 +#define MCF_DSPI_DMCR_CLRTXF (0x00000800)
5057 +/* Disable receive FIFO */
5058 +#define MCF_DSPI_DMCR_DISRXF (0x00001000)
5059 +/* Disable transmit FIFO */
5060 +#define MCF_DSPI_DMCR_DISTXF (0x00002000)
5061 +/* Module Disable */
5062 +#define MCF_DSPI_DMCR_MDIS (0x00004000)
5063 +/* Peripheral chip-select 0 inactive state */
5064 +#define MCF_DSPI_DMCR_PCSIS0 (0x00010000)
5065 +/* Peripheral chip-select 1 inactive state */
5066 +#define MCF_DSPI_DMCR_PCSIS1 (0x00020000)
5067 +/* Peripheral chip-select 2 inactive state */
5068 +#define MCF_DSPI_DMCR_PCSIS2 (0x00040000)
5069 +/* Peripheral chip-select 3 inactive state */
5070 +#define MCF_DSPI_DMCR_PCSIS3 (0x00080000)
5071 +/* Peripheral chip-select 4 inactive state */
5072 +#define MCF_DSPI_DMCR_PCSIS4 (0x00100000)
5073 +/* Peripheral chip-select 5 inactive state */
5074 +#define MCF_DSPI_DMCR_PCSIS5 (0x00200000)
5075 +/* Peripheral chip-select 6 inactive state */
5076 +#define MCF_DSPI_DMCR_PCSIS6 (0x00400000)
5077 +/* Peripheral chip-select 7 inactive state */
5078 +#define MCF_DSPI_DMCR_PCSIS7 (0x00800000)
5079 +/* Receive FIFO overflow overwrite enable */
5080 +#define MCF_DSPI_DMCR_ROOE (0x01000000)
5081 +/* Peripheral chip select strobe enable */
5082 +#define MCF_DSPI_DMCR_PCSSE (0x02000000)
5083 +/* Modified timing format enable */
5084 +#define MCF_DSPI_DMCR_MTFE (0x04000000)
5085 +/* Freeze */
5086 +#define MCF_DSPI_DMCR_FRZ (0x08000000)
5087 +/* DSPI configuration */
5088 +#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28)
5089 +/* Continuous SCK enable */
5090 +#define MCF_DSPI_DMCR_CONT_SCKE (0x40000000)
5091 +/* Master/Slave mode select */
5092 +#define MCF_DSPI_DMCR_MSTR (0x80000000)
5093 +#define MCF_DSPI_DMCR_DCONF_SPI (0x00000000)
5094 +#define MCF_DSPI_DMCR_PCSIS7_LOW (0x00000000)
5095 +#define MCF_DSPI_DMCR_PCSIS7_HIGH (0x00800000)
5096 +#define MCF_DSPI_DMCR_PCSIS6_LOW (0x00000000)
5097 +#define MCF_DSPI_DMCR_PCSIS6_HIGH (0x00400000)
5098 +#define MCF_DSPI_DMCR_PCSIS5_LOW (0x00000000)
5099 +#define MCF_DSPI_DMCR_PCSIS5_HIGH (0x00200000)
5100 +#define MCF_DSPI_DMCR_PCSIS4_LOW (0x00000000)
5101 +#define MCF_DSPI_DMCR_PCSIS4_HIGH (0x00100000)
5102 +#define MCF_DSPI_DMCR_PCSIS3_LOW (0x00000000)
5103 +#define MCF_DSPI_DMCR_PCSIS3_HIGH (0x00080000)
5104 +#define MCF_DSPI_DMCR_PCSIS2_LOW (0x00000000)
5105 +#define MCF_DSPI_DMCR_PCSIS2_HIGH (0x00040000)
5106 +#define MCF_DSPI_DMCR_PCSIS1_LOW (0x00000000)
5107 +#define MCF_DSPI_DMCR_PCSIS1_HIGH (0x00020000)
5108 +#define MCF_DSPI_DMCR_PCSIS0_LOW (0x00000000)
5109 +#define MCF_DSPI_DMCR_PCSIS0_HIGH (0x00010000)
5110 +
5111 +/* Bit definitions and macros for DTCR */
5112 +/* SPI transfer count */
5113 +#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
5114 +
5115 +/* Bit definitions and macros for DCTAR group */
5116 +/* Baud rate scaler */
5117 +#define MCF_DSPI_DCTAR_BR(x) (((x)&0x0000000F))
5118 +/* Delay after transfer scaler */
5119 +#define MCF_DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4)
5120 +/* After SCK delay scaler */
5121 +#define MCF_DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8)
5122 +/* PCS to SCK delay scaler */
5123 +#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12)
5124 +/* Baud rate prescaler */
5125 +#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16)
5126 +/* Delay after transfer prescaler */
5127 +#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18)
5128 +/* After SCK delay prescaler */
5129 +#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20)
5130 +/* PCS to SCK delay prescaler */
5131 +#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22)
5132 +/* LSB first enable */
5133 +#define MCF_DSPI_DCTAR_LSBFE (0x01000000)
5134 +/* Clock phase */
5135 +#define MCF_DSPI_DCTAR_CPHA (0x02000000)
5136 +/* Clock polarity */
5137 +#define MCF_DSPI_DCTAR_CPOL (0x04000000)
5138 +/* Frame size */
5139 +#define MCF_DSPI_DCTAR_FMSZ(x) (((x)&0x0000000F)<<27)
5140 +/* Double baud rate */
5141 +#define MCF_DSPI_DCTAR_DBR (0x80000000)
5142 +#define MCF_DSPI_DCTAR_CPOL_LOW (0x00000000)
5143 +#define MCF_DSPI_DCTAR_CPOL_HIGH (0x04000000)
5144 +#define MCF_DSPI_DCTAR_CPHA_LATCH_RISING (0x00000000)
5145 +#define MCF_DSPI_DCTAR_CPHA_LATCH_FALLING (0x02000000)
5146 +#define MCF_DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
5147 +#define MCF_DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
5148 +#define MCF_DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
5149 +#define MCF_DSPI_DCTAR_PCSSCK_7CLK (0x00C00000)
5150 +#define MCF_DSPI_DCTAR_PASC_1CLK (0x00000000)
5151 +#define MCF_DSPI_DCTAR_PASC_3CLK (0x00100000)
5152 +#define MCF_DSPI_DCTAR_PASC_5CLK (0x00200000)
5153 +#define MCF_DSPI_DCTAR_PASC_7CLK (0x00300000)
5154 +#define MCF_DSPI_DCTAR_PDT_1CLK (0x00000000)
5155 +#define MCF_DSPI_DCTAR_PDT_3CLK (0x00040000)
5156 +#define MCF_DSPI_DCTAR_PDT_5CLK (0x00080000)
5157 +#define MCF_DSPI_DCTAR_PDT_7CLK (0x000C0000)
5158 +#define MCF_DSPI_DCTAR_PBR_2CLK (0x00000000)
5159 +#define MCF_DSPI_DCTAR_PBR_3CLK (0x00010000)
5160 +#define MCF_DSPI_DCTAR_PBR_5CLK (0x00020000)
5161 +#define MCF_DSPI_DCTAR_PBR_7CLK (0x00030000)
5162 +
5163 +/* Bit definitions and macros for DCTAR0 */
5164 +/* Baud rate scaler */
5165 +#define MCF_DSPI_DCTAR0_BR(x) (((x)&0x0000000F))
5166 +/* Delay after transfer scaler */
5167 +#define MCF_DSPI_DCTAR0_DT(x) (((x)&0x0000000F)<<4)
5168 +/* After SCK delay scaler */
5169 +#define MCF_DSPI_DCTAR0_ASC(x) (((x)&0x0000000F)<<8)
5170 +/* PCS to SCK delay scaler */
5171 +#define MCF_DSPI_DCTAR0_CSSCK(x) (((x)&0x0000000F)<<12)
5172 +/* Baud rate prescaler */
5173 +#define MCF_DSPI_DCTAR0_PBR(x) (((x)&0x00000003)<<16)
5174 +/* Delay after transfer prescaler */
5175 +#define MCF_DSPI_DCTAR0_PDT(x) (((x)&0x00000003)<<18)
5176 +/* After SCK delay prescaler */
5177 +#define MCF_DSPI_DCTAR0_PASC(x) (((x)&0x00000003)<<20)
5178 +/* PCS to SCK delay prescaler */
5179 +#define MCF_DSPI_DCTAR0_PCSSCK(x) (((x)&0x00000003)<<22)
5180 +/* LSB first enable */
5181 +#define MCF_DSPI_DCTAR0_LSBFE (0x01000000)
5182 +/* Clock phase */
5183 +#define MCF_DSPI_DCTAR0_CPHA (0x02000000)
5184 +/* Clock polarity */
5185 +#define MCF_DSPI_DCTAR0_CPOL (0x04000000)
5186 +/* Frame size */
5187 +#define MCF_DSPI_DCTAR0_FMSZ(x) (((x)&0x0000000F)<<27)
5188 +/* Double baud rate */
5189 +#define MCF_DSPI_DCTAR0_DBR (0x80000000)
5190 +#define MCF_DSPI_DCTAR0_CPOL_LOW (0x00000000)
5191 +#define MCF_DSPI_DCTAR0_CPOL_HIGH (0x04000000)
5192 +#define MCF_DSPI_DCTAR0_CPHA_LATCH_RISING (0x00000000)
5193 +#define MCF_DSPI_DCTAR0_CPHA_LATCH_FALLING (0x02000000)
5194 +#define MCF_DSPI_DCTAR0_PCSSCK_1CLK (0x00000000)
5195 +#define MCF_DSPI_DCTAR0_PCSSCK_3CLK (0x00400000)
5196 +#define MCF_DSPI_DCTAR0_PCSSCK_5CLK (0x00800000)
5197 +#define MCF_DSPI_DCTAR0_PCSSCK_7CLK (0x00C00000)
5198 +#define MCF_DSPI_DCTAR0_PASC_1CLK (0x00000000)
5199 +#define MCF_DSPI_DCTAR0_PASC_3CLK (0x00100000)
5200 +#define MCF_DSPI_DCTAR0_PASC_5CLK (0x00200000)
5201 +#define MCF_DSPI_DCTAR0_PASC_7CLK (0x00300000)
5202 +#define MCF_DSPI_DCTAR0_PDT_1CLK (0x00000000)
5203 +#define MCF_DSPI_DCTAR0_PDT_3CLK (0x00040000)
5204 +#define MCF_DSPI_DCTAR0_PDT_5CLK (0x00080000)
5205 +#define MCF_DSPI_DCTAR0_PDT_7CLK (0x000C0000)
5206 +#define MCF_DSPI_DCTAR0_PBR_2CLK (0x00000000)
5207 +#define MCF_DSPI_DCTAR0_PBR_3CLK (0x00010000)
5208 +#define MCF_DSPI_DCTAR0_PBR_5CLK (0x00020000)
5209 +#define MCF_DSPI_DCTAR0_PBR_7CLK (0x00030000)
5210 +
5211 +/* Bit definitions and macros for DCTAR1 */
5212 +/* Baud rate scaler */
5213 +#define MCF_DSPI_DCTAR1_BR(x) (((x)&0x0000000F))
5214 +/* Delay after transfer scaler */
5215 +#define MCF_DSPI_DCTAR1_DT(x) (((x)&0x0000000F)<<4)
5216 +/* After SCK delay scaler */
5217 +#define MCF_DSPI_DCTAR1_ASC(x) (((x)&0x0000000F)<<8)
5218 +/* PCS to SCK delay scaler */
5219 +#define MCF_DSPI_DCTAR1_CSSCK(x) (((x)&0x0000000F)<<12)
5220 +/* Baud rate prescaler */
5221 +#define MCF_DSPI_DCTAR1_PBR(x) (((x)&0x00000003)<<16)
5222 +/* Delay after transfer prescaler */
5223 +#define MCF_DSPI_DCTAR1_PDT(x) (((x)&0x00000003)<<18)
5224 +/* After SCK delay prescaler */
5225 +#define MCF_DSPI_DCTAR1_PASC(x) (((x)&0x00000003)<<20)
5226 +/* PCS to SCK delay prescaler */
5227 +#define MCF_DSPI_DCTAR1_PCSSCK(x) (((x)&0x00000003)<<22)
5228 +/* LSB first enable */
5229 +#define MCF_DSPI_DCTAR1_LSBFE (0x01000000)
5230 +/* Clock phase */
5231 +#define MCF_DSPI_DCTAR1_CPHA (0x02000000)
5232 +/* Clock polarity */
5233 +#define MCF_DSPI_DCTAR1_CPOL (0x04000000)
5234 +/* Frame size */
5235 +#define MCF_DSPI_DCTAR1_FMSZ(x) (((x)&0x0000000F)<<27)
5236 +/* Double baud rate */
5237 +#define MCF_DSPI_DCTAR1_DBR (0x80000000)
5238 +
5239 +
5240 +/* Bit definitions and macros for DCTAR2 */
5241 +/* Baud rate scaler */
5242 +#define MCF_DSPI_DCTAR2_BR(x) (((x)&0x0000000F))
5243 +/* Delay after transfer scaler */
5244 +#define MCF_DSPI_DCTAR2_DT(x) (((x)&0x0000000F)<<4)
5245 +/* After SCK delay scaler */
5246 +#define MCF_DSPI_DCTAR2_ASC(x) (((x)&0x0000000F)<<8)
5247 +/* PCS to SCK delay scaler */
5248 +#define MCF_DSPI_DCTAR2_CSSCK(x) (((x)&0x0000000F)<<12)
5249 +/* Baud rate prescaler */
5250 +#define MCF_DSPI_DCTAR2_PBR(x) (((x)&0x00000003)<<16)
5251 +/* Delay after transfer prescaler */
5252 +#define MCF_DSPI_DCTAR2_PDT(x) (((x)&0x00000003)<<18)
5253 +/* After SCK delay prescaler */
5254 +#define MCF_DSPI_DCTAR2_PASC(x) (((x)&0x00000003)<<20)
5255 +/* PCS to SCK delay prescaler */
5256 +#define MCF_DSPI_DCTAR2_PCSSCK(x) (((x)&0x00000003)<<22)
5257 +/* LSB first enable */
5258 +#define MCF_DSPI_DCTAR2_LSBFE (0x01000000)
5259 +/* Clock phase */
5260 +#define MCF_DSPI_DCTAR2_CPHA (0x02000000)
5261 +/* Clock polarity */
5262 +#define MCF_DSPI_DCTAR2_CPOL (0x04000000)
5263 +/* Frame size */
5264 +#define MCF_DSPI_DCTAR2_FMSZ(x) (((x)&0x0000000F)<<27)
5265 +/* Double baud rate */
5266 +#define MCF_DSPI_DCTAR2_DBR (0x80000000)
5267 +
5268 +/* Bit definitions and macros for DCTAR3 */
5269 +/* Baud rate scaler */
5270 +#define MCF_DSPI_DCTAR3_BR(x) (((x)&0x0000000F))
5271 +/* Delay after transfer scaler */
5272 +#define MCF_DSPI_DCTAR3_DT(x) (((x)&0x0000000F)<<4)
5273 +/* After SCK delay scaler */
5274 +#define MCF_DSPI_DCTAR3_ASC(x) (((x)&0x0000000F)<<8)
5275 +/* PCS to SCK delay scaler */
5276 +#define MCF_DSPI_DCTAR3_CSSCK(x) (((x)&0x0000000F)<<12)
5277 +/* Baud rate prescaler */
5278 +#define MCF_DSPI_DCTAR3_PBR(x) (((x)&0x00000003)<<16)
5279 +/* Delay after transfer prescaler */
5280 +#define MCF_DSPI_DCTAR3_PDT(x) (((x)&0x00000003)<<18)
5281 +/* After SCK delay prescaler */
5282 +#define MCF_DSPI_DCTAR3_PASC(x) (((x)&0x00000003)<<20)
5283 +/* PCS to SCK delay prescaler */
5284 +#define MCF_DSPI_DCTAR3_PCSSCK(x) (((x)&0x00000003)<<22)
5285 +/* LSB first enable */
5286 +#define MCF_DSPI_DCTAR3_LSBFE (0x01000000)
5287 +/* Clock phase */
5288 +#define MCF_DSPI_DCTAR3_CPHA (0x02000000)
5289 +/* Clock polarity */
5290 +#define MCF_DSPI_DCTAR3_CPOL (0x04000000)
5291 +/* Frame size */
5292 +#define MCF_DSPI_DCTAR3_FMSZ(x) (((x)&0x0000000F)<<27)
5293 +/* Double baud rate */
5294 +#define MCF_DSPI_DCTAR3_DBR (0x80000000)
5295 +
5296 +/* Bit definitions and macros for DCTAR4 */
5297 +/* Baud rate scaler */
5298 +#define MCF_DSPI_DCTAR4_BR(x) (((x)&0x0000000F))
5299 +/* Delay after transfer scaler */
5300 +#define MCF_DSPI_DCTAR4_DT(x) (((x)&0x0000000F)<<4)
5301 +/* After SCK delay scaler */
5302 +#define MCF_DSPI_DCTAR4_ASC(x) (((x)&0x0000000F)<<8)
5303 +/* PCS to SCK delay scaler */
5304 +#define MCF_DSPI_DCTAR4_CSSCK(x) (((x)&0x0000000F)<<12)
5305 +/* Baud rate prescaler */
5306 +#define MCF_DSPI_DCTAR4_PBR(x) (((x)&0x00000003)<<16)
5307 +/* Delay after transfer prescaler */
5308 +#define MCF_DSPI_DCTAR4_PDT(x) (((x)&0x00000003)<<18)
5309 +/* After SCK delay prescaler */
5310 +#define MCF_DSPI_DCTAR4_PASC(x) (((x)&0x00000003)<<20)
5311 +/* PCS to SCK delay prescaler */
5312 +#define MCF_DSPI_DCTAR4_PCSSCK(x) (((x)&0x00000003)<<22)
5313 +/* LSB first enable */
5314 +#define MCF_DSPI_DCTAR4_LSBFE (0x01000000)
5315 +/* Clock phase */
5316 +#define MCF_DSPI_DCTAR4_CPHA (0x02000000)
5317 +/* Clock polarity */
5318 +#define MCF_DSPI_DCTAR4_CPOL (0x04000000)
5319 +/* Frame size */
5320 +#define MCF_DSPI_DCTAR4_FMSZ(x) (((x)&0x0000000F)<<27)
5321 +/* Double baud rate */
5322 +#define MCF_DSPI_DCTAR4_DBR (0x80000000)
5323 +
5324 +/* Bit definitions and macros for DCTAR5 */
5325 +/* Baud rate scaler */
5326 +#define MCF_DSPI_DCTAR5_BR(x) (((x)&0x0000000F))
5327 +/* Delay after transfer scaler */
5328 +#define MCF_DSPI_DCTAR5_DT(x) (((x)&0x0000000F)<<4)
5329 +/* After SCK delay scaler */
5330 +#define MCF_DSPI_DCTAR5_ASC(x) (((x)&0x0000000F)<<8)
5331 +/* PCS to SCK delay scaler */
5332 +#define MCF_DSPI_DCTAR5_CSSCK(x) (((x)&0x0000000F)<<12)
5333 +/* Baud rate prescaler */
5334 +#define MCF_DSPI_DCTAR5_PBR(x) (((x)&0x00000003)<<16)
5335 +/* Delay after transfer prescaler */
5336 +#define MCF_DSPI_DCTAR5_PDT(x) (((x)&0x00000003)<<18)
5337 +/* After SCK delay prescaler */
5338 +#define MCF_DSPI_DCTAR5_PASC(x) (((x)&0x00000003)<<20)
5339 +/* PCS to SCK delay prescaler */
5340 +#define MCF_DSPI_DCTAR5_PCSSCK(x) (((x)&0x00000003)<<22)
5341 +/* LSB first enable */
5342 +#define MCF_DSPI_DCTAR5_LSBFE (0x01000000)
5343 +/* Clock phase */
5344 +#define MCF_DSPI_DCTAR5_CPHA (0x02000000)
5345 +/* Clock polarity */
5346 +#define MCF_DSPI_DCTAR5_CPOL (0x04000000)
5347 +/* Frame size */
5348 +#define MCF_DSPI_DCTAR5_FMSZ(x) (((x)&0x0000000F)<<27)
5349 +/* Double baud rate */
5350 +#define MCF_DSPI_DCTAR5_DBR (0x80000000)
5351 +
5352 +/* Bit definitions and macros for DCTAR6 */
5353 +/* Baud rate scaler */
5354 +#define MCF_DSPI_DCTAR6_BR(x) (((x)&0x0000000F))
5355 +/* Delay after transfer scaler */
5356 +#define MCF_DSPI_DCTAR6_DT(x) (((x)&0x0000000F)<<4)
5357 +/* After SCK delay scaler */
5358 +#define MCF_DSPI_DCTAR6_ASC(x) (((x)&0x0000000F)<<8)
5359 +/* PCS to SCK delay scaler */
5360 +#define MCF_DSPI_DCTAR6_CSSCK(x) (((x)&0x0000000F)<<12)
5361 +/* Baud rate prescaler */
5362 +#define MCF_DSPI_DCTAR6_PBR(x) (((x)&0x00000003)<<16)
5363 +/* Delay after transfer prescaler */
5364 +#define MCF_DSPI_DCTAR6_PDT(x) (((x)&0x00000003)<<18)
5365 +/* After SCK delay prescaler */
5366 +#define MCF_DSPI_DCTAR6_PASC(x) (((x)&0x00000003)<<20)
5367 +/* PCS to SCK delay prescaler */
5368 +#define MCF_DSPI_DCTAR6_PCSSCK(x) (((x)&0x00000003)<<22)
5369 +/* LSB first enable */
5370 +#define MCF_DSPI_DCTAR6_LSBFE (0x01000000)
5371 +/* Clock phase */
5372 +#define MCF_DSPI_DCTAR6_CPHA (0x02000000)
5373 +/* Clock polarity */
5374 +#define MCF_DSPI_DCTAR6_CPOL (0x04000000)
5375 +/* Frame size */
5376 +#define MCF_DSPI_DCTAR6_FMSZ(x) (((x)&0x0000000F)<<27)
5377 +/* Double baud rate */
5378 +#define MCF_DSPI_DCTAR6_DBR (0x80000000)
5379 +
5380 +/* Bit definitions and macros for DCTAR7 */
5381 +/* Baud rate scaler */
5382 +#define MCF_DSPI_DCTAR7_BR(x) (((x)&0x0000000F))
5383 +/* Delay after transfer scaler */
5384 +#define MCF_DSPI_DCTAR7_DT(x) (((x)&0x0000000F)<<4)
5385 +/* After SCK delay scaler */
5386 +#define MCF_DSPI_DCTAR7_ASC(x) (((x)&0x0000000F)<<8)
5387 +/* PCS to SCK delay scaler */
5388 +#define MCF_DSPI_DCTAR7_CSSCK(x) (((x)&0x0000000F)<<12)
5389 +/* Baud rate prescaler */
5390 +#define MCF_DSPI_DCTAR7_PBR(x) (((x)&0x00000003)<<16)
5391 +/* Delay after transfer prescaler */
5392 +#define MCF_DSPI_DCTAR7_PDT(x) (((x)&0x00000003)<<18)
5393 +/* After SCK delay prescaler */
5394 +#define MCF_DSPI_DCTAR7_PASC(x) (((x)&0x00000003)<<20)
5395 +/* PCS to SCK delay prescaler */
5396 +#define MCF_DSPI_DCTAR7_PCSSCK(x) (((x)&0x00000003)<<22)
5397 +/* LSB first enable */
5398 +#define MCF_DSPI_DCTAR7_LSBFE (0x01000000)
5399 +/* Clock phase */
5400 +#define MCF_DSPI_DCTAR7_CPHA (0x02000000)
5401 +/* Clock polarity */
5402 +#define MCF_DSPI_DCTAR7_CPOL (0x04000000)
5403 +/* Frame size */
5404 +#define MCF_DSPI_DCTAR7_FMSZ(x) (((x)&0x0000000F)<<27)
5405 +/* Double baud rate */
5406 +#define MCF_DSPI_DCTAR7_DBR (0x80000000)
5407 +
5408 +/* Bit definitions and macros for DSR */
5409 +/* Receive next pointer */
5410 +#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F))
5411 +/* Receive FIFO counter */
5412 +#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4)
5413 +/* Transmit next pointer */
5414 +#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8)
5415 +/* Transmit FIFO counter */
5416 +#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12)
5417 +/* Receive FIFO drain flag */
5418 +#define MCF_DSPI_DSR_RFDF (0x00020000)
5419 +/* Receive FIFO overflow flag */
5420 +#define MCF_DSPI_DSR_RFOF (0x00080000)
5421 +/* Transmit FIFO fill flag */
5422 +#define MCF_DSPI_DSR_TFFF (0x02000000)
5423 +/* Transmit FIFO underflow flag */
5424 +#define MCF_DSPI_DSR_TFUF (0x08000000)
5425 +/* End of queue flag */
5426 +#define MCF_DSPI_DSR_EOQF (0x10000000)
5427 +/* Tx and Rx status (enabled | disabled) */
5428 +#define MCF_DSPI_DSR_TXRXS (0x40000000)
5429 +/* Transfer complete flag */
5430 +#define MCF_DSPI_DSR_TCF (0x80000000)
5431 +
5432 +/* Bit definitions and macros for DRSER */
5433 +/* Receive FIFO drain DMA or interrupt select */
5434 +#define MCF_DSPI_DRSER_RFDFS (0x00010000)
5435 +/* Receive FIFO drain request enable */
5436 +#define MCF_DSPI_DRSER_RFDFE (0x00020000)
5437 +/* Receive FIFO overflow request enable */
5438 +#define MCF_DSPI_DRSER_RFOFE (0x00080000)
5439 +/* Transmit FIFO fill DMA or interrupt select */
5440 +#define MCF_DSPI_DRSER_TFFFS (0x01000000)
5441 +/* Transmit FIFO fill request enable */
5442 +#define MCF_DSPI_DRSER_TFFFE (0x02000000)
5443 +/* Transmit FIFO underflow request enable */
5444 +#define MCF_DSPI_DRSER_TFUFE (0x08000000)
5445 +/* DSPI finished request enable */
5446 +#define MCF_DSPI_DRSER_EOQFE (0x10000000)
5447 +/* Transmission complete request enable */
5448 +#define MCF_DSPI_DRSER_TCFE (0x80000000)
5449 +
5450 +/* Bit definitions and macros for DTFR */
5451 +/* Transmit data */
5452 +#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF))
5453 +/* Peripheral chip select 0 */
5454 +#define MCF_DSPI_DTFR_PCS0 (0x00010000)
5455 +/* Peripheral chip select 1 */
5456 +#define MCF_DSPI_DTFR_PCS1 (0x00020000)
5457 +/* Peripheral chip select 2 */
5458 +#define MCF_DSPI_DTFR_PCS2 (0x00040000)
5459 +/* Peripheral chip select 3 */
5460 +#define MCF_DSPI_DTFR_PCS3 (0x00080000)
5461 +/* Peripheral chip select 4 */
5462 +#define MCF_DSPI_DTFR_PCS4 (0x00100000)
5463 +/* Peripheral chip select 5 */
5464 +#define MCF_DSPI_DTFR_PCS5 (0x00200000)
5465 +/* Peripheral chip select 6 */
5466 +#define MCF_DSPI_DTFR_PCS6 (0x00400000)
5467 +/* Peripheral chip select 7 */
5468 +#define MCF_DSPI_DTFR_PCS7 (0x00800000)
5469 +/* Clear SPI transfer counter */
5470 +#define MCF_DSPI_DTFR_CTCNT (0x04000000)
5471 +/* End of queue */
5472 +#define MCF_DSPI_DTFR_EOQ (0x08000000)
5473 +/* Clock and transfer attributes select */
5474 +#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28)
5475 +/* Continuous peripheral chip-select enable */
5476 +#define MCF_DSPI_DTFR_CONT (0x80000000)
5477 +
5478 +/* Bit definitions and macros for DRFR */
5479 +/* Receive data */
5480 +#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF))
5481 +
5482 +/* Bit definitions and macros for DTFDR group */
5483 +/* Transmit data */
5484 +#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF))
5485 +/* Peripheral chip select 0 */
5486 +#define MCF_DSPI_DTFDR_PCS0 (0x00010000)
5487 +/* Peripheral chip select 0 */
5488 +#define MCF_DSPI_DTFDR_PCS1 (0x00020000)
5489 +/* Peripheral chip select 0 */
5490 +#define MCF_DSPI_DTFDR_PCS2 (0x00040000)
5491 +/* Peripheral chip select 0 */
5492 +#define MCF_DSPI_DTFDR_PCS3 (0x00080000)
5493 +/* Peripheral chip select 0 */
5494 +#define MCF_DSPI_DTFDR_PCS4 (0x00100000)
5495 +/* Peripheral chip select 0 */
5496 +#define MCF_DSPI_DTFDR_PCS5 (0x00200000)
5497 +/* Peripheral chip select 0 */
5498 +#define MCF_DSPI_DTFDR_PCS6 (0x00400000)
5499 +/* Peripheral chip select 0 */
5500 +#define MCF_DSPI_DTFDR_PCS7 (0x00800000)
5501 +/* Clear SPI transfer counter */
5502 +#define MCF_DSPI_DTFDR_CTCNT (0x04000000)
5503 +/* End of queue */
5504 +#define MCF_DSPI_DTFDR_EOQ (0x08000000)
5505 +/* Clock and transfer attributes select */
5506 +#define MCF_DSPI_DTFDR_CTAS(x) (((x)&0x00000007)<<28)
5507 +/* Continuous peripheral chip-select enable */
5508 +#define MCF_DSPI_DTFDR_CONT (0x80000000)
5509 +
5510 +/* Bit definitions and macros for DTFDR0 */
5511 +/* Transmit data */
5512 +#define MCF_DSPI_DTFDR0_TXDATA(x) (((x)&0x0000FFFF))
5513 +/* Peripheral chip select 0 */
5514 +#define MCF_DSPI_DTFDR0_PCS0 (0x00010000)
5515 +/* Peripheral chip select 0 */
5516 +#define MCF_DSPI_DTFDR0_PCS1 (0x00020000)
5517 +/* Peripheral chip select 0 */
5518 +#define MCF_DSPI_DTFDR0_PCS2 (0x00040000)
5519 +/* Peripheral chip select 0 */
5520 +#define MCF_DSPI_DTFDR0_PCS3 (0x00080000)
5521 +/* Peripheral chip select 0 */
5522 +#define MCF_DSPI_DTFDR0_PCS4 (0x00100000)
5523 +/* Peripheral chip select 0 */
5524 +#define MCF_DSPI_DTFDR0_PCS5 (0x00200000)
5525 +/* Peripheral chip select 0 */
5526 +#define MCF_DSPI_DTFDR0_PCS6 (0x00400000)
5527 +/* Peripheral chip select 0 */
5528 +#define MCF_DSPI_DTFDR0_PCS7 (0x00800000)
5529 +/* Clear SPI transfer counter */
5530 +#define MCF_DSPI_DTFDR0_CTCNT (0x04000000)
5531 +/* End of queue */
5532 +#define MCF_DSPI_DTFDR0_EOQ (0x08000000)
5533 +/* Clock and transfer attributes select */
5534 +#define MCF_DSPI_DTFDR0_CTAS(x) (((x)&0x00000007)<<28)
5535 +/* Continuous peripheral chip-select enable */
5536 +#define MCF_DSPI_DTFDR0_CONT (0x80000000)
5537 +/* Bit definitions and macros for DTFDR1 */
5538 +/* Transmit data */
5539 +#define MCF_DSPI_DTFDR1_TXDATA(x) (((x)&0x0000FFFF))
5540 +/* Peripheral chip select 0 */
5541 +#define MCF_DSPI_DTFDR1_PCS0 (0x00010000)
5542 +/* Peripheral chip select 1 */
5543 +#define MCF_DSPI_DTFDR1_PCS1 (0x00020000)
5544 +/* Peripheral chip select 2 */
5545 +#define MCF_DSPI_DTFDR1_PCS2 (0x00040000)
5546 +/* Peripheral chip select 3 */
5547 +#define MCF_DSPI_DTFDR1_PCS3 (0x00080000)
5548 +/* Peripheral chip select 4 */
5549 +#define MCF_DSPI_DTFDR1_PCS4 (0x00100000)
5550 +/* Peripheral chip select 5 */
5551 +#define MCF_DSPI_DTFDR1_PCS5 (0x00200000)
5552 +/* Peripheral chip select 6 */
5553 +#define MCF_DSPI_DTFDR1_PCS6 (0x00400000)
5554 +/* Peripheral chip select 7 */
5555 +#define MCF_DSPI_DTFDR1_PCS7 (0x00800000)
5556 +/* Clear SPI transfer counter */
5557 +#define MCF_DSPI_DTFDR1_CTCNT (0x04000000)
5558 +/* End of queue */
5559 +#define MCF_DSPI_DTFDR1_EOQ (0x08000000)
5560 +/* Clock and transfer attributes select */
5561 +#define MCF_DSPI_DTFDR1_CTAS(x) (((x)&0x00000007)<<28)
5562 +/* Continuous peripheral chip-select enable */
5563 +#define MCF_DSPI_DTFDR1_CONT (0x80000000)
5564 +
5565 +/* Bit definitions and macros for DTFDR2 */
5566 +#define MCF_DSPI_DTFDR2_TXDATA(x) (((x)&0x0000FFFF))
5567 +/* Peripheral chip select 0 */
5568 +#define MCF_DSPI_DTFDR2_PCS0 (0x00010000)
5569 +/* Peripheral chip select 1 */
5570 +#define MCF_DSPI_DTFDR2_PCS1 (0x00020000)
5571 +/* Peripheral chip select 2 */
5572 +#define MCF_DSPI_DTFDR2_PCS2 (0x00040000)
5573 +/* Peripheral chip select 3 */
5574 +#define MCF_DSPI_DTFDR2_PCS3 (0x00080000)
5575 +/* Peripheral chip select 4 */
5576 +#define MCF_DSPI_DTFDR2_PCS4 (0x00100000)
5577 +/* Peripheral chip select 5 */
5578 +#define MCF_DSPI_DTFDR2_PCS5 (0x00200000)
5579 +/* Peripheral chip select 6 */
5580 +#define MCF_DSPI_DTFDR2_PCS6 (0x00400000)
5581 +/* Peripheral chip select 7 */
5582 +#define MCF_DSPI_DTFDR2_PCS7 (0x00800000)
5583 +/* Clear SPI transfer counter */
5584 +#define MCF_DSPI_DTFDR2_CTCNT (0x04000000)
5585 +/* End of queue */
5586 +#define MCF_DSPI_DTFDR2_EOQ (0x08000000)
5587 +/* Clock and transfer attributes select */
5588 +#define MCF_DSPI_DTFDR2_CTAS(x) (((x)&0x00000007)<<28)
5589 +/* Continuous peripheral chip-select enable */
5590 +#define MCF_DSPI_DTFDR2_CONT (0x80000000)
5591 +
5592 +/* Bit definitions and macros for DTFDR3 */
5593 +/* Transmit data */
5594 +#define MCF_DSPI_DTFDR3_TXDATA(x) (((x)&0x0000FFFF))
5595 +/* Peripheral chip select 0 */
5596 +#define MCF_DSPI_DTFDR3_PCS0 (0x00010000)
5597 +/* Peripheral chip select 1 */
5598 +#define MCF_DSPI_DTFDR3_PCS1 (0x00020000)
5599 +/* Peripheral chip select 2 */
5600 +#define MCF_DSPI_DTFDR3_PCS2 (0x00040000)
5601 +/* Peripheral chip select 3 */
5602 +#define MCF_DSPI_DTFDR3_PCS3 (0x00080000)
5603 +/* Peripheral chip select 4 */
5604 +#define MCF_DSPI_DTFDR3_PCS4 (0x00100000)
5605 +/* Peripheral chip select 5 */
5606 +#define MCF_DSPI_DTFDR3_PCS5 (0x00200000)
5607 +/* Peripheral chip select 6 */
5608 +#define MCF_DSPI_DTFDR3_PCS6 (0x00400000)
5609 +/* Peripheral chip select 7 */
5610 +#define MCF_DSPI_DTFDR3_PCS7 (0x00800000)
5611 +/* Clear SPI transfer counter */
5612 +#define MCF_DSPI_DTFDR3_CTCNT (0x04000000)
5613 +/* End of queue */
5614 +#define MCF_DSPI_DTFDR3_EOQ (0x08000000)
5615 +/* Clock and transfer attributes select */
5616 +#define MCF_DSPI_DTFDR3_CTAS(x) (((x)&0x00000007)<<28)
5617 +/* Continuous peripheral chip-select enable */
5618 +#define MCF_DSPI_DTFDR3_CONT (0x80000000)
5619 +
5620 +/* Bit definitions and macros for DRFDR group */
5621 +#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF))
5622 +
5623 +/* Bit definitions and macros for DRFDR0 */
5624 +#define MCF_DSPI_DRFDR0_RXDATA(x) (((x)&0x0000FFFF))
5625 +
5626 +/* Bit definitions and macros for DRFDR1 */
5627 +#define MCF_DSPI_DRFDR1_RXDATA(x) (((x)&0x0000FFFF))
5628 +
5629 +/* Bit definitions and macros for DRFDR2 */
5630 +#define MCF_DSPI_DRFDR2_RXDATA(x) (((x)&0x0000FFFF))
5631 +
5632 +/* Bit definitions and macros for DRFDR3 */
5633 +#define MCF_DSPI_DRFDR3_RXDATA(x) (((x)&0x0000FFFF))
5634 +
5635 +/********************************************************************/
5636 +
5637 +#endif /* __MCF5445X_DSPI_H__ */
5638 --- /dev/null
5639 +++ b/arch/m68k/include/asm/mcf5445x_dtim.h
5640 @@ -0,0 +1,96 @@
5641 +/*
5642 + * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5643 + *
5644 + * Matt Waddel Matt.Waddel@freescale.com
5645 + *
5646 + * This program is free software; you can redistribute it and/or modify it
5647 + * under the terms of the GNU General Public License as published by the
5648 + * Free Software Foundation; either version 2 of the License, or (at your
5649 + * option) any later version.
5650 + */
5651 +
5652 +#ifndef __MCF5445X_DTIM_H__
5653 +#define __MCF5445X_DTIM_H__
5654 +
5655 +/*********************************************************************
5656 +*
5657 +* DMA Timers (DTIM)
5658 +*
5659 +*********************************************************************/
5660 +/* Register read/write macros */
5661 +#define MCF_DTIM0_DTMR 0xFC070000 /* DMA Timer Mode Register */
5662 +#define MCF_DTIM0_DTXMR 0xFC070002 /* DMA Timer Extended Mode Register */
5663 +#define MCF_DTIM0_DTER 0xFC070003 /* DMA Timer Event Register */
5664 +#define MCF_DTIM0_DTRR 0xFC070004 /* DMA Timer Reference Register */
5665 +#define MCF_DTIM0_DTCR 0xFC070008 /* DMA Timer Capture Register */
5666 +#define MCF_DTIM0_DTCN 0xFC07000C /* DMA Timer Counter Register */
5667 +#define MCF_DTIM1_DTMR 0xFC074000 /* DMA Timer Mode Register */
5668 +#define MCF_DTIM1_DTXMR 0xFC074002 /* DMA Timer Extended Mode Register */
5669 +#define MCF_DTIM1_DTER 0xFC074003 /* DMA Timer Event Register */
5670 +#define MCF_DTIM1_DTRR 0xFC074004 /* DMA Timer Reference Register */
5671 +#define MCF_DTIM1_DTCR 0xFC074008 /* DMA Timer Capture Register */
5672 +#define MCF_DTIM1_DTCN 0xFC07400C /* DMA Timer Counter Register */
5673 +#define MCF_DTIM2_DTMR 0xFC078000 /* DMA Timer Mode Register */
5674 +#define MCF_DTIM2_DTXMR 0xFC078002 /* DMA Timer Extended Mode Register */
5675 +#define MCF_DTIM2_DTER 0xFC078003 /* DMA Timer Event Register */
5676 +#define MCF_DTIM2_DTRR 0xFC078004 /* DMA Timer Reference Register */
5677 +#define MCF_DTIM2_DTCR 0xFC078008 /* DMA Timer Capture Register */
5678 +#define MCF_DTIM2_DTCN 0xFC07800C /* DMA Timer Counter Register */
5679 +#define MCF_DTIM3_DTMR 0xFC07C000 /* DMA Timer Mode Register */
5680 +#define MCF_DTIM3_DTXMR 0xFC07C002 /* DMA Timer Extended Mode Register */
5681 +#define MCF_DTIM3_DTER 0xFC07C003 /* DMA Timer Event Register */
5682 +#define MCF_DTIM3_DTRR 0xFC07C004 /* DMA Timer Reference Register */
5683 +#define MCF_DTIM3_DTCR 0xFC07C008 /* DMA Timer Capture Register */
5684 +#define MCF_DTIM3_DTCN 0xFC07C00C /* DMA Timer Counter Register */
5685 +
5686 +/* Parameterized register read/write macros for multiple modules */
5687 +/* DMA Timer Mode Register */
5688 +#define MCF_DTIM_DTMR(x) (0xFC070000+((x)*0x4000))
5689 +/* DMA Timer Extended Mode Register */
5690 +#define MCF_DTIM_DTXMR(x) (0xFC070002+((x)*0x4000))
5691 +/* DMA Timer Event Register */
5692 +#define MCF_DTIM_DTER(x) (0xFC070003+((x)*0x4000))
5693 +/* DMA Timer Reference Register */
5694 +#define MCF_DTIM_DTRR(x) (0xFC070004+((x)*0x4000))
5695 +/* DMA Timer Capture Register */
5696 +#define MCF_DTIM_DTCR(x) (0xFC070008+((x)*0x4000))
5697 +/* DMA Timer Counter Register */
5698 +#define MCF_DTIM_DTCN(x) (0xFC07000C+((x)*0x4000))
5699 +
5700 +/* Bit definitions and macros for DTMR */
5701 +#define MCF_DTIM_DTMR_RST (0x0001) /* Reset */
5702 +#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */
5703 +#define MCF_DTIM_DTMR_FRR (0x0008) /* Free run/restart */
5704 +/* Output reference request/interrupt enable */
5705 +#define MCF_DTIM_DTMR_ORRI (0x0010)
5706 +#define MCF_DTIM_DTMR_OM (0x0020) /* Output Mode */
5707 +#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */
5708 +#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */
5709 +#define MCF_DTIM_DTMR_RST_EN (0x0001)
5710 +#define MCF_DTIM_DTMR_RST_RST (0x0000)
5711 +#define MCF_DTIM_DTMR_CE_ANY (0x00C0)
5712 +#define MCF_DTIM_DTMR_CE_FALL (0x0080)
5713 +#define MCF_DTIM_DTMR_CE_RISE (0x0040)
5714 +#define MCF_DTIM_DTMR_CE_NONE (0x0000)
5715 +#define MCF_DTIM_DTMR_CLK_DTIN (0x0006)
5716 +#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004)
5717 +#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002)
5718 +#define MCF_DTIM_DTMR_CLK_STOP (0x0000)
5719 +
5720 +/* Bit definitions and macros for DTXMR */
5721 +#define MCF_DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */
5722 +#define MCF_DTIM_DTXMR_DMAEN (0x80) /* DMA request */
5723 +
5724 +/* Bit definitions and macros for DTER */
5725 +#define MCF_DTIM_DTER_CAP (0x01) /* Capture event */
5726 +#define MCF_DTIM_DTER_REF (0x02) /* Output reference event */
5727 +
5728 +/* Interrupts used for system timers */
5729 +#define MCFSIM_ICR_TIMER0 (0xFC048040+32)
5730 +#define MCFSIM_ICR_TIMER1 (0xFC048040+33)
5731 +#define MCFSIM_ICR_TIMER2 (0xFC048040+34)
5732 +#define MCFSIM_ICR_TIMER3 (0xFC048040+35)
5733 +
5734 +/********************************************************************/
5735 +
5736 +#endif /* __MCF5445X_DTIM_H__ */
5737 --- /dev/null
5738 +++ b/arch/m68k/include/asm/mcf5445x_edma.h
5739 @@ -0,0 +1,1472 @@
5740 +/*
5741 + * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
5742 + *
5743 + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
5744 + *
5745 + * This program is free software; you can redistribute it and/or modify it
5746 + * under the terms of the GNU General Public License as published by the
5747 + * Free Software Foundation; either version 2 of the License, or (at your
5748 + * option) any later version.
5749 + */
5750 +#ifndef __MCF5445X_EDMA_H__
5751 +#define __MCF5445X_EDMA_H__
5752 +
5753 +/*
5754 + * Enhanced DMA (EDMA)
5755 + */
5756 +
5757 +/* Channels */
5758 +#define MCF_EDMA_CHAN_DREQ0 0 /* External DMA request 0 */
5759 +#define MCF_EDMA_CHAN_DREQ1 1 /* External DMA request 1 */
5760 +#define MCF_EDMA_CHAN_UART0_RX 2 /* UART0 Receive */
5761 +#define MCF_EDMA_CHAN_UART0_TX 3 /* UART0 Transmit */
5762 +#define MCF_EDMA_CHAN_UART1_RX 4 /* UART1 Receive */
5763 +#define MCF_EDMA_CHAN_UART1_TX 5 /* UART1 Transmit */
5764 +#define MCF_EDMA_CHAN_UART2_RX 6 /* UART2 Receive */
5765 +#define MCF_EDMA_CHAN_UART2_TX 7 /* UART2 Transmit */
5766 +#define MCF_EDMA_CHAN_TIMER0 8 /* Timer 0 / SSI0 Rx */
5767 +#define MCF_EDMA_CHAN_TIMER1 9 /* Timer 1 / SSI1 Rx */
5768 +#define MCF_EDMA_CHAN_TIMER2 10 /* Timer 2 / SSI0 Tx */
5769 +#define MCF_EDMA_CHAN_TIMER3 11 /* Timer 3 / SSI1 Tx */
5770 +#define MCF_EDMA_CHAN_DSPI_RX 12 /* DSPI Receive */
5771 +#define MCF_EDMA_CHAN_DSPI_TX 13 /* DSPI Transmit */
5772 +#define MCF_EDMA_CHAN_ATA_RX 14 /* ATA Receive */
5773 +#define MCF_EDMA_CHAN_ATA_TX 15 /* ATA Transmit */
5774 +
5775 +/* Register read/write macros */
5776 +#define MCF_EDMA_CR MCF_REG32(0xFC044000)
5777 +#define MCF_EDMA_ES MCF_REG32(0xFC044004)
5778 +#define MCF_EDMA_ERQ MCF_REG16(0xFC04400E)
5779 +#define MCF_EDMA_EEI MCF_REG16(0xFC044016)
5780 +#define MCF_EDMA_SERQ MCF_REG08(0xFC044018)
5781 +#define MCF_EDMA_CERQ MCF_REG08(0xFC044019)
5782 +#define MCF_EDMA_SEEI MCF_REG08(0xFC04401A)
5783 +#define MCF_EDMA_CEEI MCF_REG08(0xFC04401B)
5784 +#define MCF_EDMA_CINT MCF_REG08(0xFC04401C)
5785 +#define MCF_EDMA_CERR MCF_REG08(0xFC04401D)
5786 +#define MCF_EDMA_SSRT MCF_REG08(0xFC04401E)
5787 +#define MCF_EDMA_CDNE MCF_REG08(0xFC04401F)
5788 +#define MCF_EDMA_INTR MCF_REG16(0xFC044026)
5789 +#define MCF_EDMA_ERR MCF_REG16(0xFC04402E)
5790 +#define MCF_EDMA_DCHPRI0 MCF_REG08(0xFC044100)
5791 +#define MCF_EDMA_DCHPRI1 MCF_REG08(0xFC044101)
5792 +#define MCF_EDMA_DCHPRI2 MCF_REG08(0xFC044102)
5793 +#define MCF_EDMA_DCHPRI3 MCF_REG08(0xFC044103)
5794 +#define MCF_EDMA_DCHPRI4 MCF_REG08(0xFC044104)
5795 +#define MCF_EDMA_DCHPRI5 MCF_REG08(0xFC044105)
5796 +#define MCF_EDMA_DCHPRI6 MCF_REG08(0xFC044106)
5797 +#define MCF_EDMA_DCHPRI7 MCF_REG08(0xFC044107)
5798 +#define MCF_EDMA_DCHPRI8 MCF_REG08(0xFC044108)
5799 +#define MCF_EDMA_DCHPRI9 MCF_REG08(0xFC044109)
5800 +#define MCF_EDMA_DCHPRI10 MCF_REG08(0xFC04410A)
5801 +#define MCF_EDMA_DCHPRI11 MCF_REG08(0xFC04410B)
5802 +#define MCF_EDMA_DCHPRI12 MCF_REG08(0xFC04410C)
5803 +#define MCF_EDMA_DCHPRI13 MCF_REG08(0xFC04410D)
5804 +#define MCF_EDMA_DCHPRI14 MCF_REG08(0xFC04410E)
5805 +#define MCF_EDMA_DCHPRI15 MCF_REG08(0xFC04410F)
5806 +#define MCF_EDMA_TCD0_SADDR MCF_REG32(0xFC045000)
5807 +#define MCF_EDMA_TCD0_ATTR MCF_REG16(0xFC045004)
5808 +#define MCF_EDMA_TCD0_SOFF MCF_REG16(0xFC045006)
5809 +#define MCF_EDMA_TCD0_NBYTES MCF_REG32(0xFC045008)
5810 +#define MCF_EDMA_TCD0_SLAST MCF_REG32(0xFC04500C)
5811 +#define MCF_EDMA_TCD0_DADDR MCF_REG32(0xFC045010)
5812 +#define MCF_EDMA_TCD0_CITER_ELINK MCF_REG16(0xFC045014)
5813 +#define MCF_EDMA_TCD0_CITER MCF_REG16(0xFC045014)
5814 +#define MCF_EDMA_TCD0_DOFF MCF_REG16(0xFC045016)
5815 +#define MCF_EDMA_TCD0_DLAST_SGA MCF_REG32(0xFC045018)
5816 +#define MCF_EDMA_TCD0_BITER_ELINK MCF_REG16(0xFC04501C)
5817 +#define MCF_EDMA_TCD0_BITER MCF_REG16(0xFC04501C)
5818 +#define MCF_EDMA_TCD0_CSR MCF_REG16(0xFC04501E)
5819 +#define MCF_EDMA_TCD1_SADDR MCF_REG32(0xFC045020)
5820 +#define MCF_EDMA_TCD1_ATTR MCF_REG16(0xFC045024)
5821 +#define MCF_EDMA_TCD1_SOFF MCF_REG16(0xFC045026)
5822 +#define MCF_EDMA_TCD1_NBYTES MCF_REG32(0xFC045028)
5823 +#define MCF_EDMA_TCD1_SLAST MCF_REG32(0xFC04502C)
5824 +#define MCF_EDMA_TCD1_DADDR MCF_REG32(0xFC045030)
5825 +#define MCF_EDMA_TCD1_CITER_ELINK MCF_REG16(0xFC045034)
5826 +#define MCF_EDMA_TCD1_CITER MCF_REG16(0xFC045034)
5827 +#define MCF_EDMA_TCD1_DOFF MCF_REG16(0xFC045036)
5828 +#define MCF_EDMA_TCD1_DLAST_SGA MCF_REG32(0xFC045038)
5829 +#define MCF_EDMA_TCD1_BITER MCF_REG16(0xFC04503C)
5830 +#define MCF_EDMA_TCD1_BITER_ELINK MCF_REG16(0xFC04503C)
5831 +#define MCF_EDMA_TCD1_CSR MCF_REG16(0xFC04503E)
5832 +#define MCF_EDMA_TCD2_SADDR MCF_REG32(0xFC045040)
5833 +#define MCF_EDMA_TCD2_ATTR MCF_REG16(0xFC045044)
5834 +#define MCF_EDMA_TCD2_SOFF MCF_REG16(0xFC045046)
5835 +#define MCF_EDMA_TCD2_NBYTES MCF_REG32(0xFC045048)
5836 +#define MCF_EDMA_TCD2_SLAST MCF_REG32(0xFC04504C)
5837 +#define MCF_EDMA_TCD2_DADDR MCF_REG32(0xFC045050)
5838 +#define MCF_EDMA_TCD2_CITER MCF_REG16(0xFC045054)
5839 +#define MCF_EDMA_TCD2_CITER_ELINK MCF_REG16(0xFC045054)
5840 +#define MCF_EDMA_TCD2_DOFF MCF_REG16(0xFC045056)
5841 +#define MCF_EDMA_TCD2_DLAST_SGA MCF_REG32(0xFC045058)
5842 +#define MCF_EDMA_TCD2_BITER_ELINK MCF_REG16(0xFC04505C)
5843 +#define MCF_EDMA_TCD2_BITER MCF_REG16(0xFC04505C)
5844 +#define MCF_EDMA_TCD2_CSR MCF_REG16(0xFC04505E)
5845 +#define MCF_EDMA_TCD3_SADDR MCF_REG32(0xFC045060)
5846 +#define MCF_EDMA_TCD3_ATTR MCF_REG16(0xFC045064)
5847 +#define MCF_EDMA_TCD3_SOFF MCF_REG16(0xFC045066)
5848 +#define MCF_EDMA_TCD3_NBYTES MCF_REG32(0xFC045068)
5849 +#define MCF_EDMA_TCD3_SLAST MCF_REG32(0xFC04506C)
5850 +#define MCF_EDMA_TCD3_DADDR MCF_REG32(0xFC045070)
5851 +#define MCF_EDMA_TCD3_CITER MCF_REG16(0xFC045074)
5852 +#define MCF_EDMA_TCD3_CITER_ELINK MCF_REG16(0xFC045074)
5853 +#define MCF_EDMA_TCD3_DOFF MCF_REG16(0xFC045076)
5854 +#define MCF_EDMA_TCD3_DLAST_SGA MCF_REG32(0xFC045078)
5855 +#define MCF_EDMA_TCD3_BITER_ELINK MCF_REG16(0xFC04507C)
5856 +#define MCF_EDMA_TCD3_BITER MCF_REG16(0xFC04507C)
5857 +#define MCF_EDMA_TCD3_CSR MCF_REG16(0xFC04507E)
5858 +#define MCF_EDMA_TCD4_SADDR MCF_REG32(0xFC045080)
5859 +#define MCF_EDMA_TCD4_ATTR MCF_REG16(0xFC045084)
5860 +#define MCF_EDMA_TCD4_SOFF MCF_REG16(0xFC045086)
5861 +#define MCF_EDMA_TCD4_NBYTES MCF_REG32(0xFC045088)
5862 +#define MCF_EDMA_TCD4_SLAST MCF_REG32(0xFC04508C)
5863 +#define MCF_EDMA_TCD4_DADDR MCF_REG32(0xFC045090)
5864 +#define MCF_EDMA_TCD4_CITER MCF_REG16(0xFC045094)
5865 +#define MCF_EDMA_TCD4_CITER_ELINK MCF_REG16(0xFC045094)
5866 +#define MCF_EDMA_TCD4_DOFF MCF_REG16(0xFC045096)
5867 +#define MCF_EDMA_TCD4_DLAST_SGA MCF_REG32(0xFC045098)
5868 +#define MCF_EDMA_TCD4_BITER MCF_REG16(0xFC04509C)
5869 +#define MCF_EDMA_TCD4_BITER_ELINK MCF_REG16(0xFC04509C)
5870 +#define MCF_EDMA_TCD4_CSR MCF_REG16(0xFC04509E)
5871 +#define MCF_EDMA_TCD5_SADDR MCF_REG32(0xFC0450A0)
5872 +#define MCF_EDMA_TCD5_ATTR MCF_REG16(0xFC0450A4)
5873 +#define MCF_EDMA_TCD5_SOFF MCF_REG16(0xFC0450A6)
5874 +#define MCF_EDMA_TCD5_NBYTES MCF_REG32(0xFC0450A8)
5875 +#define MCF_EDMA_TCD5_SLAST MCF_REG32(0xFC0450AC)
5876 +#define MCF_EDMA_TCD5_DADDR MCF_REG32(0xFC0450B0)
5877 +#define MCF_EDMA_TCD5_CITER MCF_REG16(0xFC0450B4)
5878 +#define MCF_EDMA_TCD5_CITER_ELINK MCF_REG16(0xFC0450B4)
5879 +#define MCF_EDMA_TCD5_DOFF MCF_REG16(0xFC0450B6)
5880 +#define MCF_EDMA_TCD5_DLAST_SGA MCF_REG32(0xFC0450B8)
5881 +#define MCF_EDMA_TCD5_BITER_ELINK MCF_REG16(0xFC0450BC)
5882 +#define MCF_EDMA_TCD5_BITER MCF_REG16(0xFC0450BC)
5883 +#define MCF_EDMA_TCD5_CSR MCF_REG16(0xFC0450BE)
5884 +#define MCF_EDMA_TCD6_SADDR MCF_REG32(0xFC0450C0)
5885 +#define MCF_EDMA_TCD6_ATTR MCF_REG16(0xFC0450C4)
5886 +#define MCF_EDMA_TCD6_SOFF MCF_REG16(0xFC0450C6)
5887 +#define MCF_EDMA_TCD6_NBYTES MCF_REG32(0xFC0450C8)
5888 +#define MCF_EDMA_TCD6_SLAST MCF_REG32(0xFC0450CC)
5889 +#define MCF_EDMA_TCD6_DADDR MCF_REG32(0xFC0450D0)
5890 +#define MCF_EDMA_TCD6_CITER MCF_REG16(0xFC0450D4)
5891 +#define MCF_EDMA_TCD6_CITER_ELINK MCF_REG16(0xFC0450D4)
5892 +#define MCF_EDMA_TCD6_DOFF MCF_REG16(0xFC0450D6)
5893 +#define MCF_EDMA_TCD6_DLAST_SGA MCF_REG32(0xFC0450D8)
5894 +#define MCF_EDMA_TCD6_BITER_ELINK MCF_REG16(0xFC0450DC)
5895 +#define MCF_EDMA_TCD6_BITER MCF_REG16(0xFC0450DC)
5896 +#define MCF_EDMA_TCD6_CSR MCF_REG16(0xFC0450DE)
5897 +#define MCF_EDMA_TCD7_SADDR MCF_REG32(0xFC0450E0)
5898 +#define MCF_EDMA_TCD7_ATTR MCF_REG16(0xFC0450E4)
5899 +#define MCF_EDMA_TCD7_SOFF MCF_REG16(0xFC0450E6)
5900 +#define MCF_EDMA_TCD7_NBYTES MCF_REG32(0xFC0450E8)
5901 +#define MCF_EDMA_TCD7_SLAST MCF_REG32(0xFC0450EC)
5902 +#define MCF_EDMA_TCD7_DADDR MCF_REG32(0xFC0450F0)
5903 +#define MCF_EDMA_TCD7_CITER MCF_REG16(0xFC0450F4)
5904 +#define MCF_EDMA_TCD7_CITER_ELINK MCF_REG16(0xFC0450F4)
5905 +#define MCF_EDMA_TCD7_DOFF MCF_REG16(0xFC0450F6)
5906 +#define MCF_EDMA_TCD7_DLAST_SGA MCF_REG32(0xFC0450F8)
5907 +#define MCF_EDMA_TCD7_BITER_ELINK MCF_REG16(0xFC0450FC)
5908 +#define MCF_EDMA_TCD7_BITER MCF_REG16(0xFC0450FC)
5909 +#define MCF_EDMA_TCD7_CSR MCF_REG16(0xFC0450FE)
5910 +#define MCF_EDMA_TCD8_SADDR MCF_REG32(0xFC045100)
5911 +#define MCF_EDMA_TCD8_ATTR MCF_REG16(0xFC045104)
5912 +#define MCF_EDMA_TCD8_SOFF MCF_REG16(0xFC045106)
5913 +#define MCF_EDMA_TCD8_NBYTES MCF_REG32(0xFC045108)
5914 +#define MCF_EDMA_TCD8_SLAST MCF_REG32(0xFC04510C)
5915 +#define MCF_EDMA_TCD8_DADDR MCF_REG32(0xFC045110)
5916 +#define MCF_EDMA_TCD8_CITER MCF_REG16(0xFC045114)
5917 +#define MCF_EDMA_TCD8_CITER_ELINK MCF_REG16(0xFC045114)
5918 +#define MCF_EDMA_TCD8_DOFF MCF_REG16(0xFC045116)
5919 +#define MCF_EDMA_TCD8_DLAST_SGA MCF_REG32(0xFC045118)
5920 +#define MCF_EDMA_TCD8_BITER_ELINK MCF_REG16(0xFC04511C)
5921 +#define MCF_EDMA_TCD8_BITER MCF_REG16(0xFC04511C)
5922 +#define MCF_EDMA_TCD8_CSR MCF_REG16(0xFC04511E)
5923 +#define MCF_EDMA_TCD9_SADDR MCF_REG32(0xFC045120)
5924 +#define MCF_EDMA_TCD9_ATTR MCF_REG16(0xFC045124)
5925 +#define MCF_EDMA_TCD9_SOFF MCF_REG16(0xFC045126)
5926 +#define MCF_EDMA_TCD9_NBYTES MCF_REG32(0xFC045128)
5927 +#define MCF_EDMA_TCD9_SLAST MCF_REG32(0xFC04512C)
5928 +#define MCF_EDMA_TCD9_DADDR MCF_REG32(0xFC045130)
5929 +#define MCF_EDMA_TCD9_CITER_ELINK MCF_REG16(0xFC045134)
5930 +#define MCF_EDMA_TCD9_CITER MCF_REG16(0xFC045134)
5931 +#define MCF_EDMA_TCD9_DOFF MCF_REG16(0xFC045136)
5932 +#define MCF_EDMA_TCD9_DLAST_SGA MCF_REG32(0xFC045138)
5933 +#define MCF_EDMA_TCD9_BITER_ELINK MCF_REG16(0xFC04513C)
5934 +#define MCF_EDMA_TCD9_BITER MCF_REG16(0xFC04513C)
5935 +#define MCF_EDMA_TCD9_CSR MCF_REG16(0xFC04513E)
5936 +#define MCF_EDMA_TCD10_SADDR MCF_REG32(0xFC045140)
5937 +#define MCF_EDMA_TCD10_ATTR MCF_REG16(0xFC045144)
5938 +#define MCF_EDMA_TCD10_SOFF MCF_REG16(0xFC045146)
5939 +#define MCF_EDMA_TCD10_NBYTES MCF_REG32(0xFC045148)
5940 +#define MCF_EDMA_TCD10_SLAST MCF_REG32(0xFC04514C)
5941 +#define MCF_EDMA_TCD10_DADDR MCF_REG32(0xFC045150)
5942 +#define MCF_EDMA_TCD10_CITER_ELINK MCF_REG16(0xFC045154)
5943 +#define MCF_EDMA_TCD10_CITER MCF_REG16(0xFC045154)
5944 +#define MCF_EDMA_TCD10_DOFF MCF_REG16(0xFC045156)
5945 +#define MCF_EDMA_TCD10_DLAST_SGA MCF_REG32(0xFC045158)
5946 +#define MCF_EDMA_TCD10_BITER MCF_REG16(0xFC04515C)
5947 +#define MCF_EDMA_TCD10_BITER_ELINK MCF_REG16(0xFC04515C)
5948 +#define MCF_EDMA_TCD10_CSR MCF_REG16(0xFC04515E)
5949 +#define MCF_EDMA_TCD11_SADDR MCF_REG32(0xFC045160)
5950 +#define MCF_EDMA_TCD11_ATTR MCF_REG16(0xFC045164)
5951 +#define MCF_EDMA_TCD11_SOFF MCF_REG16(0xFC045166)
5952 +#define MCF_EDMA_TCD11_NBYTES MCF_REG32(0xFC045168)
5953 +#define MCF_EDMA_TCD11_SLAST MCF_REG32(0xFC04516C)
5954 +#define MCF_EDMA_TCD11_DADDR MCF_REG32(0xFC045170)
5955 +#define MCF_EDMA_TCD11_CITER MCF_REG16(0xFC045174)
5956 +#define MCF_EDMA_TCD11_CITER_ELINK MCF_REG16(0xFC045174)
5957 +#define MCF_EDMA_TCD11_DOFF MCF_REG16(0xFC045176)
5958 +#define MCF_EDMA_TCD11_DLAST_SGA MCF_REG32(0xFC045178)
5959 +#define MCF_EDMA_TCD11_BITER MCF_REG16(0xFC04517C)
5960 +#define MCF_EDMA_TCD11_BITER_ELINK MCF_REG16(0xFC04517C)
5961 +#define MCF_EDMA_TCD11_CSR MCF_REG16(0xFC04517E)
5962 +#define MCF_EDMA_TCD12_SADDR MCF_REG32(0xFC045180)
5963 +#define MCF_EDMA_TCD12_ATTR MCF_REG16(0xFC045184)
5964 +#define MCF_EDMA_TCD12_SOFF MCF_REG16(0xFC045186)
5965 +#define MCF_EDMA_TCD12_NBYTES MCF_REG32(0xFC045188)
5966 +#define MCF_EDMA_TCD12_SLAST MCF_REG32(0xFC04518C)
5967 +#define MCF_EDMA_TCD12_DADDR MCF_REG32(0xFC045190)
5968 +#define MCF_EDMA_TCD12_CITER MCF_REG16(0xFC045194)
5969 +#define MCF_EDMA_TCD12_CITER_ELINK MCF_REG16(0xFC045194)
5970 +#define MCF_EDMA_TCD12_DOFF MCF_REG16(0xFC045196)
5971 +#define MCF_EDMA_TCD12_DLAST_SGA MCF_REG32(0xFC045198)
5972 +#define MCF_EDMA_TCD12_BITER MCF_REG16(0xFC04519C)
5973 +#define MCF_EDMA_TCD12_BITER_ELINK MCF_REG16(0xFC04519C)
5974 +#define MCF_EDMA_TCD12_CSR MCF_REG16(0xFC04519E)
5975 +#define MCF_EDMA_TCD13_SADDR MCF_REG32(0xFC0451A0)
5976 +#define MCF_EDMA_TCD13_ATTR MCF_REG16(0xFC0451A4)
5977 +#define MCF_EDMA_TCD13_SOFF MCF_REG16(0xFC0451A6)
5978 +#define MCF_EDMA_TCD13_NBYTES MCF_REG32(0xFC0451A8)
5979 +#define MCF_EDMA_TCD13_SLAST MCF_REG32(0xFC0451AC)
5980 +#define MCF_EDMA_TCD13_DADDR MCF_REG32(0xFC0451B0)
5981 +#define MCF_EDMA_TCD13_CITER_ELINK MCF_REG16(0xFC0451B4)
5982 +#define MCF_EDMA_TCD13_CITER MCF_REG16(0xFC0451B4)
5983 +#define MCF_EDMA_TCD13_DOFF MCF_REG16(0xFC0451B6)
5984 +#define MCF_EDMA_TCD13_DLAST_SGA MCF_REG32(0xFC0451B8)
5985 +#define MCF_EDMA_TCD13_BITER_ELINK MCF_REG16(0xFC0451BC)
5986 +#define MCF_EDMA_TCD13_BITER MCF_REG16(0xFC0451BC)
5987 +#define MCF_EDMA_TCD13_CSR MCF_REG16(0xFC0451BE)
5988 +#define MCF_EDMA_TCD14_SADDR MCF_REG32(0xFC0451C0)
5989 +#define MCF_EDMA_TCD14_ATTR MCF_REG16(0xFC0451C4)
5990 +#define MCF_EDMA_TCD14_SOFF MCF_REG16(0xFC0451C6)
5991 +#define MCF_EDMA_TCD14_NBYTES MCF_REG32(0xFC0451C8)
5992 +#define MCF_EDMA_TCD14_SLAST MCF_REG32(0xFC0451CC)
5993 +#define MCF_EDMA_TCD14_DADDR MCF_REG32(0xFC0451D0)
5994 +#define MCF_EDMA_TCD14_CITER MCF_REG16(0xFC0451D4)
5995 +#define MCF_EDMA_TCD14_CITER_ELINK MCF_REG16(0xFC0451D4)
5996 +#define MCF_EDMA_TCD14_DOFF MCF_REG16(0xFC0451D6)
5997 +#define MCF_EDMA_TCD14_DLAST_SGA MCF_REG32(0xFC0451D8)
5998 +#define MCF_EDMA_TCD14_BITER_ELINK MCF_REG16(0xFC0451DC)
5999 +#define MCF_EDMA_TCD14_BITER MCF_REG16(0xFC0451DC)
6000 +#define MCF_EDMA_TCD14_CSR MCF_REG16(0xFC0451DE)
6001 +#define MCF_EDMA_TCD15_SADDR MCF_REG32(0xFC0451E0)
6002 +#define MCF_EDMA_TCD15_ATTR MCF_REG16(0xFC0451E4)
6003 +#define MCF_EDMA_TCD15_SOFF MCF_REG16(0xFC0451E6)
6004 +#define MCF_EDMA_TCD15_NBYTES MCF_REG32(0xFC0451E8)
6005 +#define MCF_EDMA_TCD15_SLAST MCF_REG32(0xFC0451EC)
6006 +#define MCF_EDMA_TCD15_DADDR MCF_REG32(0xFC0451F0)
6007 +#define MCF_EDMA_TCD15_CITER_ELINK MCF_REG16(0xFC0451F4)
6008 +#define MCF_EDMA_TCD15_CITER MCF_REG16(0xFC0451F4)
6009 +#define MCF_EDMA_TCD15_DOFF MCF_REG16(0xFC0451F6)
6010 +#define MCF_EDMA_TCD15_DLAST_SGA MCF_REG32(0xFC0451F8)
6011 +#define MCF_EDMA_TCD15_BITER MCF_REG16(0xFC0451FC)
6012 +#define MCF_EDMA_TCD15_BITER_ELINK MCF_REG16(0xFC0451FC)
6013 +#define MCF_EDMA_TCD15_CSR MCF_REG16(0xFC0451FE)
6014 +
6015 +/* Parameterized register read/write macros for multiple registers */
6016 +#define MCF_EDMA_DCHPRI(x) MCF_REG08(0xFC044100+((x)*0x001))
6017 +#define MCF_EDMA_TCD_SADDR(x) MCF_REG32(0xFC045000+((x)*0x020))
6018 +#define MCF_EDMA_TCD_ATTR(x) MCF_REG16(0xFC045004+((x)*0x020))
6019 +#define MCF_EDMA_TCD_SOFF(x) MCF_REG16(0xFC045006+((x)*0x020))
6020 +#define MCF_EDMA_TCD_NBYTES(x) MCF_REG32(0xFC045008+((x)*0x020))
6021 +#define MCF_EDMA_TCD_SLAST(x) MCF_REG32(0xFC04500C+((x)*0x020))
6022 +#define MCF_EDMA_TCD_DADDR(x) MCF_REG32(0xFC045010+((x)*0x020))
6023 +#define MCF_EDMA_TCD_CITER_ELINK(x) MCF_REG16(0xFC045014+((x)*0x020))
6024 +#define MCF_EDMA_TCD_CITER(x) MCF_REG16(0xFC045014+((x)*0x020))
6025 +#define MCF_EDMA_TCD_DOFF(x) MCF_REG16(0xFC045016+((x)*0x020))
6026 +#define MCF_EDMA_TCD_DLAST_SGA(x) MCF_REG32(0xFC045018+((x)*0x020))
6027 +#define MCF_EDMA_TCD_BITER_ELINK(x) MCF_REG16(0xFC04501C+((x)*0x020))
6028 +#define MCF_EDMA_TCD_BITER(x) MCF_REG16(0xFC04501C+((x)*0x020))
6029 +#define MCF_EDMA_TCD_CSR(x) MCF_REG16((0xFC04501e)+((x)*0x020))
6030 +
6031 +/* Bit definitions and macros for CR */
6032 +#define MCF_EDMA_CR_EDBG (0x00000002)
6033 +#define MCF_EDMA_CR_ERCA (0x00000004)
6034 +
6035 +/* Bit definitions and macros for ES */
6036 +#define MCF_EDMA_ES_DBE (0x00000001)
6037 +#define MCF_EDMA_ES_SBE (0x00000002)
6038 +#define MCF_EDMA_ES_SGE (0x00000004)
6039 +#define MCF_EDMA_ES_NCE (0x00000008)
6040 +#define MCF_EDMA_ES_DOE (0x00000010)
6041 +#define MCF_EDMA_ES_DAE (0x00000020)
6042 +#define MCF_EDMA_ES_SOE (0x00000040)
6043 +#define MCF_EDMA_ES_SAE (0x00000080)
6044 +#define MCF_EDMA_ES_ERRCHN(x) (((x)&0x0000000F)<<8)
6045 +#define MCF_EDMA_ES_CPE (0x00004000)
6046 +#define MCF_EDMA_ES_VLD (0x80000000)
6047 +
6048 +/* Bit definitions and macros for ERQ */
6049 +#define MCF_EDMA_ERQ_ERQ0 (0x0001)
6050 +#define MCF_EDMA_ERQ_ERQ1 (0x0002)
6051 +#define MCF_EDMA_ERQ_ERQ2 (0x0004)
6052 +#define MCF_EDMA_ERQ_ERQ3 (0x0008)
6053 +#define MCF_EDMA_ERQ_ERQ4 (0x0010)
6054 +#define MCF_EDMA_ERQ_ERQ5 (0x0020)
6055 +#define MCF_EDMA_ERQ_ERQ6 (0x0040)
6056 +#define MCF_EDMA_ERQ_ERQ7 (0x0080)
6057 +#define MCF_EDMA_ERQ_ERQ8 (0x0100)
6058 +#define MCF_EDMA_ERQ_ERQ9 (0x0200)
6059 +#define MCF_EDMA_ERQ_ERQ10 (0x0400)
6060 +#define MCF_EDMA_ERQ_ERQ11 (0x0800)
6061 +#define MCF_EDMA_ERQ_ERQ12 (0x1000)
6062 +#define MCF_EDMA_ERQ_ERQ13 (0x2000)
6063 +#define MCF_EDMA_ERQ_ERQ14 (0x4000)
6064 +#define MCF_EDMA_ERQ_ERQ15 (0x8000)
6065 +
6066 +/* Bit definitions and macros for EEI */
6067 +#define MCF_EDMA_EEI_EEI0 (0x0001)
6068 +#define MCF_EDMA_EEI_EEI1 (0x0002)
6069 +#define MCF_EDMA_EEI_EEI2 (0x0004)
6070 +#define MCF_EDMA_EEI_EEI3 (0x0008)
6071 +#define MCF_EDMA_EEI_EEI4 (0x0010)
6072 +#define MCF_EDMA_EEI_EEI5 (0x0020)
6073 +#define MCF_EDMA_EEI_EEI6 (0x0040)
6074 +#define MCF_EDMA_EEI_EEI7 (0x0080)
6075 +#define MCF_EDMA_EEI_EEI8 (0x0100)
6076 +#define MCF_EDMA_EEI_EEI9 (0x0200)
6077 +#define MCF_EDMA_EEI_EEI10 (0x0400)
6078 +#define MCF_EDMA_EEI_EEI11 (0x0800)
6079 +#define MCF_EDMA_EEI_EEI12 (0x1000)
6080 +#define MCF_EDMA_EEI_EEI13 (0x2000)
6081 +#define MCF_EDMA_EEI_EEI14 (0x4000)
6082 +#define MCF_EDMA_EEI_EEI15 (0x8000)
6083 +
6084 +/* Bit definitions and macros for SERQ */
6085 +#define MCF_EDMA_SERQ_SERQ(x) (((x)&0x0F))
6086 +#define MCF_EDMA_SERQ_SAER (0x40)
6087 +
6088 +/* Bit definitions and macros for CERQ */
6089 +#define MCF_EDMA_CERQ_CERQ(x) (((x)&0x0F))
6090 +#define MCF_EDMA_CERQ_CAER (0x40)
6091 +
6092 +/* Bit definitions and macros for SEEI */
6093 +#define MCF_EDMA_SEEI_SEEI(x) (((x)&0x0F))
6094 +#define MCF_EDMA_SEEI_SAEE (0x40)
6095 +
6096 +/* Bit definitions and macros for CEEI */
6097 +#define MCF_EDMA_CEEI_CEEI(x) (((x)&0x0F))
6098 +#define MCF_EDMA_CEEI_CAEE (0x40)
6099 +
6100 +/* Bit definitions and macros for CINT */
6101 +#define MCF_EDMA_CINT_CINT(x) (((x)&0x0F))
6102 +#define MCF_EDMA_CINT_CAIR (0x40)
6103 +
6104 +/* Bit definitions and macros for CERR */
6105 +#define MCF_EDMA_CERR_CERR(x) (((x)&0x0F))
6106 +#define MCF_EDMA_CERR_CAER (0x40)
6107 +
6108 +/* Bit definitions and macros for SSRT */
6109 +#define MCF_EDMA_SSRT_SSRT(x) (((x)&0x0F))
6110 +#define MCF_EDMA_SSRT_SAST (0x40)
6111 +
6112 +/* Bit definitions and macros for CDNE */
6113 +#define MCF_EDMA_CDNE_CDNE(x) (((x)&0x0F))
6114 +#define MCF_EDMA_CDNE_CADN (0x40)
6115 +
6116 +/* Bit definitions and macros for INTR */
6117 +#define MCF_EDMA_INTR_INT0 (0x0001)
6118 +#define MCF_EDMA_INTR_INT1 (0x0002)
6119 +#define MCF_EDMA_INTR_INT2 (0x0004)
6120 +#define MCF_EDMA_INTR_INT3 (0x0008)
6121 +#define MCF_EDMA_INTR_INT4 (0x0010)
6122 +#define MCF_EDMA_INTR_INT5 (0x0020)
6123 +#define MCF_EDMA_INTR_INT6 (0x0040)
6124 +#define MCF_EDMA_INTR_INT7 (0x0080)
6125 +#define MCF_EDMA_INTR_INT8 (0x0100)
6126 +#define MCF_EDMA_INTR_INT9 (0x0200)
6127 +#define MCF_EDMA_INTR_INT10 (0x0400)
6128 +#define MCF_EDMA_INTR_INT11 (0x0800)
6129 +#define MCF_EDMA_INTR_INT12 (0x1000)
6130 +#define MCF_EDMA_INTR_INT13 (0x2000)
6131 +#define MCF_EDMA_INTR_INT14 (0x4000)
6132 +#define MCF_EDMA_INTR_INT15 (0x8000)
6133 +
6134 +/* Bit definitions and macros for ERR */
6135 +#define MCF_EDMA_ERR_ERR0 (0x0001)
6136 +#define MCF_EDMA_ERR_ERR1 (0x0002)
6137 +#define MCF_EDMA_ERR_ERR2 (0x0004)
6138 +#define MCF_EDMA_ERR_ERR3 (0x0008)
6139 +#define MCF_EDMA_ERR_ERR4 (0x0010)
6140 +#define MCF_EDMA_ERR_ERR5 (0x0020)
6141 +#define MCF_EDMA_ERR_ERR6 (0x0040)
6142 +#define MCF_EDMA_ERR_ERR7 (0x0080)
6143 +#define MCF_EDMA_ERR_ERR8 (0x0100)
6144 +#define MCF_EDMA_ERR_ERR9 (0x0200)
6145 +#define MCF_EDMA_ERR_ERR10 (0x0400)
6146 +#define MCF_EDMA_ERR_ERR11 (0x0800)
6147 +#define MCF_EDMA_ERR_ERR12 (0x1000)
6148 +#define MCF_EDMA_ERR_ERR13 (0x2000)
6149 +#define MCF_EDMA_ERR_ERR14 (0x4000)
6150 +#define MCF_EDMA_ERR_ERR15 (0x8000)
6151 +
6152 +/* Bit definitions and macros for DCHPRI group */
6153 +#define MCF_EDMA_DCHPRI_CHPRI(x) (((x)&0x0F))
6154 +#define MCF_EDMA_DCHPRI_ECP (0x80)
6155 +
6156 +/* Bit definitions and macros for DCHPRI0 */
6157 +#define MCF_EDMA_DCHPRI0_CHPRI(x) (((x)&0x0F))
6158 +#define MCF_EDMA_DCHPRI0_ECP (0x80)
6159 +
6160 +/* Bit definitions and macros for DCHPRI1 */
6161 +#define MCF_EDMA_DCHPRI1_CHPRI(x) (((x)&0x0F))
6162 +#define MCF_EDMA_DCHPRI1_ECP (0x80)
6163 +
6164 +/* Bit definitions and macros for DCHPRI2 */
6165 +#define MCF_EDMA_DCHPRI2_CHPRI(x) (((x)&0x0F))
6166 +#define MCF_EDMA_DCHPRI2_ECP (0x80)
6167 +
6168 +/* Bit definitions and macros for DCHPRI3 */
6169 +#define MCF_EDMA_DCHPRI3_CHPRI(x) (((x)&0x0F))
6170 +#define MCF_EDMA_DCHPRI3_ECP (0x80)
6171 +
6172 +/* Bit definitions and macros for DCHPRI4 */
6173 +#define MCF_EDMA_DCHPRI4_CHPRI(x) (((x)&0x0F))
6174 +#define MCF_EDMA_DCHPRI4_ECP (0x80)
6175 +
6176 +/* Bit definitions and macros for DCHPRI5 */
6177 +#define MCF_EDMA_DCHPRI5_CHPRI(x) (((x)&0x0F))
6178 +#define MCF_EDMA_DCHPRI5_ECP (0x80)
6179 +
6180 +/* Bit definitions and macros for DCHPRI6 */
6181 +#define MCF_EDMA_DCHPRI6_CHPRI(x) (((x)&0x0F))
6182 +#define MCF_EDMA_DCHPRI6_ECP (0x80)
6183 +
6184 +/* Bit definitions and macros for DCHPRI7 */
6185 +#define MCF_EDMA_DCHPRI7_CHPRI(x) (((x)&0x0F))
6186 +#define MCF_EDMA_DCHPRI7_ECP (0x80)
6187 +
6188 +/* Bit definitions and macros for DCHPRI8 */
6189 +#define MCF_EDMA_DCHPRI8_CHPRI(x) (((x)&0x0F))
6190 +#define MCF_EDMA_DCHPRI8_ECP (0x80)
6191 +
6192 +/* Bit definitions and macros for DCHPRI9 */
6193 +#define MCF_EDMA_DCHPRI9_CHPRI(x) (((x)&0x0F))
6194 +#define MCF_EDMA_DCHPRI9_ECP (0x80)
6195 +
6196 +/* Bit definitions and macros for DCHPRI10 */
6197 +#define MCF_EDMA_DCHPRI10_CHPRI(x) (((x)&0x0F))
6198 +#define MCF_EDMA_DCHPRI10_ECP (0x80)
6199 +
6200 +/* Bit definitions and macros for DCHPRI11 */
6201 +#define MCF_EDMA_DCHPRI11_CHPRI(x) (((x)&0x0F))
6202 +#define MCF_EDMA_DCHPRI11_ECP (0x80)
6203 +
6204 +/* Bit definitions and macros for DCHPRI12 */
6205 +#define MCF_EDMA_DCHPRI12_CHPRI(x) (((x)&0x0F))
6206 +#define MCF_EDMA_DCHPRI12_ECP (0x80)
6207 +
6208 +/* Bit definitions and macros for DCHPRI13 */
6209 +#define MCF_EDMA_DCHPRI13_CHPRI(x) (((x)&0x0F))
6210 +#define MCF_EDMA_DCHPRI13_ECP (0x80)
6211 +
6212 +/* Bit definitions and macros for DCHPRI14 */
6213 +#define MCF_EDMA_DCHPRI14_CHPRI(x) (((x)&0x0F))
6214 +#define MCF_EDMA_DCHPRI14_ECP (0x80)
6215 +
6216 +/* Bit definitions and macros for DCHPRI15 */
6217 +#define MCF_EDMA_DCHPRI15_CHPRI(x) (((x)&0x0F))
6218 +#define MCF_EDMA_DCHPRI15_ECP (0x80)
6219 +
6220 +/* Bit definitions and macros for TCD_SADDR group */
6221 +#define MCF_EDMA_TCD_SADDR_SADDR(x) (x)
6222 +
6223 +/* Bit definitions and macros for TCD0_SADDR */
6224 +#define MCF_EDMA_TCD0_SADDR_SADDR(x) (x)
6225 +
6226 +/* Bit definitions and macros for TCD_ATTR group */
6227 +#define MCF_EDMA_TCD_ATTR_DSIZE(x) (((x)&0x0007))
6228 +#define MCF_EDMA_TCD_ATTR_DMOD(x) (((x)&0x001F)<<3)
6229 +#define MCF_EDMA_TCD_ATTR_SSIZE(x) (((x)&0x0007)<<8)
6230 +#define MCF_EDMA_TCD_ATTR_SMOD(x) (((x)&0x001F)<<11)
6231 +#define MCF_EDMA_TCD_ATTR_SSIZE_8BIT (0x0000)
6232 +#define MCF_EDMA_TCD_ATTR_SSIZE_16BIT (0x0100)
6233 +#define MCF_EDMA_TCD_ATTR_SSIZE_32BIT (0x0200)
6234 +#define MCF_EDMA_TCD_ATTR_SSIZE_16BYTE (0x0400)
6235 +#define MCF_EDMA_TCD_ATTR_DSIZE_8BIT (0x0000)
6236 +#define MCF_EDMA_TCD_ATTR_DSIZE_16BIT (0x0001)
6237 +#define MCF_EDMA_TCD_ATTR_DSIZE_32BIT (0x0002)
6238 +#define MCF_EDMA_TCD_ATTR_DSIZE_16BYTE (0x0004)
6239 +
6240 +/* Bit definitions and macros for TCD0_ATTR */
6241 +#define MCF_EDMA_TCD0_ATTR_DSIZE(x) (((x)&0x0007))
6242 +#define MCF_EDMA_TCD0_ATTR_DMOD(x) (((x)&0x001F)<<3)
6243 +#define MCF_EDMA_TCD0_ATTR_SSIZE(x) (((x)&0x0007)<<8)
6244 +#define MCF_EDMA_TCD0_ATTR_SMOD(x) (((x)&0x001F)<<11)
6245 +#define MCF_EDMA_TCD0_ATTR_SSIZE_8BIT (0x0000)
6246 +#define MCF_EDMA_TCD0_ATTR_SSIZE_16BIT (0x0100)
6247 +#define MCF_EDMA_TCD0_ATTR_SSIZE_32BIT (0x0200)
6248 +#define MCF_EDMA_TCD0_ATTR_SSIZE_16BYTE (0x0400)
6249 +#define MCF_EDMA_TCD0_ATTR_DSIZE_8BIT (0x0000)
6250 +#define MCF_EDMA_TCD0_ATTR_DSIZE_16BIT (0x0001)
6251 +#define MCF_EDMA_TCD0_ATTR_DSIZE_32BIT (0x0002)
6252 +#define MCF_EDMA_TCD0_ATTR_DSIZE_16BYTE (0x0004)
6253 +
6254 +/* Bit definitions and macros for TCD_SOFF group */
6255 +#define MCF_EDMA_TCD_SOFF_SOFF(x) (x)
6256 +
6257 +/* Bit definitions and macros for TCD0_SOFF */
6258 +#define MCF_EDMA_TCD0_SOFF_SOFF(x) (x)
6259 +
6260 +/* Bit definitions and macros for TCD_NBYTES group */
6261 +#define MCF_EDMA_TCD_NBYTES_NBYTES(x) (x)
6262 +
6263 +/* Bit definitions and macros for TCD0_NBYTES */
6264 +#define MCF_EDMA_TCD0_NBYTES_NBYTES(x) (x)
6265 +
6266 +/* Bit definitions and macros for TCD_SLAST group */
6267 +#define MCF_EDMA_TCD_SLAST_SLAST(x) (x)
6268 +
6269 +/* Bit definitions and macros for TCD0_SLAST */
6270 +#define MCF_EDMA_TCD0_SLAST_SLAST(x) (x)
6271 +
6272 +/* Bit definitions and macros for TCD_DADDR group */
6273 +#define MCF_EDMA_TCD_DADDR_DADDR(x) (x)
6274 +
6275 +/* Bit definitions and macros for TCD0_DADDR */
6276 +#define MCF_EDMA_TCD0_DADDR_DADDR(x) (x)
6277 +
6278 +/* Bit definitions and macros for TCD_CITER_ELINK group */
6279 +#define MCF_EDMA_TCD_CITER_ELINK_CITER(x) (((x)&0x01FF))
6280 +#define MCF_EDMA_TCD_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6281 +#define MCF_EDMA_TCD_CITER_ELINK_E_LINK (0x8000)
6282 +
6283 +/* Bit definitions and macros for TCD0_CITER_ELINK */
6284 +#define MCF_EDMA_TCD0_CITER_ELINK_CITER(x) (((x)&0x01FF))
6285 +#define MCF_EDMA_TCD0_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6286 +#define MCF_EDMA_TCD0_CITER_ELINK_E_LINK (0x8000)
6287 +
6288 +/* Bit definitions and macros for TCD_CITER group */
6289 +#define MCF_EDMA_TCD_CITER_CITER(x) (((x)&0x7FFF))
6290 +#define MCF_EDMA_TCD_CITER_E_LINK (0x8000)
6291 +
6292 +/* Bit definitions and macros for TCD0_CITER */
6293 +#define MCF_EDMA_TCD0_CITER_CITER(x) (((x)&0x7FFF))
6294 +#define MCF_EDMA_TCD0_CITER_E_LINK (0x8000)
6295 +
6296 +/* Bit definitions and macros for TCD_DOFF group */
6297 +#define MCF_EDMA_TCD_DOFF_DOFF(x) (x)
6298 +
6299 +/* Bit definitions and macros for TCD0_DOFF */
6300 +#define MCF_EDMA_TCD0_DOFF_DOFF(x) (x)
6301 +
6302 +/* Bit definitions and macros for TCD_DLAST_SGA group */
6303 +#define MCF_EDMA_TCD_DLAST_SGA_DLAST_SGA(x) (x)
6304 +
6305 +/* Bit definitions and macros for TCD0_DLAST_SGA */
6306 +#define MCF_EDMA_TCD0_DLAST_SGA_DLAST_SGA(x) (x)
6307 +
6308 +/* Bit definitions and macros for TCD_BITER_ELINK group */
6309 +#define MCF_EDMA_TCD_BITER_ELINK_BITER(x) (((x)&0x01FF))
6310 +#define MCF_EDMA_TCD_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6311 +#define MCF_EDMA_TCD_BITER_ELINK_E_LINK (0x8000)
6312 +
6313 +/* Bit definitions and macros for TCD0_BITER_ELINK */
6314 +#define MCF_EDMA_TCD0_BITER_ELINK_BITER(x) (((x)&0x01FF))
6315 +#define MCF_EDMA_TCD0_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6316 +#define MCF_EDMA_TCD0_BITER_ELINK_E_LINK (0x8000)
6317 +
6318 +/* Bit definitions and macros for TCD_BITER group */
6319 +#define MCF_EDMA_TCD_BITER_BITER(x) (((x)&0x7FFF))
6320 +#define MCF_EDMA_TCD_BITER_E_LINK (0x8000)
6321 +
6322 +/* Bit definitions and macros for TCD0_BITER */
6323 +#define MCF_EDMA_TCD0_BITER_BITER(x) (((x)&0x7FFF))
6324 +#define MCF_EDMA_TCD0_BITER_E_LINK (0x8000)
6325 +
6326 +/* Bit definitions and macros for TCD_CSR group */
6327 +#define MCF_EDMA_TCD_CSR_START (0x0001)
6328 +#define MCF_EDMA_TCD_CSR_INT_MAJOR (0x0002)
6329 +#define MCF_EDMA_TCD_CSR_INT_HALF (0x0004)
6330 +#define MCF_EDMA_TCD_CSR_D_REQ (0x0008)
6331 +#define MCF_EDMA_TCD_CSR_E_SG (0x0010)
6332 +#define MCF_EDMA_TCD_CSR_E_LINK (0x0020)
6333 +#define MCF_EDMA_TCD_CSR_ACTIVE (0x0040)
6334 +#define MCF_EDMA_TCD_CSR_DONE (0x0080)
6335 +#define MCF_EDMA_TCD_CSR_LINKCH(x) (((x)&0x003F)<<8)
6336 +#define MCF_EDMA_TCD_CSR_BWC(x) (((x)&0x0003)<<14)
6337 +#define MCF_EDMA_TCD_CSR_BWC_NO_STALL (0x0000)
6338 +#define MCF_EDMA_TCD_CSR_BWC_4CYC_STALL (0x8000)
6339 +#define MCF_EDMA_TCD_CSR_BWC_8CYC_STALL (0xC000)
6340 +
6341 +/* Bit definitions and macros for TCD0_CSR */
6342 +#define MCF_EDMA_TCD0_CSR_START (0x0001)
6343 +#define MCF_EDMA_TCD0_CSR_INT_MAJOR (0x0002)
6344 +#define MCF_EDMA_TCD0_CSR_INT_HALF (0x0004)
6345 +#define MCF_EDMA_TCD0_CSR_D_REQ (0x0008)
6346 +#define MCF_EDMA_TCD0_CSR_E_SG (0x0010)
6347 +#define MCF_EDMA_TCD0_CSR_E_LINK (0x0020)
6348 +#define MCF_EDMA_TCD0_CSR_ACTIVE (0x0040)
6349 +#define MCF_EDMA_TCD0_CSR_DONE (0x0080)
6350 +#define MCF_EDMA_TCD0_CSR_LINKCH(x) (((x)&0x003F)<<8)
6351 +#define MCF_EDMA_TCD0_CSR_BWC(x) (((x)&0x0003)<<14)
6352 +#define MCF_EDMA_TCD0_CSR_BWC_NO_STALL (0x0000)
6353 +#define MCF_EDMA_TCD0_CSR_BWC_4CYC_STALL (0x8000)
6354 +#define MCF_EDMA_TCD0_CSR_BWC_8CYC_STALL (0xC000)
6355 +
6356 +/* Bit definitions and macros for TCD1_SADDR */
6357 +#define MCF_EDMA_TCD1_SADDR_SADDR(x) (x)
6358 +
6359 +/* Bit definitions and macros for TCD1_ATTR */
6360 +#define MCF_EDMA_TCD1_ATTR_DSIZE(x) (((x)&0x0007))
6361 +#define MCF_EDMA_TCD1_ATTR_DMOD(x) (((x)&0x001F)<<3)
6362 +#define MCF_EDMA_TCD1_ATTR_SSIZE(x) (((x)&0x0007)<<8)
6363 +#define MCF_EDMA_TCD1_ATTR_SMOD(x) (((x)&0x001F)<<11)
6364 +
6365 +/* Bit definitions and macros for TCD1_SOFF */
6366 +#define MCF_EDMA_TCD1_SOFF_SOFF(x) (x)
6367 +
6368 +/* Bit definitions and macros for TCD1_NBYTES */
6369 +#define MCF_EDMA_TCD1_NBYTES_NBYTES(x) (x)
6370 +
6371 +/* Bit definitions and macros for TCD1_SLAST */
6372 +#define MCF_EDMA_TCD1_SLAST_SLAST(x) (x)
6373 +
6374 +/* Bit definitions and macros for TCD1_DADDR */
6375 +#define MCF_EDMA_TCD1_DADDR_DADDR(x) (x)
6376 +
6377 +/* Bit definitions and macros for TCD1_CITER_ELINK */
6378 +#define MCF_EDMA_TCD1_CITER_ELINK_CITER(x) (((x)&0x01FF))
6379 +#define MCF_EDMA_TCD1_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6380 +#define MCF_EDMA_TCD1_CITER_ELINK_E_LINK (0x8000)
6381 +
6382 +/* Bit definitions and macros for TCD1_CITER */
6383 +#define MCF_EDMA_TCD1_CITER_CITER(x) (((x)&0x7FFF))
6384 +#define MCF_EDMA_TCD1_CITER_E_LINK (0x8000)
6385 +
6386 +/* Bit definitions and macros for TCD1_DOFF */
6387 +#define MCF_EDMA_TCD1_DOFF_DOFF(x) (x)
6388 +
6389 +/* Bit definitions and macros for TCD1_DLAST_SGA */
6390 +#define MCF_EDMA_TCD1_DLAST_SGA_DLAST_SGA(x) (x)
6391 +
6392 +/* Bit definitions and macros for TCD1_BITER */
6393 +#define MCF_EDMA_TCD1_BITER_BITER(x) (((x)&0x7FFF))
6394 +#define MCF_EDMA_TCD1_BITER_E_LINK (0x8000)
6395 +
6396 +/* Bit definitions and macros for TCD1_BITER_ELINK */
6397 +#define MCF_EDMA_TCD1_BITER_ELINK_BITER(x) (((x)&0x01FF))
6398 +#define MCF_EDMA_TCD1_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6399 +#define MCF_EDMA_TCD1_BITER_ELINK_E_LINK (0x8000)
6400 +
6401 +/* Bit definitions and macros for TCD1_CSR */
6402 +#define MCF_EDMA_TCD1_CSR_START (0x0001)
6403 +#define MCF_EDMA_TCD1_CSR_INT_MAJOR (0x0002)
6404 +#define MCF_EDMA_TCD1_CSR_INT_HALF (0x0004)
6405 +#define MCF_EDMA_TCD1_CSR_D_REQ (0x0008)
6406 +#define MCF_EDMA_TCD1_CSR_E_SG (0x0010)
6407 +#define MCF_EDMA_TCD1_CSR_E_LINK (0x0020)
6408 +#define MCF_EDMA_TCD1_CSR_ACTIVE (0x0040)
6409 +#define MCF_EDMA_TCD1_CSR_DONE (0x0080)
6410 +#define MCF_EDMA_TCD1_CSR_LINKCH(x) (((x)&0x003F)<<8)
6411 +#define MCF_EDMA_TCD1_CSR_BWC(x) (((x)&0x0003)<<14)
6412 +
6413 +/* Bit definitions and macros for TCD2_SADDR */
6414 +#define MCF_EDMA_TCD2_SADDR_SADDR(x) (x)
6415 +
6416 +/* Bit definitions and macros for TCD2_ATTR */
6417 +#define MCF_EDMA_TCD2_ATTR_DSIZE(x) (((x)&0x0007))
6418 +#define MCF_EDMA_TCD2_ATTR_DMOD(x) (((x)&0x001F)<<3)
6419 +#define MCF_EDMA_TCD2_ATTR_SSIZE(x) (((x)&0x0007)<<8)
6420 +#define MCF_EDMA_TCD2_ATTR_SMOD(x) (((x)&0x001F)<<11)
6421 +
6422 +/* Bit definitions and macros for TCD2_SOFF */
6423 +#define MCF_EDMA_TCD2_SOFF_SOFF(x) (x)
6424 +
6425 +/* Bit definitions and macros for TCD2_NBYTES */
6426 +#define MCF_EDMA_TCD2_NBYTES_NBYTES(x) (x)
6427 +
6428 +/* Bit definitions and macros for TCD2_SLAST */
6429 +#define MCF_EDMA_TCD2_SLAST_SLAST(x) (x)
6430 +
6431 +/* Bit definitions and macros for TCD2_DADDR */
6432 +#define MCF_EDMA_TCD2_DADDR_DADDR(x) (x)
6433 +
6434 +/* Bit definitions and macros for TCD2_CITER */
6435 +#define MCF_EDMA_TCD2_CITER_CITER(x) (((x)&0x7FFF))
6436 +#define MCF_EDMA_TCD2_CITER_E_LINK (0x8000)
6437 +
6438 +/* Bit definitions and macros for TCD2_CITER_ELINK */
6439 +#define MCF_EDMA_TCD2_CITER_ELINK_CITER(x) (((x)&0x01FF))
6440 +#define MCF_EDMA_TCD2_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6441 +#define MCF_EDMA_TCD2_CITER_ELINK_E_LINK (0x8000)
6442 +
6443 +/* Bit definitions and macros for TCD2_DOFF */
6444 +#define MCF_EDMA_TCD2_DOFF_DOFF(x) (x)
6445 +
6446 +/* Bit definitions and macros for TCD2_DLAST_SGA */
6447 +#define MCF_EDMA_TCD2_DLAST_SGA_DLAST_SGA(x) (x)
6448 +
6449 +/* Bit definitions and macros for TCD2_BITER_ELINK */
6450 +#define MCF_EDMA_TCD2_BITER_ELINK_BITER(x) (((x)&0x01FF))
6451 +#define MCF_EDMA_TCD2_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6452 +#define MCF_EDMA_TCD2_BITER_ELINK_E_LINK (0x8000)
6453 +
6454 +/* Bit definitions and macros for TCD2_BITER */
6455 +#define MCF_EDMA_TCD2_BITER_BITER(x) (((x)&0x7FFF))
6456 +#define MCF_EDMA_TCD2_BITER_E_LINK (0x8000)
6457 +
6458 +/* Bit definitions and macros for TCD2_CSR */
6459 +#define MCF_EDMA_TCD2_CSR_START (0x0001)
6460 +#define MCF_EDMA_TCD2_CSR_INT_MAJOR (0x0002)
6461 +#define MCF_EDMA_TCD2_CSR_INT_HALF (0x0004)
6462 +#define MCF_EDMA_TCD2_CSR_D_REQ (0x0008)
6463 +#define MCF_EDMA_TCD2_CSR_E_SG (0x0010)
6464 +#define MCF_EDMA_TCD2_CSR_E_LINK (0x0020)
6465 +#define MCF_EDMA_TCD2_CSR_ACTIVE (0x0040)
6466 +#define MCF_EDMA_TCD2_CSR_DONE (0x0080)
6467 +#define MCF_EDMA_TCD2_CSR_LINKCH(x) (((x)&0x003F)<<8)
6468 +#define MCF_EDMA_TCD2_CSR_BWC(x) (((x)&0x0003)<<14)
6469 +
6470 +/* Bit definitions and macros for TCD3_SADDR */
6471 +#define MCF_EDMA_TCD3_SADDR_SADDR(x) (x)
6472 +
6473 +/* Bit definitions and macros for TCD3_ATTR */
6474 +#define MCF_EDMA_TCD3_ATTR_DSIZE(x) (((x)&0x0007))
6475 +#define MCF_EDMA_TCD3_ATTR_DMOD(x) (((x)&0x001F)<<3)
6476 +#define MCF_EDMA_TCD3_ATTR_SSIZE(x) (((x)&0x0007)<<8)
6477 +#define MCF_EDMA_TCD3_ATTR_SMOD(x) (((x)&0x001F)<<11)
6478 +
6479 +/* Bit definitions and macros for TCD3_SOFF */
6480 +#define MCF_EDMA_TCD3_SOFF_SOFF(x) (x)
6481 +
6482 +/* Bit definitions and macros for TCD3_NBYTES */
6483 +#define MCF_EDMA_TCD3_NBYTES_NBYTES(x) (x)
6484 +
6485 +/* Bit definitions and macros for TCD3_SLAST */
6486 +#define MCF_EDMA_TCD3_SLAST_SLAST(x) (x)
6487 +
6488 +/* Bit definitions and macros for TCD3_DADDR */
6489 +#define MCF_EDMA_TCD3_DADDR_DADDR(x) (x)
6490 +
6491 +/* Bit definitions and macros for TCD3_CITER */
6492 +#define MCF_EDMA_TCD3_CITER_CITER(x) (((x)&0x7FFF))
6493 +#define MCF_EDMA_TCD3_CITER_E_LINK (0x8000)
6494 +
6495 +/* Bit definitions and macros for TCD3_CITER_ELINK */
6496 +#define MCF_EDMA_TCD3_CITER_ELINK_CITER(x) (((x)&0x01FF))
6497 +#define MCF_EDMA_TCD3_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6498 +#define MCF_EDMA_TCD3_CITER_ELINK_E_LINK (0x8000)
6499 +
6500 +/* Bit definitions and macros for TCD3_DOFF */
6501 +#define MCF_EDMA_TCD3_DOFF_DOFF(x) (x)
6502 +
6503 +/* Bit definitions and macros for TCD3_DLAST_SGA */
6504 +#define MCF_EDMA_TCD3_DLAST_SGA_DLAST_SGA(x) (x)
6505 +
6506 +/* Bit definitions and macros for TCD3_BITER_ELINK */
6507 +#define MCF_EDMA_TCD3_BITER_ELINK_BITER(x) (((x)&0x01FF))
6508 +#define MCF_EDMA_TCD3_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6509 +#define MCF_EDMA_TCD3_BITER_ELINK_E_LINK (0x8000)
6510 +
6511 +/* Bit definitions and macros for TCD3_BITER */
6512 +#define MCF_EDMA_TCD3_BITER_BITER(x) (((x)&0x7FFF))
6513 +#define MCF_EDMA_TCD3_BITER_E_LINK (0x8000)
6514 +
6515 +/* Bit definitions and macros for TCD3_CSR */
6516 +#define MCF_EDMA_TCD3_CSR_START (0x0001)
6517 +#define MCF_EDMA_TCD3_CSR_INT_MAJOR (0x0002)
6518 +#define MCF_EDMA_TCD3_CSR_INT_HALF (0x0004)
6519 +#define MCF_EDMA_TCD3_CSR_D_REQ (0x0008)
6520 +#define MCF_EDMA_TCD3_CSR_E_SG (0x0010)
6521 +#define MCF_EDMA_TCD3_CSR_E_LINK (0x0020)
6522 +#define MCF_EDMA_TCD3_CSR_ACTIVE (0x0040)
6523 +#define MCF_EDMA_TCD3_CSR_DONE (0x0080)
6524 +#define MCF_EDMA_TCD3_CSR_LINKCH(x) (((x)&0x003F)<<8)
6525 +#define MCF_EDMA_TCD3_CSR_BWC(x) (((x)&0x0003)<<14)
6526 +
6527 +/* Bit definitions and macros for TCD4_SADDR */
6528 +#define MCF_EDMA_TCD4_SADDR_SADDR(x) (x)
6529 +
6530 +/* Bit definitions and macros for TCD4_ATTR */
6531 +#define MCF_EDMA_TCD4_ATTR_DSIZE(x) (((x)&0x0007))
6532 +#define MCF_EDMA_TCD4_ATTR_DMOD(x) (((x)&0x001F)<<3)
6533 +#define MCF_EDMA_TCD4_ATTR_SSIZE(x) (((x)&0x0007)<<8)
6534 +#define MCF_EDMA_TCD4_ATTR_SMOD(x) (((x)&0x001F)<<11)
6535 +
6536 +/* Bit definitions and macros for TCD4_SOFF */
6537 +#define MCF_EDMA_TCD4_SOFF_SOFF(x) (x)
6538 +
6539 +/* Bit definitions and macros for TCD4_NBYTES */
6540 +#define MCF_EDMA_TCD4_NBYTES_NBYTES(x) (x)
6541 +
6542 +/* Bit definitions and macros for TCD4_SLAST */
6543 +#define MCF_EDMA_TCD4_SLAST_SLAST(x) (x)
6544 +
6545 +/* Bit definitions and macros for TCD4_DADDR */
6546 +#define MCF_EDMA_TCD4_DADDR_DADDR(x) (x)
6547 +
6548 +/* Bit definitions and macros for TCD4_CITER */
6549 +#define MCF_EDMA_TCD4_CITER_CITER(x) (((x)&0x7FFF))
6550 +#define MCF_EDMA_TCD4_CITER_E_LINK (0x8000)
6551 +
6552 +/* Bit definitions and macros for TCD4_CITER_ELINK */
6553 +#define MCF_EDMA_TCD4_CITER_ELINK_CITER(x) (((x)&0x01FF))
6554 +#define MCF_EDMA_TCD4_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6555 +#define MCF_EDMA_TCD4_CITER_ELINK_E_LINK (0x8000)
6556 +
6557 +/* Bit definitions and macros for TCD4_DOFF */
6558 +#define MCF_EDMA_TCD4_DOFF_DOFF(x) (x)
6559 +
6560 +/* Bit definitions and macros for TCD4_DLAST_SGA */
6561 +#define MCF_EDMA_TCD4_DLAST_SGA_DLAST_SGA(x) (x)
6562 +
6563 +/* Bit definitions and macros for TCD4_BITER */
6564 +#define MCF_EDMA_TCD4_BITER_BITER(x) (((x)&0x7FFF))
6565 +#define MCF_EDMA_TCD4_BITER_E_LINK (0x8000)
6566 +
6567 +/* Bit definitions and macros for TCD4_BITER_ELINK */
6568 +#define MCF_EDMA_TCD4_BITER_ELINK_BITER(x) (((x)&0x01FF))
6569 +#define MCF_EDMA_TCD4_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6570 +#define MCF_EDMA_TCD4_BITER_ELINK_E_LINK (0x8000)
6571 +
6572 +/* Bit definitions and macros for TCD4_CSR */
6573 +#define MCF_EDMA_TCD4_CSR_START (0x0001)
6574 +#define MCF_EDMA_TCD4_CSR_INT_MAJOR (0x0002)
6575 +#define MCF_EDMA_TCD4_CSR_INT_HALF (0x0004)
6576 +#define MCF_EDMA_TCD4_CSR_D_REQ (0x0008)
6577 +#define MCF_EDMA_TCD4_CSR_E_SG (0x0010)
6578 +#define MCF_EDMA_TCD4_CSR_E_LINK (0x0020)
6579 +#define MCF_EDMA_TCD4_CSR_ACTIVE (0x0040)
6580 +#define MCF_EDMA_TCD4_CSR_DONE (0x0080)
6581 +#define MCF_EDMA_TCD4_CSR_LINKCH(x) (((x)&0x003F)<<8)
6582 +#define MCF_EDMA_TCD4_CSR_BWC(x) (((x)&0x0003)<<14)
6583 +
6584 +/* Bit definitions and macros for TCD5_SADDR */
6585 +#define MCF_EDMA_TCD5_SADDR_SADDR(x) (x)
6586 +
6587 +/* Bit definitions and macros for TCD5_ATTR */
6588 +#define MCF_EDMA_TCD5_ATTR_DSIZE(x) (((x)&0x0007))
6589 +#define MCF_EDMA_TCD5_ATTR_DMOD(x) (((x)&0x001F)<<3)
6590 +#define MCF_EDMA_TCD5_ATTR_SSIZE(x) (((x)&0x0007)<<8)
6591 +#define MCF_EDMA_TCD5_ATTR_SMOD(x) (((x)&0x001F)<<11)
6592 +
6593 +/* Bit definitions and macros for TCD5_SOFF */
6594 +#define MCF_EDMA_TCD5_SOFF_SOFF(x) (x)
6595 +
6596 +/* Bit definitions and macros for TCD5_NBYTES */
6597 +#define MCF_EDMA_TCD5_NBYTES_NBYTES(x) (x)
6598 +
6599 +/* Bit definitions and macros for TCD5_SLAST */
6600 +#define MCF_EDMA_TCD5_SLAST_SLAST(x) (x)
6601 +
6602 +/* Bit definitions and macros for TCD5_DADDR */
6603 +#define MCF_EDMA_TCD5_DADDR_DADDR(x) (x)
6604 +
6605 +/* Bit definitions and macros for TCD5_CITER */
6606 +#define MCF_EDMA_TCD5_CITER_CITER(x) (((x)&0x7FFF))
6607 +#define MCF_EDMA_TCD5_CITER_E_LINK (0x8000)
6608 +
6609 +/* Bit definitions and macros for TCD5_CITER_ELINK */
6610 +#define MCF_EDMA_TCD5_CITER_ELINK_CITER(x) (((x)&0x01FF))
6611 +#define MCF_EDMA_TCD5_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6612 +#define MCF_EDMA_TCD5_CITER_ELINK_E_LINK (0x8000)
6613 +
6614 +/* Bit definitions and macros for TCD5_DOFF */
6615 +#define MCF_EDMA_TCD5_DOFF_DOFF(x) (x)
6616 +
6617 +/* Bit definitions and macros for TCD5_DLAST_SGA */
6618 +#define MCF_EDMA_TCD5_DLAST_SGA_DLAST_SGA(x) (x)
6619 +
6620 +/* Bit definitions and macros for TCD5_BITER_ELINK */
6621 +#define MCF_EDMA_TCD5_BITER_ELINK_BITER(x) (((x)&0x01FF))
6622 +#define MCF_EDMA_TCD5_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6623 +#define MCF_EDMA_TCD5_BITER_ELINK_E_LINK (0x8000)
6624 +
6625 +/* Bit definitions and macros for TCD5_BITER */
6626 +#define MCF_EDMA_TCD5_BITER_BITER(x) (((x)&0x7FFF))
6627 +#define MCF_EDMA_TCD5_BITER_E_LINK (0x8000)
6628 +
6629 +/* Bit definitions and macros for TCD5_CSR */
6630 +#define MCF_EDMA_TCD5_CSR_START (0x0001)
6631 +#define MCF_EDMA_TCD5_CSR_INT_MAJOR (0x0002)
6632 +#define MCF_EDMA_TCD5_CSR_INT_HALF (0x0004)
6633 +#define MCF_EDMA_TCD5_CSR_D_REQ (0x0008)
6634 +#define MCF_EDMA_TCD5_CSR_E_SG (0x0010)
6635 +#define MCF_EDMA_TCD5_CSR_E_LINK (0x0020)
6636 +#define MCF_EDMA_TCD5_CSR_ACTIVE (0x0040)
6637 +#define MCF_EDMA_TCD5_CSR_DONE (0x0080)
6638 +#define MCF_EDMA_TCD5_CSR_LINKCH(x) (((x)&0x003F)<<8)
6639 +#define MCF_EDMA_TCD5_CSR_BWC(x) (((x)&0x0003)<<14)
6640 +
6641 +/* Bit definitions and macros for TCD6_SADDR */
6642 +#define MCF_EDMA_TCD6_SADDR_SADDR(x) (x)
6643 +
6644 +/* Bit definitions and macros for TCD6_ATTR */
6645 +#define MCF_EDMA_TCD6_ATTR_DSIZE(x) (((x)&0x0007))
6646 +#define MCF_EDMA_TCD6_ATTR_DMOD(x) (((x)&0x001F)<<3)
6647 +#define MCF_EDMA_TCD6_ATTR_SSIZE(x) (((x)&0x0007)<<8)
6648 +#define MCF_EDMA_TCD6_ATTR_SMOD(x) (((x)&0x001F)<<11)
6649 +
6650 +/* Bit definitions and macros for TCD6_SOFF */
6651 +#define MCF_EDMA_TCD6_SOFF_SOFF(x) (x)
6652 +
6653 +/* Bit definitions and macros for TCD6_NBYTES */
6654 +#define MCF_EDMA_TCD6_NBYTES_NBYTES(x) (x)
6655 +
6656 +/* Bit definitions and macros for TCD6_SLAST */
6657 +#define MCF_EDMA_TCD6_SLAST_SLAST(x) (x)
6658 +
6659 +/* Bit definitions and macros for TCD6_DADDR */
6660 +#define MCF_EDMA_TCD6_DADDR_DADDR(x) (x)
6661 +
6662 +/* Bit definitions and macros for TCD6_CITER */
6663 +#define MCF_EDMA_TCD6_CITER_CITER(x) (((x)&0x7FFF))
6664 +#define MCF_EDMA_TCD6_CITER_E_LINK (0x8000)
6665 +
6666 +/* Bit definitions and macros for TCD6_CITER_ELINK */
6667 +#define MCF_EDMA_TCD6_CITER_ELINK_CITER(x) (((x)&0x01FF))
6668 +#define MCF_EDMA_TCD6_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6669 +#define MCF_EDMA_TCD6_CITER_ELINK_E_LINK (0x8000)
6670 +
6671 +/* Bit definitions and macros for TCD6_DOFF */
6672 +#define MCF_EDMA_TCD6_DOFF_DOFF(x) (x)
6673 +
6674 +/* Bit definitions and macros for TCD6_DLAST_SGA */
6675 +#define MCF_EDMA_TCD6_DLAST_SGA_DLAST_SGA(x) (x)
6676 +
6677 +/* Bit definitions and macros for TCD6_BITER_ELINK */
6678 +#define MCF_EDMA_TCD6_BITER_ELINK_BITER(x) (((x)&0x01FF))
6679 +#define MCF_EDMA_TCD6_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6680 +#define MCF_EDMA_TCD6_BITER_ELINK_E_LINK (0x8000)
6681 +
6682 +/* Bit definitions and macros for TCD6_BITER */
6683 +#define MCF_EDMA_TCD6_BITER_BITER(x) (((x)&0x7FFF))
6684 +#define MCF_EDMA_TCD6_BITER_E_LINK (0x8000)
6685 +
6686 +/* Bit definitions and macros for TCD6_CSR */
6687 +#define MCF_EDMA_TCD6_CSR_START (0x0001)
6688 +#define MCF_EDMA_TCD6_CSR_INT_MAJOR (0x0002)
6689 +#define MCF_EDMA_TCD6_CSR_INT_HALF (0x0004)
6690 +#define MCF_EDMA_TCD6_CSR_D_REQ (0x0008)
6691 +#define MCF_EDMA_TCD6_CSR_E_SG (0x0010)
6692 +#define MCF_EDMA_TCD6_CSR_E_LINK (0x0020)
6693 +#define MCF_EDMA_TCD6_CSR_ACTIVE (0x0040)
6694 +#define MCF_EDMA_TCD6_CSR_DONE (0x0080)
6695 +#define MCF_EDMA_TCD6_CSR_LINKCH(x) (((x)&0x003F)<<8)
6696 +#define MCF_EDMA_TCD6_CSR_BWC(x) (((x)&0x0003)<<14)
6697 +
6698 +/* Bit definitions and macros for TCD7_SADDR */
6699 +#define MCF_EDMA_TCD7_SADDR_SADDR(x) (x)
6700 +
6701 +/* Bit definitions and macros for TCD7_ATTR */
6702 +#define MCF_EDMA_TCD7_ATTR_DSIZE(x) (((x)&0x0007))
6703 +#define MCF_EDMA_TCD7_ATTR_DMOD(x) (((x)&0x001F)<<3)
6704 +#define MCF_EDMA_TCD7_ATTR_SSIZE(x) (((x)&0x0007)<<8)
6705 +#define MCF_EDMA_TCD7_ATTR_SMOD(x) (((x)&0x001F)<<11)
6706 +
6707 +/* Bit definitions and macros for TCD7_SOFF */
6708 +#define MCF_EDMA_TCD7_SOFF_SOFF(x) (x)
6709 +
6710 +/* Bit definitions and macros for TCD7_NBYTES */
6711 +#define MCF_EDMA_TCD7_NBYTES_NBYTES(x) (x)
6712 +
6713 +/* Bit definitions and macros for TCD7_SLAST */
6714 +#define MCF_EDMA_TCD7_SLAST_SLAST(x) (x)
6715 +
6716 +/* Bit definitions and macros for TCD7_DADDR */
6717 +#define MCF_EDMA_TCD7_DADDR_DADDR(x) (x)
6718 +
6719 +/* Bit definitions and macros for TCD7_CITER */
6720 +#define MCF_EDMA_TCD7_CITER_CITER(x) (((x)&0x7FFF))
6721 +#define MCF_EDMA_TCD7_CITER_E_LINK (0x8000)
6722 +
6723 +/* Bit definitions and macros for TCD7_CITER_ELINK */
6724 +#define MCF_EDMA_TCD7_CITER_ELINK_CITER(x) (((x)&0x01FF))
6725 +#define MCF_EDMA_TCD7_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6726 +#define MCF_EDMA_TCD7_CITER_ELINK_E_LINK (0x8000)
6727 +
6728 +/* Bit definitions and macros for TCD7_DOFF */
6729 +#define MCF_EDMA_TCD7_DOFF_DOFF(x) (x)
6730 +
6731 +/* Bit definitions and macros for TCD7_DLAST_SGA */
6732 +#define MCF_EDMA_TCD7_DLAST_SGA_DLAST_SGA(x) (x)
6733 +
6734 +/* Bit definitions and macros for TCD7_BITER_ELINK */
6735 +#define MCF_EDMA_TCD7_BITER_ELINK_BITER(x) (((x)&0x01FF))
6736 +#define MCF_EDMA_TCD7_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6737 +#define MCF_EDMA_TCD7_BITER_ELINK_E_LINK (0x8000)
6738 +
6739 +/* Bit definitions and macros for TCD7_BITER */
6740 +#define MCF_EDMA_TCD7_BITER_BITER(x) (((x)&0x7FFF))
6741 +#define MCF_EDMA_TCD7_BITER_E_LINK (0x8000)
6742 +
6743 +/* Bit definitions and macros for TCD7_CSR */
6744 +#define MCF_EDMA_TCD7_CSR_START (0x0001)
6745 +#define MCF_EDMA_TCD7_CSR_INT_MAJOR (0x0002)
6746 +#define MCF_EDMA_TCD7_CSR_INT_HALF (0x0004)
6747 +#define MCF_EDMA_TCD7_CSR_D_REQ (0x0008)
6748 +#define MCF_EDMA_TCD7_CSR_E_SG (0x0010)
6749 +#define MCF_EDMA_TCD7_CSR_E_LINK (0x0020)
6750 +#define MCF_EDMA_TCD7_CSR_ACTIVE (0x0040)
6751 +#define MCF_EDMA_TCD7_CSR_DONE (0x0080)
6752 +#define MCF_EDMA_TCD7_CSR_LINKCH(x) (((x)&0x003F)<<8)
6753 +#define MCF_EDMA_TCD7_CSR_BWC(x) (((x)&0x0003)<<14)
6754 +
6755 +/* Bit definitions and macros for TCD8_SADDR */
6756 +#define MCF_EDMA_TCD8_SADDR_SADDR(x) (x)
6757 +
6758 +/* Bit definitions and macros for TCD8_ATTR */
6759 +#define MCF_EDMA_TCD8_ATTR_DSIZE(x) (((x)&0x0007))
6760 +#define MCF_EDMA_TCD8_ATTR_DMOD(x) (((x)&0x001F)<<3)
6761 +#define MCF_EDMA_TCD8_ATTR_SSIZE(x) (((x)&0x0007)<<8)
6762 +#define MCF_EDMA_TCD8_ATTR_SMOD(x) (((x)&0x001F)<<11)
6763 +
6764 +/* Bit definitions and macros for TCD8_SOFF */
6765 +#define MCF_EDMA_TCD8_SOFF_SOFF(x) (x)
6766 +
6767 +/* Bit definitions and macros for TCD8_NBYTES */
6768 +#define MCF_EDMA_TCD8_NBYTES_NBYTES(x) (x)
6769 +
6770 +/* Bit definitions and macros for TCD8_SLAST */
6771 +#define MCF_EDMA_TCD8_SLAST_SLAST(x) (x)
6772 +
6773 +/* Bit definitions and macros for TCD8_DADDR */
6774 +#define MCF_EDMA_TCD8_DADDR_DADDR(x) (x)
6775 +
6776 +/* Bit definitions and macros for TCD8_CITER */
6777 +#define MCF_EDMA_TCD8_CITER_CITER(x) (((x)&0x7FFF))
6778 +#define MCF_EDMA_TCD8_CITER_E_LINK (0x8000)
6779 +
6780 +/* Bit definitions and macros for TCD8_CITER_ELINK */
6781 +#define MCF_EDMA_TCD8_CITER_ELINK_CITER(x) (((x)&0x01FF))
6782 +#define MCF_EDMA_TCD8_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6783 +#define MCF_EDMA_TCD8_CITER_ELINK_E_LINK (0x8000)
6784 +
6785 +/* Bit definitions and macros for TCD8_DOFF */
6786 +#define MCF_EDMA_TCD8_DOFF_DOFF(x) (x)
6787 +
6788 +/* Bit definitions and macros for TCD8_DLAST_SGA */
6789 +#define MCF_EDMA_TCD8_DLAST_SGA_DLAST_SGA(x) (x)
6790 +
6791 +/* Bit definitions and macros for TCD8_BITER_ELINK */
6792 +#define MCF_EDMA_TCD8_BITER_ELINK_BITER(x) (((x)&0x01FF))
6793 +#define MCF_EDMA_TCD8_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6794 +#define MCF_EDMA_TCD8_BITER_ELINK_E_LINK (0x8000)
6795 +
6796 +/* Bit definitions and macros for TCD8_BITER */
6797 +#define MCF_EDMA_TCD8_BITER_BITER(x) (((x)&0x7FFF))
6798 +#define MCF_EDMA_TCD8_BITER_E_LINK (0x8000)
6799 +
6800 +/* Bit definitions and macros for TCD8_CSR */
6801 +#define MCF_EDMA_TCD8_CSR_START (0x0001)
6802 +#define MCF_EDMA_TCD8_CSR_INT_MAJOR (0x0002)
6803 +#define MCF_EDMA_TCD8_CSR_INT_HALF (0x0004)
6804 +#define MCF_EDMA_TCD8_CSR_D_REQ (0x0008)
6805 +#define MCF_EDMA_TCD8_CSR_E_SG (0x0010)
6806 +#define MCF_EDMA_TCD8_CSR_E_LINK (0x0020)
6807 +#define MCF_EDMA_TCD8_CSR_ACTIVE (0x0040)
6808 +#define MCF_EDMA_TCD8_CSR_DONE (0x0080)
6809 +#define MCF_EDMA_TCD8_CSR_LINKCH(x) (((x)&0x003F)<<8)
6810 +#define MCF_EDMA_TCD8_CSR_BWC(x) (((x)&0x0003)<<14)
6811 +
6812 +/* Bit definitions and macros for TCD9_SADDR */
6813 +#define MCF_EDMA_TCD9_SADDR_SADDR(x) (x)
6814 +
6815 +/* Bit definitions and macros for TCD9_ATTR */
6816 +#define MCF_EDMA_TCD9_ATTR_DSIZE(x) (((x)&0x0007))
6817 +#define MCF_EDMA_TCD9_ATTR_DMOD(x) (((x)&0x001F)<<3)
6818 +#define MCF_EDMA_TCD9_ATTR_SSIZE(x) (((x)&0x0007)<<8)
6819 +#define MCF_EDMA_TCD9_ATTR_SMOD(x) (((x)&0x001F)<<11)
6820 +
6821 +/* Bit definitions and macros for TCD9_SOFF */
6822 +#define MCF_EDMA_TCD9_SOFF_SOFF(x) (x)
6823 +
6824 +/* Bit definitions and macros for TCD9_NBYTES */
6825 +#define MCF_EDMA_TCD9_NBYTES_NBYTES(x) (x)
6826 +
6827 +/* Bit definitions and macros for TCD9_SLAST */
6828 +#define MCF_EDMA_TCD9_SLAST_SLAST(x) (x)
6829 +
6830 +/* Bit definitions and macros for TCD9_DADDR */
6831 +#define MCF_EDMA_TCD9_DADDR_DADDR(x) (x)
6832 +
6833 +/* Bit definitions and macros for TCD9_CITER_ELINK */
6834 +#define MCF_EDMA_TCD9_CITER_ELINK_CITER(x) (((x)&0x01FF))
6835 +#define MCF_EDMA_TCD9_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6836 +#define MCF_EDMA_TCD9_CITER_ELINK_E_LINK (0x8000)
6837 +
6838 +/* Bit definitions and macros for TCD9_CITER */
6839 +#define MCF_EDMA_TCD9_CITER_CITER(x) (((x)&0x7FFF))
6840 +#define MCF_EDMA_TCD9_CITER_E_LINK (0x8000)
6841 +
6842 +/* Bit definitions and macros for TCD9_DOFF */
6843 +#define MCF_EDMA_TCD9_DOFF_DOFF(x) (x)
6844 +
6845 +/* Bit definitions and macros for TCD9_DLAST_SGA */
6846 +#define MCF_EDMA_TCD9_DLAST_SGA_DLAST_SGA(x) (x)
6847 +
6848 +/* Bit definitions and macros for TCD9_BITER_ELINK */
6849 +#define MCF_EDMA_TCD9_BITER_ELINK_BITER(x) (((x)&0x01FF))
6850 +#define MCF_EDMA_TCD9_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6851 +#define MCF_EDMA_TCD9_BITER_ELINK_E_LINK (0x8000)
6852 +
6853 +/* Bit definitions and macros for TCD9_BITER */
6854 +#define MCF_EDMA_TCD9_BITER_BITER(x) (((x)&0x7FFF))
6855 +#define MCF_EDMA_TCD9_BITER_E_LINK (0x8000)
6856 +
6857 +/* Bit definitions and macros for TCD9_CSR */
6858 +#define MCF_EDMA_TCD9_CSR_START (0x0001)
6859 +#define MCF_EDMA_TCD9_CSR_INT_MAJOR (0x0002)
6860 +#define MCF_EDMA_TCD9_CSR_INT_HALF (0x0004)
6861 +#define MCF_EDMA_TCD9_CSR_D_REQ (0x0008)
6862 +#define MCF_EDMA_TCD9_CSR_E_SG (0x0010)
6863 +#define MCF_EDMA_TCD9_CSR_E_LINK (0x0020)
6864 +#define MCF_EDMA_TCD9_CSR_ACTIVE (0x0040)
6865 +#define MCF_EDMA_TCD9_CSR_DONE (0x0080)
6866 +#define MCF_EDMA_TCD9_CSR_LINKCH(x) (((x)&0x003F)<<8)
6867 +#define MCF_EDMA_TCD9_CSR_BWC(x) (((x)&0x0003)<<14)
6868 +
6869 +/* Bit definitions and macros for TCD10_SADDR */
6870 +#define MCF_EDMA_TCD10_SADDR_SADDR(x) (x)
6871 +
6872 +/* Bit definitions and macros for TCD10_ATTR */
6873 +#define MCF_EDMA_TCD10_ATTR_DSIZE(x) (((x)&0x0007))
6874 +#define MCF_EDMA_TCD10_ATTR_DMOD(x) (((x)&0x001F)<<3)
6875 +#define MCF_EDMA_TCD10_ATTR_SSIZE(x) (((x)&0x0007)<<8)
6876 +#define MCF_EDMA_TCD10_ATTR_SMOD(x) (((x)&0x001F)<<11)
6877 +
6878 +/* Bit definitions and macros for TCD10_SOFF */
6879 +#define MCF_EDMA_TCD10_SOFF_SOFF(x) (x)
6880 +
6881 +/* Bit definitions and macros for TCD10_NBYTES */
6882 +#define MCF_EDMA_TCD10_NBYTES_NBYTES(x) (x)
6883 +
6884 +/* Bit definitions and macros for TCD10_SLAST */
6885 +#define MCF_EDMA_TCD10_SLAST_SLAST(x) (x)
6886 +
6887 +/* Bit definitions and macros for TCD10_DADDR */
6888 +#define MCF_EDMA_TCD10_DADDR_DADDR(x) (x)
6889 +
6890 +/* Bit definitions and macros for TCD10_CITER_ELINK */
6891 +#define MCF_EDMA_TCD10_CITER_ELINK_CITER(x) (((x)&0x01FF))
6892 +#define MCF_EDMA_TCD10_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6893 +#define MCF_EDMA_TCD10_CITER_ELINK_E_LINK (0x8000)
6894 +
6895 +/* Bit definitions and macros for TCD10_CITER */
6896 +#define MCF_EDMA_TCD10_CITER_CITER(x) (((x)&0x7FFF))
6897 +#define MCF_EDMA_TCD10_CITER_E_LINK (0x8000)
6898 +
6899 +/* Bit definitions and macros for TCD10_DOFF */
6900 +#define MCF_EDMA_TCD10_DOFF_DOFF(x) (x)
6901 +
6902 +/* Bit definitions and macros for TCD10_DLAST_SGA */
6903 +#define MCF_EDMA_TCD10_DLAST_SGA_DLAST_SGA(x) (x)
6904 +
6905 +/* Bit definitions and macros for TCD10_BITER */
6906 +#define MCF_EDMA_TCD10_BITER_BITER(x) (((x)&0x7FFF))
6907 +#define MCF_EDMA_TCD10_BITER_E_LINK (0x8000)
6908 +
6909 +/* Bit definitions and macros for TCD10_BITER_ELINK */
6910 +#define MCF_EDMA_TCD10_BITER_ELINK_BITER(x) (((x)&0x01FF))
6911 +#define MCF_EDMA_TCD10_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6912 +#define MCF_EDMA_TCD10_BITER_ELINK_E_LINK (0x8000)
6913 +
6914 +/* Bit definitions and macros for TCD10_CSR */
6915 +#define MCF_EDMA_TCD10_CSR_START (0x0001)
6916 +#define MCF_EDMA_TCD10_CSR_INT_MAJOR (0x0002)
6917 +#define MCF_EDMA_TCD10_CSR_INT_HALF (0x0004)
6918 +#define MCF_EDMA_TCD10_CSR_D_REQ (0x0008)
6919 +#define MCF_EDMA_TCD10_CSR_E_SG (0x0010)
6920 +#define MCF_EDMA_TCD10_CSR_E_LINK (0x0020)
6921 +#define MCF_EDMA_TCD10_CSR_ACTIVE (0x0040)
6922 +#define MCF_EDMA_TCD10_CSR_DONE (0x0080)
6923 +#define MCF_EDMA_TCD10_CSR_LINKCH(x) (((x)&0x003F)<<8)
6924 +#define MCF_EDMA_TCD10_CSR_BWC(x) (((x)&0x0003)<<14)
6925 +
6926 +/* Bit definitions and macros for TCD11_SADDR */
6927 +#define MCF_EDMA_TCD11_SADDR_SADDR(x) (x)
6928 +
6929 +/* Bit definitions and macros for TCD11_ATTR */
6930 +#define MCF_EDMA_TCD11_ATTR_DSIZE(x) (((x)&0x0007))
6931 +#define MCF_EDMA_TCD11_ATTR_DMOD(x) (((x)&0x001F)<<3)
6932 +#define MCF_EDMA_TCD11_ATTR_SSIZE(x) (((x)&0x0007)<<8)
6933 +#define MCF_EDMA_TCD11_ATTR_SMOD(x) (((x)&0x001F)<<11)
6934 +
6935 +/* Bit definitions and macros for TCD11_SOFF */
6936 +#define MCF_EDMA_TCD11_SOFF_SOFF(x) (x)
6937 +
6938 +/* Bit definitions and macros for TCD11_NBYTES */
6939 +#define MCF_EDMA_TCD11_NBYTES_NBYTES(x) (x)
6940 +
6941 +/* Bit definitions and macros for TCD11_SLAST */
6942 +#define MCF_EDMA_TCD11_SLAST_SLAST(x) (x)
6943 +
6944 +/* Bit definitions and macros for TCD11_DADDR */
6945 +#define MCF_EDMA_TCD11_DADDR_DADDR(x) (x)
6946 +
6947 +/* Bit definitions and macros for TCD11_CITER */
6948 +#define MCF_EDMA_TCD11_CITER_CITER(x) (((x)&0x7FFF))
6949 +#define MCF_EDMA_TCD11_CITER_E_LINK (0x8000)
6950 +
6951 +/* Bit definitions and macros for TCD11_CITER_ELINK */
6952 +#define MCF_EDMA_TCD11_CITER_ELINK_CITER(x) (((x)&0x01FF))
6953 +#define MCF_EDMA_TCD11_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6954 +#define MCF_EDMA_TCD11_CITER_ELINK_E_LINK (0x8000)
6955 +
6956 +/* Bit definitions and macros for TCD11_DOFF */
6957 +#define MCF_EDMA_TCD11_DOFF_DOFF(x) (x)
6958 +
6959 +/* Bit definitions and macros for TCD11_DLAST_SGA */
6960 +#define MCF_EDMA_TCD11_DLAST_SGA_DLAST_SGA(x) (x)
6961 +
6962 +/* Bit definitions and macros for TCD11_BITER */
6963 +#define MCF_EDMA_TCD11_BITER_BITER(x) (((x)&0x7FFF))
6964 +#define MCF_EDMA_TCD11_BITER_E_LINK (0x8000)
6965 +
6966 +/* Bit definitions and macros for TCD11_BITER_ELINK */
6967 +#define MCF_EDMA_TCD11_BITER_ELINK_BITER(x) (((x)&0x01FF))
6968 +#define MCF_EDMA_TCD11_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
6969 +#define MCF_EDMA_TCD11_BITER_ELINK_E_LINK (0x8000)
6970 +
6971 +/* Bit definitions and macros for TCD11_CSR */
6972 +#define MCF_EDMA_TCD11_CSR_START (0x0001)
6973 +#define MCF_EDMA_TCD11_CSR_INT_MAJOR (0x0002)
6974 +#define MCF_EDMA_TCD11_CSR_INT_HALF (0x0004)
6975 +#define MCF_EDMA_TCD11_CSR_D_REQ (0x0008)
6976 +#define MCF_EDMA_TCD11_CSR_E_SG (0x0010)
6977 +#define MCF_EDMA_TCD11_CSR_E_LINK (0x0020)
6978 +#define MCF_EDMA_TCD11_CSR_ACTIVE (0x0040)
6979 +#define MCF_EDMA_TCD11_CSR_DONE (0x0080)
6980 +#define MCF_EDMA_TCD11_CSR_LINKCH(x) (((x)&0x003F)<<8)
6981 +#define MCF_EDMA_TCD11_CSR_BWC(x) (((x)&0x0003)<<14)
6982 +
6983 +/* Bit definitions and macros for TCD12_SADDR */
6984 +#define MCF_EDMA_TCD12_SADDR_SADDR(x) (x)
6985 +
6986 +/* Bit definitions and macros for TCD12_ATTR */
6987 +#define MCF_EDMA_TCD12_ATTR_DSIZE(x) (((x)&0x0007))
6988 +#define MCF_EDMA_TCD12_ATTR_DMOD(x) (((x)&0x001F)<<3)
6989 +#define MCF_EDMA_TCD12_ATTR_SSIZE(x) (((x)&0x0007)<<8)
6990 +#define MCF_EDMA_TCD12_ATTR_SMOD(x) (((x)&0x001F)<<11)
6991 +
6992 +/* Bit definitions and macros for TCD12_SOFF */
6993 +#define MCF_EDMA_TCD12_SOFF_SOFF(x) (x)
6994 +
6995 +/* Bit definitions and macros for TCD12_NBYTES */
6996 +#define MCF_EDMA_TCD12_NBYTES_NBYTES(x) (x)
6997 +
6998 +/* Bit definitions and macros for TCD12_SLAST */
6999 +#define MCF_EDMA_TCD12_SLAST_SLAST(x) (x)
7000 +
7001 +/* Bit definitions and macros for TCD12_DADDR */
7002 +#define MCF_EDMA_TCD12_DADDR_DADDR(x) (x)
7003 +
7004 +/* Bit definitions and macros for TCD12_CITER */
7005 +#define MCF_EDMA_TCD12_CITER_CITER(x) (((x)&0x7FFF))
7006 +#define MCF_EDMA_TCD12_CITER_E_LINK (0x8000)
7007 +
7008 +/* Bit definitions and macros for TCD12_CITER_ELINK */
7009 +#define MCF_EDMA_TCD12_CITER_ELINK_CITER(x) (((x)&0x01FF))
7010 +#define MCF_EDMA_TCD12_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
7011 +#define MCF_EDMA_TCD12_CITER_ELINK_E_LINK (0x8000)
7012 +
7013 +/* Bit definitions and macros for TCD12_DOFF */
7014 +#define MCF_EDMA_TCD12_DOFF_DOFF(x) (x)
7015 +
7016 +/* Bit definitions and macros for TCD12_DLAST_SGA */
7017 +#define MCF_EDMA_TCD12_DLAST_SGA_DLAST_SGA(x) (x)
7018 +
7019 +/* Bit definitions and macros for TCD12_BITER */
7020 +#define MCF_EDMA_TCD12_BITER_BITER(x) (((x)&0x7FFF))
7021 +#define MCF_EDMA_TCD12_BITER_E_LINK (0x8000)
7022 +
7023 +/* Bit definitions and macros for TCD12_BITER_ELINK */
7024 +#define MCF_EDMA_TCD12_BITER_ELINK_BITER(x) (((x)&0x01FF))
7025 +#define MCF_EDMA_TCD12_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
7026 +#define MCF_EDMA_TCD12_BITER_ELINK_E_LINK (0x8000)
7027 +
7028 +/* Bit definitions and macros for TCD12_CSR */
7029 +#define MCF_EDMA_TCD12_CSR_START (0x0001)
7030 +#define MCF_EDMA_TCD12_CSR_INT_MAJOR (0x0002)
7031 +#define MCF_EDMA_TCD12_CSR_INT_HALF (0x0004)
7032 +#define MCF_EDMA_TCD12_CSR_D_REQ (0x0008)
7033 +#define MCF_EDMA_TCD12_CSR_E_SG (0x0010)
7034 +#define MCF_EDMA_TCD12_CSR_E_LINK (0x0020)
7035 +#define MCF_EDMA_TCD12_CSR_ACTIVE (0x0040)
7036 +#define MCF_EDMA_TCD12_CSR_DONE (0x0080)
7037 +#define MCF_EDMA_TCD12_CSR_LINKCH(x) (((x)&0x003F)<<8)
7038 +#define MCF_EDMA_TCD12_CSR_BWC(x) (((x)&0x0003)<<14)
7039 +
7040 +/* Bit definitions and macros for TCD13_SADDR */
7041 +#define MCF_EDMA_TCD13_SADDR_SADDR(x) (x)
7042 +
7043 +/* Bit definitions and macros for TCD13_ATTR */
7044 +#define MCF_EDMA_TCD13_ATTR_DSIZE(x) (((x)&0x0007))
7045 +#define MCF_EDMA_TCD13_ATTR_DMOD(x) (((x)&0x001F)<<3)
7046 +#define MCF_EDMA_TCD13_ATTR_SSIZE(x) (((x)&0x0007)<<8)
7047 +#define MCF_EDMA_TCD13_ATTR_SMOD(x) (((x)&0x001F)<<11)
7048 +
7049 +/* Bit definitions and macros for TCD13_SOFF */
7050 +#define MCF_EDMA_TCD13_SOFF_SOFF(x) (x)
7051 +
7052 +/* Bit definitions and macros for TCD13_NBYTES */
7053 +#define MCF_EDMA_TCD13_NBYTES_NBYTES(x) (x)
7054 +
7055 +/* Bit definitions and macros for TCD13_SLAST */
7056 +#define MCF_EDMA_TCD13_SLAST_SLAST(x) (x)
7057 +
7058 +/* Bit definitions and macros for TCD13_DADDR */
7059 +#define MCF_EDMA_TCD13_DADDR_DADDR(x) (x)
7060 +
7061 +/* Bit definitions and macros for TCD13_CITER_ELINK */
7062 +#define MCF_EDMA_TCD13_CITER_ELINK_CITER(x) (((x)&0x01FF))
7063 +#define MCF_EDMA_TCD13_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
7064 +#define MCF_EDMA_TCD13_CITER_ELINK_E_LINK (0x8000)
7065 +
7066 +/* Bit definitions and macros for TCD13_CITER */
7067 +#define MCF_EDMA_TCD13_CITER_CITER(x) (((x)&0x7FFF))
7068 +#define MCF_EDMA_TCD13_CITER_E_LINK (0x8000)
7069 +
7070 +/* Bit definitions and macros for TCD13_DOFF */
7071 +#define MCF_EDMA_TCD13_DOFF_DOFF(x) (x)
7072 +
7073 +/* Bit definitions and macros for TCD13_DLAST_SGA */
7074 +#define MCF_EDMA_TCD13_DLAST_SGA_DLAST_SGA(x) (x)
7075 +
7076 +/* Bit definitions and macros for TCD13_BITER_ELINK */
7077 +#define MCF_EDMA_TCD13_BITER_ELINK_BITER(x) (((x)&0x01FF))
7078 +#define MCF_EDMA_TCD13_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
7079 +#define MCF_EDMA_TCD13_BITER_ELINK_E_LINK (0x8000)
7080 +
7081 +/* Bit definitions and macros for TCD13_BITER */
7082 +#define MCF_EDMA_TCD13_BITER_BITER(x) (((x)&0x7FFF))
7083 +#define MCF_EDMA_TCD13_BITER_E_LINK (0x8000)
7084 +
7085 +/* Bit definitions and macros for TCD13_CSR */
7086 +#define MCF_EDMA_TCD13_CSR_START (0x0001)
7087 +#define MCF_EDMA_TCD13_CSR_INT_MAJOR (0x0002)
7088 +#define MCF_EDMA_TCD13_CSR_INT_HALF (0x0004)
7089 +#define MCF_EDMA_TCD13_CSR_D_REQ (0x0008)
7090 +#define MCF_EDMA_TCD13_CSR_E_SG (0x0010)
7091 +#define MCF_EDMA_TCD13_CSR_E_LINK (0x0020)
7092 +#define MCF_EDMA_TCD13_CSR_ACTIVE (0x0040)
7093 +#define MCF_EDMA_TCD13_CSR_DONE (0x0080)
7094 +#define MCF_EDMA_TCD13_CSR_LINKCH(x) (((x)&0x003F)<<8)
7095 +#define MCF_EDMA_TCD13_CSR_BWC(x) (((x)&0x0003)<<14)
7096 +
7097 +/* Bit definitions and macros for TCD14_SADDR */
7098 +#define MCF_EDMA_TCD14_SADDR_SADDR(x) (x)
7099 +
7100 +/* Bit definitions and macros for TCD14_ATTR */
7101 +#define MCF_EDMA_TCD14_ATTR_DSIZE(x) (((x)&0x0007))
7102 +#define MCF_EDMA_TCD14_ATTR_DMOD(x) (((x)&0x001F)<<3)
7103 +#define MCF_EDMA_TCD14_ATTR_SSIZE(x) (((x)&0x0007)<<8)
7104 +#define MCF_EDMA_TCD14_ATTR_SMOD(x) (((x)&0x001F)<<11)
7105 +
7106 +/* Bit definitions and macros for TCD14_SOFF */
7107 +#define MCF_EDMA_TCD14_SOFF_SOFF(x) (x)
7108 +
7109 +/* Bit definitions and macros for TCD14_NBYTES */
7110 +#define MCF_EDMA_TCD14_NBYTES_NBYTES(x) (x)
7111 +
7112 +/* Bit definitions and macros for TCD14_SLAST */
7113 +#define MCF_EDMA_TCD14_SLAST_SLAST(x) (x)
7114 +
7115 +/* Bit definitions and macros for TCD14_DADDR */
7116 +#define MCF_EDMA_TCD14_DADDR_DADDR(x) (x)
7117 +
7118 +/* Bit definitions and macros for TCD14_CITER */
7119 +#define MCF_EDMA_TCD14_CITER_CITER(x) (((x)&0x7FFF))
7120 +#define MCF_EDMA_TCD14_CITER_E_LINK (0x8000)
7121 +
7122 +/* Bit definitions and macros for TCD14_CITER_ELINK */
7123 +#define MCF_EDMA_TCD14_CITER_ELINK_CITER(x) (((x)&0x01FF))
7124 +#define MCF_EDMA_TCD14_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
7125 +#define MCF_EDMA_TCD14_CITER_ELINK_E_LINK (0x8000)
7126 +
7127 +/* Bit definitions and macros for TCD14_DOFF */
7128 +#define MCF_EDMA_TCD14_DOFF_DOFF(x) (x)
7129 +
7130 +/* Bit definitions and macros for TCD14_DLAST_SGA */
7131 +#define MCF_EDMA_TCD14_DLAST_SGA_DLAST_SGA(x) (x)
7132 +
7133 +/* Bit definitions and macros for TCD14_BITER_ELINK */
7134 +#define MCF_EDMA_TCD14_BITER_ELINK_BITER(x) (((x)&0x01FF))
7135 +#define MCF_EDMA_TCD14_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
7136 +#define MCF_EDMA_TCD14_BITER_ELINK_E_LINK (0x8000)
7137 +
7138 +/* Bit definitions and macros for TCD14_BITER */
7139 +#define MCF_EDMA_TCD14_BITER_BITER(x) (((x)&0x7FFF))
7140 +#define MCF_EDMA_TCD14_BITER_E_LINK (0x8000)
7141 +
7142 +/* Bit definitions and macros for TCD14_CSR */
7143 +#define MCF_EDMA_TCD14_CSR_START (0x0001)
7144 +#define MCF_EDMA_TCD14_CSR_INT_MAJOR (0x0002)
7145 +#define MCF_EDMA_TCD14_CSR_INT_HALF (0x0004)
7146 +#define MCF_EDMA_TCD14_CSR_D_REQ (0x0008)
7147 +#define MCF_EDMA_TCD14_CSR_E_SG (0x0010)
7148 +#define MCF_EDMA_TCD14_CSR_E_LINK (0x0020)
7149 +#define MCF_EDMA_TCD14_CSR_ACTIVE (0x0040)
7150 +#define MCF_EDMA_TCD14_CSR_DONE (0x0080)
7151 +#define MCF_EDMA_TCD14_CSR_LINKCH(x) (((x)&0x003F)<<8)
7152 +#define MCF_EDMA_TCD14_CSR_BWC(x) (((x)&0x0003)<<14)
7153 +
7154 +/* Bit definitions and macros for TCD15_SADDR */
7155 +#define MCF_EDMA_TCD15_SADDR_SADDR(x) (x)
7156 +
7157 +/* Bit definitions and macros for TCD15_ATTR */
7158 +#define MCF_EDMA_TCD15_ATTR_DSIZE(x) (((x)&0x0007))
7159 +#define MCF_EDMA_TCD15_ATTR_DMOD(x) (((x)&0x001F)<<3)
7160 +#define MCF_EDMA_TCD15_ATTR_SSIZE(x) (((x)&0x0007)<<8)
7161 +#define MCF_EDMA_TCD15_ATTR_SMOD(x) (((x)&0x001F)<<11)
7162 +
7163 +/* Bit definitions and macros for TCD15_SOFF */
7164 +#define MCF_EDMA_TCD15_SOFF_SOFF(x) (x)
7165 +
7166 +/* Bit definitions and macros for TCD15_NBYTES */
7167 +#define MCF_EDMA_TCD15_NBYTES_NBYTES(x) (x)
7168 +
7169 +/* Bit definitions and macros for TCD15_SLAST */
7170 +#define MCF_EDMA_TCD15_SLAST_SLAST(x) (x)
7171 +
7172 +/* Bit definitions and macros for TCD15_DADDR */
7173 +#define MCF_EDMA_TCD15_DADDR_DADDR(x) (x)
7174 +
7175 +/* Bit definitions and macros for TCD15_CITER_ELINK */
7176 +#define MCF_EDMA_TCD15_CITER_ELINK_CITER(x) (((x)&0x01FF))
7177 +#define MCF_EDMA_TCD15_CITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
7178 +#define MCF_EDMA_TCD15_CITER_ELINK_E_LINK (0x8000)
7179 +
7180 +/* Bit definitions and macros for TCD15_CITER */
7181 +#define MCF_EDMA_TCD15_CITER_CITER(x) (((x)&0x7FFF))
7182 +#define MCF_EDMA_TCD15_CITER_E_LINK (0x8000)
7183 +
7184 +/* Bit definitions and macros for TCD15_DOFF */
7185 +#define MCF_EDMA_TCD15_DOFF_DOFF(x) (x)
7186 +
7187 +/* Bit definitions and macros for TCD15_DLAST_SGA */
7188 +#define MCF_EDMA_TCD15_DLAST_SGA_DLAST_SGA(x) (x)
7189 +
7190 +/* Bit definitions and macros for TCD15_BITER */
7191 +#define MCF_EDMA_TCD15_BITER_BITER(x) (((x)&0x7FFF))
7192 +#define MCF_EDMA_TCD15_BITER_E_LINK (0x8000)
7193 +
7194 +/* Bit definitions and macros for TCD15_BITER_ELINK */
7195 +#define MCF_EDMA_TCD15_BITER_ELINK_BITER(x) (((x)&0x01FF))
7196 +#define MCF_EDMA_TCD15_BITER_ELINK_LINKCH(x) (((x)&0x003F)<<9)
7197 +#define MCF_EDMA_TCD15_BITER_ELINK_E_LINK (0x8000)
7198 +
7199 +/* Bit definitions and macros for TCD15_CSR */
7200 +#define MCF_EDMA_TCD15_CSR_START (0x0001)
7201 +#define MCF_EDMA_TCD15_CSR_INT_MAJOR (0x0002)
7202 +#define MCF_EDMA_TCD15_CSR_INT_HALF (0x0004)
7203 +#define MCF_EDMA_TCD15_CSR_D_REQ (0x0008)
7204 +#define MCF_EDMA_TCD15_CSR_E_SG (0x0010)
7205 +#define MCF_EDMA_TCD15_CSR_E_LINK (0x0020)
7206 +#define MCF_EDMA_TCD15_CSR_ACTIVE (0x0040)
7207 +#define MCF_EDMA_TCD15_CSR_DONE (0x0080)
7208 +#define MCF_EDMA_TCD15_CSR_LINKCH(x) (((x)&0x003F)<<8)
7209 +#define MCF_EDMA_TCD15_CSR_BWC(x) (((x)&0x0003)<<14)
7210 +
7211 +#endif /* __MCF5445X_EDMA_H__ */
7212 --- /dev/null
7213 +++ b/arch/m68k/include/asm/mcf5445x_eport.h
7214 @@ -0,0 +1,117 @@
7215 +/*
7216 + * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
7217 + *
7218 + * Kurt Mahan kmahan@freescale.com
7219 + *
7220 + * This program is free software; you can redistribute it and/or modify it
7221 + * under the terms of the GNU General Public License as published by the
7222 + * Free Software Foundation; either version 2 of the License, or (at your
7223 + * option) any later version.
7224 + */
7225 +
7226 +#ifndef __MCF5445X_EPORT_H__
7227 +#define __MCF5445X_EPORT_H__
7228 +
7229 +/*********************************************************************
7230 +*
7231 +* Edge Port Module (EPORT)
7232 +*
7233 +*********************************************************************/
7234 +
7235 +/* Register read/write macros */
7236 +#define MCF_EPORT_EPPAR MCF_REG16(0xFC094000)
7237 +#define MCF_EPORT_EPDDR MCF_REG08(0xFC094002)
7238 +#define MCF_EPORT_EPIER MCF_REG08(0xFC094003)
7239 +#define MCF_EPORT_EPDR MCF_REG08(0xFC094004)
7240 +#define MCF_EPORT_EPPDR MCF_REG08(0xFC094005)
7241 +#define MCF_EPORT_EPFR MCF_REG08(0xFC094006)
7242 +
7243 +/* Bit definitions and macros for EPPAR */
7244 +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
7245 +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
7246 +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
7247 +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
7248 +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
7249 +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
7250 +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
7251 +#define MCF_EPORT_EPPAR_LEVEL (0)
7252 +#define MCF_EPORT_EPPAR_RISING (1)
7253 +#define MCF_EPORT_EPPAR_FALLING (2)
7254 +#define MCF_EPORT_EPPAR_BOTH (3)
7255 +#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000)
7256 +#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
7257 +#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
7258 +#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
7259 +#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000)
7260 +#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
7261 +#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
7262 +#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
7263 +#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000)
7264 +#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400)
7265 +#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800)
7266 +#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00)
7267 +#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000)
7268 +#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100)
7269 +#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200)
7270 +#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300)
7271 +#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000)
7272 +#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040)
7273 +#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080)
7274 +#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0)
7275 +#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000)
7276 +#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010)
7277 +#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020)
7278 +#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030)
7279 +#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000)
7280 +#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004)
7281 +#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008)
7282 +#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C)
7283 +
7284 +/* Bit definitions and macros for EPDDR */
7285 +#define MCF_EPORT_EPDDR_EPDD1 (0x02)
7286 +#define MCF_EPORT_EPDDR_EPDD2 (0x04)
7287 +#define MCF_EPORT_EPDDR_EPDD3 (0x08)
7288 +#define MCF_EPORT_EPDDR_EPDD4 (0x10)
7289 +#define MCF_EPORT_EPDDR_EPDD5 (0x20)
7290 +#define MCF_EPORT_EPDDR_EPDD6 (0x40)
7291 +#define MCF_EPORT_EPDDR_EPDD7 (0x80)
7292 +
7293 +/* Bit definitions and macros for EPIER */
7294 +#define MCF_EPORT_EPIER_EPIE1 (0x02)
7295 +#define MCF_EPORT_EPIER_EPIE2 (0x04)
7296 +#define MCF_EPORT_EPIER_EPIE3 (0x08)
7297 +#define MCF_EPORT_EPIER_EPIE4 (0x10)
7298 +#define MCF_EPORT_EPIER_EPIE5 (0x20)
7299 +#define MCF_EPORT_EPIER_EPIE6 (0x40)
7300 +#define MCF_EPORT_EPIER_EPIE7 (0x80)
7301 +
7302 +/* Bit definitions and macros for EPDR */
7303 +#define MCF_EPORT_EPDR_EPD1 (0x02)
7304 +#define MCF_EPORT_EPDR_EPD2 (0x04)
7305 +#define MCF_EPORT_EPDR_EPD3 (0x08)
7306 +#define MCF_EPORT_EPDR_EPD4 (0x10)
7307 +#define MCF_EPORT_EPDR_EPD5 (0x20)
7308 +#define MCF_EPORT_EPDR_EPD6 (0x40)
7309 +#define MCF_EPORT_EPDR_EPD7 (0x80)
7310 +
7311 +/* Bit definitions and macros for EPPDR */
7312 +#define MCF_EPORT_EPPDR_EPPD1 (0x02)
7313 +#define MCF_EPORT_EPPDR_EPPD2 (0x04)
7314 +#define MCF_EPORT_EPPDR_EPPD3 (0x08)
7315 +#define MCF_EPORT_EPPDR_EPPD4 (0x10)
7316 +#define MCF_EPORT_EPPDR_EPPD5 (0x20)
7317 +#define MCF_EPORT_EPPDR_EPPD6 (0x40)
7318 +#define MCF_EPORT_EPPDR_EPPD7 (0x80)
7319 +
7320 +/* Bit definitions and macros for EPFR */
7321 +#define MCF_EPORT_EPFR_EPF1 (0x02)
7322 +#define MCF_EPORT_EPFR_EPF2 (0x04)
7323 +#define MCF_EPORT_EPFR_EPF3 (0x08)
7324 +#define MCF_EPORT_EPFR_EPF4 (0x10)
7325 +#define MCF_EPORT_EPFR_EPF5 (0x20)
7326 +#define MCF_EPORT_EPFR_EPF6 (0x40)
7327 +#define MCF_EPORT_EPFR_EPF7 (0x80)
7328 +
7329 +/********************************************************************/
7330 +
7331 +#endif /* __MCF5445X_EPORT_H__ */
7332 --- /dev/null
7333 +++ b/arch/m68k/include/asm/mcf5445x_fbcs.h
7334 @@ -0,0 +1,200 @@
7335 +/*
7336 + * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
7337 + *
7338 + * Matt Waddel Matt.Waddel@freescale.com
7339 + *
7340 + * This program is free software; you can redistribute it and/or modify it
7341 + * under the terms of the GNU General Public License as published by the
7342 + * Free Software Foundation; either version 2 of the License, or (at your
7343 + * option) any later version.
7344 + */
7345 +
7346 +#ifndef __MCF5445X_FBCS_H__
7347 +#define __MCF5445X_FBCS_H__
7348 +
7349 +/*********************************************************************
7350 +*
7351 +* FlexBus Chip Selects (FBCS)
7352 +*
7353 +*********************************************************************/
7354 +
7355 +/* Register read/write macros */
7356 +#define MCF_FBCS_CSAR0 MCF_REG32(0xFC008000) /* Chip-select Addr Register */
7357 +#define MCF_FBCS_CSMR0 MCF_REG32(0xFC008004) /* Chip-select Mask Register */
7358 +#define MCF_FBCS_CSCR0 MCF_REG32(0xFC008008) /* Chip-select Cntl Register */
7359 +#define MCF_FBCS_CSAR1 MCF_REG32(0xFC00800C) /* Chip-select Addr Register */
7360 +#define MCF_FBCS_CSMR1 MCF_REG32(0xFC008010) /* Chip-select Mask Register */
7361 +#define MCF_FBCS_CSCR1 MCF_REG32(0xFC008014) /* Chip-select Cntl Register */
7362 +#define MCF_FBCS_CSAR2 MCF_REG32(0xFC008018) /* Chip-select Addr Register */
7363 +#define MCF_FBCS_CSMR2 MCF_REG32(0xFC00801C) /* Chip-select Mask Register */
7364 +#define MCF_FBCS_CSCR2 MCF_REG32(0xFC008020) /* Chip-select Cntl Register */
7365 +#define MCF_FBCS_CSAR3 MCF_REG32(0xFC008024) /* Chip-select Addr Register */
7366 +#define MCF_FBCS_CSMR3 MCF_REG32(0xFC008028) /* Chip-select Mask Register */
7367 +#define MCF_FBCS_CSCR3 MCF_REG32(0xFC00802C) /* Chip-select Cntl Register */
7368 +
7369 +/* Parameterized register read/write macros for multiple registers */
7370 +/* Chip-select Addr Register */
7371 +#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C))
7372 +/* Chip-select Mask Register */
7373 +#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C))
7374 +/* Chip-select Cntl Register */
7375 +#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C))
7376 +
7377 +/* Bit definitions and macros for CSAR group */
7378 +#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
7379 +
7380 +/* Bit definitions and macros for CSAR0 */
7381 +#define MCF_FBCS_CSAR0_BA(x) ((x)&0xFFFF0000)
7382 +
7383 +/* Bit definitions and macros for CSMR group */
7384 +#define MCF_FBCS_CSMR_V (0x00000001) /* Valid bit */
7385 +#define MCF_FBCS_CSMR_WP (0x00000100) /* Write protect */
7386 +#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */
7387 +#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
7388 +#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
7389 +#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
7390 +#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
7391 +#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
7392 +#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000)
7393 +#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000)
7394 +#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000)
7395 +#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000)
7396 +#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000)
7397 +#define MCF_FBCS_CSMR_BAM_8M (0x007F0000)
7398 +#define MCF_FBCS_CSMR_BAM_4M (0x003F0000)
7399 +#define MCF_FBCS_CSMR_BAM_2M (0x001F0000)
7400 +#define MCF_FBCS_CSMR_BAM_1M (0x000F0000)
7401 +#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000)
7402 +#define MCF_FBCS_CSMR_BAM_512K (0x00070000)
7403 +#define MCF_FBCS_CSMR_BAM_256K (0x00030000)
7404 +#define MCF_FBCS_CSMR_BAM_128K (0x00010000)
7405 +#define MCF_FBCS_CSMR_BAM_64K (0x00000000)
7406 +
7407 +/* Bit definitions and macros for CSMR0 */
7408 +#define MCF_FBCS_CSMR0_V (0x00000001) /* Valid bit */
7409 +#define MCF_FBCS_CSMR0_WP (0x00000100) /* Write protect */
7410 +#define MCF_FBCS_CSMR0_BAM(x) (((x)&0x0000FFFF)<<16) /* Base addr mask */
7411 +#define MCF_FBCS_CSMR0_BAM_4G (0xFFFF0000)
7412 +#define MCF_FBCS_CSMR0_BAM_2G (0x7FFF0000)
7413 +#define MCF_FBCS_CSMR0_BAM_1G (0x3FFF0000)
7414 +#define MCF_FBCS_CSMR0_BAM_1024M (0x3FFF0000)
7415 +#define MCF_FBCS_CSMR0_BAM_512M (0x1FFF0000)
7416 +#define MCF_FBCS_CSMR0_BAM_256M (0x0FFF0000)
7417 +#define MCF_FBCS_CSMR0_BAM_128M (0x07FF0000)
7418 +#define MCF_FBCS_CSMR0_BAM_64M (0x03FF0000)
7419 +#define MCF_FBCS_CSMR0_BAM_32M (0x01FF0000)
7420 +#define MCF_FBCS_CSMR0_BAM_16M (0x00FF0000)
7421 +#define MCF_FBCS_CSMR0_BAM_8M (0x007F0000)
7422 +#define MCF_FBCS_CSMR0_BAM_4M (0x003F0000)
7423 +#define MCF_FBCS_CSMR0_BAM_2M (0x001F0000)
7424 +#define MCF_FBCS_CSMR0_BAM_1M (0x000F0000)
7425 +#define MCF_FBCS_CSMR0_BAM_1024K (0x000F0000)
7426 +#define MCF_FBCS_CSMR0_BAM_512K (0x00070000)
7427 +#define MCF_FBCS_CSMR0_BAM_256K (0x00030000)
7428 +#define MCF_FBCS_CSMR0_BAM_128K (0x00010000)
7429 +#define MCF_FBCS_CSMR0_BAM_64K (0x00000000)
7430 +
7431 +/* Bit definitions and macros for CSCR group */
7432 +#define MCF_FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */
7433 +#define MCF_FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */
7434 +#define MCF_FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */
7435 +#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */
7436 +#define MCF_FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */
7437 +#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
7438 +/* Write address hold or deselect */
7439 +#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16)
7440 +/* Read address hold or deselect */
7441 +#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18)
7442 +#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
7443 +#define MCF_FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */
7444 +/* Secondary wait states */
7445 +#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26)
7446 +#define MCF_FBCS_CSCR_PS_8 (0x00000040)
7447 +#define MCF_FBCS_CSCR_PS_16 (0x00000080)
7448 +#define MCF_FBCS_CSCR_PS_32 (0x00000000)
7449 +
7450 +/* Bit definitions and macros for CSCR0 */
7451 +#define MCF_FBCS_CSCR0_BSTW (0x00000008) /* Burst-write enable */
7452 +#define MCF_FBCS_CSCR0_BSTR (0x00000010) /* Burst-read enable */
7453 +#define MCF_FBCS_CSCR0_BEM (0x00000020) /* Byte-enable mode */
7454 +#define MCF_FBCS_CSCR0_PS(x) (((x)&0x00000003)<<6) /* Port size */
7455 +#define MCF_FBCS_CSCR0_AA (0x00000100) /* Auto-acknowledge */
7456 +#define MCF_FBCS_CSCR0_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
7457 +/* Write address hold or deselect */
7458 +#define MCF_FBCS_CSCR0_WRAH(x) (((x)&0x00000003)<<16)
7459 +/* Read address hold or deselect */
7460 +#define MCF_FBCS_CSCR0_RDAH(x) (((x)&0x00000003)<<18)
7461 +#define MCF_FBCS_CSCR0_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
7462 +#define MCF_FBCS_CSCR0_SWSEN (0x00800000) /* Secondary wait state enable */
7463 +/* Secondary wait states */
7464 +#define MCF_FBCS_CSCR0_SWS(x) (((x)&0x0000003F)<<26)
7465 +#define MCF_FBCS_CSCR0_PS_8 (0x00000040)
7466 +#define MCF_FBCS_CSCR0_PS_16 (0x00000080)
7467 +#define MCF_FBCS_CSCR0_PS_32 (0x00000000)
7468 +
7469 +/* Bit definitions and macros for CSMR1 */
7470 +#define MCF_FBCS_CSMR1_V (0x00000001) /* Valid bit */
7471 +#define MCF_FBCS_CSMR1_WP (0x00000100) /* Write protect */
7472 +#define MCF_FBCS_CSMR1_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
7473 +
7474 +/* Bit definitions and macros for CSCR1 */
7475 +#define MCF_FBCS_CSCR1_BSTW (0x00000008) /* Burst-write enable */
7476 +#define MCF_FBCS_CSCR1_BSTR (0x00000010) /* Burst-read enable */
7477 +#define MCF_FBCS_CSCR1_BEM (0x00000020) /* Byte-enable mode */
7478 +#define MCF_FBCS_CSCR1_PS(x) (((x)&0x00000003)<<6) /* Port size */
7479 +#define MCF_FBCS_CSCR1_AA (0x00000100) /* Auto-acknowledge */
7480 +#define MCF_FBCS_CSCR1_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
7481 +/* Write address hold or deselect */
7482 +#define MCF_FBCS_CSCR1_WRAH(x) (((x)&0x00000003)<<16)
7483 +/* Read address hold or deselect */
7484 +#define MCF_FBCS_CSCR1_RDAH(x) (((x)&0x00000003)<<18)
7485 +#define MCF_FBCS_CSCR1_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
7486 +#define MCF_FBCS_CSCR1_SWSEN (0x00800000) /* Secondary wait state enable */
7487 +/* Secondary wait states */
7488 +#define MCF_FBCS_CSCR1_SWS(x) (((x)&0x0000003F)<<26)
7489 +
7490 +/* Bit definitions and macros for CSMR2 */
7491 +#define MCF_FBCS_CSMR2_V (0x00000001) /* Valid bit */
7492 +#define MCF_FBCS_CSMR2_WP (0x00000100) /* Write protect */
7493 +#define MCF_FBCS_CSMR2_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
7494 +
7495 +/* Bit definitions and macros for CSCR2 */
7496 +#define MCF_FBCS_CSCR2_BSTW (0x00000008) /* Burst-write enable */
7497 +#define MCF_FBCS_CSCR2_BSTR (0x00000010) /* Burst-read enable */
7498 +#define MCF_FBCS_CSCR2_BEM (0x00000020) /* Byte-enable mode */
7499 +#define MCF_FBCS_CSCR2_PS(x) (((x)&0x00000003)<<6) /* Port size */
7500 +#define MCF_FBCS_CSCR2_AA (0x00000100) /* Auto-acknowledge */
7501 +#define MCF_FBCS_CSCR2_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
7502 +/* Write address hold or deselect */
7503 +#define MCF_FBCS_CSCR2_WRAH(x) (((x)&0x00000003)<<16)
7504 +/* Read address hold or deselect */
7505 +#define MCF_FBCS_CSCR2_RDAH(x) (((x)&0x00000003)<<18)
7506 +#define MCF_FBCS_CSCR2_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
7507 +#define MCF_FBCS_CSCR2_SWSEN (0x00800000) /* Secondary wait state enable */
7508 +/* Secondary wait states */
7509 +#define MCF_FBCS_CSCR2_SWS(x) (((x)&0x0000003F)<<26)
7510 +
7511 +/* Bit definitions and macros for CSMR3 */
7512 +#define MCF_FBCS_CSMR3_V (0x00000001) /* Valid bit */
7513 +#define MCF_FBCS_CSMR3_WP (0x00000100) /* Write protect */
7514 +#define MCF_FBCS_CSMR3_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
7515 +
7516 +/* Bit definitions and macros for CSCR3 */
7517 +#define MCF_FBCS_CSCR3_BSTW (0x00000008) /* Burst-write enable */
7518 +#define MCF_FBCS_CSCR3_BSTR (0x00000010) /* Burst-read enable */
7519 +#define MCF_FBCS_CSCR3_BEM (0x00000020) /* Byte-enable mode */
7520 +#define MCF_FBCS_CSCR3_PS(x) (((x)&0x00000003)<<6) /* Port size */
7521 +#define MCF_FBCS_CSCR3_AA (0x00000100) /* Auto-acknowledge */
7522 +#define MCF_FBCS_CSCR3_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
7523 +/* Write address hold or deselect */
7524 +#define MCF_FBCS_CSCR3_WRAH(x) (((x)&0x00000003)<<16)
7525 +/* Read address hold or deselect */
7526 +#define MCF_FBCS_CSCR3_RDAH(x) (((x)&0x00000003)<<18)
7527 +#define MCF_FBCS_CSCR3_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
7528 +#define MCF_FBCS_CSCR3_SWSEN (0x00800000) /* Secondary wait state enable */
7529 +/* Secondary wait states */
7530 +#define MCF_FBCS_CSCR3_SWS(x) (((x)&0x0000003F)<<26)
7531 +
7532 +/********************************************************************/
7533 +
7534 +#endif /* __MCF5445X_FBCS_H__ */
7535 --- /dev/null
7536 +++ b/arch/m68k/include/asm/mcf5445x_gpio.h
7537 @@ -0,0 +1,1411 @@
7538 +/*
7539 + * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
7540 + *
7541 + * Matt Waddel Matt.Waddel@freescale.com
7542 + *
7543 + * This program is free software; you can redistribute it and/or modify it
7544 + * under the terms of the GNU General Public License as published by the
7545 + * Free Software Foundation; either version 2 of the License, or (at your
7546 + * option) any later version.
7547 + */
7548 +
7549 +#ifndef __MCF5445X_GPIO_H__
7550 +#define __MCF5445X_GPIO_H__
7551 +
7552 +/*********************************************************************
7553 +*
7554 +* General Purpose I/O Module (GPIO)
7555 +*
7556 +*********************************************************************/
7557 +
7558 +/* Register read/write macros */
7559 +#define MCF_GPIO_PODR_FEC0H \
7560 + MCF_REG08(0xFC0A4000) /* FEC0 High Port Output Data Register */
7561 +#define MCF_GPIO_PODR_FEC0L \
7562 + MCF_REG08(0xFC0A4001) /* FEC0 Low Port Output Data Register */
7563 +#define MCF_GPIO_PODR_SSI \
7564 + MCF_REG08(0xFC0A4002) /* SSI Port Output Data Register */
7565 +#define MCF_GPIO_PODR_FBCTL \
7566 + MCF_REG08(0xFC0A4003) /* Flexbus Control Port Output Data Register */
7567 +/* Flexbus Byte Enable Port Output Data Register */
7568 +#define MCF_GPIO_PODR_BE MCF_REG08(0xFC0A4004)
7569 +/* Flexbus Chip-Select Port Output Data Register */
7570 +#define MCF_GPIO_PODR_CS MCF_REG08(0xFC0A4005)
7571 +#define MCF_GPIO_PODR_DMA \
7572 + MCF_REG08(0xFC0A4006) /* DMA Port Output Data Register */
7573 +#define MCF_GPIO_PODR_FECI2C \
7574 + MCF_REG08(0xFC0A4007) /* FEC1 / I2C Port Output Data Register */
7575 +#define MCF_GPIO_PODR_UART \
7576 + MCF_REG08(0xFC0A4009) /* UART Port Output Data Register */
7577 +#define MCF_GPIO_PODR_DSPI \
7578 + MCF_REG08(0xFC0A400A) /* DSPI Port Output Data Register */
7579 +#define MCF_GPIO_PODR_TIMER \
7580 + MCF_REG08(0xFC0A400B) /* Timer Port Output Data Register */
7581 +#define MCF_GPIO_PODR_PCI \
7582 + MCF_REG08(0xFC0A400C) /* PCI Port Output Data Register */
7583 +#define MCF_GPIO_PODR_USB \
7584 + MCF_REG08(0xFC0A400D) /* USB Port Output Data Register */
7585 +#define MCF_GPIO_PODR_ATAH \
7586 + MCF_REG08(0xFC0A400E) /* ATA High Port Output Data Register */
7587 +#define MCF_GPIO_PODR_ATAL \
7588 + MCF_REG08(0xFC0A400F) /* ATA Low Port Output Data Register */
7589 +#define MCF_GPIO_PODR_FEC1H \
7590 + MCF_REG08(0xFC0A4010) /* FEC1 High Port Output Data Register */
7591 +#define MCF_GPIO_PODR_FEC1L \
7592 + MCF_REG08(0xFC0A4011) /* FEC1 Low Port Output Data Register */
7593 +#define MCF_GPIO_PODR_FBADH \
7594 + MCF_REG08(0xFC0A4014) /* Flexbus AD High Port Output Data Register */
7595 +/* Flexbus AD Med-High Port Output Data Register */
7596 +#define MCF_GPIO_PODR_FBADMH MCF_REG08(0xFC0A4015)
7597 +/* Flexbus AD Med-Low Port Output Data Register */
7598 +#define MCF_GPIO_PODR_FBADML MCF_REG08(0xFC0A4016)
7599 +#define MCF_GPIO_PODR_FBADL \
7600 + MCF_REG08(0xFC0A4017) /* Flexbus AD Low Port Output Data Register */
7601 +#define MCF_GPIO_PDDR_FEC0H \
7602 + MCF_REG08(0xFC0A4018) /* FEC0 High Port Data Direction Register */
7603 +#define MCF_GPIO_PDDR_FEC0L \
7604 + MCF_REG08(0xFC0A4019) /* FEC0 Low Port Data Direction Register */
7605 +#define MCF_GPIO_PDDR_SSI \
7606 + MCF_REG08(0xFC0A401A) /* SSI Port Data Direction Register */
7607 +/* Flexbus Control Port Data Direction Register */
7608 +#define MCF_GPIO_PDDR_FBCTL MCF_REG08(0xFC0A401B)
7609 +/* Flexbus Byte Enable Port Data Direction Register */
7610 +#define MCF_GPIO_PDDR_BE MCF_REG08(0xFC0A401C)
7611 +/* Flexbus Chip-Select Port Data Direction Register */
7612 +#define MCF_GPIO_PDDR_CS MCF_REG08(0xFC0A401D)
7613 +#define MCF_GPIO_PDDR_DMA \
7614 + MCF_REG08(0xFC0A401E) /* DMA Port Data Direction Register */
7615 +#define MCF_GPIO_PDDR_FECI2C \
7616 + MCF_REG08(0xFC0A401F) /* FEC1 / I2C Port Data Direction Register */
7617 +#define MCF_GPIO_PDDR_UART \
7618 + MCF_REG08(0xFC0A4021) /* UART Port Data Direction Register */
7619 +#define MCF_GPIO_PDDR_DSPI \
7620 + MCF_REG08(0xFC0A4022) /* DSPI Port Data Direction Register */
7621 +#define MCF_GPIO_PDDR_TIMER \
7622 + MCF_REG08(0xFC0A4023) /* Timer Port Data Direction Register */
7623 +#define MCF_GPIO_PDDR_PCI \
7624 + MCF_REG08(0xFC0A4024) /* PCI Port Data Direction Register */
7625 +#define MCF_GPIO_PDDR_USB \
7626 + MCF_REG08(0xFC0A4025) /* USB Port Data Direction Register */
7627 +#define MCF_GPIO_PDDR_ATAH \
7628 + MCF_REG08(0xFC0A4026) /* ATA High Port Data Direction Register */
7629 +#define MCF_GPIO_PDDR_ATAL \
7630 + MCF_REG08(0xFC0A4027) /* ATA Low Port Data Direction Register */
7631 +#define MCF_GPIO_PDDR_FEC1H \
7632 + MCF_REG08(0xFC0A4028) /* FEC1 High Port Data Direction Register */
7633 +#define MCF_GPIO_PDDR_FEC1L \
7634 + MCF_REG08(0xFC0A4029) /* FEC1 Low Port Data Direction Register */
7635 +/* Flexbus AD High Port Data Direction Register */
7636 +#define MCF_GPIO_PDDR_FBADH MCF_REG08(0xFC0A402C)
7637 +/* Flexbus AD Med-High Port Data Direction Register */
7638 +#define MCF_GPIO_PDDR_FBADMH MCF_REG08(0xFC0A402D)
7639 +/* Flexbus AD Med-Low Port Data Direction Register */
7640 +#define MCF_GPIO_PDDR_FBADML MCF_REG08(0xFC0A402E)
7641 +/* Flexbus AD Low Port Data Direction Register */
7642 +#define MCF_GPIO_PDDR_FBADL MCF_REG08(0xFC0A402F)
7643 +#define MCF_GPIO_PPDSDR_FEC0H \
7644 + MCF_REG08(0xFC0A4030) /* FEC0 High Port Pin Data/Set Data Register */
7645 +#define MCF_GPIO_PPDSDR_FEC0L \
7646 + MCF_REG08(0xFC0A4031) /* FEC0 Low Port Clear Output Data Register */
7647 +#define MCF_GPIO_PPDSDR_SSI \
7648 + MCF_REG08(0xFC0A4032) /* SSI Port Pin Data/Set Data Register */
7649 +/* Flexbus Control Port Pin Data/Set Data Register */
7650 +#define MCF_GPIO_PPDSDR_FBCTL MCF_REG08(0xFC0A4033)
7651 +/* Flexbus Byte Enable Port Pin Data/Set Data Register */
7652 +#define MCF_GPIO_PPDSDR_BE MCF_REG08(0xFC0A4034)
7653 +/* Flexbus Chip-Select Port Pin Data/Set Data Register */
7654 +#define MCF_GPIO_PPDSDR_CS MCF_REG08(0xFC0A4035)
7655 +#define MCF_GPIO_PPDSDR_DMA \
7656 + MCF_REG08(0xFC0A4036) /* DMA Port Pin Data/Set Data Register */
7657 +#define MCF_GPIO_PPDSDR_FECI2C \
7658 + MCF_REG08(0xFC0A4037) /* FEC1 / I2C Port Pin Data/Set Data Register */
7659 +#define MCF_GPIO_PPDSDR_UART \
7660 + MCF_REG08(0xFC0A4039) /* UART Port Pin Data/Set Data Register */
7661 +#define MCF_GPIO_PPDSDR_DSPI \
7662 + MCF_REG08(0xFC0A403A) /* DSPI Port Pin Data/Set Data Register */
7663 +#define MCF_GPIO_PPDSDR_TIMER \
7664 + MCF_REG08(0xFC0A403B) /* FTimer Port Pin Data/Set Data Register */
7665 +#define MCF_GPIO_PPDSDR_PCI \
7666 + MCF_REG08(0xFC0A403C) /* PCI Port Pin Data/Set Data Register */
7667 +#define MCF_GPIO_PPDSDR_USB \
7668 + MCF_REG08(0xFC0A403D) /* USB Port Pin Data/Set Data Register */
7669 +#define MCF_GPIO_PPDSDR_ATAH \
7670 + MCF_REG08(0xFC0A403E) /* ATA High Port Pin Data/Set Data Register */
7671 +#define MCF_GPIO_PPDSDR_ATAL \
7672 + MCF_REG08(0xFC0A403F) /* ATA Low Port Pin Data/Set Data Register */
7673 +#define MCF_GPIO_PPDSDR_FEC1H \
7674 + MCF_REG08(0xFC0A4040) /* FEC1 High Port Pin Data/Set Data Register */
7675 +#define MCF_GPIO_PPDSDR_FEC1L \
7676 + MCF_REG08(0xFC0A4041) /* FEC1 Low Port Pin Data/Set Data Register */
7677 +/* Flexbus AD High Port Pin Data/Set Data Register */
7678 +#define MCF_GPIO_PPDSDR_FBADH MCF_REG08(0xFC0A4044)
7679 +/* Flexbus AD Med-High Port Pin Data/Set Data Register */
7680 +#define MCF_GPIO_PPDSDR_FBADMH MCF_REG08(0xFC0A4045)
7681 +/* Flexbus AD Med-Low Port Pin Data/Set Data Register */
7682 +#define MCF_GPIO_PPDSDR_FBADML MCF_REG08(0xFC0A4046)
7683 +/* Flexbus AD Low Port Pin Data/Set Data Register */
7684 +#define MCF_GPIO_PPDSDR_FBADL MCF_REG08(0xFC0A4047)
7685 +#define MCF_GPIO_PCLRR_FEC0H \
7686 + MCF_REG08(0xFC0A4048) /* FEC0 High Port Clear Output Data Register */
7687 +#define MCF_GPIO_PCLRR_FEC0L \
7688 + MCF_REG08(0xFC0A4049) /* FEC0 Low Port Pin Data/Set Data Register */
7689 +#define MCF_GPIO_PCLRR_SSI \
7690 + MCF_REG08(0xFC0A404A) /* SSI Port Clear Output Data Register */
7691 +/* Flexbus Control Port Clear Output Data Register */
7692 +#define MCF_GPIO_PCLRR_FBCTL MCF_REG08(0xFC0A404B)
7693 +/* Flexbus Byte Enable Port Clear Output Data Register */
7694 +#define MCF_GPIO_PCLRR_BE MCF_REG08(0xFC0A404C)
7695 +/* Flexbus Chip-Select Port Clear Output Data Register */
7696 +#define MCF_GPIO_PCLRR_CS MCF_REG08(0xFC0A404D)
7697 +#define MCF_GPIO_PCLRR_DMA \
7698 + MCF_REG08(0xFC0A404E) /* DMA Port Clear Output Data Register */
7699 +#define MCF_GPIO_PCLRR_FECI2C \
7700 + MCF_REG08(0xFC0A404F) /* FEC1 / I2C Port Clear Output Data Register */
7701 +#define MCF_GPIO_PCLRR_UART \
7702 + MCF_REG08(0xFC0A4051) /* UART Port Clear Output Data Register */
7703 +#define MCF_GPIO_PCLRR_DSPI \
7704 + MCF_REG08(0xFC0A4052) /* DSPI Port Clear Output Data Register */
7705 +#define MCF_GPIO_PCLRR_TIMER \
7706 + MCF_REG08(0xFC0A4053) /* Timer Port Clear Output Data Register */
7707 +#define MCF_GPIO_PCLRR_PCI \
7708 + MCF_REG08(0xFC0A4054) /* PCI Port Clear Output Data Register */
7709 +#define MCF_GPIO_PCLRR_USB \
7710 + MCF_REG08(0xFC0A4055) /* USB Port Clear Output Data Register */
7711 +#define MCF_GPIO_PCLRR_ATAH \
7712 + MCF_REG08(0xFC0A4056) /* ATA High Port Clear Output Data Register */
7713 +#define MCF_GPIO_PCLRR_ATAL \
7714 + MCF_REG08(0xFC0A4057) /* ATA Low Port Clear Output Data Register */
7715 +#define MCF_GPIO_PCLRR_FEC1H \
7716 + MCF_REG08(0xFC0A4058) /* FEC1 High Port Clear Output Data Register */
7717 +#define MCF_GPIO_PCLRR_FEC1L \
7718 + MCF_REG08(0xFC0A4059) /* FEC1 Low Port Clear Output Data Register */
7719 +/* Flexbus AD High Port Clear Output Data Register */
7720 +#define MCF_GPIO_PCLRR_FBADH MCF_REG08(0xFC0A405C)
7721 +/* Flexbus AD Med-High Port Clear Output Data Register */
7722 +#define MCF_GPIO_PCLRR_FBADMH MCF_REG08(0xFC0A405D)
7723 +/* Flexbus AD Med-Low Port Clear Output Data Register */
7724 +#define MCF_GPIO_PCLRR_FBADML MCF_REG08(0xFC0A405E)
7725 +/* Flexbus AD Low Port Clear Output Data Register */
7726 +#define MCF_GPIO_PCLRR_FBADL MCF_REG08(0xFC0A405F)
7727 +#define MCF_GPIO_PAR_FEC \
7728 + MCF_REG08(0xFC0A4060) /* FEC Pin Assignment Register */
7729 +#define MCF_GPIO_PAR_DMA \
7730 + MCF_REG08(0xFC0A4061) /* DMA Pin Assignment Register */
7731 +#define MCF_GPIO_PAR_FBCTL \
7732 + MCF_REG08(0xFC0A4062) /* Flexbus Control Pin Assignment Register */
7733 +#define MCF_GPIO_PAR_DSPI \
7734 + MCF_REG08(0xFC0A4063) /* DSPI Pin Assignment Register */
7735 +/* Flexbus Byte-Enable Pin Assignment Register */
7736 +#define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4064)
7737 +/* Flexbus Chip-Select Pin Assignment Register */
7738 +#define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4065)
7739 +#define MCF_GPIO_PAR_TIMER \
7740 + MCF_REG08(0xFC0A4066) /* Time Pin Assignment Register */
7741 +#define MCF_GPIO_PAR_USB \
7742 + MCF_REG08(0xFC0A4067) /* USB Pin Assignment Register */
7743 +#define MCF_GPIO_PAR_UART \
7744 + MCF_REG08(0xFC0A4069) /* UART Pin Assignment Register */
7745 +#define MCF_GPIO_PAR_FECI2C \
7746 + MCF_REG16(0xFC0A406A) /* FEC / I2C Pin Assignment Register */
7747 +#define MCF_GPIO_PAR_SSI \
7748 + MCF_REG16(0xFC0A406C) /* SSI Pin Assignment Register */
7749 +#define MCF_GPIO_PAR_ATA \
7750 + MCF_REG16(0xFC0A406E) /* ATA Pin Assignment Register */
7751 +#define MCF_GPIO_PAR_IRQ \
7752 + MCF_REG08(0xFC0A4070) /* IRQ Pin Assignment Register */
7753 +#define MCF_GPIO_PAR_PCI \
7754 + MCF_REG16(0xFC0A4072) /* PCI Pin Assignment Register */
7755 +#define MCF_GPIO_MSCR_SDRAM \
7756 + MCF_REG08(0xFC0A4074) /* SDRAM Mode Select Control Register */
7757 +#define MCF_GPIO_MSCR_PCI \
7758 + MCF_REG08(0xFC0A4075) /* PCI Mode Select Control Register */
7759 +#define MCF_GPIO_DSCR_I2C \
7760 + MCF_REG08(0xFC0A4078) /* I2C Drive Strength Control Register */
7761 +#define MCF_GPIO_DSCR_FLEXBUS \
7762 + MCF_REG08(0xFC0A4079) /* FLEXBUS Drive Strength Control Register */
7763 +#define MCF_GPIO_DSCR_FEC \
7764 + MCF_REG08(0xFC0A407A) /* FEC Drive Strength Control Register */
7765 +#define MCF_GPIO_DSCR_UART \
7766 + MCF_REG08(0xFC0A407B) /* UART Drive Strength Control Register */
7767 +#define MCF_GPIO_DSCR_DSPI \
7768 + MCF_REG08(0xFC0A407C) /* DSPI Drive Strength Control Register */
7769 +#define MCF_GPIO_DSCR_TIMER \
7770 + MCF_REG08(0xFC0A407D) /* TIMER Drive Strength Control Register */
7771 +#define MCF_GPIO_DSCR_SSI \
7772 + MCF_REG08(0xFC0A407E) /* SSI Drive Strength Control Register */
7773 +#define MCF_GPIO_DSCR_DMA \
7774 + MCF_REG08(0xFC0A407F) /* DMA Drive Strength Control Register */
7775 +#define MCF_GPIO_DSCR_DEBUG \
7776 + MCF_REG08(0xFC0A4080) /* DEBUG Drive Strength Control Register */
7777 +#define MCF_GPIO_DSCR_RESET \
7778 + MCF_REG08(0xFC0A4081) /* RESET Drive Strength Control Register */
7779 +#define MCF_GPIO_DSCR_IRQ \
7780 + MCF_REG08(0xFC0A4082) /* IRQ Drive Strength Control Register */
7781 +#define MCF_GPIO_DSCR_USB \
7782 + MCF_REG08(0xFC0A4083) /* USB Drive Strength Control Register */
7783 +#define MCF_GPIO_DSCR_ATA \
7784 + MCF_REG08(0xFC0A4084) /* ATA Drive Strength Control Register */
7785 +
7786 +/* Bit definitions and macros for PODR_FEC0H */
7787 +#define MCF_GPIO_PODR_FEC0H_PODR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */
7788 +#define MCF_GPIO_PODR_FEC0H_PODR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */
7789 +#define MCF_GPIO_PODR_FEC0H_PODR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */
7790 +#define MCF_GPIO_PODR_FEC0H_PODR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */
7791 +#define MCF_GPIO_PODR_FEC0H_PODR4 (0x10) /* FEC0_COL / ULPI_DATA7 */
7792 +#define MCF_GPIO_PODR_FEC0H_PODR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */
7793 +#define MCF_GPIO_PODR_FEC0H_PODR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */
7794 +#define MCF_GPIO_PODR_FEC0H_PODR7 (0x80) /* FEC0_TXCLK
7795 + / FEC0_RMII_REF_CLK */
7796 +
7797 +/* Bit definitions and macros for PODR_FEC0L */
7798 +#define MCF_GPIO_PODR_FEC0L_PODR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */
7799 +#define MCF_GPIO_PODR_FEC0L_PODR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */
7800 +#define MCF_GPIO_PODR_FEC0L_PODR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */
7801 +#define MCF_GPIO_PODR_FEC0L_PODR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */
7802 +#define MCF_GPIO_PODR_FEC0L_PODR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */
7803 +#define MCF_GPIO_PODR_FEC0L_PODR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */
7804 +#define MCF_GPIO_PODR_FEC0L_PODR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */
7805 +#define MCF_GPIO_PODR_FEC0L_PODR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */
7806 +
7807 +/* Bit definitions and macros for PODR_SSI */
7808 +#define MCF_GPIO_PODR_SSI_PODR0 (0x01) /* SSI_TXD / U1TXD */
7809 +#define MCF_GPIO_PODR_SSI_PODR1 (0x02) /* SSI_RXD / U1RXD */
7810 +#define MCF_GPIO_PODR_SSI_PODR2 (0x04) /* SSI_FS / U1RTS */
7811 +#define MCF_GPIO_PODR_SSI_PODR3 (0x08) /* SSI_BCLK / U1CTS */
7812 +#define MCF_GPIO_PODR_SSI_PODR4 (0x10) /* SSI_MCLK */
7813 +
7814 +/* Bit definitions and macros for PODR_FBCTL */
7815 +#define MCF_GPIO_PODR_FBCTL_PODR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */
7816 +#define MCF_GPIO_PODR_FBCTL_PODR1 (0x02) /* FB_RW */
7817 +#define MCF_GPIO_PODR_FBCTL_PODR2 (0x04) /* FB_TA */
7818 +#define MCF_GPIO_PODR_FBCTL_PODR3 (0x08) /* FB_OE */
7819 +
7820 +/* Bit definitions and macros for PODR_BE */
7821 +#define MCF_GPIO_PODR_BE_PODR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */
7822 +#define MCF_GPIO_PODR_BE_PODR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */
7823 +#define MCF_GPIO_PODR_BE_PODR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */
7824 +#define MCF_GPIO_PODR_BE_PODR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */
7825 +
7826 +/* Bit definitions and macros for PODR_CS */
7827 +#define MCF_GPIO_PODR_CS_PODR1 (0x02) /* FB_CS1 */
7828 +#define MCF_GPIO_PODR_CS_PODR2 (0x04) /* FB_CS2 */
7829 +#define MCF_GPIO_PODR_CS_PODR3 (0x08) /* FB_CS3 */
7830 +
7831 +/* Bit definitions and macros for PODR_DMA */
7832 +#define MCF_GPIO_PODR_DMA_PODR0 (0x01) /* DREQ0 */
7833 +#define MCF_GPIO_PODR_DMA_PODR1 (0x02) /* DACK0 / DSPI_PCS3 */
7834 +#define MCF_GPIO_PODR_DMA_PODR2 (0x04) /* DREQ1 / USB_CLKIN */
7835 +#define MCF_GPIO_PODR_DMA_PODR3 (0x08) /* DACK1 / ULPI_DIR */
7836 +
7837 +/* Bit definitions and macros for PODR_FECI2C */
7838 +#define MCF_GPIO_PODR_FECI2C_PODR0 (0x01) /* I2C_SDA / U2RXD */
7839 +#define MCF_GPIO_PODR_FECI2C_PODR1 (0x02) /* I2C_SCL / U2TXD */
7840 +#define MCF_GPIO_PODR_FECI2C_PODR2 (0x04) /* FEC0_MDIO */
7841 +#define MCF_GPIO_PODR_FECI2C_PODR3 (0x08) /* FEC0_MDC */
7842 +#define MCF_GPIO_PODR_FECI2C_PODR4 (0x10) /* FEC1_MDIO / ATA_DIOW */
7843 +#define MCF_GPIO_PODR_FECI2C_PODR5 (0x20) /* FEC1_MDC / ATA_DIOR */
7844 +
7845 +/* Bit definitions and macros for PODR_UART */
7846 +#define MCF_GPIO_PODR_UART_PODR0 (0x01) /* U1TXD */
7847 +#define MCF_GPIO_PODR_UART_PODR1 (0x02) /* U1RXD */
7848 +#define MCF_GPIO_PODR_UART_PODR2 (0x04) /* U1RTS */
7849 +#define MCF_GPIO_PODR_UART_PODR3 (0x08) /* U0CTS */
7850 +#define MCF_GPIO_PODR_UART_PODR4 (0x10) /* U1TXD */
7851 +#define MCF_GPIO_PODR_UART_PODR5 (0x20) /* U1RXD */
7852 +#define MCF_GPIO_PODR_UART_PODR6 (0x40) /* U1RTS */
7853 +#define MCF_GPIO_PODR_UART_PODR7 (0x80) /* U1CTS */
7854 +
7855 +/* Bit definitions and macros for PODR_DSPI */
7856 +#define MCF_GPIO_PODR_DSPI_PODR0 (0x01) /* DSPI_SOUT / SBF_DO */
7857 +#define MCF_GPIO_PODR_DSPI_PODR1 (0x02) /* DSPI_SIN / SBF_DI */
7858 +#define MCF_GPIO_PODR_DSPI_PODR2 (0x04) /* DSPI_SCK / SBF_CK */
7859 +#define MCF_GPIO_PODR_DSPI_PODR3 (0x08) /* DSPI_PCS0/SS */
7860 +#define MCF_GPIO_PODR_DSPI_PODR4 (0x10) /* DSPI_PCS1 / SBF_CS */
7861 +#define MCF_GPIO_PODR_DSPI_PODR5 (0x20) /* DSPI_PCS2 */
7862 +#define MCF_GPIO_PODR_DSPI_PODR6 (0x40) /* DSPI_PCS5/SS */
7863 +
7864 +/* Bit definitions and macros for PODR_TIMER */
7865 +#define MCF_GPIO_PODR_TIMER_PODR0 (0x01) /* T0IN / T0OUT / U2RTS */
7866 +#define MCF_GPIO_PODR_TIMER_PODR1 (0x02) /* T1IN / T1OUT / U2CTS */
7867 +#define MCF_GPIO_PODR_TIMER_PODR2 (0x04) /* T2IN / T2OUT / U2TXD */
7868 +#define MCF_GPIO_PODR_TIMER_PODR3 (0x08) /* T3IN / T3OUT / U2RXD */
7869 +
7870 +/* Bit definitions and macros for PODR_PCI */
7871 +#define MCF_GPIO_PODR_PCI_PODR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */
7872 +#define MCF_GPIO_PODR_PCI_PODR1 (0x02) /* PCI_REQ1 */
7873 +#define MCF_GPIO_PODR_PCI_PODR2 (0x04) /* PCI_REQ2 */
7874 +#define MCF_GPIO_PODR_PCI_PODR3 (0x08) /* PCI_REQ3 / ATA_INTR */
7875 +#define MCF_GPIO_PODR_PCI_PODR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */
7876 +#define MCF_GPIO_PODR_PCI_PODR5 (0x20) /* PCI_GNT1 / */
7877 +#define MCF_GPIO_PODR_PCI_PODR6 (0x40) /* PCI_GNT2 / */
7878 +#define MCF_GPIO_PODR_PCI_PODR7 (0x80) /* PCI_GNT3 / ATA_DMACK */
7879 +
7880 +/* Bit definitions and macros for PODR_USB */
7881 +#define MCF_GPIO_PODR_USB_PODR0 (0x01) /* USB_VBUS_OC / ULPI_STP */
7882 +#define MCF_GPIO_PODR_USB_PODR1 (0x02) /* USB_VBUS_EN / USB_PULLUP
7883 + / ULPI_NXT */
7884 +
7885 +/* Bit definitions and macros for PODR_ATAH */
7886 +#define MCF_GPIO_PODR_ATAH_PODR0 (0x01) /* ATA_DA0 */
7887 +#define MCF_GPIO_PODR_ATAH_PODR1 (0x02) /* ATA_DA1 */
7888 +#define MCF_GPIO_PODR_ATAH_PODR2 (0x04) /* ATA_DA2 */
7889 +#define MCF_GPIO_PODR_ATAH_PODR3 (0x08) /* ATA_CS0 */
7890 +#define MCF_GPIO_PODR_ATAH_PODR4 (0x10) /* ATA_CS1 */
7891 +#define MCF_GPIO_PODR_ATAH_PODR5 (0x20) /* ATA_BUFFER_EN */
7892 +
7893 +/* Bit definitions and macros for PODR_ATAL */
7894 +#define MCF_GPIO_PODR_ATAL_PODR0 (0x01) /* ATA_IORDY */
7895 +#define MCF_GPIO_PODR_ATAL_PODR1 (0x02) /* ATA_DMARQ */
7896 +#define MCF_GPIO_PODR_ATAL_PODR2 (0x04) /* ATA_RESET */
7897 +
7898 +/* Bit definitions and macros for PODR_FEC1H */
7899 +#define MCF_GPIO_PODR_FEC1H_PODR0 (0x01) /* FEC1_CRS / ATA_DATA6 */
7900 +/* FEC1_RXD0 / FEC1_RMII_RXD0 / ATA_DATA13 */
7901 +#define MCF_GPIO_PODR_FEC1H_PODR1 (0x02)
7902 +/* FEC1_RXDV / FEC1_RMII_CRS_DV / ATA_DATA15 */
7903 +#define MCF_GPIO_PODR_FEC1H_PODR2 (0x04)
7904 +#define MCF_GPIO_PODR_FEC1H_PODR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */
7905 +#define MCF_GPIO_PODR_FEC1H_PODR4 (0x10) /* FEC1_COL / ATA_DATA7 */
7906 +/* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */
7907 +#define MCF_GPIO_PODR_FEC1H_PODR5 (0x20)
7908 +/* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */
7909 +#define MCF_GPIO_PODR_FEC1H_PODR6 (0x40)
7910 +/* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
7911 +#define MCF_GPIO_PODR_FEC1H_PODR7 (0x80)
7912 +
7913 +/* Bit definitions and macros for PODR_FEC1L */
7914 +#define MCF_GPIO_PODR_FEC1L_PODR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER
7915 + / ATA_DATA12 */
7916 +#define MCF_GPIO_PODR_FEC1L_PODR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1
7917 + / ATA_DATA14 */
7918 +#define MCF_GPIO_PODR_FEC1L_PODR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */
7919 +#define MCF_GPIO_PODR_FEC1L_PODR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */
7920 +#define MCF_GPIO_PODR_FEC1L_PODR4 (0x10) /* FEC1_TXER / ATA_DATA0 */
7921 +#define MCF_GPIO_PODR_FEC1L_PODR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1
7922 + / ATA_DATA10 */
7923 +#define MCF_GPIO_PODR_FEC1L_PODR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */
7924 +#define MCF_GPIO_PODR_FEC1L_PODR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */
7925 +
7926 +/* Bit definitions and macros for PODR_FBADH */
7927 +#define MCF_GPIO_PODR_FBADH_PODR0 (0x01) /* FB_AD24 */
7928 +#define MCF_GPIO_PODR_FBADH_PODR1 (0x02) /* FB_AD25 */
7929 +#define MCF_GPIO_PODR_FBADH_PODR2 (0x04) /* FB_AD26 */
7930 +#define MCF_GPIO_PODR_FBADH_PODR3 (0x08) /* FB_AD27 */
7931 +#define MCF_GPIO_PODR_FBADH_PODR4 (0x10) /* FB_AD28 */
7932 +#define MCF_GPIO_PODR_FBADH_PODR5 (0x20) /* FB_AD29 */
7933 +#define MCF_GPIO_PODR_FBADH_PODR6 (0x40) /* FB_AD30 */
7934 +#define MCF_GPIO_PODR_FBADH_PODR7 (0x80) /* FB_AD31 */
7935 +
7936 +/* Bit definitions and macros for PODR_FBADMH */
7937 +#define MCF_GPIO_PODR_FBADMH_PODR0 (0x01) /* FB_AD16 */
7938 +#define MCF_GPIO_PODR_FBADMH_PODR1 (0x02) /* FB_AD17 */
7939 +#define MCF_GPIO_PODR_FBADMH_PODR2 (0x04) /* FB_AD18 */
7940 +#define MCF_GPIO_PODR_FBADMH_PODR3 (0x08) /* FB_AD19 */
7941 +#define MCF_GPIO_PODR_FBADMH_PODR4 (0x10) /* FB_AD20 */
7942 +#define MCF_GPIO_PODR_FBADMH_PODR5 (0x20) /* FB_AD21 */
7943 +#define MCF_GPIO_PODR_FBADMH_PODR6 (0x40) /* FB_AD22 */
7944 +#define MCF_GPIO_PODR_FBADMH_PODR7 (0x80) /* FB_AD23 */
7945 +
7946 +/* Bit definitions and macros for PODR_FBADML */
7947 +#define MCF_GPIO_PODR_FBADML_PODR0 (0x01) /* FB_AD8 */
7948 +#define MCF_GPIO_PODR_FBADML_PODR1 (0x02) /* FB_AD9 */
7949 +#define MCF_GPIO_PODR_FBADML_PODR2 (0x04) /* FB_AD10 */
7950 +#define MCF_GPIO_PODR_FBADML_PODR3 (0x08) /* FB_AD11 */
7951 +#define MCF_GPIO_PODR_FBADML_PODR4 (0x10) /* FB_AD12 */
7952 +#define MCF_GPIO_PODR_FBADML_PODR5 (0x20) /* FB_AD13 */
7953 +#define MCF_GPIO_PODR_FBADML_PODR6 (0x40) /* FB_AD14 */
7954 +#define MCF_GPIO_PODR_FBADML_PODR7 (0x80) /* FB_AD15 */
7955 +
7956 +/* Bit definitions and macros for PODR_FBADL */
7957 +#define MCF_GPIO_PODR_FBADL_PODR0 (0x01) /* FB_AD0 */
7958 +#define MCF_GPIO_PODR_FBADL_PODR1 (0x02) /* FB_AD1 */
7959 +#define MCF_GPIO_PODR_FBADL_PODR2 (0x04) /* FB_AD2 */
7960 +#define MCF_GPIO_PODR_FBADL_PODR3 (0x08) /* FB_AD3 */
7961 +#define MCF_GPIO_PODR_FBADL_PODR4 (0x10) /* FB_AD4 */
7962 +#define MCF_GPIO_PODR_FBADL_PODR5 (0x20) /* FB_AD5 */
7963 +#define MCF_GPIO_PODR_FBADL_PODR6 (0x40) /* FB_AD6 */
7964 +#define MCF_GPIO_PODR_FBADL_PODR7 (0x80) /* FB_AD7 */
7965 +
7966 +/* Bit definitions and macros for PDDR_FEC0H */
7967 +#define MCF_GPIO_PDDR_FEC0H_PDDR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */
7968 +#define MCF_GPIO_PDDR_FEC0H_PDDR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */
7969 +#define MCF_GPIO_PDDR_FEC0H_PDDR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */
7970 +#define MCF_GPIO_PDDR_FEC0H_PDDR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */
7971 +#define MCF_GPIO_PDDR_FEC0H_PDDR4 (0x10) /* FEC0_COL / ULPI_DATA7 */
7972 +#define MCF_GPIO_PDDR_FEC0H_PDDR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */
7973 +#define MCF_GPIO_PDDR_FEC0H_PDDR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */
7974 +#define MCF_GPIO_PDDR_FEC0H_PDDR7 (0x80) /* FEC0_TXCLK
7975 + / FEC0_RMII_REF_CLK */
7976 +
7977 +/* Bit definitions and macros for PDDR_FEC0L */
7978 +#define MCF_GPIO_PDDR_FEC0L_PDDR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */
7979 +#define MCF_GPIO_PDDR_FEC0L_PDDR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */
7980 +#define MCF_GPIO_PDDR_FEC0L_PDDR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */
7981 +#define MCF_GPIO_PDDR_FEC0L_PDDR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */
7982 +#define MCF_GPIO_PDDR_FEC0L_PDDR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */
7983 +#define MCF_GPIO_PDDR_FEC0L_PDDR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */
7984 +#define MCF_GPIO_PDDR_FEC0L_PDDR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */
7985 +#define MCF_GPIO_PDDR_FEC0L_PDDR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */
7986 +
7987 +/* Bit definitions and macros for PDDR_SSI */
7988 +#define MCF_GPIO_PDDR_SSI_PDDR0 (0x01) /* SSI_TXD / U1TXD */
7989 +#define MCF_GPIO_PDDR_SSI_PDDR1 (0x02) /* SSI_RXD / U1RXD */
7990 +#define MCF_GPIO_PDDR_SSI_PDDR2 (0x04) /* SSI_FS / U1RTS */
7991 +#define MCF_GPIO_PDDR_SSI_PDDR3 (0x08) /* SSI_BCLK / U1CTS */
7992 +#define MCF_GPIO_PDDR_SSI_PDDR4 (0x10) /* SSI_MCLK */
7993 +
7994 +/* Bit definitions and macros for PDDR_FBCTL */
7995 +#define MCF_GPIO_PDDR_FBCTL_PDDR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */
7996 +#define MCF_GPIO_PDDR_FBCTL_PDDR1 (0x02) /* FB_RW */
7997 +#define MCF_GPIO_PDDR_FBCTL_PDDR2 (0x04) /* FB_TA */
7998 +#define MCF_GPIO_PDDR_FBCTL_PDDR3 (0x08) /* FB_OE */
7999 +
8000 +/* Bit definitions and macros for PDDR_BE */
8001 +#define MCF_GPIO_PDDR_BE_PDDR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */
8002 +#define MCF_GPIO_PDDR_BE_PDDR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */
8003 +#define MCF_GPIO_PDDR_BE_PDDR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */
8004 +#define MCF_GPIO_PDDR_BE_PDDR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */
8005 +
8006 +/* Bit definitions and macros for PDDR_CS */
8007 +#define MCF_GPIO_PDDR_CS_PDDR1 (0x02) /* FB_CS1 */
8008 +#define MCF_GPIO_PDDR_CS_PDDR2 (0x04) /* FB_CS2 */
8009 +#define MCF_GPIO_PDDR_CS_PDDR3 (0x08) /* FB_CS3 */
8010 +
8011 +/* Bit definitions and macros for PDDR_DMA */
8012 +#define MCF_GPIO_PDDR_DMA_PDDR0 (0x01) /* DREQ0 */
8013 +#define MCF_GPIO_PDDR_DMA_PDDR1 (0x02) /* DACK0 / DSPI_PCS3 */
8014 +#define MCF_GPIO_PDDR_DMA_PDDR2 (0x04) /* DREQ1 / USB_CLKIN */
8015 +#define MCF_GPIO_PDDR_DMA_PDDR3 (0x08) /* DACK1 / ULPI_DIR */
8016 +
8017 +/* Bit definitions and macros for PDDR_FECI2C */
8018 +#define MCF_GPIO_PDDR_FECI2C_PDDR0 (0x01) /* I2C_SDA / U2RXD */
8019 +#define MCF_GPIO_PDDR_FECI2C_PDDR1 (0x02) /* I2C_SCL / U2TXD */
8020 +#define MCF_GPIO_PDDR_FECI2C_PDDR2 (0x04) /* FEC0_MDIO */
8021 +#define MCF_GPIO_PDDR_FECI2C_PDDR3 (0x08) /* FEC0_MDC */
8022 +#define MCF_GPIO_PDDR_FECI2C_PDDR4 (0x10) /* FEC1_MDIO / ATA_DIOW */
8023 +#define MCF_GPIO_PDDR_FECI2C_PDDR5 (0x20) /* FEC1_MDC / ATA_DIOR */
8024 +
8025 +/* Bit definitions and macros for PDDR_UART */
8026 +#define MCF_GPIO_PDDR_UART_PDDR0 (0x01) /* U1TXD */
8027 +#define MCF_GPIO_PDDR_UART_PDDR1 (0x02) /* U1RXD */
8028 +#define MCF_GPIO_PDDR_UART_PDDR2 (0x04) /* U1RTS */
8029 +#define MCF_GPIO_PDDR_UART_PDDR3 (0x08) /* U0CTS */
8030 +#define MCF_GPIO_PDDR_UART_PDDR4 (0x10) /* U1TXD */
8031 +#define MCF_GPIO_PDDR_UART_PDDR5 (0x20) /* U1RXD */
8032 +#define MCF_GPIO_PDDR_UART_PDDR6 (0x40) /* U1RTS */
8033 +#define MCF_GPIO_PDDR_UART_PDDR7 (0x80) /* U1CTS */
8034 +
8035 +/* Bit definitions and macros for PDDR_DSPI */
8036 +#define MCF_GPIO_PDDR_DSPI_PDDR0 (0x01) /* DSPI_SOUT / SBF_DO */
8037 +#define MCF_GPIO_PDDR_DSPI_PDDR1 (0x02) /* DSPI_SIN / SBF_DI */
8038 +#define MCF_GPIO_PDDR_DSPI_PDDR2 (0x04) /* DSPI_SCK / SBF_CK */
8039 +#define MCF_GPIO_PDDR_DSPI_PDDR3 (0x08) /* DSPI_PCS0/SS */
8040 +#define MCF_GPIO_PDDR_DSPI_PDDR4 (0x10) /* DSPI_PCS1 / SBF_CS */
8041 +#define MCF_GPIO_PDDR_DSPI_PDDR5 (0x20) /* DSPI_PCS2 */
8042 +#define MCF_GPIO_PDDR_DSPI_PDDR6 (0x40) /* DSPI_PCS5/SS */
8043 +
8044 +/* Bit definitions and macros for PDDR_TIMER */
8045 +#define MCF_GPIO_PDDR_TIMER_PDDR0 (0x01) /* T0IN / T0OUT / U2RTS */
8046 +#define MCF_GPIO_PDDR_TIMER_PDDR1 (0x02) /* T1IN / T1OUT / U2CTS */
8047 +#define MCF_GPIO_PDDR_TIMER_PDDR2 (0x04) /* T2IN / T2OUT / U2TXD */
8048 +#define MCF_GPIO_PDDR_TIMER_PDDR3 (0x08) /* T3IN / T3OUT / U2RXD */
8049 +
8050 +/* Bit definitions and macros for PDDR_PCI */
8051 +#define MCF_GPIO_PDDR_PCI_PDDR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */
8052 +#define MCF_GPIO_PDDR_PCI_PDDR1 (0x02) /* PCI_REQ1 */
8053 +#define MCF_GPIO_PDDR_PCI_PDDR2 (0x04) /* PCI_REQ2 */
8054 +#define MCF_GPIO_PDDR_PCI_PDDR3 (0x08) /* PCI_REQ3 / ATA_INTR */
8055 +#define MCF_GPIO_PDDR_PCI_PDDR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */
8056 +#define MCF_GPIO_PDDR_PCI_PDDR5 (0x20) /* PCI_GNT1 / */
8057 +#define MCF_GPIO_PDDR_PCI_PDDR6 (0x40) /* PCI_GNT2 / */
8058 +#define MCF_GPIO_PDDR_PCI_PDDR7 (0x80) /* PCI_GNT3 / ATA_DMACK */
8059 +
8060 +/* Bit definitions and macros for PDDR_USB */
8061 +#define MCF_GPIO_PDDR_USB_PDDR0 (0x01) /* USB_VBUS_OC / ULPI_STP */
8062 +#define MCF_GPIO_PDDR_USB_PDDR1 (0x02) /* USB_VBUS_EN / USB_PULLUP
8063 + / ULPI_NXT */
8064 +
8065 +/* Bit definitions and macros for PDDR_ATAH */
8066 +#define MCF_GPIO_PDDR_ATAH_PDDR0 (0x01) /* ATA_DA0 */
8067 +#define MCF_GPIO_PDDR_ATAH_PDDR1 (0x02) /* ATA_DA1 */
8068 +#define MCF_GPIO_PDDR_ATAH_PDDR2 (0x04) /* ATA_DA2 */
8069 +#define MCF_GPIO_PDDR_ATAH_PDDR3 (0x08) /* ATA_CS0 */
8070 +#define MCF_GPIO_PDDR_ATAH_PDDR4 (0x10) /* ATA_CS1 */
8071 +#define MCF_GPIO_PDDR_ATAH_PDDR5 (0x20) /* ATA_BUFFER_EN */
8072 +
8073 +/* Bit definitions and macros for PDDR_ATAL */
8074 +#define MCF_GPIO_PDDR_ATAL_PDDR0 (0x01) /* ATA_IORDY */
8075 +#define MCF_GPIO_PDDR_ATAL_PDDR1 (0x02) /* ATA_DMARQ */
8076 +#define MCF_GPIO_PDDR_ATAL_PDDR2 (0x04) /* ATA_RESET */
8077 +
8078 +/* Bit definitions and macros for PDDR_FEC1H */
8079 +#define MCF_GPIO_PDDR_FEC1H_PDDR0 (0x01) /* FEC1_CRS / ATA_DATA6 */
8080 +#define MCF_GPIO_PDDR_FEC1H_PDDR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0
8081 + / ATA_DATA13 */
8082 +#define MCF_GPIO_PDDR_FEC1H_PDDR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV
8083 + / ATA_DATA15 */
8084 +#define MCF_GPIO_PDDR_FEC1H_PDDR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */
8085 +#define MCF_GPIO_PDDR_FEC1H_PDDR4 (0x10) /* FEC1_COL / ATA_DATA7 */
8086 +/* FEC1_TXD0 / FEC1_RMII_TXD0 / ATA_DATA9 */
8087 +#define MCF_GPIO_PDDR_FEC1H_PDDR5 (0x20)
8088 +/* FEC1_TXEN / FEC1_RMII_TXEN / ATA_DATA8 */
8089 +#define MCF_GPIO_PDDR_FEC1H_PDDR6 (0x40)
8090 +/* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
8091 +#define MCF_GPIO_PDDR_FEC1H_PDDR7 (0x80)
8092 +
8093 +/* Bit definitions and macros for PDDR_FEC1L */
8094 +#define MCF_GPIO_PDDR_FEC1L_PDDR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER
8095 + / ATA_DATA12 */
8096 +#define MCF_GPIO_PDDR_FEC1L_PDDR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1
8097 + / ATA_DATA14 */
8098 +#define MCF_GPIO_PDDR_FEC1L_PDDR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */
8099 +#define MCF_GPIO_PDDR_FEC1L_PDDR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */
8100 +#define MCF_GPIO_PDDR_FEC1L_PDDR4 (0x10) /* FEC1_TXER / ATA_DATA0 */
8101 +#define MCF_GPIO_PDDR_FEC1L_PDDR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1
8102 + / ATA_DATA10 */
8103 +#define MCF_GPIO_PDDR_FEC1L_PDDR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */
8104 +#define MCF_GPIO_PDDR_FEC1L_PDDR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */
8105 +
8106 +/* Bit definitions and macros for PDDR_FBADH */
8107 +#define MCF_GPIO_PDDR_FBADH_PDDR0 (0x01) /* FB_AD24 */
8108 +#define MCF_GPIO_PDDR_FBADH_PDDR1 (0x02) /* FB_AD25 */
8109 +#define MCF_GPIO_PDDR_FBADH_PDDR2 (0x04) /* FB_AD26 */
8110 +#define MCF_GPIO_PDDR_FBADH_PDDR3 (0x08) /* FB_AD27 */
8111 +#define MCF_GPIO_PDDR_FBADH_PDDR4 (0x10) /* FB_AD28 */
8112 +#define MCF_GPIO_PDDR_FBADH_PDDR5 (0x20) /* FB_AD29 */
8113 +#define MCF_GPIO_PDDR_FBADH_PDDR6 (0x40) /* FB_AD30 */
8114 +#define MCF_GPIO_PDDR_FBADH_PDDR7 (0x80) /* FB_AD31 */
8115 +
8116 +/* Bit definitions and macros for PDDR_FBADMH */
8117 +#define MCF_GPIO_PDDR_FBADMH_PDDR0 (0x01) /* FB_AD16 */
8118 +#define MCF_GPIO_PDDR_FBADMH_PDDR1 (0x02) /* FB_AD17 */
8119 +#define MCF_GPIO_PDDR_FBADMH_PDDR2 (0x04) /* FB_AD18 */
8120 +#define MCF_GPIO_PDDR_FBADMH_PDDR3 (0x08) /* FB_AD19 */
8121 +#define MCF_GPIO_PDDR_FBADMH_PDDR4 (0x10) /* FB_AD20 */
8122 +#define MCF_GPIO_PDDR_FBADMH_PDDR5 (0x20) /* FB_AD21 */
8123 +#define MCF_GPIO_PDDR_FBADMH_PDDR6 (0x40) /* FB_AD22 */
8124 +#define MCF_GPIO_PDDR_FBADMH_PDDR7 (0x80) /* FB_AD23 */
8125 +
8126 +/* Bit definitions and macros for PDDR_FBADML */
8127 +#define MCF_GPIO_PDDR_FBADML_PDDR0 (0x01) /* FB_AD8 */
8128 +#define MCF_GPIO_PDDR_FBADML_PDDR1 (0x02) /* FB_AD9 */
8129 +#define MCF_GPIO_PDDR_FBADML_PDDR2 (0x04) /* FB_AD10 */
8130 +#define MCF_GPIO_PDDR_FBADML_PDDR3 (0x08) /* FB_AD11 */
8131 +#define MCF_GPIO_PDDR_FBADML_PDDR4 (0x10) /* FB_AD12 */
8132 +#define MCF_GPIO_PDDR_FBADML_PDDR5 (0x20) /* FB_AD13 */
8133 +#define MCF_GPIO_PDDR_FBADML_PDDR6 (0x40) /* FB_AD14 */
8134 +#define MCF_GPIO_PDDR_FBADML_PDDR7 (0x80) /* FB_AD15 */
8135 +
8136 +/* Bit definitions and macros for PDDR_FBADL */
8137 +#define MCF_GPIO_PDDR_FBADL_PDDR0 (0x01) /* FB_AD0 */
8138 +#define MCF_GPIO_PDDR_FBADL_PDDR1 (0x02) /* FB_AD1 */
8139 +#define MCF_GPIO_PDDR_FBADL_PDDR2 (0x04) /* FB_AD2 */
8140 +#define MCF_GPIO_PDDR_FBADL_PDDR3 (0x08) /* FB_AD3 */
8141 +#define MCF_GPIO_PDDR_FBADL_PDDR4 (0x10) /* FB_AD4 */
8142 +#define MCF_GPIO_PDDR_FBADL_PDDR5 (0x20) /* FB_AD5 */
8143 +#define MCF_GPIO_PDDR_FBADL_PDDR6 (0x40) /* FB_AD6 */
8144 +#define MCF_GPIO_PDDR_FBADL_PDDR7 (0x80) /* FB_AD7 */
8145 +
8146 +/* Bit definitions and macros for PPDSDR_FEC0H */
8147 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */
8148 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */
8149 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR2 (0x04) /* FEC0_RXDV
8150 + / FEC0_RMII_CRS_DV */
8151 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */
8152 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR4 (0x10) /* FEC0_COL / ULPI_DATA7 */
8153 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */
8154 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */
8155 +#define MCF_GPIO_PPDSDR_FEC0H_PPDR7 (0x80) /* FEC0_TXCLK
8156 + / FEC0_RMII_REF_CLK */
8157 +
8158 +/* Bit definitions and macros for PPDSDR_FEC0L */
8159 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */
8160 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */
8161 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */
8162 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */
8163 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */
8164 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */
8165 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */
8166 +#define MCF_GPIO_PPDSDR_FEC0L_PCLRR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */
8167 +
8168 +/* Bit definitions and macros for PPDSDR_SSI */
8169 +#define MCF_GPIO_PPDSDR_SSI_PPDR0 (0x01) /* SSI_TXD / U1TXD */
8170 +#define MCF_GPIO_PPDSDR_SSI_PPDR1 (0x02) /* SSI_RXD / U1RXD */
8171 +#define MCF_GPIO_PPDSDR_SSI_PPDR2 (0x04) /* SSI_FS / U1RTS */
8172 +#define MCF_GPIO_PPDSDR_SSI_PPDR3 (0x08) /* SSI_BCLK / U1CTS */
8173 +#define MCF_GPIO_PPDSDR_SSI_PPDR4 (0x10) /* SSI_MCLK */
8174 +
8175 +/* Bit definitions and macros for PPDSDR_FBCTL */
8176 +#define MCF_GPIO_PPDSDR_FBCTL_PPDR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */
8177 +#define MCF_GPIO_PPDSDR_FBCTL_PPDR1 (0x02) /* FB_RW */
8178 +#define MCF_GPIO_PPDSDR_FBCTL_PPDR2 (0x04) /* FB_TA */
8179 +#define MCF_GPIO_PPDSDR_FBCTL_PPDR3 (0x08) /* FB_OE */
8180 +
8181 +/* Bit definitions and macros for PPDSDR_BE */
8182 +#define MCF_GPIO_PPDSDR_BE_PPDR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */
8183 +#define MCF_GPIO_PPDSDR_BE_PPDR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */
8184 +#define MCF_GPIO_PPDSDR_BE_PPDR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */
8185 +#define MCF_GPIO_PPDSDR_BE_PPDR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */
8186 +
8187 +/* Bit definitions and macros for PPDSDR_CS */
8188 +#define MCF_GPIO_PPDSDR_CS_PPDR1 (0x02) /* FB_CS1 */
8189 +#define MCF_GPIO_PPDSDR_CS_PPDR2 (0x04) /* FB_CS2 */
8190 +#define MCF_GPIO_PPDSDR_CS_PPDR3 (0x08) /* FB_CS3 */
8191 +
8192 +/* Bit definitions and macros for PPDSDR_DMA */
8193 +#define MCF_GPIO_PPDSDR_DMA_PPDR0 (0x01) /* DREQ0 */
8194 +#define MCF_GPIO_PPDSDR_DMA_PPDR1 (0x02) /* DACK0 / DSPI_PCS3 */
8195 +#define MCF_GPIO_PPDSDR_DMA_PPDR2 (0x04) /* DREQ1 / USB_CLKIN */
8196 +#define MCF_GPIO_PPDSDR_DMA_PPDR3 (0x08) /* DACK1 / ULPI_DIR */
8197 +
8198 +/* Bit definitions and macros for PPDSDR_FECI2C */
8199 +#define MCF_GPIO_PPDSDR_FECI2C_PPDR0 (0x01) /* I2C_SDA / U2RXD */
8200 +#define MCF_GPIO_PPDSDR_FECI2C_PPDR1 (0x02) /* I2C_SCL / U2TXD */
8201 +#define MCF_GPIO_PPDSDR_FECI2C_PPDR2 (0x04) /* FEC0_MDIO */
8202 +#define MCF_GPIO_PPDSDR_FECI2C_PPDR3 (0x08) /* FEC0_MDC */
8203 +#define MCF_GPIO_PPDSDR_FECI2C_PPDR4 (0x10) /* FEC1_MDIO / ATA_DIOW */
8204 +#define MCF_GPIO_PPDSDR_FECI2C_PPDR5 (0x20) /* FEC1_MDC / ATA_DIOR */
8205 +
8206 +/* Bit definitions and macros for PPDSDR_UART */
8207 +#define MCF_GPIO_PPDSDR_UART_PPDR0 (0x01) /* U1TXD */
8208 +#define MCF_GPIO_PPDSDR_UART_PPDR1 (0x02) /* U1RXD */
8209 +#define MCF_GPIO_PPDSDR_UART_PPDR2 (0x04) /* U1RTS */
8210 +#define MCF_GPIO_PPDSDR_UART_PPDR3 (0x08) /* U0CTS */
8211 +#define MCF_GPIO_PPDSDR_UART_PPDR4 (0x10) /* U1TXD */
8212 +#define MCF_GPIO_PPDSDR_UART_PPDR5 (0x20) /* U1RXD */
8213 +#define MCF_GPIO_PPDSDR_UART_PPDR6 (0x40) /* U1RTS */
8214 +#define MCF_GPIO_PPDSDR_UART_PPDR7 (0x80) /* U1CTS */
8215 +
8216 +/* Bit definitions and macros for PPDSDR_DSPI */
8217 +#define MCF_GPIO_PPDSDR_DSPI_PPDR0 (0x01) /* DSPI_SOUT / SBF_DO */
8218 +#define MCF_GPIO_PPDSDR_DSPI_PPDR1 (0x02) /* DSPI_SIN / SBF_DI */
8219 +#define MCF_GPIO_PPDSDR_DSPI_PPDR2 (0x04) /* DSPI_SCK / SBF_CK */
8220 +#define MCF_GPIO_PPDSDR_DSPI_PPDR3 (0x08) /* DSPI_PCS0/SS */
8221 +#define MCF_GPIO_PPDSDR_DSPI_PPDR4 (0x10) /* DSPI_PCS1 / SBF_CS */
8222 +#define MCF_GPIO_PPDSDR_DSPI_PPDR5 (0x20) /* DSPI_PCS2 */
8223 +#define MCF_GPIO_PPDSDR_DSPI_PPDR6 (0x40) /* DSPI_PCS5/SS */
8224 +
8225 +/* Bit definitions and macros for PPDSDR_TIMER */
8226 +#define MCF_GPIO_PPDSDR_TIMER_PPDR0 (0x01) /* T0IN / T0OUT / U2RTS */
8227 +#define MCF_GPIO_PPDSDR_TIMER_PPDR1 (0x02) /* T1IN / T1OUT / U2CTS */
8228 +#define MCF_GPIO_PPDSDR_TIMER_PPDR2 (0x04) /* T2IN / T2OUT / U2TXD */
8229 +#define MCF_GPIO_PPDSDR_TIMER_PPDR3 (0x08) /* T3IN / T3OUT / U2RXD */
8230 +
8231 +/* Bit definitions and macros for PPDSDR_PCI */
8232 +#define MCF_GPIO_PPDSDR_PCI_PPDR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */
8233 +#define MCF_GPIO_PPDSDR_PCI_PPDR1 (0x02) /* PCI_REQ1 */
8234 +#define MCF_GPIO_PPDSDR_PCI_PPDR2 (0x04) /* PCI_REQ2 */
8235 +#define MCF_GPIO_PPDSDR_PCI_PPDR3 (0x08) /* PCI_REQ3 / ATA_INTR */
8236 +#define MCF_GPIO_PPDSDR_PCI_PPDR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */
8237 +#define MCF_GPIO_PPDSDR_PCI_PPDR5 (0x20) /* PCI_GNT1 / */
8238 +#define MCF_GPIO_PPDSDR_PCI_PPDR6 (0x40) /* PCI_GNT2 / */
8239 +#define MCF_GPIO_PPDSDR_PCI_PPDR7 (0x80) /* PCI_GNT3 / ATA_DMACK */
8240 +
8241 +/* Bit definitions and macros for PPDSDR_USB */
8242 +#define MCF_GPIO_PPDSDR_USB_PPDR0 (0x01) /* USB_VBUS_OC / ULPI_STP */
8243 +#define MCF_GPIO_PPDSDR_USB_PPDR1 (0x02) /* USB_VBUS_EN / USB_PULLUP
8244 + / ULPI_NXT */
8245 +
8246 +/* Bit definitions and macros for PPDSDR_ATAH */
8247 +#define MCF_GPIO_PPDSDR_ATAH_PPDR0 (0x01) /* ATA_DA0 */
8248 +#define MCF_GPIO_PPDSDR_ATAH_PPDR1 (0x02) /* ATA_DA1 */
8249 +#define MCF_GPIO_PPDSDR_ATAH_PPDR2 (0x04) /* ATA_DA2 */
8250 +#define MCF_GPIO_PPDSDR_ATAH_PPDR3 (0x08) /* ATA_CS0 */
8251 +#define MCF_GPIO_PPDSDR_ATAH_PPDR4 (0x10) /* ATA_CS1 */
8252 +#define MCF_GPIO_PPDSDR_ATAH_PPDR5 (0x20) /* ATA_BUFFER_EN */
8253 +
8254 +/* Bit definitions and macros for PPDSDR_ATAL */
8255 +#define MCF_GPIO_PPDSDR_ATAL_PPDR0 (0x01) /* ATA_IORDY */
8256 +#define MCF_GPIO_PPDSDR_ATAL_PPDR1 (0x02) /* ATA_DMARQ */
8257 +#define MCF_GPIO_PPDSDR_ATAL_PPDR2 (0x04) /* ATA_RESET */
8258 +
8259 +/* Bit definitions and macros for PPDSDR_FEC1H */
8260 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR0 (0x01) /* FEC1_CRS / ATA_DATA6 */
8261 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0
8262 + / ATA_DATA13 */
8263 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV
8264 + / ATA_DATA15 */
8265 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */
8266 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR4 (0x10) /* FEC1_COL / ATA_DATA7 */
8267 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0
8268 + / ATA_DATA9 */
8269 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN
8270 + / ATA_DATA8 */
8271 +/* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
8272 +#define MCF_GPIO_PPDSDR_FEC1H_PPDR7 (0x80)
8273 +
8274 +/* Bit definitions and macros for PPDSDR_FEC1L */
8275 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER
8276 + / ATA_DATA12 */
8277 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1
8278 + / ATA_DATA14 */
8279 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */
8280 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */
8281 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR4 (0x10) /* FEC1_TXER / ATA_DATA0 */
8282 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1
8283 + / ATA_DATA10 */
8284 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */
8285 +#define MCF_GPIO_PPDSDR_FEC1L_PPDR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */
8286 +
8287 +/* Bit definitions and macros for PPDSDR_FBADH */
8288 +#define MCF_GPIO_PPDSDR_FBADH_PPDR0 (0x01) /* FB_AD24 */
8289 +#define MCF_GPIO_PPDSDR_FBADH_PPDR1 (0x02) /* FB_AD25 */
8290 +#define MCF_GPIO_PPDSDR_FBADH_PPDR2 (0x04) /* FB_AD26 */
8291 +#define MCF_GPIO_PPDSDR_FBADH_PPDR3 (0x08) /* FB_AD27 */
8292 +#define MCF_GPIO_PPDSDR_FBADH_PPDR4 (0x10) /* FB_AD28 */
8293 +#define MCF_GPIO_PPDSDR_FBADH_PPDR5 (0x20) /* FB_AD29 */
8294 +#define MCF_GPIO_PPDSDR_FBADH_PPDR6 (0x40) /* FB_AD30 */
8295 +#define MCF_GPIO_PPDSDR_FBADH_PPDR7 (0x80) /* FB_AD31 */
8296 +
8297 +/* Bit definitions and macros for PPDSDR_FBADMH */
8298 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR0 (0x01) /* FB_AD16 */
8299 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR1 (0x02) /* FB_AD17 */
8300 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR2 (0x04) /* FB_AD18 */
8301 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR3 (0x08) /* FB_AD19 */
8302 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR4 (0x10) /* FB_AD20 */
8303 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR5 (0x20) /* FB_AD21 */
8304 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR6 (0x40) /* FB_AD22 */
8305 +#define MCF_GPIO_PPDSDR_FBADMH_PPDR7 (0x80) /* FB_AD23 */
8306 +
8307 +/* Bit definitions and macros for PPDSDR_FBADML */
8308 +#define MCF_GPIO_PPDSDR_FBADML_PPDR0 (0x01) /* FB_AD8 */
8309 +#define MCF_GPIO_PPDSDR_FBADML_PPDR1 (0x02) /* FB_AD9 */
8310 +#define MCF_GPIO_PPDSDR_FBADML_PPDR2 (0x04) /* FB_AD10 */
8311 +#define MCF_GPIO_PPDSDR_FBADML_PPDR3 (0x08) /* FB_AD11 */
8312 +#define MCF_GPIO_PPDSDR_FBADML_PPDR4 (0x10) /* FB_AD12 */
8313 +#define MCF_GPIO_PPDSDR_FBADML_PPDR5 (0x20) /* FB_AD13 */
8314 +#define MCF_GPIO_PPDSDR_FBADML_PPDR6 (0x40) /* FB_AD14 */
8315 +#define MCF_GPIO_PPDSDR_FBADML_PPDR7 (0x80) /* FB_AD15 */
8316 +
8317 +/* Bit definitions and macros for PPDSDR_FBADL */
8318 +#define MCF_GPIO_PPDSDR_FBADL_PPDR0 (0x01) /* FB_AD0 */
8319 +#define MCF_GPIO_PPDSDR_FBADL_PPDR1 (0x02) /* FB_AD1 */
8320 +#define MCF_GPIO_PPDSDR_FBADL_PPDR2 (0x04) /* FB_AD2 */
8321 +#define MCF_GPIO_PPDSDR_FBADL_PPDR3 (0x08) /* FB_AD3 */
8322 +#define MCF_GPIO_PPDSDR_FBADL_PPDR4 (0x10) /* FB_AD4 */
8323 +#define MCF_GPIO_PPDSDR_FBADL_PPDR5 (0x20) /* FB_AD5 */
8324 +#define MCF_GPIO_PPDSDR_FBADL_PPDR6 (0x40) /* FB_AD6 */
8325 +#define MCF_GPIO_PPDSDR_FBADL_PPDR7 (0x80) /* FB_AD7 */
8326 +
8327 +/* Bit definitions and macros for PCLRR_FEC0H */
8328 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR0 (0x01) /* FEC0_CRS / ULPI_DATA6 */
8329 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR1 (0x02) /* FEC0_RXD0 / FEC0_RMII_RXD0 */
8330 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR2 (0x04) /* FEC0_RXDV/FEC0_RMII_CRS_DV */
8331 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR3 (0x08) /* FEC0_RXCLK / ULPI_DATA1 */
8332 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR4 (0x10) /* FEC0_COL / ULPI_DATA7 */
8333 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR5 (0x20) /* FEC0_TXD0 / FEC0_RMII_TXD0 */
8334 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR6 (0x40) /* FEC0_TXEN / FEC0_RMII_TXEN */
8335 +#define MCF_GPIO_PCLRR_FEC0H_PCLRR7 (0x80) /* FEC0_TXCLK
8336 + / FEC0_RMII_REF_CLK */
8337 +
8338 +/* Bit definitions and macros for PCLRR_FEC0L */
8339 +#define MCF_GPIO_PCLRR_FEC0L_PPDR0 (0x01) /* FEC0_RXER / FEC0_RMII_RXER */
8340 +#define MCF_GPIO_PCLRR_FEC0L_PPDR1 (0x02) /* FEC0_RXD1 / FEC0_RMII_RXD1 */
8341 +#define MCF_GPIO_PCLRR_FEC0L_PPDR2 (0x04) /* FEC0_RXD2 / ULPI_DATA4 */
8342 +#define MCF_GPIO_PCLRR_FEC0L_PPDR3 (0x08) /* FEC0_RXD3 / ULPI_DATA5 */
8343 +#define MCF_GPIO_PCLRR_FEC0L_PPDR4 (0x10) /* FEC0_TXER / ULPI_DATA0 */
8344 +#define MCF_GPIO_PCLRR_FEC0L_PPDR5 (0x20) /* FEC0_TXD1 / FEC0_RMII_TXD1 */
8345 +#define MCF_GPIO_PCLRR_FEC0L_PPDR6 (0x40) /* FEC0_TXD2 / ULPI_DATA2 */
8346 +#define MCF_GPIO_PCLRR_FEC0L_PPDR7 (0x80) /* FEC0_TXD3 / ULPI_DATA3 */
8347 +
8348 +/* Bit definitions and macros for PCLRR_SSI */
8349 +#define MCF_GPIO_PCLRR_SSI_PCLRR0 (0x01) /* SSI_TXD / U1TXD */
8350 +#define MCF_GPIO_PCLRR_SSI_PCLRR1 (0x02) /* SSI_RXD / U1RXD */
8351 +#define MCF_GPIO_PCLRR_SSI_PCLRR2 (0x04) /* SSI_FS / U1RTS */
8352 +#define MCF_GPIO_PCLRR_SSI_PCLRR3 (0x08) /* SSI_BCLK / U1CTS */
8353 +#define MCF_GPIO_PCLRR_SSI_PCLRR4 (0x10) /* SSI_MCLK */
8354 +
8355 +/* Bit definitions and macros for PCLRR_FBCTL */
8356 +#define MCF_GPIO_PCLRR_FBCTL_PCLRR0 (0x01) /* FB_TS / FB_ALE / FB_TBST */
8357 +#define MCF_GPIO_PCLRR_FBCTL_PCLRR1 (0x02) /* FB_RW */
8358 +#define MCF_GPIO_PCLRR_FBCTL_PCLRR2 (0x04) /* FB_TA */
8359 +#define MCF_GPIO_PCLRR_FBCTL_PCLRR3 (0x08) /* FB_OE */
8360 +
8361 +/* Bit definitions and macros for PCLRR_BE */
8362 +#define MCF_GPIO_PCLRR_BE_PCLRR0 (0x01) /* FB_BE/BWE0 / FB_SIZ0 */
8363 +#define MCF_GPIO_PCLRR_BE_PCLRR1 (0x02) /* FB_BE/BWE1 / FB_SIZ1 */
8364 +#define MCF_GPIO_PCLRR_BE_PCLRR2 (0x04) /* FB_BE/BWE2 / FB_SIZ2 */
8365 +#define MCF_GPIO_PCLRR_BE_PCLRR3 (0x08) /* FB_BE/BWE3 / FB_SIZ3 */
8366 +
8367 +/* Bit definitions and macros for PCLRR_CS */
8368 +#define MCF_GPIO_PCLRR_CS_PCLRR1 (0x02) /* FB_CS1 */
8369 +#define MCF_GPIO_PCLRR_CS_PCLRR2 (0x04) /* FB_CS2 */
8370 +#define MCF_GPIO_PCLRR_CS_PCLRR3 (0x08) /* FB_CS3 */
8371 +
8372 +/* Bit definitions and macros for PCLRR_DMA */
8373 +#define MCF_GPIO_PCLRR_DMA_PCLRR0 (0x01) /* DREQ0 */
8374 +#define MCF_GPIO_PCLRR_DMA_PCLRR1 (0x02) /* DACK0 / DSPI_PCS3 */
8375 +#define MCF_GPIO_PCLRR_DMA_PCLRR2 (0x04) /* DREQ1 / USB_CLKIN */
8376 +#define MCF_GPIO_PCLRR_DMA_PCLRR3 (0x08) /* DACK1 / ULPI_DIR */
8377 +
8378 +/* Bit definitions and macros for PCLRR_FECI2C */
8379 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR0 (0x01) /* I2C_SDA / U2RXD */
8380 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR1 (0x02) /* I2C_SCL / U2TXD */
8381 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR2 (0x04) /* FEC0_MDIO */
8382 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR3 (0x08) /* FEC0_MDC */
8383 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR4 (0x10) /* FEC1_MDIO / ATA_DIOW */
8384 +#define MCF_GPIO_PCLRR_FECI2C_PCLRR5 (0x20) /* FEC1_MDC / ATA_DIOR */
8385 +
8386 +/* Bit definitions and macros for PCLRR_UART */
8387 +#define MCF_GPIO_PCLRR_UART_PCLRR0 (0x01) /* U1TXD */
8388 +#define MCF_GPIO_PCLRR_UART_PCLRR1 (0x02) /* U1RXD */
8389 +#define MCF_GPIO_PCLRR_UART_PCLRR2 (0x04) /* U1RTS */
8390 +#define MCF_GPIO_PCLRR_UART_PCLRR3 (0x08) /* U0CTS */
8391 +#define MCF_GPIO_PCLRR_UART_PCLRR4 (0x10) /* U1TXD */
8392 +#define MCF_GPIO_PCLRR_UART_PCLRR5 (0x20) /* U1RXD */
8393 +#define MCF_GPIO_PCLRR_UART_PCLRR6 (0x40) /* U1RTS */
8394 +#define MCF_GPIO_PCLRR_UART_PCLRR7 (0x80) /* U1CTS */
8395 +
8396 +/* Bit definitions and macros for PCLRR_DSPI */
8397 +#define MCF_GPIO_PCLRR_DSPI_PCLRR0 (0x01) /* DSPI_SOUT / SBF_DO */
8398 +#define MCF_GPIO_PCLRR_DSPI_PCLRR1 (0x02) /* DSPI_SIN / SBF_DI */
8399 +#define MCF_GPIO_PCLRR_DSPI_PCLRR2 (0x04) /* DSPI_SCK / SBF_CK */
8400 +#define MCF_GPIO_PCLRR_DSPI_PCLRR3 (0x08) /* DSPI_PCS0/SS */
8401 +#define MCF_GPIO_PCLRR_DSPI_PCLRR4 (0x10) /* DSPI_PCS1 / SBF_CS */
8402 +#define MCF_GPIO_PCLRR_DSPI_PCLRR5 (0x20) /* DSPI_PCS2 */
8403 +#define MCF_GPIO_PCLRR_DSPI_PCLRR6 (0x40) /* DSPI_PCS5/SS */
8404 +
8405 +/* Bit definitions and macros for PCLRR_TIMER */
8406 +#define MCF_GPIO_PCLRR_TIMER_PCLRR0 (0x01) /* T0IN / T0OUT / U2RTS */
8407 +#define MCF_GPIO_PCLRR_TIMER_PCLRR1 (0x02) /* T1IN / T1OUT / U2CTS */
8408 +#define MCF_GPIO_PCLRR_TIMER_PCLRR2 (0x04) /* T2IN / T2OUT / U2TXD */
8409 +#define MCF_GPIO_PCLRR_TIMER_PCLRR3 (0x08) /* T3IN / T3OUT / U2RXD */
8410 +
8411 +/* Bit definitions and macros for PCLRR_PCI */
8412 +#define MCF_GPIO_PCLRR_PCI_PCLRR0 (0x01) /* PCI_REQ0/PCI_EXTGNT */
8413 +#define MCF_GPIO_PCLRR_PCI_PCLRR1 (0x02) /* PCI_REQ1 */
8414 +#define MCF_GPIO_PCLRR_PCI_PCLRR2 (0x04) /* PCI_REQ2 */
8415 +#define MCF_GPIO_PCLRR_PCI_PCLRR3 (0x08) /* PCI_REQ3 / ATA_INTR */
8416 +#define MCF_GPIO_PCLRR_PCI_PCLRR4 (0x10) /* PCI_GNT0/PCI_EXTREQ */
8417 +#define MCF_GPIO_PCLRR_PCI_PCLRR5 (0x20) /* PCI_GNT1 / */
8418 +#define MCF_GPIO_PCLRR_PCI_PCLRR6 (0x40) /* PCI_GNT2 / */
8419 +#define MCF_GPIO_PCLRR_PCI_PCLRR7 (0x80) /* PCI_GNT3 / ATA_DMACK */
8420 +
8421 +/* Bit definitions and macros for PCLRR_USB */
8422 +#define MCF_GPIO_PCLRR_USB_PCLRR0 (0x01) /* USB_VBUS_OC / ULPI_STP */
8423 +#define MCF_GPIO_PCLRR_USB_PCLRR1 (0x02) /* USB_VBUS_EN / USB_PULLUP
8424 + / ULPI_NXT */
8425 +
8426 +/* Bit definitions and macros for PCLRR_ATAH */
8427 +#define MCF_GPIO_PCLRR_ATAH_PCLRR0 (0x01) /* ATA_DA0 */
8428 +#define MCF_GPIO_PCLRR_ATAH_PCLRR1 (0x02) /* ATA_DA1 */
8429 +#define MCF_GPIO_PCLRR_ATAH_PCLRR2 (0x04) /* ATA_DA2 */
8430 +#define MCF_GPIO_PCLRR_ATAH_PCLRR3 (0x08) /* ATA_CS0 */
8431 +#define MCF_GPIO_PCLRR_ATAH_PCLRR4 (0x10) /* ATA_CS1 */
8432 +#define MCF_GPIO_PCLRR_ATAH_PCLRR5 (0x20) /* ATA_BUFFER_EN */
8433 +
8434 +/* Bit definitions and macros for PCLRR_ATAL */
8435 +#define MCF_GPIO_PCLRR_ATAL_PCLRR0 (0x01) /* ATA_IORDY */
8436 +#define MCF_GPIO_PCLRR_ATAL_PCLRR1 (0x02) /* ATA_DMARQ */
8437 +#define MCF_GPIO_PCLRR_ATAL_PCLRR2 (0x04) /* ATA_RESET */
8438 +
8439 +/* Bit definitions and macros for PCLRR_FEC1H */
8440 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR0 (0x01) /* FEC1_CRS / ATA_DATA6 */
8441 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR1 (0x02) /* FEC1_RXD0 / FEC1_RMII_RXD0
8442 + /ATA_DATA13 */
8443 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR2 (0x04) /* FEC1_RXDV / FEC1_RMII_CRS_DV
8444 + / ATA_DATA15 */
8445 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR3 (0x08) /* FEC1_RXCLK / ATA_DATA5 */
8446 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR4 (0x10) /* FEC1_COL / ATA_DATA7 */
8447 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR5 (0x20) /* FEC1_TXD0 / FEC1_RMII_TXD0
8448 + / ATA_DATA9 */
8449 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR6 (0x40) /* FEC1_TXEN / FEC1_RMII_TXEN
8450 + / ATA_DATA8 */
8451 +/* FEC1_TXCLK / FEC1_RMII_REF_CLK / ATA_DATA11 */
8452 +#define MCF_GPIO_PCLRR_FEC1H_PCLRR7 (0x80)
8453 +
8454 +/* Bit definitions and macros for PCLRR_FEC1L */
8455 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR0 (0x01) /* FEC1_RXER / FEC1_RMII_RXER
8456 + / ATA_DATA12 */
8457 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR1 (0x02) /* FEC1_RXD1 / FEC1_RMII_RXD1
8458 + / ATA_DATA14 */
8459 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR2 (0x04) /* FEC1_RXD2 / ATA_DATA3 */
8460 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR3 (0x08) /* FEC1_RXD3 / ATA_DATA4 */
8461 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR4 (0x10) /* FEC1_TXER / ATA_DATA0 */
8462 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR5 (0x20) /* FEC1_TXD1 / FEC1_RMII_TXD1
8463 + / ATA_DATA10 */
8464 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR6 (0x40) /* FEC1_TXD2 / ATA_DATA1 */
8465 +#define MCF_GPIO_PCLRR_FEC1L_PCLRR7 (0x80) /* FEC1_TXD3 / ATA_DATA2 */
8466 +
8467 +/* Bit definitions and macros for PCLRR_FBADH */
8468 +#define MCF_GPIO_PCLRR_FBADH_PCLRR0 (0x01) /* FB_AD24 */
8469 +#define MCF_GPIO_PCLRR_FBADH_PCLRR1 (0x02) /* FB_AD25 */
8470 +#define MCF_GPIO_PCLRR_FBADH_PCLRR2 (0x04) /* FB_AD26 */
8471 +#define MCF_GPIO_PCLRR_FBADH_PCLRR3 (0x08) /* FB_AD27 */
8472 +#define MCF_GPIO_PCLRR_FBADH_PCLRR4 (0x10) /* FB_AD28 */
8473 +#define MCF_GPIO_PCLRR_FBADH_PCLRR5 (0x20) /* FB_AD29 */
8474 +#define MCF_GPIO_PCLRR_FBADH_PCLRR6 (0x40) /* FB_AD30 */
8475 +#define MCF_GPIO_PCLRR_FBADH_PCLRR7 (0x80) /* FB_AD31 */
8476 +
8477 +/* Bit definitions and macros for PCLRR_FBADMH */
8478 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR0 (0x01) /* FB_AD16 */
8479 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR1 (0x02) /* FB_AD17 */
8480 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR2 (0x04) /* FB_AD18 */
8481 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR3 (0x08) /* FB_AD19 */
8482 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR4 (0x10) /* FB_AD20 */
8483 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR5 (0x20) /* FB_AD21 */
8484 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR6 (0x40) /* FB_AD22 */
8485 +#define MCF_GPIO_PCLRR_FBADMH_PCLRR7 (0x80) /* FB_AD23 */
8486 +
8487 +/* Bit definitions and macros for PCLRR_FBADML */
8488 +#define MCF_GPIO_PCLRR_FBADML_PCLRR0 (0x01) /* FB_AD8 */
8489 +#define MCF_GPIO_PCLRR_FBADML_PCLRR1 (0x02) /* FB_AD9 */
8490 +#define MCF_GPIO_PCLRR_FBADML_PCLRR2 (0x04) /* FB_AD10 */
8491 +#define MCF_GPIO_PCLRR_FBADML_PCLRR3 (0x08) /* FB_AD11 */
8492 +#define MCF_GPIO_PCLRR_FBADML_PCLRR4 (0x10) /* FB_AD12 */
8493 +#define MCF_GPIO_PCLRR_FBADML_PCLRR5 (0x20) /* FB_AD13 */
8494 +#define MCF_GPIO_PCLRR_FBADML_PCLRR6 (0x40) /* FB_AD14 */
8495 +#define MCF_GPIO_PCLRR_FBADML_PCLRR7 (0x80) /* FB_AD15 */
8496 +
8497 +/* Bit definitions and macros for PCLRR_FBADL */
8498 +#define MCF_GPIO_PCLRR_FBADL_PCLRR0 (0x01) /* FB_AD0 */
8499 +#define MCF_GPIO_PCLRR_FBADL_PCLRR1 (0x02) /* FB_AD1 */
8500 +#define MCF_GPIO_PCLRR_FBADL_PCLRR2 (0x04) /* FB_AD2 */
8501 +#define MCF_GPIO_PCLRR_FBADL_PCLRR3 (0x08) /* FB_AD3 */
8502 +#define MCF_GPIO_PCLRR_FBADL_PCLRR4 (0x10) /* FB_AD4 */
8503 +#define MCF_GPIO_PCLRR_FBADL_PCLRR5 (0x20) /* FB_AD5 */
8504 +#define MCF_GPIO_PCLRR_FBADL_PCLRR6 (0x40) /* FB_AD6 */
8505 +#define MCF_GPIO_PCLRR_FBADL_PCLRR7 (0x80) /* FB_AD7 */
8506 +
8507 +/* Bit definitions and macros for PAR_FEC */
8508 +#define MCF_GPIO_PAR_FEC_FEC0(x) (((x)&0x07))
8509 +#define MCF_GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4)
8510 +#define MCF_GPIO_PAR_FEC_FEC1_MASK (0x8F)
8511 +#define MCF_GPIO_PAR_FEC_FEC1_MII (0x70)
8512 +#define MCF_GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30)
8513 +#define MCF_GPIO_PAR_FEC_FEC1_RMII_ATA (0x20)
8514 +#define MCF_GPIO_PAR_FEC_FEC1_ATA (0x10)
8515 +#define MCF_GPIO_PAR_FEC_FEC1_GPIO (0x00)
8516 +#define MCF_GPIO_PAR_FEC_FEC0_MASK (0xF8)
8517 +#define MCF_GPIO_PAR_FEC_FEC0_MII (0x07)
8518 +#define MCF_GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03)
8519 +#define MCF_GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02)
8520 +#define MCF_GPIO_PAR_FEC_FEC0_ULPI (0x01)
8521 +#define MCF_GPIO_PAR_FEC_FEC0_GPIO (0x00)
8522 +
8523 +/* Bit definitions and macros for PAR_DMA */
8524 +#define MCF_GPIO_PAR_DMA_DREQ0 (0x01)
8525 +#define MCF_GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2)
8526 +#define MCF_GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4)
8527 +#define MCF_GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
8528 +#define MCF_GPIO_PAR_DMA_DACK1_MASK (0x3F)
8529 +#define MCF_GPIO_PAR_DMA_DACK1_DACK1 (0xC0)
8530 +#define MCF_GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40)
8531 +#define MCF_GPIO_PAR_DMA_DACK1_GPIO (0x00)
8532 +#define MCF_GPIO_PAR_DMA_DREQ1_MASK (0xCF)
8533 +#define MCF_GPIO_PAR_DMA_DREQ1_DREQ1 (0x30)
8534 +#define MCF_GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10)
8535 +#define MCF_GPIO_PAR_DMA_DREQ1_GPIO (0x00)
8536 +#define MCF_GPIO_PAR_DMA_DACK0_MASK (0xF3)
8537 +#define MCF_GPIO_PAR_DMA_DACK0_DACK1 (0x0C)
8538 +#define MCF_GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04)
8539 +#define MCF_GPIO_PAR_DMA_DACK0_GPIO (0x00)
8540 +#define MCF_GPIO_PAR_DMA_DREQ0_DREQ0 (0x01)
8541 +#define MCF_GPIO_PAR_DMA_DREQ0_GPIO (0x00)
8542 +
8543 +/* Bit definitions and macros for PAR_FBCTL */
8544 +#define MCF_GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3)
8545 +#define MCF_GPIO_PAR_FBCTL_RW (0x20)
8546 +#define MCF_GPIO_PAR_FBCTL_TA (0x40)
8547 +#define MCF_GPIO_PAR_FBCTL_OE (0x80)
8548 +#define MCF_GPIO_PAR_FBCTL_OE_OE (0x80)
8549 +#define MCF_GPIO_PAR_FBCTL_OE_GPIO (0x00)
8550 +#define MCF_GPIO_PAR_FBCTL_TA_TA (0x40)
8551 +#define MCF_GPIO_PAR_FBCTL_TA_GPIO (0x00)
8552 +#define MCF_GPIO_PAR_FBCTL_RW_RW (0x20)
8553 +#define MCF_GPIO_PAR_FBCTL_RW_GPIO (0x00)
8554 +#define MCF_GPIO_PAR_FBCTL_TS_MASK (0xE7)
8555 +#define MCF_GPIO_PAR_FBCTL_TS_TS (0x18)
8556 +#define MCF_GPIO_PAR_FBCTL_TS_ALE (0x10)
8557 +#define MCF_GPIO_PAR_FBCTL_TS_TBST (0x08)
8558 +#define MCF_GPIO_PAR_FBCTL_TS_GPIO (0x80)
8559 +
8560 +/* Bit definitions and macros for PAR_DSPI */
8561 +#define MCF_GPIO_PAR_DSPI_SCK (0x01)
8562 +#define MCF_GPIO_PAR_DSPI_SOUT (0x02)
8563 +#define MCF_GPIO_PAR_DSPI_SIN (0x04)
8564 +#define MCF_GPIO_PAR_DSPI_PCS0 (0x08)
8565 +#define MCF_GPIO_PAR_DSPI_PCS1 (0x10)
8566 +#define MCF_GPIO_PAR_DSPI_PCS2 (0x20)
8567 +#define MCF_GPIO_PAR_DSPI_PCS5 (0x40)
8568 +#define MCF_GPIO_PAR_DSPI_PCS5_PCS5 (0x40)
8569 +#define MCF_GPIO_PAR_DSPI_PCS5_GPIO (0x00)
8570 +#define MCF_GPIO_PAR_DSPI_PCS2_PCS2 (0x20)
8571 +#define MCF_GPIO_PAR_DSPI_PCS2_GPIO (0x00)
8572 +#define MCF_GPIO_PAR_DSPI_PCS1_PCS1 (0x10)
8573 +#define MCF_GPIO_PAR_DSPI_PCS1_GPIO (0x00)
8574 +#define MCF_GPIO_PAR_DSPI_PCS0_PCS0 (0x08)
8575 +#define MCF_GPIO_PAR_DSPI_PCS0_GPIO (0x00)
8576 +#define MCF_GPIO_PAR_DSPI_SIN_SIN (0x04)
8577 +#define MCF_GPIO_PAR_DSPI_SIN_GPIO (0x00)
8578 +#define MCF_GPIO_PAR_DSPI_SOUT_SOUT (0x02)
8579 +#define MCF_GPIO_PAR_DSPI_SOUT_GPIO (0x00)
8580 +#define MCF_GPIO_PAR_DSPI_SCK_SCK (0x01)
8581 +#define MCF_GPIO_PAR_DSPI_SCK_GPIO (0x00)
8582 +
8583 +/* Bit definitions and macros for PAR_BE */
8584 +#define MCF_GPIO_PAR_BE_BE0 (0x01)
8585 +#define MCF_GPIO_PAR_BE_BE1 (0x04)
8586 +#define MCF_GPIO_PAR_BE_BE2(x) (((x)&0x03)<<4)
8587 +#define MCF_GPIO_PAR_BE_BE3(x) (((x)&0x03)<<6)
8588 +#define MCF_GPIO_PAR_BE_BE3_MASK (0x3F)
8589 +#define MCF_GPIO_PAR_BE_BE3_BE3 (0xC0)
8590 +#define MCF_GPIO_PAR_BE_BE3_TSIZ1 (0x80)
8591 +#define MCF_GPIO_PAR_BE_BE3_GPIO (0x00)
8592 +#define MCF_GPIO_PAR_BE_BE2_MASK (0xCF)
8593 +#define MCF_GPIO_PAR_BE_BE2_BE2 (0x30)
8594 +#define MCF_GPIO_PAR_BE_BE2_TSIZ0 (0x20)
8595 +#define MCF_GPIO_PAR_BE_BE2_GPIO (0x00)
8596 +#define MCF_GPIO_PAR_BE_BE1_BE1 (0x04)
8597 +#define MCF_GPIO_PAR_BE_BE1_GPIO (0x00)
8598 +#define MCF_GPIO_PAR_BE_BE0_BE0 (0x01)
8599 +#define MCF_GPIO_PAR_BE_BE0_GPIO (0x00)
8600 +
8601 +/* Bit definitions and macros for PAR_CS */
8602 +#define MCF_GPIO_PAR_CS_CS1 (0x02)
8603 +#define MCF_GPIO_PAR_CS_CS2 (0x04)
8604 +#define MCF_GPIO_PAR_CS_CS3 (0x08)
8605 +#define MCF_GPIO_PAR_CS_CS3_CS3 (0x08)
8606 +#define MCF_GPIO_PAR_CS_CS3_GPIO (0x00)
8607 +#define MCF_GPIO_PAR_CS_CS2_CS2 (0x04)
8608 +#define MCF_GPIO_PAR_CS_CS2_GPIO (0x00)
8609 +#define MCF_GPIO_PAR_CS_CS1_CS1 (0x02)
8610 +#define MCF_GPIO_PAR_CS_CS1_GPIO (0x00)
8611 +
8612 +/* Bit definitions and macros for PAR_TIMER */
8613 +#define MCF_GPIO_PAR_TIMER_T0IN(x) (((x)&0x03))
8614 +#define MCF_GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
8615 +#define MCF_GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
8616 +#define MCF_GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
8617 +#define MCF_GPIO_PAR_TIMER_T3IN_MASK (0x3F)
8618 +#define MCF_GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
8619 +#define MCF_GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
8620 +#define MCF_GPIO_PAR_TIMER_T3IN_U2RXD (0x40)
8621 +#define MCF_GPIO_PAR_TIMER_T3IN_GPIO (0x00)
8622 +#define MCF_GPIO_PAR_TIMER_T2IN_MASK (0xCF)
8623 +#define MCF_GPIO_PAR_TIMER_T2IN_T2IN (0x30)
8624 +#define MCF_GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
8625 +#define MCF_GPIO_PAR_TIMER_T2IN_U2TXD (0x10)
8626 +#define MCF_GPIO_PAR_TIMER_T2IN_GPIO (0x00)
8627 +#define MCF_GPIO_PAR_TIMER_T1IN_MASK (0xF3)
8628 +#define MCF_GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
8629 +#define MCF_GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
8630 +#define MCF_GPIO_PAR_TIMER_T1IN_U2CTS (0x04)
8631 +#define MCF_GPIO_PAR_TIMER_T1IN_GPIO (0x00)
8632 +#define MCF_GPIO_PAR_TIMER_T0IN_MASK (0xFC)
8633 +#define MCF_GPIO_PAR_TIMER_T0IN_T0IN (0x03)
8634 +#define MCF_GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
8635 +#define MCF_GPIO_PAR_TIMER_T0IN_U2RTS (0x01)
8636 +#define MCF_GPIO_PAR_TIMER_T0IN_GPIO (0x00)
8637 +
8638 +/* Bit definitions and macros for PAR_USB */
8639 +#define MCF_GPIO_PAR_USB_VBUSOC(x) (((x)&0x03))
8640 +#define MCF_GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2)
8641 +#define MCF_GPIO_PAR_USB_VBUSEN_MASK (0xF3)
8642 +#define MCF_GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C)
8643 +#define MCF_GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08)
8644 +#define MCF_GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04)
8645 +#define MCF_GPIO_PAR_USB_VBUSEN_GPIO (0x00)
8646 +#define MCF_GPIO_PAR_USB_VBUSOC_MASK (0xFC)
8647 +#define MCF_GPIO_PAR_USB_VBUSOC_VBUSOC (0x03)
8648 +#define MCF_GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01)
8649 +#define MCF_GPIO_PAR_USB_VBUSOC_GPIO (0x00)
8650 +
8651 +/* Bit definitions and macros for PAR_UART */
8652 +#define MCF_GPIO_PAR_UART_U0TXD (0x01)
8653 +#define MCF_GPIO_PAR_UART_U0RXD (0x02)
8654 +#define MCF_GPIO_PAR_UART_U0RTS (0x04)
8655 +#define MCF_GPIO_PAR_UART_U0CTS (0x08)
8656 +#define MCF_GPIO_PAR_UART_U1TXD (0x10)
8657 +#define MCF_GPIO_PAR_UART_U1RXD (0x20)
8658 +#define MCF_GPIO_PAR_UART_U1RTS (0x40)
8659 +#define MCF_GPIO_PAR_UART_U1CTS (0x80)
8660 +#define MCF_GPIO_PAR_UART_U1CTS_U1CTS (0x80)
8661 +#define MCF_GPIO_PAR_UART_U1CTS_GPIO (0x00)
8662 +#define MCF_GPIO_PAR_UART_U1RTS_U1RTS (0x40)
8663 +#define MCF_GPIO_PAR_UART_U1RTS_GPIO (0x00)
8664 +#define MCF_GPIO_PAR_UART_U1RXD_U1RXD (0x20)
8665 +#define MCF_GPIO_PAR_UART_U1RXD_GPIO (0x00)
8666 +#define MCF_GPIO_PAR_UART_U1TXD_U1TXD (0x10)
8667 +#define MCF_GPIO_PAR_UART_U1TXD_GPIO (0x00)
8668 +#define MCF_GPIO_PAR_UART_U0CTS_U0CTS (0x08)
8669 +#define MCF_GPIO_PAR_UART_U0CTS_GPIO (0x00)
8670 +#define MCF_GPIO_PAR_UART_U0RTS_U0RTS (0x04)
8671 +#define MCF_GPIO_PAR_UART_U0RTS_GPIO (0x00)
8672 +#define MCF_GPIO_PAR_UART_U0RXD_U0RXD (0x02)
8673 +#define MCF_GPIO_PAR_UART_U0RXD_GPIO (0x00)
8674 +#define MCF_GPIO_PAR_UART_U0TXD_U0TXD (0x01)
8675 +#define MCF_GPIO_PAR_UART_U0TXD_GPIO (0x00)
8676 +
8677 +/* Bit definitions and macros for PAR_FECI2C */
8678 +#define MCF_GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003))
8679 +#define MCF_GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2)
8680 +#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x0003))
8681 +#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x0003)<<2)
8682 +#define MCF_GPIO_PAR_FECI2C_MDIO0 (0x0010)
8683 +#define MCF_GPIO_PAR_FECI2C_MDC0 (0x0040)
8684 +#define MCF_GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8)
8685 +#define MCF_GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10)
8686 +#define MCF_GPIO_PAR_FECI2C_MDC1_MASK (0xF3FF)
8687 +#define MCF_GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00)
8688 +#define MCF_GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800)
8689 +#define MCF_GPIO_PAR_FECI2C_MDC1_GPIO (0x0000)
8690 +#define MCF_GPIO_PAR_FECI2C_MDIO1_MASK (0xFCFF)
8691 +#define MCF_GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300)
8692 +#define MCF_GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200)
8693 +#define MCF_GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000)
8694 +#define MCF_GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040)
8695 +#define MCF_GPIO_PAR_FECI2C_MDC0_GPIO (0x0000)
8696 +#define MCF_GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010)
8697 +#define MCF_GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000)
8698 +#define MCF_GPIO_PAR_FECI2C_SCL_MASK (0xFFF3)
8699 +#define MCF_GPIO_PAR_FECI2C_SCL_SCL (0x000C)
8700 +#define MCF_GPIO_PAR_FECI2C_SCL_U2TXD (0x0004)
8701 +#define MCF_GPIO_PAR_FECI2C_SCL_GPIO (0x0000)
8702 +#define MCF_GPIO_PAR_FECI2C_SDA_MASK (0xFFFC)
8703 +#define MCF_GPIO_PAR_FECI2C_SDA_SDA (0x0003)
8704 +#define MCF_GPIO_PAR_FECI2C_SDA_U2RXD (0x0001)
8705 +#define MCF_GPIO_PAR_FECI2C_SDA_GPIO (0x0000)
8706 +
8707 +/* Bit definitions and macros for PAR_SSI */
8708 +#define MCF_GPIO_PAR_SSI_MCLK (0x0001)
8709 +#define MCF_GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2)
8710 +#define MCF_GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4)
8711 +#define MCF_GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6)
8712 +#define MCF_GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8)
8713 +#define MCF_GPIO_PAR_SSI_BCLK_MASK (0xFCFF)
8714 +#define MCF_GPIO_PAR_SSI_BCLK_BCLK (0x0300)
8715 +#define MCF_GPIO_PAR_SSI_BCLK_U1CTS (0x0200)
8716 +#define MCF_GPIO_PAR_SSI_BCLK_GPIO (0x0000)
8717 +#define MCF_GPIO_PAR_SSI_FS_MASK (0xFF3F)
8718 +#define MCF_GPIO_PAR_SSI_FS_FS (0x00C0)
8719 +#define MCF_GPIO_PAR_SSI_FS_U1RTS (0x0080)
8720 +#define MCF_GPIO_PAR_SSI_FS_GPIO (0x0000)
8721 +#define MCF_GPIO_PAR_SSI_SRXD_MASK (0xFFCF)
8722 +#define MCF_GPIO_PAR_SSI_SRXD_SRXD (0x0030)
8723 +#define MCF_GPIO_PAR_SSI_SRXD_U1RXD (0x0020)
8724 +#define MCF_GPIO_PAR_SSI_SRXD_GPIO (0x0000)
8725 +#define MCF_GPIO_PAR_SSI_STXD_MASK (0xFFF3)
8726 +#define MCF_GPIO_PAR_SSI_STXD_STXD (0x000C)
8727 +#define MCF_GPIO_PAR_SSI_STXD_U1TXD (0x0008)
8728 +#define MCF_GPIO_PAR_SSI_STXD_GPIO (0x0000)
8729 +#define MCF_GPIO_PAR_SSI_MCLK_MCLK (0x0001)
8730 +#define MCF_GPIO_PAR_SSI_MCLK_GPIO (0x0000)
8731 +
8732 +/* Bit definitions and macros for PAR_ATA */
8733 +#define MCF_GPIO_PAR_ATA_IORDY (0x0001)
8734 +#define MCF_GPIO_PAR_ATA_DMARQ (0x0002)
8735 +#define MCF_GPIO_PAR_ATA_RESET (0x0004)
8736 +#define MCF_GPIO_PAR_ATA_DA0 (0x0020)
8737 +#define MCF_GPIO_PAR_ATA_DA1 (0x0040)
8738 +#define MCF_GPIO_PAR_ATA_DA2 (0x0080)
8739 +#define MCF_GPIO_PAR_ATA_CS0 (0x0100)
8740 +#define MCF_GPIO_PAR_ATA_CS1 (0x0200)
8741 +#define MCF_GPIO_PAR_ATA_BUFEN (0x0400)
8742 +#define MCF_GPIO_PAR_ATA_BUFEN_BUFEN (0x0400)
8743 +#define MCF_GPIO_PAR_ATA_BUFEN_GPIO (0x0000)
8744 +#define MCF_GPIO_PAR_ATA_CS1_CS1 (0x0200)
8745 +#define MCF_GPIO_PAR_ATA_CS1_GPIO (0x0000)
8746 +#define MCF_GPIO_PAR_ATA_CS0_CS0 (0x0100)
8747 +#define MCF_GPIO_PAR_ATA_CS0_GPIO (0x0000)
8748 +#define MCF_GPIO_PAR_ATA_DA2_DA2 (0x0080)
8749 +#define MCF_GPIO_PAR_ATA_DA2_GPIO (0x0000)
8750 +#define MCF_GPIO_PAR_ATA_DA1_DA1 (0x0040)
8751 +#define MCF_GPIO_PAR_ATA_DA1_GPIO (0x0000)
8752 +#define MCF_GPIO_PAR_ATA_DA0_DA0 (0x0020)
8753 +#define MCF_GPIO_PAR_ATA_DA0_GPIO (0x0000)
8754 +#define MCF_GPIO_PAR_ATA_RESET_RESET (0x0004)
8755 +#define MCF_GPIO_PAR_ATA_RESET_GPIO (0x0000)
8756 +#define MCF_GPIO_PAR_ATA_DMARQ_DMARQ (0x0002)
8757 +#define MCF_GPIO_PAR_ATA_DMARQ_GPIO (0x0000)
8758 +#define MCF_GPIO_PAR_ATA_IORDY_IORDY (0x0001)
8759 +#define MCF_GPIO_PAR_ATA_IORDY_GPIO (0x0000)
8760 +
8761 +/* Bit definitions and macros for PAR_IRQ */
8762 +#define MCF_GPIO_PAR_IRQ_IRQ1 (0x02)
8763 +#define MCF_GPIO_PAR_IRQ_IRQ4 (0x10)
8764 +#define MCF_GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10)
8765 +#define MCF_GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
8766 +#define MCF_GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02)
8767 +#define MCF_GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
8768 +
8769 +/* Bit definitions and macros for PAR_PCI */
8770 +#define MCF_GPIO_PAR_PCI_REQ0 (0x0001)
8771 +#define MCF_GPIO_PAR_PCI_REQ1 (0x0004)
8772 +#define MCF_GPIO_PAR_PCI_REQ2 (0x0010)
8773 +#define MCF_GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6)
8774 +#define MCF_GPIO_PAR_PCI_GNT0 (0x0100)
8775 +#define MCF_GPIO_PAR_PCI_GNT1 (0x0400)
8776 +#define MCF_GPIO_PAR_PCI_GNT2 (0x1000)
8777 +#define MCF_GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14)
8778 +#define MCF_GPIO_PAR_PCI_GNT3_MASK (0x3FFF)
8779 +#define MCF_GPIO_PAR_PCI_GNT3_GNT3 (0xC000)
8780 +#define MCF_GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000)
8781 +#define MCF_GPIO_PAR_PCI_GNT3_GPIO (0x0000)
8782 +#define MCF_GPIO_PAR_PCI_GNT2_GNT2 (0x1000)
8783 +#define MCF_GPIO_PAR_PCI_GNT2_GPIO (0x0000)
8784 +#define MCF_GPIO_PAR_PCI_GNT1_GNT1 (0x0400)
8785 +#define MCF_GPIO_PAR_PCI_GNT1_GPIO (0x0000)
8786 +#define MCF_GPIO_PAR_PCI_GNT0_GNT0 (0x0100)
8787 +#define MCF_GPIO_PAR_PCI_GNT0_GPIO (0x0000)
8788 +#define MCF_GPIO_PAR_PCI_REQ3_MASK (0xFF3F)
8789 +#define MCF_GPIO_PAR_PCI_REQ3_REQ3 (0x00C0)
8790 +#define MCF_GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080)
8791 +#define MCF_GPIO_PAR_PCI_REQ3_GPIO (0x0000)
8792 +#define MCF_GPIO_PAR_PCI_REQ2_REQ2 (0x0010)
8793 +#define MCF_GPIO_PAR_PCI_REQ2_GPIO (0x0000)
8794 +#define MCF_GPIO_PAR_PCI_REQ1_REQ1 (0x0040)
8795 +#define MCF_GPIO_PAR_PCI_REQ1_GPIO (0x0000)
8796 +#define MCF_GPIO_PAR_PCI_REQ0_REQ0 (0x0001)
8797 +#define MCF_GPIO_PAR_PCI_REQ0_GPIO (0x0000)
8798 +
8799 +/* Bit definitions and macros for MSCR_SDRAM */
8800 +#define MCF_GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03))
8801 +#define MCF_GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2)
8802 +#define MCF_GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4)
8803 +#define MCF_GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6)
8804 +#define MCF_GPIO_MSCR_SDRAM_SDDATA_MASK (0x3F)
8805 +#define MCF_GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0)
8806 +#define MCF_GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80)
8807 +#define MCF_GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40)
8808 +#define MCF_GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00)
8809 +#define MCF_GPIO_MSCR_SDRAM_SDDQS_MASK (0xCF)
8810 +#define MCF_GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30)
8811 +#define MCF_GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20)
8812 +#define MCF_GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10)
8813 +#define MCF_GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00)
8814 +#define MCF_GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3)
8815 +#define MCF_GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C)
8816 +#define MCF_GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08)
8817 +#define MCF_GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04)
8818 +#define MCF_GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00)
8819 +#define MCF_GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC)
8820 +#define MCF_GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03)
8821 +#define MCF_GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02)
8822 +#define MCF_GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01)
8823 +#define MCF_GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00)
8824 +
8825 +/* Bit definitions and macros for MSCR_PCI */
8826 +#define MCF_GPIO_MSCR_PCI_PCI (0x01)
8827 +#define MCF_GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01)
8828 +#define MCF_GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00)
8829 +
8830 +/* Bit definitions and macros for DSCR_I2C */
8831 +#define MCF_GPIO_DSCR_I2C_I2C(x) (((x)&0x03))
8832 +#define MCF_GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03)
8833 +#define MCF_GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02)
8834 +#define MCF_GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01)
8835 +#define MCF_GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00)
8836 +
8837 +/* Bit definitions and macros for DSCR_FLEXBUS */
8838 +#define MCF_GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03))
8839 +#define MCF_GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2)
8840 +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4)
8841 +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6)
8842 +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0)
8843 +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30P (0x80)
8844 +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40)
8845 +#define MCF_GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00)
8846 +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30)
8847 +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20)
8848 +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10)
8849 +#define MCF_GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00)
8850 +#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C)
8851 +#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08)
8852 +#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04)
8853 +#define MCF_GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00)
8854 +#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03)
8855 +#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02)
8856 +#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01)
8857 +#define MCF_GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00)
8858 +
8859 +/* Bit definitions and macros for DSCR_FEC */
8860 +#define MCF_GPIO_DSCR_FEC_FEC0(x) (((x)&0x03))
8861 +#define MCF_GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2)
8862 +#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C)
8863 +#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08)
8864 +#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04)
8865 +#define MCF_GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00)
8866 +#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03)
8867 +#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02)
8868 +#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01)
8869 +#define MCF_GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00)
8870 +
8871 +/* Bit definitions and macros for DSCR_UART */
8872 +#define MCF_GPIO_DSCR_UART_UART0(x) (((x)&0x03))
8873 +#define MCF_GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2)
8874 +#define MCF_GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C)
8875 +#define MCF_GPIO_DSCR_UART_UART1_LOAD_30PF (0x08)
8876 +#define MCF_GPIO_DSCR_UART_UART1_LOAD_20PF (0x04)
8877 +#define MCF_GPIO_DSCR_UART_UART1_LOAD_10PF (0x00)
8878 +#define MCF_GPIO_DSCR_UART_UART0_LOAD_50PF (0x03)
8879 +#define MCF_GPIO_DSCR_UART_UART0_LOAD_30PF (0x02)
8880 +#define MCF_GPIO_DSCR_UART_UART0_LOAD_20PF (0x01)
8881 +#define MCF_GPIO_DSCR_UART_UART0_LOAD_10PF (0x00)
8882 +
8883 +/* Bit definitions and macros for DSCR_DSPI */
8884 +#define MCF_GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03))
8885 +#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03)
8886 +#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02)
8887 +#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01)
8888 +#define MCF_GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00)
8889 +
8890 +/* Bit definitions and macros for DSCR_TIMER */
8891 +#define MCF_GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03))
8892 +#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03)
8893 +#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02)
8894 +#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01)
8895 +#define MCF_GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00)
8896 +
8897 +/* Bit definitions and macros for DSCR_SSI */
8898 +#define MCF_GPIO_DSCR_SSI_SSI(x) (((x)&0x03))
8899 +#define MCF_GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03)
8900 +#define MCF_GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02)
8901 +#define MCF_GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01)
8902 +#define MCF_GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00)
8903 +
8904 +/* Bit definitions and macros for DSCR_DMA */
8905 +#define MCF_GPIO_DSCR_DMA_DMA(x) (((x)&0x03))
8906 +#define MCF_GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03)
8907 +#define MCF_GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02)
8908 +#define MCF_GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01)
8909 +#define MCF_GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00)
8910 +
8911 +/* Bit definitions and macros for DSCR_DEBUG */
8912 +#define MCF_GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03))
8913 +#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03)
8914 +#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02)
8915 +#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01)
8916 +#define MCF_GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00)
8917 +
8918 +/* Bit definitions and macros for DSCR_RESET */
8919 +#define MCF_GPIO_DSCR_RESET_RESET(x) (((x)&0x03))
8920 +#define MCF_GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03)
8921 +#define MCF_GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02)
8922 +#define MCF_GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01)
8923 +#define MCF_GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00)
8924 +
8925 +/* Bit definitions and macros for DSCR_IRQ */
8926 +#define MCF_GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03))
8927 +#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03)
8928 +#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02)
8929 +#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01)
8930 +#define MCF_GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00)
8931 +
8932 +/* Bit definitions and macros for DSCR_USB */
8933 +#define MCF_GPIO_DSCR_USB_USB(x) (((x)&0x03))
8934 +#define MCF_GPIO_DSCR_USB_USB_LOAD_50PF (0x03)
8935 +#define MCF_GPIO_DSCR_USB_USB_LOAD_30PF (0x02)
8936 +#define MCF_GPIO_DSCR_USB_USB_LOAD_20PF (0x01)
8937 +#define MCF_GPIO_DSCR_USB_USB_LOAD_10PF (0x00)
8938 +
8939 +/* Bit definitions and macros for DSCR_ATA */
8940 +#define MCF_GPIO_DSCR_ATA_ATA(x) (((x)&0x03))
8941 +#define MCF_GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03)
8942 +#define MCF_GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02)
8943 +#define MCF_GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01)
8944 +#define MCF_GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00)
8945 +
8946 +/********************************************************************/
8947 +
8948 +#endif /* __MCF5445X_GPIO_H__ */
8949 --- /dev/null
8950 +++ b/arch/m68k/include/asm/mcf5445x_intc.h
8951 @@ -0,0 +1,724 @@
8952 +/*
8953 + * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
8954 + *
8955 + * Matt Waddel Matt.Waddel@freescale.com
8956 + *
8957 + * This program is free software; you can redistribute it and/or modify it
8958 + * under the terms of the GNU General Public License as published by the
8959 + * Free Software Foundation; either version 2 of the License, or (at your
8960 + * option) any later version.
8961 + */
8962 +
8963 +#ifndef __MCF5445X_INTC_H__
8964 +#define __MCF5445X_INTC_H__
8965 +
8966 +/*********************************************************************
8967 +*
8968 +* Interrupt Controller (INTC)
8969 +*
8970 +*********************************************************************/
8971 +
8972 +/* Register read/write macros */
8973 +#define MCF_INTC0_IPRH MCF_REG32(0xFC048000)
8974 +#define MCF_INTC0_IPRL MCF_REG32(0xFC048004)
8975 +#define MCF_INTC0_IMRH MCF_REG32(0xFC048008)
8976 +#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C)
8977 +#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010)
8978 +#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014)
8979 +#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A)
8980 +#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C)
8981 +#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D)
8982 +#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E)
8983 +#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F)
8984 +#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041)
8985 +#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042)
8986 +#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043)
8987 +#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044)
8988 +#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045)
8989 +#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046)
8990 +#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047)
8991 +#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048)
8992 +#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049)
8993 +#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A)
8994 +#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B)
8995 +#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C)
8996 +#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D)
8997 +#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E)
8998 +#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F)
8999 +#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050)
9000 +#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051)
9001 +#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052)
9002 +#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053)
9003 +#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054)
9004 +#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055)
9005 +#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056)
9006 +#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057)
9007 +#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058)
9008 +#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059)
9009 +#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A)
9010 +#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B)
9011 +#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C)
9012 +#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D)
9013 +#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E)
9014 +#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F)
9015 +#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060)
9016 +#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061)
9017 +#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062)
9018 +#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063)
9019 +#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064)
9020 +#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065)
9021 +#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066)
9022 +#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067)
9023 +#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068)
9024 +#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069)
9025 +#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A)
9026 +#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B)
9027 +#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C)
9028 +#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D)
9029 +#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E)
9030 +#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F)
9031 +#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070)
9032 +#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071)
9033 +#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072)
9034 +#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073)
9035 +#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074)
9036 +#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075)
9037 +#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076)
9038 +#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077)
9039 +#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078)
9040 +#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079)
9041 +#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A)
9042 +#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B)
9043 +#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C)
9044 +#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D)
9045 +#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E)
9046 +#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F)
9047 +#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0)
9048 +#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4)
9049 +#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8)
9050 +#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC)
9051 +#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0)
9052 +#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4)
9053 +#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8)
9054 +#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC)
9055 +#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000)
9056 +#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004)
9057 +#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008)
9058 +#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C)
9059 +#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010)
9060 +#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014)
9061 +#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A)
9062 +#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C)
9063 +#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D)
9064 +#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E)
9065 +#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F)
9066 +#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041)
9067 +#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042)
9068 +#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043)
9069 +#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044)
9070 +#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045)
9071 +#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046)
9072 +#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047)
9073 +#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048)
9074 +#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049)
9075 +#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A)
9076 +#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B)
9077 +#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C)
9078 +#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D)
9079 +#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E)
9080 +#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F)
9081 +#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050)
9082 +#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051)
9083 +#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052)
9084 +#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053)
9085 +#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054)
9086 +#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055)
9087 +#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056)
9088 +#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057)
9089 +#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058)
9090 +#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059)
9091 +#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A)
9092 +#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B)
9093 +#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C)
9094 +#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D)
9095 +#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E)
9096 +#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F)
9097 +#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060)
9098 +#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061)
9099 +#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062)
9100 +#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063)
9101 +#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064)
9102 +#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065)
9103 +#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066)
9104 +#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067)
9105 +#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068)
9106 +#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069)
9107 +#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A)
9108 +#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B)
9109 +#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C)
9110 +#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D)
9111 +#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E)
9112 +#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F)
9113 +#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070)
9114 +#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071)
9115 +#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072)
9116 +#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073)
9117 +#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074)
9118 +#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075)
9119 +#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076)
9120 +#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077)
9121 +#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078)
9122 +#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079)
9123 +#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A)
9124 +#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B)
9125 +#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C)
9126 +#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D)
9127 +#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E)
9128 +#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F)
9129 +#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0)
9130 +#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4)
9131 +#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8)
9132 +#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC)
9133 +#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0)
9134 +#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4)
9135 +#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8
9136 +#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC)
9137 +
9138 +/* Parameterized register read/write macros for multiple registers */
9139 +#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048041+((x-1)*0x001))
9140 +#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x-1)*0x004))
9141 +#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C041+((x-1)*0x001))
9142 +#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x-1)*0x004))
9143 +
9144 +/* Parameterized register read/write macros for multiple modules */
9145 +#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000))
9146 +#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000))
9147 +#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000))
9148 +#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000))
9149 +#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000))
9150 +#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000))
9151 +#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000))
9152 +#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000))
9153 +#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000))
9154 +#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000))
9155 +#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000))
9156 +#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000))
9157 +#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000))
9158 +#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000))
9159 +#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000))
9160 +#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000))
9161 +#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000))
9162 +#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000))
9163 +#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000))
9164 +#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000))
9165 +#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000))
9166 +#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000))
9167 +#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000))
9168 +#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000))
9169 +#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000))
9170 +#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000))
9171 +#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000))
9172 +#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000))
9173 +#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000))
9174 +#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000))
9175 +#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000))
9176 +#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000))
9177 +#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000))
9178 +#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000))
9179 +#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000))
9180 +#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000))
9181 +#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000))
9182 +#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000))
9183 +#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000))
9184 +#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000))
9185 +#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000))
9186 +#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000))
9187 +#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000))
9188 +#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000))
9189 +#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000))
9190 +#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000))
9191 +#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000))
9192 +#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000))
9193 +#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000))
9194 +#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000))
9195 +#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000))
9196 +#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000))
9197 +#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000))
9198 +#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000))
9199 +#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000))
9200 +#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000))
9201 +#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000))
9202 +#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000))
9203 +#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000))
9204 +#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000))
9205 +#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000))
9206 +#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000))
9207 +#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000))
9208 +#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000))
9209 +#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000))
9210 +#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000))
9211 +#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000))
9212 +#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000))
9213 +#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000))
9214 +#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000))
9215 +#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000))
9216 +#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000))
9217 +#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000))
9218 +#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000))
9219 +#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000))
9220 +#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000))
9221 +#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000))
9222 +#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000))
9223 +#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000))
9224 +#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000))
9225 +#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000))
9226 +#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000))
9227 +
9228 +/* Bit definitions and macros for IPRH */
9229 +#define MCF_INTC_IPRH_INT32 (0x00000001)
9230 +#define MCF_INTC_IPRH_INT33 (0x00000002)
9231 +#define MCF_INTC_IPRH_INT34 (0x00000004)
9232 +#define MCF_INTC_IPRH_INT35 (0x00000008)
9233 +#define MCF_INTC_IPRH_INT36 (0x00000010)
9234 +#define MCF_INTC_IPRH_INT37 (0x00000020)
9235 +#define MCF_INTC_IPRH_INT38 (0x00000040)
9236 +#define MCF_INTC_IPRH_INT39 (0x00000080)
9237 +#define MCF_INTC_IPRH_INT40 (0x00000100)
9238 +#define MCF_INTC_IPRH_INT41 (0x00000200)
9239 +#define MCF_INTC_IPRH_INT42 (0x00000400)
9240 +#define MCF_INTC_IPRH_INT43 (0x00000800)
9241 +#define MCF_INTC_IPRH_INT44 (0x00001000)
9242 +#define MCF_INTC_IPRH_INT45 (0x00002000)
9243 +#define MCF_INTC_IPRH_INT46 (0x00004000)
9244 +#define MCF_INTC_IPRH_INT47 (0x00008000)
9245 +#define MCF_INTC_IPRH_INT48 (0x00010000)
9246 +#define MCF_INTC_IPRH_INT49 (0x00020000)
9247 +#define MCF_INTC_IPRH_INT50 (0x00040000)
9248 +#define MCF_INTC_IPRH_INT51 (0x00080000)
9249 +#define MCF_INTC_IPRH_INT52 (0x00100000)
9250 +#define MCF_INTC_IPRH_INT53 (0x00200000)
9251 +#define MCF_INTC_IPRH_INT54 (0x00400000)
9252 +#define MCF_INTC_IPRH_INT55 (0x00800000)
9253 +#define MCF_INTC_IPRH_INT56 (0x01000000)
9254 +#define MCF_INTC_IPRH_INT57 (0x02000000)
9255 +#define MCF_INTC_IPRH_INT58 (0x04000000)
9256 +#define MCF_INTC_IPRH_INT59 (0x08000000)
9257 +#define MCF_INTC_IPRH_INT60 (0x10000000)
9258 +#define MCF_INTC_IPRH_INT61 (0x20000000)
9259 +#define MCF_INTC_IPRH_INT62 (0x40000000)
9260 +#define MCF_INTC_IPRH_INT63 (0x80000000)
9261 +
9262 +/* Bit definitions and macros for IPRL */
9263 +#define MCF_INTC_IPRL_INT0 (0x00000001)
9264 +#define MCF_INTC_IPRL_INT1 (0x00000002)
9265 +#define MCF_INTC_IPRL_INT2 (0x00000004)
9266 +#define MCF_INTC_IPRL_INT3 (0x00000008)
9267 +#define MCF_INTC_IPRL_INT4 (0x00000010)
9268 +#define MCF_INTC_IPRL_INT5 (0x00000020)
9269 +#define MCF_INTC_IPRL_INT6 (0x00000040)
9270 +#define MCF_INTC_IPRL_INT7 (0x00000080)
9271 +#define MCF_INTC_IPRL_INT8 (0x00000100)
9272 +#define MCF_INTC_IPRL_INT9 (0x00000200)
9273 +#define MCF_INTC_IPRL_INT10 (0x00000400)
9274 +#define MCF_INTC_IPRL_INT11 (0x00000800)
9275 +#define MCF_INTC_IPRL_INT12 (0x00001000)
9276 +#define MCF_INTC_IPRL_INT13 (0x00002000)
9277 +#define MCF_INTC_IPRL_INT14 (0x00004000)
9278 +#define MCF_INTC_IPRL_INT15 (0x00008000)
9279 +#define MCF_INTC_IPRL_INT16 (0x00010000)
9280 +#define MCF_INTC_IPRL_INT17 (0x00020000)
9281 +#define MCF_INTC_IPRL_INT18 (0x00040000)
9282 +#define MCF_INTC_IPRL_INT19 (0x00080000)
9283 +#define MCF_INTC_IPRL_INT20 (0x00100000)
9284 +#define MCF_INTC_IPRL_INT21 (0x00200000)
9285 +#define MCF_INTC_IPRL_INT22 (0x00400000)
9286 +#define MCF_INTC_IPRL_INT23 (0x00800000)
9287 +#define MCF_INTC_IPRL_INT24 (0x01000000)
9288 +#define MCF_INTC_IPRL_INT25 (0x02000000)
9289 +#define MCF_INTC_IPRL_INT26 (0x04000000)
9290 +#define MCF_INTC_IPRL_INT27 (0x08000000)
9291 +#define MCF_INTC_IPRL_INT28 (0x10000000)
9292 +#define MCF_INTC_IPRL_INT29 (0x20000000)
9293 +#define MCF_INTC_IPRL_INT30 (0x40000000)
9294 +#define MCF_INTC_IPRL_INT31 (0x80000000)
9295 +
9296 +/* Bit definitions and macros for IMRH */
9297 +#define MCF_INTC_IMRH_INT_MASK32 (0x00000001)
9298 +#define MCF_INTC_IMRH_INT_MASK33 (0x00000002)
9299 +#define MCF_INTC_IMRH_INT_MASK34 (0x00000004)
9300 +#define MCF_INTC_IMRH_INT_MASK35 (0x00000008)
9301 +#define MCF_INTC_IMRH_INT_MASK36 (0x00000010)
9302 +#define MCF_INTC_IMRH_INT_MASK37 (0x00000020)
9303 +#define MCF_INTC_IMRH_INT_MASK38 (0x00000040)
9304 +#define MCF_INTC_IMRH_INT_MASK39 (0x00000080)
9305 +#define MCF_INTC_IMRH_INT_MASK40 (0x00000100)
9306 +#define MCF_INTC_IMRH_INT_MASK41 (0x00000200)
9307 +#define MCF_INTC_IMRH_INT_MASK42 (0x00000400)
9308 +#define MCF_INTC_IMRH_INT_MASK43 (0x00000800)
9309 +#define MCF_INTC_IMRH_INT_MASK44 (0x00001000)
9310 +#define MCF_INTC_IMRH_INT_MASK45 (0x00002000)
9311 +#define MCF_INTC_IMRH_INT_MASK46 (0x00004000)
9312 +#define MCF_INTC_IMRH_INT_MASK47 (0x00008000)
9313 +#define MCF_INTC_IMRH_INT_MASK48 (0x00010000)
9314 +#define MCF_INTC_IMRH_INT_MASK49 (0x00020000)
9315 +#define MCF_INTC_IMRH_INT_MASK50 (0x00040000)
9316 +#define MCF_INTC_IMRH_INT_MASK51 (0x00080000)
9317 +#define MCF_INTC_IMRH_INT_MASK52 (0x00100000)
9318 +#define MCF_INTC_IMRH_INT_MASK53 (0x00200000)
9319 +#define MCF_INTC_IMRH_INT_MASK54 (0x00400000)
9320 +#define MCF_INTC_IMRH_INT_MASK55 (0x00800000)
9321 +#define MCF_INTC_IMRH_INT_MASK56 (0x01000000)
9322 +#define MCF_INTC_IMRH_INT_MASK57 (0x02000000)
9323 +#define MCF_INTC_IMRH_INT_MASK58 (0x04000000)
9324 +#define MCF_INTC_IMRH_INT_MASK59 (0x08000000)
9325 +#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
9326 +#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
9327 +#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
9328 +#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
9329 +
9330 +/* Bit definitions and macros for IMRL */
9331 +#define MCF_INTC_IMRL_INT_MASK0 (0x00000001)
9332 +#define MCF_INTC_IMRL_INT_MASK1 (0x00000002)
9333 +#define MCF_INTC_IMRL_INT_MASK2 (0x00000004)
9334 +#define MCF_INTC_IMRL_INT_MASK3 (0x00000008)
9335 +#define MCF_INTC_IMRL_INT_MASK4 (0x00000010)
9336 +#define MCF_INTC_IMRL_INT_MASK5 (0x00000020)
9337 +#define MCF_INTC_IMRL_INT_MASK6 (0x00000040)
9338 +#define MCF_INTC_IMRL_INT_MASK7 (0x00000080)
9339 +#define MCF_INTC_IMRL_INT_MASK8 (0x00000100)
9340 +#define MCF_INTC_IMRL_INT_MASK9 (0x00000200)
9341 +#define MCF_INTC_IMRL_INT_MASK10 (0x00000400)
9342 +#define MCF_INTC_IMRL_INT_MASK11 (0x00000800)
9343 +#define MCF_INTC_IMRL_INT_MASK12 (0x00001000)
9344 +#define MCF_INTC_IMRL_INT_MASK13 (0x00002000)
9345 +#define MCF_INTC_IMRL_INT_MASK14 (0x00004000)
9346 +#define MCF_INTC_IMRL_INT_MASK15 (0x00008000)
9347 +#define MCF_INTC_IMRL_INT_MASK16 (0x00010000)
9348 +#define MCF_INTC_IMRL_INT_MASK17 (0x00020000)
9349 +#define MCF_INTC_IMRL_INT_MASK18 (0x00040000)
9350 +#define MCF_INTC_IMRL_INT_MASK19 (0x00080000)
9351 +#define MCF_INTC_IMRL_INT_MASK20 (0x00100000)
9352 +#define MCF_INTC_IMRL_INT_MASK21 (0x00200000)
9353 +#define MCF_INTC_IMRL_INT_MASK22 (0x00400000)
9354 +#define MCF_INTC_IMRL_INT_MASK23 (0x00800000)
9355 +#define MCF_INTC_IMRL_INT_MASK24 (0x01000000)
9356 +#define MCF_INTC_IMRL_INT_MASK25 (0x02000000)
9357 +#define MCF_INTC_IMRL_INT_MASK26 (0x04000000)
9358 +#define MCF_INTC_IMRL_INT_MASK27 (0x08000000)
9359 +#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
9360 +#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
9361 +#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
9362 +#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
9363 +
9364 +/* Bit definitions and macros for INTFRCH */
9365 +#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001)
9366 +#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002)
9367 +#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004)
9368 +#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008)
9369 +#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010)
9370 +#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020)
9371 +#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040)
9372 +#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080)
9373 +#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100)
9374 +#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200)
9375 +#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400)
9376 +#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800)
9377 +#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000)
9378 +#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000)
9379 +#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000)
9380 +#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000)
9381 +#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000)
9382 +#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000)
9383 +#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000)
9384 +#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000)
9385 +#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000)
9386 +#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000)
9387 +#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000)
9388 +#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000)
9389 +#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000)
9390 +#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000)
9391 +#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000)
9392 +#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000)
9393 +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
9394 +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
9395 +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
9396 +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
9397 +
9398 +/* Bit definitions and macros for INTFRCL */
9399 +#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001)
9400 +#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002)
9401 +#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004)
9402 +#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008)
9403 +#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010)
9404 +#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020)
9405 +#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040)
9406 +#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080)
9407 +#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100)
9408 +#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200)
9409 +#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400)
9410 +#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800)
9411 +#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000)
9412 +#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000)
9413 +#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000)
9414 +#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000)
9415 +#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000)
9416 +#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000)
9417 +#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000)
9418 +#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000)
9419 +#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000)
9420 +#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000)
9421 +#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000)
9422 +#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000)
9423 +#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000)
9424 +#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000)
9425 +#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000)
9426 +#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000)
9427 +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
9428 +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
9429 +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
9430 +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
9431 +
9432 +/* Bit definitions and macros for ICONFIG */
9433 +#define MCF_INTC_ICONFIG_EMASK (0x0020)
9434 +#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200)
9435 +#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400)
9436 +#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800)
9437 +#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000)
9438 +#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000)
9439 +#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000)
9440 +#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000)
9441 +
9442 +/* Bit definitions and macros for SIMR */
9443 +#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F))
9444 +
9445 +/* Bit definitions and macros for CIMR */
9446 +#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F))
9447 +
9448 +/* Bit definitions and macros for CLMASK */
9449 +#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F))
9450 +
9451 +/* Bit definitions and macros for SLMASK */
9452 +#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F))
9453 +
9454 +/* Bit definitions and macros for ICR group */
9455 +#define MCF_INTC_ICR_IL(x) (((x)&0x07))
9456 +
9457 +/* Bit definitions and macros for ICR1 */
9458 +#define MCF_INTC_ICR1_IL(x) (((x)&0x07))
9459 +
9460 +/* Bit definitions and macros for ICR2 */
9461 +#define MCF_INTC_ICR2_IL(x) (((x)&0x07))
9462 +
9463 +/* Bit definitions and macros for ICR3 */
9464 +#define MCF_INTC_ICR3_IL(x) (((x)&0x07))
9465 +
9466 +/* Bit definitions and macros for ICR4 */
9467 +#define MCF_INTC_ICR4_IL(x) (((x)&0x07))
9468 +
9469 +/* Bit definitions and macros for ICR5 */
9470 +#define MCF_INTC_ICR5_IL(x) (((x)&0x07))
9471 +
9472 +/* Bit definitions and macros for ICR6 */
9473 +#define MCF_INTC_ICR6_IL(x) (((x)&0x07))
9474 +
9475 +/* Bit definitions and macros for ICR7 */
9476 +#define MCF_INTC_ICR7_IL(x) (((x)&0x07))
9477 +
9478 +/* Bit definitions and macros for ICR8 */
9479 +#define MCF_INTC_ICR8_IL(x) (((x)&0x07))
9480 +
9481 +/* Bit definitions and macros for ICR9 */
9482 +#define MCF_INTC_ICR9_IL(x) (((x)&0x07))
9483 +
9484 +/* Bit definitions and macros for ICR10 */
9485 +#define MCF_INTC_ICR10_IL(x) (((x)&0x07))
9486 +
9487 +/* Bit definitions and macros for ICR11 */
9488 +#define MCF_INTC_ICR11_IL(x) (((x)&0x07))
9489 +
9490 +/* Bit definitions and macros for ICR12 */
9491 +#define MCF_INTC_ICR12_IL(x) (((x)&0x07))
9492 +
9493 +/* Bit definitions and macros for ICR13 */
9494 +#define MCF_INTC_ICR13_IL(x) (((x)&0x07))
9495 +
9496 +/* Bit definitions and macros for ICR14 */
9497 +#define MCF_INTC_ICR14_IL(x) (((x)&0x07))
9498 +
9499 +/* Bit definitions and macros for ICR15 */
9500 +#define MCF_INTC_ICR15_IL(x) (((x)&0x07))
9501 +
9502 +/* Bit definitions and macros for ICR16 */
9503 +#define MCF_INTC_ICR16_IL(x) (((x)&0x07))
9504 +
9505 +/* Bit definitions and macros for ICR17 */
9506 +#define MCF_INTC_ICR17_IL(x) (((x)&0x07))
9507 +
9508 +/* Bit definitions and macros for ICR18 */
9509 +#define MCF_INTC_ICR18_IL(x) (((x)&0x07))
9510 +
9511 +/* Bit definitions and macros for ICR19 */
9512 +#define MCF_INTC_ICR19_IL(x) (((x)&0x07))
9513 +
9514 +/* Bit definitions and macros for ICR20 */
9515 +#define MCF_INTC_ICR20_IL(x) (((x)&0x07))
9516 +
9517 +/* Bit definitions and macros for ICR21 */
9518 +#define MCF_INTC_ICR21_IL(x) (((x)&0x07))
9519 +
9520 +/* Bit definitions and macros for ICR22 */
9521 +#define MCF_INTC_ICR22_IL(x) (((x)&0x07))
9522 +
9523 +/* Bit definitions and macros for ICR23 */
9524 +#define MCF_INTC_ICR23_IL(x) (((x)&0x07))
9525 +
9526 +/* Bit definitions and macros for ICR24 */
9527 +#define MCF_INTC_ICR24_IL(x) (((x)&0x07))
9528 +
9529 +/* Bit definitions and macros for ICR25 */
9530 +#define MCF_INTC_ICR25_IL(x) (((x)&0x07))
9531 +
9532 +/* Bit definitions and macros for ICR26 */
9533 +#define MCF_INTC_ICR26_IL(x) (((x)&0x07))
9534 +
9535 +/* Bit definitions and macros for ICR27 */
9536 +#define MCF_INTC_ICR27_IL(x) (((x)&0x07))
9537 +
9538 +/* Bit definitions and macros for ICR28 */
9539 +#define MCF_INTC_ICR28_IL(x) (((x)&0x07))
9540 +
9541 +/* Bit definitions and macros for ICR29 */
9542 +#define MCF_INTC_ICR29_IL(x) (((x)&0x07))
9543 +
9544 +/* Bit definitions and macros for ICR30 */
9545 +#define MCF_INTC_ICR30_IL(x) (((x)&0x07))
9546 +
9547 +/* Bit definitions and macros for ICR31 */
9548 +#define MCF_INTC_ICR31_IL(x) (((x)&0x07))
9549 +
9550 +/* Bit definitions and macros for ICR32 */
9551 +#define MCF_INTC_ICR32_IL(x) (((x)&0x07))
9552 +
9553 +/* Bit definitions and macros for ICR33 */
9554 +#define MCF_INTC_ICR33_IL(x) (((x)&0x07))
9555 +
9556 +/* Bit definitions and macros for ICR34 */
9557 +#define MCF_INTC_ICR34_IL(x) (((x)&0x07))
9558 +
9559 +/* Bit definitions and macros for ICR35 */
9560 +#define MCF_INTC_ICR35_IL(x) (((x)&0x07))
9561 +
9562 +/* Bit definitions and macros for ICR36 */
9563 +#define MCF_INTC_ICR36_IL(x) (((x)&0x07))
9564 +
9565 +/* Bit definitions and macros for ICR37 */
9566 +#define MCF_INTC_ICR37_IL(x) (((x)&0x07))
9567 +
9568 +/* Bit definitions and macros for ICR38 */
9569 +#define MCF_INTC_ICR38_IL(x) (((x)&0x07))
9570 +
9571 +/* Bit definitions and macros for ICR39 */
9572 +#define MCF_INTC_ICR39_IL(x) (((x)&0x07))
9573 +
9574 +/* Bit definitions and macros for ICR40 */
9575 +#define MCF_INTC_ICR40_IL(x) (((x)&0x07))
9576 +
9577 +/* Bit definitions and macros for ICR41 */
9578 +#define MCF_INTC_ICR41_IL(x) (((x)&0x07))
9579 +
9580 +/* Bit definitions and macros for ICR42 */
9581 +#define MCF_INTC_ICR42_IL(x) (((x)&0x07))
9582 +
9583 +/* Bit definitions and macros for ICR43 */
9584 +#define MCF_INTC_ICR43_IL(x) (((x)&0x07))
9585 +
9586 +/* Bit definitions and macros for ICR44 */
9587 +#define MCF_INTC_ICR44_IL(x) (((x)&0x07))
9588 +
9589 +/* Bit definitions and macros for ICR45 */
9590 +#define MCF_INTC_ICR45_IL(x) (((x)&0x07))
9591 +
9592 +/* Bit definitions and macros for ICR46 */
9593 +#define MCF_INTC_ICR46_IL(x) (((x)&0x07))
9594 +
9595 +/* Bit definitions and macros for ICR47 */
9596 +#define MCF_INTC_ICR47_IL(x) (((x)&0x07))
9597 +
9598 +/* Bit definitions and macros for ICR48 */
9599 +#define MCF_INTC_ICR48_IL(x) (((x)&0x07))
9600 +
9601 +/* Bit definitions and macros for ICR49 */
9602 +#define MCF_INTC_ICR49_IL(x) (((x)&0x07))
9603 +
9604 +/* Bit definitions and macros for ICR50 */
9605 +#define MCF_INTC_ICR50_IL(x) (((x)&0x07))
9606 +
9607 +/* Bit definitions and macros for ICR51 */
9608 +#define MCF_INTC_ICR51_IL(x) (((x)&0x07))
9609 +
9610 +/* Bit definitions and macros for ICR52 */
9611 +#define MCF_INTC_ICR52_IL(x) (((x)&0x07))
9612 +
9613 +/* Bit definitions and macros for ICR53 */
9614 +#define MCF_INTC_ICR53_IL(x) (((x)&0x07))
9615 +
9616 +/* Bit definitions and macros for ICR54 */
9617 +#define MCF_INTC_ICR54_IL(x) (((x)&0x07))
9618 +
9619 +/* Bit definitions and macros for ICR55 */
9620 +#define MCF_INTC_ICR55_IL(x) (((x)&0x07))
9621 +
9622 +/* Bit definitions and macros for ICR56 */
9623 +#define MCF_INTC_ICR56_IL(x) (((x)&0x07))
9624 +
9625 +/* Bit definitions and macros for ICR57 */
9626 +#define MCF_INTC_ICR57_IL(x) (((x)&0x07))
9627 +
9628 +/* Bit definitions and macros for ICR58 */
9629 +#define MCF_INTC_ICR58_IL(x) (((x)&0x07))
9630 +
9631 +/* Bit definitions and macros for ICR59 */
9632 +#define MCF_INTC_ICR59_IL(x) (((x)&0x07))
9633 +
9634 +/* Bit definitions and macros for ICR60 */
9635 +#define MCF_INTC_ICR60_IL(x) (((x)&0x07))
9636 +
9637 +/* Bit definitions and macros for ICR61 */
9638 +#define MCF_INTC_ICR61_IL(x) (((x)&0x07))
9639 +
9640 +/* Bit definitions and macros for ICR62 */
9641 +#define MCF_INTC_ICR62_IL(x) (((x)&0x07))
9642 +
9643 +/* Bit definitions and macros for ICR63 */
9644 +#define MCF_INTC_ICR63_IL(x) (((x)&0x07))
9645 +
9646 +/* Bit definitions and macros for SWIACK */
9647 +#define MCF_INTC_SWIACK_VECTOR(x) (x)
9648 +
9649 +/* Bit definitions and macros for LIACK group */
9650 +#define MCF_INTC_LIACK_VECTOR(x) (x)
9651 +
9652 +/* Bit definitions and macros for L1IACK */
9653 +#define MCF_INTC_L1IACK_VECTOR(x) (x)
9654 +
9655 +/* Bit definitions and macros for L2IACK */
9656 +#define MCF_INTC_L2IACK_VECTOR(x) (x)
9657 +
9658 +/* Bit definitions and macros for L3IACK */
9659 +#define MCF_INTC_L3IACK_VECTOR(x) (x)
9660 +
9661 +/* Bit definitions and macros for L4IACK */
9662 +#define MCF_INTC_L4IACK_VECTOR(x) (x)
9663 +
9664 +/* Bit definitions and macros for L5IACK */
9665 +#define MCF_INTC_L5IACK_VECTOR(x) (x)
9666 +
9667 +/* Bit definitions and macros for L6IACK */
9668 +#define MCF_INTC_L6IACK_VECTOR(x) (x)
9669 +
9670 +/* Bit definitions and macros for L7IACK */
9671 +#define MCF_INTC_L7IACK_VECTOR(x) (x)
9672 +
9673 +/********************************************************************/
9674 +
9675 +#endif /* __MCF5445X_INTC_H__ */
9676 --- /dev/null
9677 +++ b/arch/m68k/include/asm/mcf5445x_pci.h
9678 @@ -0,0 +1,238 @@
9679 +/*
9680 + * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
9681 + *
9682 + * Kurt Mahan kmahan@freescale.com
9683 + *
9684 + * This program is free software; you can redistribute it and/or modify it
9685 + * under the terms of the GNU General Public License as published by the
9686 + * Free Software Foundation; either version 2 of the License, or (at your
9687 + * option) any later version.
9688 + */
9689 +
9690 +#ifndef __MCF5445X_PCI_H__
9691 +#define __MCF5445X_PCI_H__
9692 +
9693 +/*********************************************************************
9694 +*
9695 +* PCI Bus Controller (PCI)
9696 +*
9697 +*********************************************************************/
9698 +
9699 +/* Register read/write macros */
9700 +#define MCF_PCI_PCIIDR MCF_REG32(0xFC0A8000)
9701 +#define MCF_PCI_PCISCR MCF_REG32(0xFC0A8004)
9702 +#define MCF_PCI_PCICCRIR MCF_REG32(0xFC0A8008)
9703 +#define MCF_PCI_PCICR1 MCF_REG32(0xFC0A800C)
9704 +#define MCF_PCI_PCIBAR0 MCF_REG32(0xFC0A8010)
9705 +#define MCF_PCI_PCIBAR1 MCF_REG32(0xFC0A8014)
9706 +#define MCF_PCI_PCIBAR2 MCF_REG32(0xFC0A8018)
9707 +#define MCF_PCI_PCIBAR3 MCF_REG32(0xFC0A801C)
9708 +#define MCF_PCI_PCIBAR4 MCF_REG32(0xFC0A8020)
9709 +#define MCF_PCI_PCIBAR5 MCF_REG32(0xFC0A8024)
9710 +#define MCF_PCI_PCISID MCF_REG32(0xFC0A802C)
9711 +#define MCF_PCI_PCICR2 MCF_REG32(0xFC0A803C)
9712 +#define MCF_PCI_PCIGSCR MCF_REG32(0xFC0A8060)
9713 +#define MCF_PCI_PCITBATR0A MCF_REG32(0xFC0A8064)
9714 +#define MCF_PCI_PCITBATR1A MCF_REG32(0xFC0A8068)
9715 +#define MCF_PCI_PCITCR MCF_REG32(0xFC0A806C)
9716 +#define MCF_PCI_PCIIW0BTAR MCF_REG32(0xFC0A8070)
9717 +#define MCF_PCI_PCIIW1BTAR MCF_REG32(0xFC0A8074)
9718 +#define MCF_PCI_PCIIW2BTAR MCF_REG32(0xFC0A8078)
9719 +#define MCF_PCI_PCIIWCR MCF_REG32(0xFC0A8080)
9720 +#define MCF_PCI_PCIICR MCF_REG32(0xFC0A8084)
9721 +#define MCF_PCI_PCIISR MCF_REG32(0xFC0A8088)
9722 +#define MCF_PCI_PCITCR2 MCF_REG32(0xFC0A808C)
9723 +#define MCF_PCI_PCITBATR0 MCF_REG32(0xFC0A8090)
9724 +#define MCF_PCI_PCITBATR1 MCF_REG32(0xFC0A8094)
9725 +#define MCF_PCI_PCITBATR2 MCF_REG32(0xFC0A8098)
9726 +#define MCF_PCI_PCITBATR3 MCF_REG32(0xFC0A809C)
9727 +#define MCF_PCI_PCITBATR4 MCF_REG32(0xFC0A80A0)
9728 +#define MCF_PCI_PCITBATR5 MCF_REG32(0xFC0A80A4)
9729 +#define MCF_PCI_PCICAR MCF_REG32(0xFC0A80F8)
9730 +
9731 +/* Parameterized register read/write macros for multiple registers */
9732 +#define MCF_PCI_PCIIWBTAR(x) MCF_REG32(0xFC0A8070+((x)*0x004))
9733 +
9734 +/* Bit definitions and macros for PCIIDR */
9735 +#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0x0000FFFF))
9736 +#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16)
9737 +
9738 +/* Bit definitions and macros for PCISCR */
9739 +#define MCF_PCI_PCISCR_M (0x00000002)
9740 +#define MCF_PCI_PCISCR_B (0x00000004)
9741 +#define MCF_PCI_PCISCR_SP (0x00000008)
9742 +#define MCF_PCI_PCISCR_MW (0x00000010)
9743 +#define MCF_PCI_PCISCR_PER (0x00000040)
9744 +#define MCF_PCI_PCISCR_S (0x00000100)
9745 +#define MCF_PCI_PCISCR_F (0x00000200)
9746 +#define MCF_PCI_PCISCR_C (0x00100000)
9747 +#define MCF_PCI_PCISCR_66M (0x00200000)
9748 +#define MCF_PCI_PCISCR_R (0x00400000)
9749 +#define MCF_PCI_PCISCR_FC (0x00800000)
9750 +#define MCF_PCI_PCISCR_DP (0x01000000)
9751 +#define MCF_PCI_PCISCR_DT(x) (((x)&0x00000003)<<25)
9752 +#define MCF_PCI_PCISCR_TS (0x08000000)
9753 +#define MCF_PCI_PCISCR_TR (0x10000000)
9754 +#define MCF_PCI_PCISCR_MA (0x20000000)
9755 +#define MCF_PCI_PCISCR_SE (0x40000000)
9756 +#define MCF_PCI_PCISCR_PE (0x80000000)
9757 +
9758 +/* Bit definitions and macros for PCICCRIR */
9759 +#define MCF_PCI_PCICCRIR_REVID(x) (((x)&0x000000FF))
9760 +#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8)
9761 +
9762 +/* Bit definitions and macros for PCICR1 */
9763 +#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F))
9764 +#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8)
9765 +#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16)
9766 +#define MCF_PCI_PCICR1_BIST(x) (((x)&0x000000FF)<<24)
9767 +
9768 +/* Bit definitions and macros for PCIBAR0 */
9769 +#define MCF_PCI_PCIBAR0_IO (0x00000001)
9770 +#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x00000003)<<1)
9771 +#define MCF_PCI_PCIBAR0_PREF (0x00000008)
9772 +#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x00003FFF)<<18)
9773 +
9774 +/* Bit definitions and macros for PCIBAR1 */
9775 +#define MCF_PCI_PCIBAR1_IO (0x00000001)
9776 +#define MCF_PCI_PCIBAR1_PREF (0x00000008)
9777 +#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x00000FFF)<<20)
9778 +
9779 +/* Bit definitions and macros for PCIBAR2 */
9780 +#define MCF_PCI_PCIBAR2_IO (0x00000001)
9781 +#define MCF_PCI_PCIBAR2_RANGE(x) (((x)&0x00000003)<<1)
9782 +#define MCF_PCI_PCIBAR2_PREF (0x00000008)
9783 +#define MCF_PCI_PCIBAR2_BAR2(x) (((x)&0x000003FF)<<22)
9784 +
9785 +/* Bit definitions and macros for PCIBAR3 */
9786 +#define MCF_PCI_PCIBAR3_IO (0x00000001)
9787 +#define MCF_PCI_PCIBAR3_PREF (0x00000008)
9788 +#define MCF_PCI_PCIBAR3_BAR3(x) (((x)&0x000000FF)<<24)
9789 +
9790 +/* Bit definitions and macros for PCIBAR4 */
9791 +#define MCF_PCI_PCIBAR4_IO (0x00000001)
9792 +#define MCF_PCI_PCIBAR4_RANGE(x) (((x)&0x00000003)<<1)
9793 +#define MCF_PCI_PCIBAR4_PREF (0x00000008)
9794 +#define MCF_PCI_PCIBAR4_BAR4(x) (((x)&0x0000001F)<<27)
9795 +
9796 +/* Bit definitions and macros for PCIBAR5 */
9797 +#define MCF_PCI_PCIBAR5_IO (0x00000001)
9798 +#define MCF_PCI_PCIBAR5_PREF (0x00000008)
9799 +#define MCF_PCI_PCIBAR5_BAR5(x) (((x)&0x0000000F)<<28)
9800 +
9801 +/* Bit definitions and macros for PCISID */
9802 +#define MCF_PCI_PCISID_VENDORID(x) (((x)&0x0000FFFF))
9803 +#define MCF_PCI_PCISID_ID(x) (((x)&0x0000FFFF)<<16)
9804 +
9805 +/* Bit definitions and macros for PCICR2 */
9806 +#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0x000000FF))
9807 +#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8)
9808 +#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16)
9809 +#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24)
9810 +
9811 +/* Bit definitions and macros for PCIGSCR */
9812 +#define MCF_PCI_PCIGSCR_PR (0x00000001)
9813 +#define MCF_PCI_PCIGSCR_SEE (0x00001000)
9814 +#define MCF_PCI_PCIGSCR_PEE (0x00002000)
9815 +#define MCF_PCI_PCIGSCR_SE (0x10000000)
9816 +#define MCF_PCI_PCIGSCR_PE (0x20000000)
9817 +
9818 +/* Bit definitions and macros for PCITBATR0A */
9819 +#define MCF_PCI_PCITBATR0A_EN (0x00000001)
9820 +#define MCF_PCI_PCITBATR0A_BAT0(x) (((x)&0x00003FFF)<<18)
9821 +
9822 +/* Bit definitions and macros for PCITBATR1A */
9823 +#define MCF_PCI_PCITBATR1A_EN (0x00000001)
9824 +#define MCF_PCI_PCITBATR1A_BAT1(x) (((x)&0x00000FFF)<<20)
9825 +
9826 +/* Bit definitions and macros for PCITCR */
9827 +#define MCF_PCI_PCITCR_WCT(x) (((x)&0x000000FF))
9828 +#define MCF_PCI_PCITCR_WCD (0x00000100)
9829 +#define MCF_PCI_PCITCR_P (0x00010000)
9830 +#define MCF_PCI_PCITCR_PID (0x00020000)
9831 +#define MCF_PCI_PCITCR_LD (0x01000000)
9832 +
9833 +/* Bit definitions and macros for PCIIWBTAR group */
9834 +#define MCF_PCI_PCIIWBTAR_WBA(x) ((((x)&0xFF000000)))
9835 +#define MCF_PCI_PCIIWBTAR_WAM(x) ((((x)&0xFF000000)
9836 +#define MCF_PCI_PCIIWBTAR_WTA(x) ((((x)&0xFF000000)
9837 +
9838 +/* Bit definitions and macros for PCIIW0BTAR */
9839 +#define MCF_PCI_PCIIW0BTAR_WBA(x) ((((x)&0xFF000000)))
9840 +#define MCF_PCI_PCIIW0BTAR_WAM(x) ((((x)&0xFF000000)
9841 +#define MCF_PCI_PCIIW0BTAR_WTA(x) ((((x)&0xFF000000)
9842 +
9843 +/* Bit definitions and macros for PCIIWCR */
9844 +#define MCF_PCI_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8)
9845 +#define MCF_PCI_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16)
9846 +#define MCF_PCI_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24)
9847 +#define MCF_PCI_PCIIWCR_WINCTRL0_ENABLE (0x01000000)
9848 +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x01000000)
9849 +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000)
9850 +#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000)
9851 +#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x09000000)
9852 +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x00010000)
9853 +#define MCF_PCI_PCIIWCR_WINCTRL1_ENABLE (0x00010000)
9854 +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000)
9855 +#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000)
9856 +#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x00090000)
9857 +#define MCF_PCI_PCIIWCR_WINCTRL2_ENABLE (0x00000100)
9858 +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x00000100)
9859 +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300)
9860 +#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500)
9861 +#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x00000900)
9862 +
9863 +/* Bit definitions and macros for PCIICR */
9864 +#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0x000000FF))
9865 +#define MCF_PCI_PCIICR_TAE (0x01000000)
9866 +#define MCF_PCI_PCIICR_IAE (0x02000000)
9867 +#define MCF_PCI_PCIICR_REE (0x04000000)
9868 +
9869 +/* Bit definitions and macros for PCIISR */
9870 +#define MCF_PCI_PCIISR_TA (0x01000000)
9871 +#define MCF_PCI_PCIISR_IA (0x02000000)
9872 +#define MCF_PCI_PCIISR_RE (0x04000000)
9873 +
9874 +/* Bit definitions and macros for PCITCR2 */
9875 +#define MCF_PCI_PCITCR2_CR (0x00000001)
9876 +#define MCF_PCI_PCITCR2_B0E (0x00000100)
9877 +#define MCF_PCI_PCITCR2_B1E (0x00000200)
9878 +#define MCF_PCI_PCITCR2_B2E (0x00000400)
9879 +#define MCF_PCI_PCITCR2_B3E (0x00000800)
9880 +#define MCF_PCI_PCITCR2_B4E (0x00001000)
9881 +#define MCF_PCI_PCITCR2_B5E (0x00002000)
9882 +
9883 +/* Bit definitions and macros for PCITBATR0 */
9884 +#define MCF_PCI_PCITBATR0_EN (0x00000001)
9885 +#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18)
9886 +
9887 +/* Bit definitions and macros for PCITBATR1 */
9888 +#define MCF_PCI_PCITBATR1_EN (0x00000001)
9889 +#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x00000FFF)<<20)
9890 +
9891 +/* Bit definitions and macros for PCITBATR2 */
9892 +#define MCF_PCI_PCITBATR2_EN (0x00000001)
9893 +#define MCF_PCI_PCITBATR2_BAT2(x) (((x)&0x000003FF)<<22)
9894 +
9895 +/* Bit definitions and macros for PCITBATR3 */
9896 +#define MCF_PCI_PCITBATR3_EN (0x00000001)
9897 +#define MCF_PCI_PCITBATR3_BAT3(x) (((x)&0x000000FF)<<24)
9898 +
9899 +/* Bit definitions and macros for PCITBATR4 */
9900 +#define MCF_PCI_PCITBATR4_EN (0x00000001)
9901 +#define MCF_PCI_PCITBATR4_BAT4(x) (((x)&0x0000001F)<<27)
9902 +
9903 +/* Bit definitions and macros for PCITBATR5 */
9904 +#define MCF_PCI_PCITBATR5_EN (0x00000001)
9905 +#define MCF_PCI_PCITBATR5_BAT5(x) (((x)&0x0000000F)<<28)
9906 +
9907 +/* Bit definitions and macros for PCICAR */
9908 +#define MCF_PCI_PCICAR_DWORD(x) ((x)&0x000000FC)
9909 +#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8)
9910 +#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11)
9911 +#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16)
9912 +#define MCF_PCI_PCICAR_E (0x80000000)
9913 +
9914 +/********************************************************************/
9915 +
9916 +#endif /* __MCF5445X_PCI_H__ */
9917 --- /dev/null
9918 +++ b/arch/m68k/include/asm/mcf5445x_pciarb.h
9919 @@ -0,0 +1,40 @@
9920 +/*
9921 + * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
9922 + *
9923 + * Kurt Mahan kmahan@freescale.com
9924 + *
9925 + * This program is free software; you can redistribute it and/or modify it
9926 + * under the terms of the GNU General Public License as published by the
9927 + * Free Software Foundation; either version 2 of the License, or (at your
9928 + * option) any later version.
9929 + */
9930 +
9931 +#ifndef __MCF5445X_PCIARB_H__
9932 +#define __MCF5445X_PCIARB_H__
9933 +
9934 +/*********************************************************************
9935 +*
9936 +* PCI Arbiter Module (PCIARB)
9937 +*
9938 +*********************************************************************/
9939 +
9940 +/* Register read/write macros */
9941 +#define MCF_PCIARB_PACR MCF_REG32(0xFC0AC000)
9942 +#define MCF_PCIARB_PASR MCF_REG32(0xFC0AC004)
9943 +
9944 +/* Bit definitions and macros for PACR */
9945 +#define MCF_PCIARB_PACR_INTMPRI (0x00000001)
9946 +#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1)
9947 +#define MCF_PCIARB_PACR_RA (0x00008000)
9948 +#define MCF_PCIARB_PACR_INTMINTEN (0x00010000)
9949 +#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17)
9950 +#define MCF_PCIARB_PACR_PKMD (0x40000000)
9951 +#define MCF_PCIARB_PACR_DS (0x80000000)
9952 +
9953 +/* Bit definitions and macros for PASR */
9954 +#define MCF_PCIARB_PASR_ITLMBK (0x00010000)
9955 +#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17)
9956 +
9957 +/********************************************************************/
9958 +
9959 +#endif /* __MCF5445X_PCIARB_H__ */
9960 --- /dev/null
9961 +++ b/arch/m68k/include/asm/mcf5445x_rtc.h
9962 @@ -0,0 +1,114 @@
9963 +/*
9964 + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
9965 + *
9966 + * Author: ChengJu Cai, B22600@freescale.com
9967 + *
9968 + * Description:
9969 + * This file is the register definition of m5445x RTC module
9970 + *
9971 + * Changelog:
9972 + *
9973 + *
9974 + * This file is part of the Linux kernel
9975 + *
9976 + * This is free software; you can redistribute it and/or modify
9977 + * it under the terms of the GNU General Public License as published by
9978 + * the Free Software Foundation; either version 2 of the License, or
9979 + * (at your option) any later version.
9980 + *
9981 + */
9982 +
9983 +#ifndef __MCF5445X_RTC_H__
9984 +#define __MCF5445X_RTC_H__
9985 +
9986 +/*********************************************************************
9987 +*
9988 +* Real-time Clock (RTC)
9989 +*
9990 +*********************************************************************/
9991 +#ifndef MCFINT_VECBASE
9992 +#define MCFINT_VECBASE 64
9993 +#endif
9994 +
9995 +#define MCFSIM_ICR_RTC (0xFC048040 + 63)
9996 +
9997 +/* Register read/write macros */
9998 +#define MCF_RTC_HOURMIN 0xFC03C000
9999 +#define MCF_RTC_SECONDS 0xFC03C004
10000 +#define MCF_RTC_ALRM_HM 0xFC03C008
10001 +#define MCF_RTC_ALRM_SEC 0xFC03C00C
10002 +#define MCF_RTC_CR 0xFC03C010
10003 +#define MCF_RTC_ISR 0xFC03C014
10004 +#define MCF_RTC_IER 0xFC03C018
10005 +#define MCF_RTC_STPWCH 0xFC03C01C
10006 +#define MCF_RTC_DAYS 0xFC03C020
10007 +#define MCF_RTC_ALRM_DAY 0xFC03C024
10008 +#define MCF_RTC_GOCU 0xFC03C034
10009 +#define MCF_RTC_GOCL 0xFC03C038
10010 +
10011 +/* Bit definitions and macros for MCF_RTC_HOURMIN */
10012 +#define MCF_RTC_HOURMIN_MINUTES(x) (((x) & 0x0000003F) << 0)
10013 +#define MCF_RTC_HOURMIN_HOURS(x) (((x) & 0x0000001F) << 8)
10014 +
10015 +/* Bit definitions and macros for MCF_RTC_SECONDS */
10016 +#define MCF_RTC_SECONDS_SECONDS(x) (((x) & 0x0000003F) << 0)
10017 +
10018 +/* Bit definitions and macros for MCF_RTC_ALRM_HM */
10019 +#define MCF_RTC_ALRM_HM_MINUTES(x) (((x) & 0x0000003F) << 0)
10020 +#define MCF_RTC_ALRM_HM_HOURS(x) (((x) & 0x0000001F) << 8)
10021 +
10022 +/* Bit definitions and macros for MCF_RTC_ALRM_SEC */
10023 +#define MCF_RTC_ALRM_SEC_SECONDS(x) (((x) & 0x0000003F) << 0)
10024 +
10025 +/* Bit definitions and macros for MCF_RTC_CR */
10026 +#define MCF_RTC_CR_SWR 0x00000001
10027 +#define MCF_RTC_CR_EN 0x00000080
10028 +
10029 +/* Bit definitions and macros for MCF_RTC_ISR */
10030 +#define MCF_RTC_ISR_SW 0x00000001
10031 +#define MCF_RTC_ISR_MIN 0x00000002
10032 +#define MCF_RTC_ISR_ALM 0x00000004
10033 +#define MCF_RTC_ISR_DAY 0x00000008
10034 +#define MCF_RTC_ISR_1HZ 0x00000010
10035 +#define MCF_RTC_ISR_HR 0x00000020
10036 +#define MCF_RTC_ISR_2HZ 0x00000080
10037 +#define MCF_RTC_ISR_SAM0 0x00000100
10038 +#define MCF_RTC_ISR_SAM1 0x00000200
10039 +#define MCF_RTC_ISR_SAM2 0x00000400
10040 +#define MCF_RTC_ISR_SAM3 0x00000800
10041 +#define MCF_RTC_ISR_SAM4 0x00001000
10042 +#define MCF_RTC_ISR_SAM5 0x00002000
10043 +#define MCF_RTC_ISR_SAM6 0x00004000
10044 +#define MCF_RTC_ISR_SAM7 0x00008000
10045 +
10046 +/* Bit definitions and macros for MCF_RTC_IER */
10047 +#define MCF_RTC_IER_SW 0x00000001
10048 +#define MCF_RTC_IER_MIN 0x00000002
10049 +#define MCF_RTC_IER_ALM 0x00000004
10050 +#define MCF_RTC_IER_DAY 0x00000008
10051 +#define MCF_RTC_IER_1HZ 0x00000010
10052 +#define MCF_RTC_IER_HR 0x00000020
10053 +#define MCF_RTC_IER_2HZ 0x00000080
10054 +#define MCF_RTC_IER_SAM0 0x00000100
10055 +#define MCF_RTC_IER_SAM1 0x00000200
10056 +#define MCF_RTC_IER_SAM2 0x00000400
10057 +#define MCF_RTC_IER_SAM3 0x00000800
10058 +#define MCF_RTC_IER_SAM4 0x00001000
10059 +#define MCF_RTC_IER_SAM5 0x00002000
10060 +#define MCF_RTC_IER_SAM6 0x00004000
10061 +#define MCF_RTC_IER_SAM7 0x00008000
10062 +
10063 +/* Bit definitions and macros for MCF_RTC_STPWCH */
10064 +#define MCF_RTC_STPWCH_CNT(x) (((x) & 0x0000003F) << 0)
10065 +
10066 +/* Bit definitions and macros for MCF_RTC_DAYS */
10067 +#define MCF_RTC_DAYS_DAYS(x) (((x) & 0x0000FFFF) << 0)
10068 +
10069 +/* Bit definitions and macros for MCF_RTC_ALRM_DAY */
10070 +#define MCF_RTC_ALRM_DAY_DAYS(x) (((x) & 0x0000FFFF) << 0)
10071 +
10072 +/* Interrupt source */
10073 +#define MCFINT_RTC 63
10074 +/*********************************************************************/
10075 +
10076 +#endif
10077 --- /dev/null
10078 +++ b/arch/m68k/include/asm/mcf5445x_scm.h
10079 @@ -0,0 +1,48 @@
10080 +/*
10081 + * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
10082 + *
10083 + * Author: ChengJu Cai<B22600@freescale.com>
10084 + *
10085 + * Description:
10086 + * This file is the register definition of m5445x's SCM module
10087 + *
10088 + * Changelog:
10089 + * Thur Sep 03 2009 ChengJu Cai <B22600@freescale.com>
10090 + * - create
10091 + *
10092 + * This file is part of the Linux kernel
10093 + *
10094 + * This is free software; you can redistribute it and/or modify
10095 + * it under the terms of the GNU General Public License as published by
10096 + * the Free Software Foundation; either version 2 of the License, or
10097 + * (at your option) any later version.
10098 + *
10099 + */
10100 +#ifndef __MCF5445X_SCM_H__
10101 +#define __MCF5445X_SCM_H__
10102 +
10103 +/*********************************************************************
10104 +*
10105 +* System Control Module (SCM)
10106 +*
10107 +*********************************************************************/
10108 +
10109 +/* Core Watchdog(CW) Register read/write macros */
10110 +#define MCF_SCM_CWCR MCF_REG16(0xFC040016) /* CW Control Register */
10111 +#define MCF_SCM_CWSR MCF_REG08(0xFC04001B) /* CW Service Register */
10112 +
10113 +/* CW Bit definitions and macros for SWCR */
10114 +#define MCF_SCM_CWCR_RO (0x8000) /* CWCR is read-only */
10115 +#define MCF_SCM_CWCR_CWRWR (0x0100) /* CW run when halted */
10116 +#define MCF_SCM_CWCR_CWE (0x0080) /* CW timer enable */
10117 +#define MCF_SCM_CWCR_CWRI(x) (((x) & 0x03) << 5) /* CW reset/interrupt */
10118 +#define MCF_SCM_CWCR_CWT(x) (((x) & 0x1F) << 0) /* CW time-out period */
10119 +
10120 +#ifdef CONFIG_M54455
10121 +#define MCF_GPT_MAX_TIMEOUT 16
10122 +#elif defined(CONFIG_M54451)
10123 +#define MCF_GPT_MAX_TIMEOUT 17
10124 +#endif
10125 +/********************************************************************/
10126 +
10127 +#endif /* __MCF5445X_SCM_H__ */
10128 --- /dev/null
10129 +++ b/arch/m68k/include/asm/mcf5445x_sdramc.h
10130 @@ -0,0 +1,142 @@
10131 +/*
10132 + * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
10133 + *
10134 + * Matt Waddel Matt.Waddel@freescale.com
10135 + *
10136 + * This program is free software; you can redistribute it and/or modify it
10137 + * under the terms of the GNU General Public License as published by the
10138 + * Free Software Foundation; either version 2 of the License, or (at your
10139 + * option) any later version.
10140 + */
10141 +
10142 +#ifndef __MCF5445X_SDRAMC_H__
10143 +#define __MCF5445X_SDRAMC_H__
10144 +
10145 +/*********************************************************************
10146 +*
10147 +* SDRAM Controller (SDRAMC)
10148 +*
10149 +*********************************************************************/
10150 +
10151 +/* Register read/write macros */
10152 +#define MCF_SDRAMC_SDMR \
10153 + (*(vuint32 *)(0xFC0B8000)) /* SDRAM Mode/Extended Mode Register */
10154 +#define MCF_SDRAMC_SDCR \
10155 + (*(vuint32 *)(0xFC0B8004)) /* SDRAM Control Register */
10156 +#define MCF_SDRAMC_SDCFG1 \
10157 + (*(vuint32 *)(0xFC0B8008)) /* SDRAM Configuration Register 1 */
10158 +#define MCF_SDRAMC_SDCFG2 \
10159 + (*(vuint32 *)(0xFC0B800C)) /* SDRAM Configuration Register 2 */
10160 +#define MCF_SDRAMC_SDCS0 \
10161 + (*(vuint32 *)(0xFC0B8110)) /* SDRAM Chip Select Register */
10162 +#define MCF_SDRAMC_SDCS1 \
10163 + (*(vuint32 *)(0xFC0B8114)) /* SDRAM Chip Select Register */
10164 +
10165 +/* Parameterized register read/write macros for multiple registers */
10166 +/* SDRAM Chip Select Register */
10167 +#define MCF_SDRAMC_SDCS(x) (*(vuint32 *)(0xFC0B8110+((x)*0x004)))
10168 +
10169 +/* Bit definitions and macros for SDMR */
10170 +#define MCF_SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
10171 +#define MCF_SDRAMC_SDMR_CMD (0x00010000) /* Command */
10172 +#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
10173 +#define MCF_SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
10174 +#define MCF_SDRAMC_SDMR_BK_LMR (0x00000000)
10175 +#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000)
10176 +
10177 +/* Bit definitions and macros for SDCR */
10178 +#define MCF_SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
10179 +#define MCF_SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
10180 +#define MCF_SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
10181 +#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
10182 +#define MCF_SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
10183 +#define MCF_SDRAMC_SDCR_REF_CNT(x) \
10184 + (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */
10185 +#define MCF_SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
10186 +#define MCF_SDRAMC_SDCR_ADDR_MUX(x) \
10187 + (((x)&0x00000003)<<24) /* Internal Address Mux Select */
10188 +#define MCF_SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
10189 +#define MCF_SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
10190 +#define MCF_SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
10191 +#define MCF_SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */
10192 +/* SDRAM Mode Register Programming Enable */
10193 +#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
10194 +#define MCF_SDRAMC_SDCR_DQS_OE_BOTH (0x00000C00)
10195 +
10196 +/* Bit definitions and macros for SDCFG1 */
10197 +#define MCF_SDRAMC_SDCFG1_WT_LAT(x) \
10198 + (((x)&0x00000007)<<4) /* Write Latency */
10199 +#define MCF_SDRAMC_SDCFG1_REF2ACT(x) \
10200 + (((x)&0x0000000F)<<8) /* Refresh to active delay */
10201 +#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) \
10202 + (((x)&0x00000007)<<12) /* Precharge to active delay */
10203 +#define MCF_SDRAMC_SDCFG1_ACT2RW(x) \
10204 + (((x)&0x00000007)<<16) /* Active to read/write delay */
10205 +#define MCF_SDRAMC_SDCFG1_RD_LAT(x) \
10206 + (((x)&0x0000000F)<<20) /* Read CAS Latency */
10207 +#define MCF_SDRAMC_SDCFG1_SWT2RWP(x) \
10208 + (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */
10209 +#define MCF_SDRAMC_SDCFG1_SRD2RWP(x) \
10210 + (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */
10211 +
10212 +/* Bit definitions and macros for SDCFG2 */
10213 +#define MCF_SDRAMC_SDCFG2_BL(x) \
10214 + (((x)&0x0000000F)<<16) /* Burst Length */
10215 +#define MCF_SDRAMC_SDCFG2_BRD2W(x) \
10216 + (((x)&0x0000000F)<<20) /* Burst read to write delay */
10217 +#define MCF_SDRAMC_SDCFG2_BWT2RWP(x) \
10218 + (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */
10219 +#define MCF_SDRAMC_SDCFG2_BRD2RP(x) \
10220 + (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */
10221 +
10222 +/* Bit definitions and macros for SDCS group */
10223 +#define MCF_SDRAMC_SDCS_CSSZ(x) \
10224 + (((x)&0x0000001F)) /* Chip-Select Size */
10225 +#define MCF_SDRAMC_SDCS_CSBA(x) \
10226 + (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
10227 +#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
10228 +#define MCF_SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
10229 +#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
10230 +#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
10231 +#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
10232 +#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
10233 +#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
10234 +#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
10235 +#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
10236 +#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
10237 +#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
10238 +#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
10239 +#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
10240 +#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
10241 +#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
10242 +
10243 +/* Bit definitions and macros for SDCS0 */
10244 +#define MCF_SDRAMC_SDCS0_CSSZ(x) \
10245 + (((x)&0x0000001F)) /* Chip-Select Size */
10246 +#define MCF_SDRAMC_SDCS0_CSBA(x) \
10247 + (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
10248 +#define MCF_SDRAMC_SDCS0_BA(x) ((x)&0xFFF00000)
10249 +#define MCF_SDRAMC_SDCS0_CSSZ_DISABLE (0x00000000)
10250 +#define MCF_SDRAMC_SDCS0_CSSZ_1MBYTE (0x00000013)
10251 +#define MCF_SDRAMC_SDCS0_CSSZ_2MBYTE (0x00000014)
10252 +#define MCF_SDRAMC_SDCS0_CSSZ_4MBYTE (0x00000015)
10253 +#define MCF_SDRAMC_SDCS0_CSSZ_8MBYTE (0x00000016)
10254 +#define MCF_SDRAMC_SDCS0_CSSZ_16MBYTE (0x00000017)
10255 +#define MCF_SDRAMC_SDCS0_CSSZ_32MBYTE (0x00000018)
10256 +#define MCF_SDRAMC_SDCS0_CSSZ_64MBYTE (0x00000019)
10257 +#define MCF_SDRAMC_SDCS0_CSSZ_128MBYTE (0x0000001A)
10258 +#define MCF_SDRAMC_SDCS0_CSSZ_256MBYTE (0x0000001B)
10259 +#define MCF_SDRAMC_SDCS0_CSSZ_512MBYTE (0x0000001C)
10260 +#define MCF_SDRAMC_SDCS0_CSSZ_1GBYTE (0x0000001D)
10261 +#define MCF_SDRAMC_SDCS0_CSSZ_2GBYTE (0x0000001E)
10262 +#define MCF_SDRAMC_SDCS0_CSSZ_4GBYTE (0x0000001F)
10263 +
10264 +/* Bit definitions and macros for SDCS1 */
10265 +#define MCF_SDRAMC_SDCS1_CSSZ(x) \
10266 + (((x)&0x0000001F)) /* Chip-Select Size */
10267 +#define MCF_SDRAMC_SDCS1_CSBA(x) \
10268 + (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
10269 +
10270 +/********************************************************************/
10271 +
10272 +#endif /* __MCF5445X_SDRAMC_H__ */
10273 --- /dev/null
10274 +++ b/arch/m68k/include/asm/mcf5445x_ssi.h
10275 @@ -0,0 +1,187 @@
10276 +/*
10277 + * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
10278 + *
10279 + * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
10280 + *
10281 + * This program is free software; you can redistribute it and/or modify it
10282 + * under the terms of the GNU General Public License as published by the
10283 + * Free Software Foundation; either version 2 of the License, or (at your
10284 + * option) any later version.
10285 + */
10286 +
10287 +#ifndef __MCF5445X_SSI_H__
10288 +#define __MCF5445X_SSI_H__
10289 +
10290 +/*********************************************************************
10291 +*
10292 +* Synchronous Serial Interface (SSI)
10293 +*
10294 +*********************************************************************/
10295 +
10296 +/* Register read/write macros */
10297 +#define MCF_SSI_TX0 MCF_REG32(0xFC0BC000)
10298 +#define MCF_SSI_TX1 MCF_REG32(0xFC0BC004)
10299 +#define MCF_SSI_RX0 MCF_REG32(0xFC0BC008)
10300 +#define MCF_SSI_RX1 MCF_REG32(0xFC0BC00C)
10301 +#define MCF_SSI_CR MCF_REG32(0xFC0BC010)
10302 +#define MCF_SSI_ISR MCF_REG32(0xFC0BC014)
10303 +#define MCF_SSI_IER MCF_REG32(0xFC0BC018)
10304 +#define MCF_SSI_TCR MCF_REG32(0xFC0BC01C)
10305 +#define MCF_SSI_RCR MCF_REG32(0xFC0BC020)
10306 +#define MCF_SSI_CCR MCF_REG32(0xFC0BC024)
10307 +#define MCF_SSI_FCSR MCF_REG32(0xFC0BC02C)
10308 +#define MCF_SSI_ACR MCF_REG32(0xFC0BC038)
10309 +#define MCF_SSI_ACADD MCF_REG32(0xFC0BC03C)
10310 +#define MCF_SSI_ACDAT MCF_REG32(0xFC0BC040)
10311 +#define MCF_SSI_ATAG MCF_REG32(0xFC0BC044)
10312 +#define MCF_SSI_TMASK MCF_REG32(0xFC0BC048)
10313 +#define MCF_SSI_RMASK MCF_REG32(0xFC0BC04C)
10314 +
10315 +/* Parameterized register read/write macros for multiple registers */
10316 +#define MCF_SSI_TX(x) MCF_REG32(0xFC0BC000+((x)*0x004))
10317 +#define MCF_SSI_RX(x) MCF_REG32(0xFC0BC008+((x)*0x004))
10318 +
10319 +/* Bit definitions and macros for TX group */
10320 +#define MCF_SSI_TX_SSI_TX(x) (x)
10321 +
10322 +/* Bit definitions and macros for TX0 */
10323 +#define MCF_SSI_TX0_SSI_TX(x) (x)
10324 +
10325 +/* Bit definitions and macros for TX1 */
10326 +#define MCF_SSI_TX1_SSI_TX(x) (x)
10327 +
10328 +/* Bit definitions and macros for RX group */
10329 +#define MCF_SSI_RX_SSI_RX(x) (x)
10330 +
10331 +/* Bit definitions and macros for RX0 */
10332 +#define MCF_SSI_RX0_SSI_RX(x) (x)
10333 +
10334 +/* Bit definitions and macros for RX1 */
10335 +#define MCF_SSI_RX1_SSI_RX(x) (x)
10336 +
10337 +/* Bit definitions and macros for CR */
10338 +#define MCF_SSI_CR_SSI_EN (0x00000001)
10339 +#define MCF_SSI_CR_TE (0x00000002)
10340 +#define MCF_SSI_CR_RE (0x00000004)
10341 +#define MCF_SSI_CR_NET (0x00000008)
10342 +#define MCF_SSI_CR_SYN (0x00000010)
10343 +#define MCF_SSI_CR_I2S(x) (((x)&0x00000003)<<5)
10344 +#define MCF_SSI_CR_MCE (0x00000080)
10345 +#define MCF_SSI_CR_TCH (0x00000100)
10346 +#define MCF_SSI_CR_CIS (0x00000200)
10347 +#define MCF_SSI_CR_I2S_NORMAL (0x00000000)
10348 +#define MCF_SSI_CR_I2S_MASTER (0x00000020)
10349 +#define MCF_SSI_CR_I2S_SLAVE (0x00000040)
10350 +
10351 +/* Bit definitions and macros for ISR */
10352 +#define MCF_SSI_ISR_TFE0 (0x00000001)
10353 +#define MCF_SSI_ISR_TFE1 (0x00000002)
10354 +#define MCF_SSI_ISR_RFF0 (0x00000004)
10355 +#define MCF_SSI_ISR_RFF1 (0x00000008)
10356 +#define MCF_SSI_ISR_RLS (0x00000010)
10357 +#define MCF_SSI_ISR_TLS (0x00000020)
10358 +#define MCF_SSI_ISR_RFS (0x00000040)
10359 +#define MCF_SSI_ISR_TFS (0x00000080)
10360 +#define MCF_SSI_ISR_TUE0 (0x00000100)
10361 +#define MCF_SSI_ISR_TUE1 (0x00000200)
10362 +#define MCF_SSI_ISR_ROE0 (0x00000400)
10363 +#define MCF_SSI_ISR_ROE1 (0x00000800)
10364 +#define MCF_SSI_ISR_TDE0 (0x00001000)
10365 +#define MCF_SSI_ISR_TDE1 (0x00002000)
10366 +#define MCF_SSI_ISR_RDR0 (0x00004000)
10367 +#define MCF_SSI_ISR_RDR1 (0x00008000)
10368 +#define MCF_SSI_ISR_RXT (0x00010000)
10369 +#define MCF_SSI_ISR_CMDDU (0x00020000)
10370 +#define MCF_SSI_ISR_CMDAU (0x00040000)
10371 +
10372 +/* Bit definitions and macros for IER */
10373 +#define MCF_SSI_IER_TFE0 (0x00000001)
10374 +#define MCF_SSI_IER_TFE1 (0x00000002)
10375 +#define MCF_SSI_IER_RFF0 (0x00000004)
10376 +#define MCF_SSI_IER_RFF1 (0x00000008)
10377 +#define MCF_SSI_IER_RLS (0x00000010)
10378 +#define MCF_SSI_IER_TLS (0x00000020)
10379 +#define MCF_SSI_IER_RFS (0x00000040)
10380 +#define MCF_SSI_IER_TFS (0x00000080)
10381 +#define MCF_SSI_IER_TUE0 (0x00000100)
10382 +#define MCF_SSI_IER_TUE1 (0x00000200)
10383 +#define MCF_SSI_IER_ROE0 (0x00000400)
10384 +#define MCF_SSI_IER_ROE1 (0x00000800)
10385 +#define MCF_SSI_IER_TDE0 (0x00001000)
10386 +#define MCF_SSI_IER_TDE1 (0x00002000)
10387 +#define MCF_SSI_IER_RDR0 (0x00004000)
10388 +#define MCF_SSI_IER_RDR1 (0x00008000)
10389 +#define MCF_SSI_IER_RXT (0x00010000)
10390 +#define MCF_SSI_IER_CMDU (0x00020000)
10391 +#define MCF_SSI_IER_CMDAU (0x00040000)
10392 +#define MCF_SSI_IER_TIE (0x00080000)
10393 +#define MCF_SSI_IER_TDMAE (0x00100000)
10394 +#define MCF_SSI_IER_RIE (0x00200000)
10395 +#define MCF_SSI_IER_RDMAE (0x00400000)
10396 +
10397 +/* Bit definitions and macros for TCR */
10398 +#define MCF_SSI_TCR_TEFS (0x00000001)
10399 +#define MCF_SSI_TCR_TFSL (0x00000002)
10400 +#define MCF_SSI_TCR_TFSI (0x00000004)
10401 +#define MCF_SSI_TCR_TSCKP (0x00000008)
10402 +#define MCF_SSI_TCR_TSHFD (0x00000010)
10403 +#define MCF_SSI_TCR_TXDIR (0x00000020)
10404 +#define MCF_SSI_TCR_TFDIR (0x00000040)
10405 +#define MCF_SSI_TCR_TFEN0 (0x00000080)
10406 +#define MCF_SSI_TCR_TFEN1 (0x00000100)
10407 +#define MCF_SSI_TCR_TXBIT0 (0x00000200)
10408 +
10409 +/* Bit definitions and macros for RCR */
10410 +#define MCF_SSI_RCR_REFS (0x00000001)
10411 +#define MCF_SSI_RCR_RFSL (0x00000002)
10412 +#define MCF_SSI_RCR_RFSI (0x00000004)
10413 +#define MCF_SSI_RCR_RSCKP (0x00000008)
10414 +#define MCF_SSI_RCR_RSHFD (0x00000010)
10415 +#define MCF_SSI_RCR_RFEN0 (0x00000080)
10416 +#define MCF_SSI_RCR_RFEN1 (0x00000100)
10417 +#define MCF_SSI_RCR_RXBIT0 (0x00000200)
10418 +#define MCF_SSI_RCR_RXEXT (0x00000400)
10419 +
10420 +/* Bit definitions and macros for CCR */
10421 +#define MCF_SSI_CCR_PM(x) (((x)&0x000000FF))
10422 +#define MCF_SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
10423 +#define MCF_SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
10424 +#define MCF_SSI_CCR_PSR (0x00020000)
10425 +#define MCF_SSI_CCR_DIV2 (0x00040000)
10426 +
10427 +/* Bit definitions and macros for FCSR */
10428 +#define MCF_SSI_FCSR_TFWM0(x) (((x)&0x0000000F))
10429 +#define MCF_SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
10430 +#define MCF_SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
10431 +#define MCF_SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
10432 +#define MCF_SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
10433 +#define MCF_SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
10434 +#define MCF_SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
10435 +#define MCF_SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
10436 +
10437 +/* Bit definitions and macros for ACR */
10438 +#define MCF_SSI_ACR_AC97EN (0x00000001)
10439 +#define MCF_SSI_ACR_FV (0x00000002)
10440 +#define MCF_SSI_ACR_TIF (0x00000004)
10441 +#define MCF_SSI_ACR_RD (0x00000008)
10442 +#define MCF_SSI_ACR_WR (0x00000010)
10443 +#define MCF_SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
10444 +
10445 +/* Bit definitions and macros for ACADD */
10446 +#define MCF_SSI_ACADD_SSI_ACADD(x) (((x)&0x0007FFFF))
10447 +
10448 +/* Bit definitions and macros for ACDAT */
10449 +#define MCF_SSI_ACDAT_SSI_ACDAT(x) (((x)&0x0007FFFF))
10450 +
10451 +/* Bit definitions and macros for ATAG */
10452 +#define MCF_SSI_ATAG_DDI_ATAG(x) (((x)&0x0000FFFF))
10453 +
10454 +/* Bit definitions and macros for TMASK */
10455 +#define MCF_SSI_TMASK_SSI_TMASK(x) (x)
10456 +
10457 +/* Bit definitions and macros for RMASK */
10458 +#define MCF_SSI_RMASK_SSI_RMASK(x) (x)
10459 +
10460 +/********************************************************************/
10461 +
10462 +#endif /* __MCF5445X_SSI_H__ */
10463 --- /dev/null
10464 +++ b/arch/m68k/include/asm/mcf5445x_xbs.h
10465 @@ -0,0 +1,81 @@
10466 +/*
10467 + * Copyright (C) 2007-2011 Freescale Semiconductor, Inc. All Rights Reserved.
10468 + *
10469 + * Kurt Mahan kmahan@freescale.com
10470 + *
10471 + * This program is free software; you can redistribute it and/or modify it
10472 + * under the terms of the GNU General Public License as published by the
10473 + * Free Software Foundation; either version 2 of the License, or (at your
10474 + * option) any later version.
10475 + */
10476 +
10477 +#ifndef __MCF5445X_XBS_H__
10478 +#define __MCF5445X_XBS_H__
10479 +
10480 +/*
10481 + * Crossbar Switch (XBS)
10482 + */
10483 +
10484 +/* Register read/write macros */
10485 +#define MCF_XBS_PRS1 MCF_REG32(0xFC004100) /* Flexbus Priority */
10486 +#define MCF_XBS_CRS1 MCF_REG32(0xFC004110) /* Flexbus Control */
10487 +#define MCF_XBS_PRS2 MCF_REG32(0xFC004200) /* SDRam Priority */
10488 +#define MCF_XBS_CRS2 MCF_REG32(0xFC004210) /* SDRam Control */
10489 +#define MCF_XBS_PRS3 MCF_REG32(0xFC004300) /* ATA Priority */
10490 +#define MCF_XBS_CRS3 MCF_REG32(0xFC004310) /* ATA Control */
10491 +#define MCF_XBS_PRS4 MCF_REG32(0xFC004400) /* SRAM Priority */
10492 +#define MCF_XBS_CRS4 MCF_REG32(0xFC004410) /* SRAM Control */
10493 +#define MCF_XBS_PRS5 MCF_REG32(0xFC004500) /* PCI Priority */
10494 +#define MCF_XBS_CRS5 MCF_REG32(0xFC004510) /* PCI Control */
10495 +#define MCF_XBS_PRS6 MCF_REG32(0xFC004600) /* Slave6 Priority */
10496 +#define MCF_XBS_CRS6 MCF_REG32(0xFC004610) /* Slave6 Control */
10497 +#define MCF_XBS_PRS7 MCF_REG32(0xFC004700) /* Other Priority */
10498 +#define MCF_XBS_CRS7 MCF_REG32(0xFC004710) /* Other Control */
10499 +
10500 +/* Priorities */
10501 +#define MCF_XBS_PRI_1 0 /* Level 1 (highest) */
10502 +#define MCF_XBS_PRI_2 1 /* Level 2 */
10503 +#define MCF_XBS_PRI_3 2 /* Level 3 */
10504 +#define MCF_XBS_PRI_4 3 /* Level 4 */
10505 +#define MCF_XBS_PRI_5 4 /* Level 5 */
10506 +#define MCF_XBS_PRI_6 5 /* Level 6 */
10507 +#define MCF_XBS_PRI_7 6 /* Level 7 (lowest) */
10508 +#define MCF_XBS_PRI_MASK 7 /* Mask (Not a valid level) */
10509 +
10510 +/* Priority Register (PRSn) Defs */
10511 +#define MCF_XBS_PRS_MACRO(m, p) ((p)<<((m)<<2))
10512 +#define MCF_XBS_PRS_M0(p) MCF_XBS_PRS_MACRO(0, p) /* Coldfire Core */
10513 +#define MCF_XBS_PRS_M1(p) MCF_XBS_PRS_MACRO(1, p) /* eDMA */
10514 +#define MCF_XBS_PRS_M2(p) MCF_XBS_PRS_MACRO(2, p) /* FEC0 */
10515 +#define MCF_XBS_PRS_M3(p) MCF_XBS_PRS_MACRO(3, p) /* FEC1 */
10516 +#define MCF_XBS_PRS_M4(p) MCF_XBS_PRS_MACRO(4, p) /* Master 4 */
10517 +#define MCF_XBS_PRS_M5(p) MCF_XBS_PRS_MACRO(5, p) /* PCI */
10518 +#define MCF_XBS_PRS_M6(p) MCF_XBS_PRS_MACRO(6, p) /* USB OTG */
10519 +#define MCF_XBS_PRS_M7(p) MCF_XBS_PRS_MACRO(7, p) /* Serial Boot */
10520 +
10521 +/* Control Register (CRSn) Defs */
10522 +#define MCF_XBS_CRS_RO 0x80000000 /* Read Only */
10523 +#define MCF_XBS_CRS_ARB 0x00000100 /* Arbitration Mode */
10524 +#define MCF_XBS_CRS_PCTL 0x00000030 /* Parking Control */
10525 +#define MCF_XBS_CRS_PARK 0x00000007 /* Park Location */
10526 +
10527 +/* MCF_XBS_CRS_ARB Defs */
10528 +#define MCF_ABS_CRS_ARB_FIXED 0x00000000 /* Fixed priority */
10529 +#define MCF_ABS_CRS_ARB_ROUND 0x00000100 /* Round Robin priority */
10530 +
10531 +/* MCF_XBS_CRS_PCTL Defs */
10532 +#define MCF_ABS_CRS_PCTL_PARK 0x00000000 /* Park on the defined PARK */
10533 +#define MCF_ABS_CRS_PCTL_LAST 0x00000010 /* Park on the last master */
10534 +#define MCF_ABS_CRS_PCTL_NONE 0x00000020 /* Don't park */
10535 +
10536 +/* MCF_XBS_CRS_PARK Defs */
10537 +#define MCF_ABS_CRS_PARK_M0 0x00000000 /* Park on Coldfire Core */
10538 +#define MCF_ABS_CRS_PARK_M1 0x00000001 /* Park on eDMA */
10539 +#define MCF_ABS_CRS_PARK_M2 0x00000002 /* Park on FEC0 */
10540 +#define MCF_ABS_CRS_PARK_M3 0x00000003 /* Park on FEC1 */
10541 +#define MCF_ABS_CRS_PARK_M4 0x00000004 /* Park on Reserved */
10542 +#define MCF_ABS_CRS_PARK_M5 0x00000005 /* Park on PCI */
10543 +#define MCF_ABS_CRS_PARK_M6 0x00000006 /* Park on USB OTG */
10544 +#define MCF_ABS_CRS_PARK_M7 0x00000007 /* Park on Serial Boot */
10545 +
10546 +#endif /* __MCF5445X_XBS_H__ */
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