target/linux/cns3xxx/patches-3.3/470-gpio_irq.patch

   1 --- a/arch/arm/mach-cns3xxx/Makefile
   2 +++ b/arch/arm/mach-cns3xxx/Makefile
   3 @@ -1,4 +1,4 @@
   4 -obj-$(CONFIG_ARCH_CNS3XXX)             += core.o pm.o devices.o
   5 +obj-$(CONFIG_ARCH_CNS3XXX)             += core.o gpio.o pm.o devices.o
   6  obj-$(CONFIG_PCI)                      += pcie.o
   7  obj-$(CONFIG_MACH_CNS3420VB)           += cns3420vb.o
   8  obj-$(CONFIG_MACH_GW2388)              += laguna.o
   9 --- a/arch/arm/mach-cns3xxx/cns3420vb.c
  10 +++ b/arch/arm/mach-cns3xxx/cns3420vb.c
  11 @@ -199,7 +199,10 @@ static void __init cns3420_init(void)
  12
  13         cns3xxx_ahci_init();
  14         cns3xxx_sdhci_init();
  15 -
  16 +       cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
  17 +               NR_IRQS_CNS3XXX);
  18 +       cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
  19 +               NR_IRQS_CNS3XXX + 32);
  20         cns3xxx_pcie_init(0x3);
  21
  22         pm_power_off = cns3xxx_power_off;
  23 --- a/arch/arm/mach-cns3xxx/core.c
  24 +++ b/arch/arm/mach-cns3xxx/core.c
  25 @@ -21,7 +21,6 @@
  26  #include <asm/hardware/gic.h>
  27  #include <asm/smp_twd.h>
  28  #include <asm/hardware/cache-l2x0.h>
  29 -#include <asm/gpio.h>
  30  #include <mach/cns3xxx.h>
  31  #include "core.h"
  32
  33 @@ -83,73 +82,12 @@ static struct map_desc cns3xxx_io_desc[]
  34         },
  35  };
  36
  37 -static inline void gpio_line_config(u8 line, u32 direction)
  38 -{
  39 -       u32 reg;
  40 -       if (direction) {
  41 -               if (line < 32) {
  42 -                       reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
  43 -                       reg |= (1 << line);
  44 -                       __raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
  45 -               } else {
  46 -                       reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
  47 -                       reg |= (1 << (line - 32));
  48 -                       __raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
  49 -               }
  50 -       } else {
  51 -               if (line < 32) {
  52 -                       reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
  53 -                       reg &= ~(1 << line);
  54 -                       __raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
  55 -               } else {
  56 -                       reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
  57 -                       reg &= ~(1 << (line - 32));
  58 -                       __raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
  59 -               }
  60 -       }
  61 -}
  62 -
  63 -static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
  64 -{
  65 -       gpio_line_config(gpio, CNS3XXX_GPIO_IN);
  66 -       return 0;
  67 -}
  68 -
  69 -static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
  70 -{
  71 -       gpio_line_set(gpio, level);
  72 -       gpio_line_config(gpio, CNS3XXX_GPIO_OUT);
  73 -       return 0;
  74 -}
  75 -
  76 -static int cns3xxx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
  77 -{
  78 -       return gpio_get_value(gpio);
  79 -}
  80 -
  81 -static void cns3xxx_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
  82 -{
  83 -       gpio_set_value(gpio, value);
  84 -}
  85 -
  86 -static struct gpio_chip cns3xxx_gpio_chip = {
  87 -       .label                  = "CNS3XXX_GPIO_CHIP",
  88 -       .direction_input        = cns3xxx_gpio_direction_input,
  89 -       .direction_output       = cns3xxx_gpio_direction_output,
  90 -       .get                    = cns3xxx_gpio_get_value,
  91 -       .set                    = cns3xxx_gpio_set_value,
  92 -       .base                   = 0,
  93 -       .ngpio                  = 64,
  94 -};
  95 -
  96  void __init cns3xxx_common_init(void)
  97  {
  98  #ifdef CONFIG_LOCAL_TIMERS
  99         twd_base = (void __iomem *) CNS3XXX_TC11MP_TWD_BASE_VIRT;
 100  #endif
 101         iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
 102 -
 103 -       gpiochip_add(&cns3xxx_gpio_chip);
 104  }
 105
 106  /* used by entry-macro.S */
 107 --- a/arch/arm/Kconfig
 108 +++ b/arch/arm/Kconfig
 109 @@ -366,7 +366,8 @@ config ARCH_CLPS711X
 110  config ARCH_CNS3XXX
 111         bool "Cavium Networks CNS3XXX family"
 112         select CPU_V6K
 113 -       select ARCH_WANT_OPTIONAL_GPIOLIB
 114 +       select ARCH_REQUIRE_GPIOLIB
 115 +       select GENERIC_IRQ_CHIP
 116         select GENERIC_CLOCKEVENTS
 117         select ARM_GIC
 118         select CLKDEV_LOOKUP
 119 --- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
 120 +++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
 121 @@ -627,7 +627,7 @@ int cns3xxx_cpu_clock(void);
 122
 123  #if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX)
 124  #undef NR_IRQS
 125 -#define NR_IRQS                                NR_IRQS_CNS3XXX
 126 +#define NR_IRQS                                (NR_IRQS_CNS3XXX + 64)
 127  #endif
 128
 129  #endif /* __MACH_BOARD_CNS3XXX_H */