target/linux/bcm63xx/patches-5.15/416-BCM63XX-add-a-fixup-for-ath9k-devices.patch

   1 From bbebbf735a02b6d044ed928978ab4bd5f1833364 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jonas.gorski@gmail.com>
   3 Date: Thu, 3 May 2012 14:36:11 +0200
   4 Subject: [PATCH 61/72] BCM63XX: add a fixup for ath9k devices
   5
   6 ---
   7  arch/mips/bcm63xx/Makefile                         |    3 +-
   8  arch/mips/bcm63xx/pci-ath9k-fixup.c                |  190 ++++++++++++++++++++
   9  .../include/asm/mach-bcm63xx/pci_ath9k_fixup.h     |    7 +
  10  3 files changed, 199 insertions(+), 1 deletion(-)
  11  create mode 100644 arch/mips/bcm63xx/pci-ath9k-fixup.c
  12  create mode 100644 arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h
  13
  14 --- a/arch/mips/bcm63xx/Makefile
  15 +++ b/arch/mips/bcm63xx/Makefile
  16 @@ -3,7 +3,7 @@ obj-y           += clk.o cpu.o cs.o gpio.o irq.o
  17                    setup.o timer.o dev-enet.o dev-flash.o dev-pcmcia.o \
  18                    dev-rng.o dev-wdt.o \
  19                    dev-usb-ehci.o dev-usb-ohci.o dev-usb-usbd.o usb-common.o \
  20 -                  sprom.o
  21 +                  pci-ath9k-fixup.o sprom.o
  22  obj-$(CONFIG_EARLY_PRINTK)     += early_printk.o
  23
  24  obj-y          += boards/
  25 --- /dev/null
  26 +++ b/arch/mips/bcm63xx/pci-ath9k-fixup.c
  27 @@ -0,0 +1,205 @@
  28 +/*
  29 + *  Broadcom BCM63XX Ath9k EEPROM fixup helper.
  30 + *
  31 + *  Copytight (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
  32 + *
  33 + *  Based on
  34 + *
  35 + *  Atheros AP94 reference board PCI initialization
  36 + *
  37 + *  Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
  38 + *
  39 + *  This program is free software; you can redistribute it and/or modify it
  40 + *  under the terms of the GNU General Public License version 2 as published
  41 + *  by the Free Software Foundation.
  42 + */
  43 +
  44 +#include <linux/if_ether.h>
  45 +#include <linux/pci.h>
  46 +#include <linux/delay.h>
  47 +#include <linux/ath9k_platform.h>
  48 +
  49 +#include <bcm63xx_cpu.h>
  50 +#include <bcm63xx_regs.h>
  51 +#include <bcm63xx_io.h>
  52 +#include <bcm63xx_nvram.h>
  53 +#include <bcm63xx_dev_pci.h>
  54 +#include <bcm63xx_dev_flash.h>
  55 +#include <pci_ath9k_fixup.h>
  56 +
  57 +#define bcm_hsspi_writel(v, o) bcm_rset_writel(RSET_HSSPI, (v), (o))
  58 +
  59 +struct ath9k_fixup {
  60 +       unsigned slot;
  61 +       u8 mac[ETH_ALEN];
  62 +       struct ath9k_platform_data pdata;
  63 +};
  64 +
  65 +static int ath9k_num_fixups;
  66 +static struct ath9k_fixup ath9k_fixups[2] = {
  67 +       {
  68 +               .slot = 255,
  69 +               .pdata = {
  70 +                       .led_pin        = -1,
  71 +               },
  72 +       },
  73 +       {
  74 +               .slot = 255,
  75 +               .pdata = {
  76 +                       .led_pin        = -1,
  77 +               },
  78 +       },
  79 +};
  80 +
  81 +static u16 *bcm63xx_read_eeprom(u16 *eeprom, u32 offset)
  82 +{
  83 +       u32 addr;
  84 +
  85 +       if (BCMCPU_IS_6328()) {
  86 +               addr = 0x18000000;
  87 +       } else {
  88 +               addr = bcm_mpi_readl(MPI_CSBASE_REG(0));
  89 +               addr &= MPI_CSBASE_BASE_MASK;
  90 +       }
  91 +
  92 +       switch (bcm63xx_flash_get_type()) {
  93 +       case BCM63XX_FLASH_TYPE_PARALLEL:
  94 +               memcpy(eeprom, (void *)KSEG1ADDR(addr + offset), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16));
  95 +               return eeprom;
  96 +       case BCM63XX_FLASH_TYPE_SERIAL:
  97 +               /* the first megabyte is memory mapped */
  98 +               if (offset < 0x100000) {
  99 +                       memcpy(eeprom, (void *)KSEG1ADDR(addr + offset), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16));
 100 +                       return eeprom;
 101 +               }
 102 +
 103 +               if (BCMCPU_IS_6328()) {
 104 +                       /* we can change the memory mapped megabyte */
 105 +                       bcm_hsspi_writel(offset & 0xf00000, 0x18);
 106 +                       memcpy(eeprom, (void *)KSEG1ADDR(addr + (offset & 0xfffff)), ATH9K_PLAT_EEP_MAX_WORDS * sizeof(u16));
 107 +                       bcm_hsspi_writel(0, 0x18);
 108 +                       return eeprom;
 109 +               }
 110 +               /* can't do anything here without talking to the SPI controller. */
 111 +               fallthrough;
 112 +       case BCM63XX_FLASH_TYPE_NAND:
 113 +       default:
 114 +               return NULL;
 115 +       }
 116 +}
 117 +
 118 +static void ath9k_pci_fixup(struct pci_dev *dev)
 119 +{
 120 +       void __iomem *mem;
 121 +       struct ath9k_platform_data *pdata = NULL;
 122 +       struct pci_dev *bridge = pci_upstream_bridge(dev);
 123 +       u16 *cal_data = NULL;
 124 +       u16 cmd;
 125 +       u32 bar0;
 126 +       u32 val;
 127 +       unsigned i;
 128 +       int rc;
 129 +
 130 +       for (i = 0; i < ath9k_num_fixups; i++) {
 131 +               if (ath9k_fixups[i].slot != PCI_SLOT(dev->devfn))
 132 +                       continue;
 133 +
 134 +               cal_data = ath9k_fixups[i].pdata.eeprom_data;
 135 +               pdata = &ath9k_fixups[i].pdata;
 136 +               break;
 137 +       }
 138 +
 139 +       if (cal_data == NULL)
 140 +               return;
 141 +
 142 +       if (*cal_data != 0xa55a) {
 143 +               pr_err("pci %s: invalid calibration data\n", pci_name(dev));
 144 +               return;
 145 +       }
 146 +
 147 +       pr_info("pci %s: fixup device configuration\n", pci_name(dev));
 148 +
 149 +       switch (bcm63xx_get_cpu_id()) {
 150 +       case BCM6328_CPU_ID:
 151 +               val = BCM_PCIE_MEM_BASE_PA_6328;
 152 +               break;
 153 +       case BCM6348_CPU_ID:
 154 +       case BCM6358_CPU_ID:
 155 +       case BCM6368_CPU_ID:
 156 +               val = BCM_PCI_MEM_BASE_PA;
 157 +               break;
 158 +       default:
 159 +               BUG();
 160 +       }
 161 +
 162 +       mem = ioremap(val, 0x10000);
 163 +       if (!mem) {
 164 +               pr_err("pci %s: ioremap error\n", pci_name(dev));
 165 +               return;
 166 +       }
 167 +
 168 +       if (bridge) {
 169 +               rc = pci_enable_device(bridge);
 170 +               if (rc < 0)
 171 +                       pr_err("pci %s: bridge enable error\n", pci_name(dev));
 172 +       }
 173 +
 174 +       pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
 175 +       pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
 176 +       pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, val);
 177 +
 178 +       pci_read_config_word(dev, PCI_COMMAND, &cmd);
 179 +       cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 180 +       pci_write_config_word(dev, PCI_COMMAND, cmd);
 181 +
 182 +       /* set offset to first reg address */
 183 +       cal_data += 3;
 184 +       while(*cal_data != 0xffff) {
 185 +               u32 reg;
 186 +               reg = *cal_data++;
 187 +               val = *cal_data++;
 188 +               val |= (*cal_data++) << 16;
 189 +
 190 +               writel(val, mem + reg);
 191 +               udelay(100);
 192 +       }
 193 +
 194 +       pci_read_config_dword(dev, PCI_VENDOR_ID, &val);
 195 +       dev->vendor = val & 0xffff;
 196 +       dev->device = (val >> 16) & 0xffff;
 197 +
 198 +       pci_read_config_dword(dev, PCI_CLASS_REVISION, &val);
 199 +       dev->revision = val & 0xff;
 200 +       dev->class = val >> 8; /* upper 3 bytes */
 201 +
 202 +       pci_read_config_word(dev, PCI_COMMAND, &cmd);
 203 +       cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 204 +       pci_write_config_word(dev, PCI_COMMAND, cmd);
 205 +
 206 +       pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
 207 +
 208 +       if (bridge)
 209 +               pci_disable_device(bridge);
 210 +
 211 +       iounmap(mem);
 212 +
 213 +       dev->dev.platform_data = pdata;
 214 +}
 215 +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup);
 216 +
 217 +void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset)
 218 +{
 219 +       if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups))
 220 +               return;
 221 +
 222 +       ath9k_fixups[ath9k_num_fixups].slot = slot;
 223 +
 224 +       if (!bcm63xx_read_eeprom(ath9k_fixups[ath9k_num_fixups].pdata.eeprom_data, offset))
 225 +               return;
 226 +
 227 +       if (bcm63xx_nvram_get_mac_address(ath9k_fixups[ath9k_num_fixups].mac))
 228 +               return;
 229 +
 230 +       ath9k_fixups[ath9k_num_fixups].pdata.macaddr = ath9k_fixups[ath9k_num_fixups].mac;
 231 +       ath9k_num_fixups++;
 232 +}
 233 --- /dev/null
 234 +++ b/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h
 235 @@ -0,0 +1,7 @@
 236 +#ifndef _PCI_ATH9K_FIXUP
 237 +#define _PCI_ATH9K_FIXUP
 238 +
 239 +
 240 +void pci_enable_ath9k_fixup(unsigned slot, u32 offset) __init;
 241 +
 242 +#endif /* _PCI_ATH9K_FIXUP */