target/linux/bcm27xx/patches-6.1/950-0739-bcm2835-dma-Fixes-for-dma_abort.patch

   1 From 4db71468da38668b1b2b5ad3d8bf120f702b6387 Mon Sep 17 00:00:00 2001
   2 From: Dom Cobley <popcornmix@gmail.com>
   3 Date: Thu, 25 May 2023 17:04:20 +0100
   4 Subject: [PATCH] bcm2835-dma: Fixes for dma_abort
   5
   6 There is a problem with the current abort scheme
   7 when dma is blocked on a DREQ which prevents halting.
   8
   9 This is triggered by SPI driver which aborts dma
  10 in this state and so leads to a halt timeout.
  11
  12 Discussion with Broadcom suggests the sequence:
  13
  14 CS.ACTIVE=0
  15 while (CS.OUTSTANDING_TRANSACTIONS == 0)
  16   wait()
  17 DEBUG.RESET=1
  18
  19 should be safe on a dma40 channel.
  20
  21 Unfortunately the non-dma40 channels don't have
  22 OUTSTANDING_TRANSACTIONS, so we need a more
  23 complicated scheme.
  24
  25 We attempt to abort the channel, which will work
  26 if there is no blocked DREQ.
  27
  28 It it times out, we can assume there is no AXI
  29 transfer in progress and reset anyway.
  30
  31 The length of the timeout is observed at ~20us.
  32
  33 Signed-off-by: Dom Cobley <popcornmix@gmail.com>
  34 ---
  35  drivers/dma/bcm2835-dma.c | 74 +++++++++++++++++++++------------------
  36  1 file changed, 40 insertions(+), 34 deletions(-)
  37
  38 --- a/drivers/dma/bcm2835-dma.c
  39 +++ b/drivers/dma/bcm2835-dma.c
  40 @@ -245,6 +245,7 @@ struct bcm2835_desc {
  41  #define BCM2711_DMA40_ERR              BIT(10)
  42  #define BCM2711_DMA40_QOS(x)           (((x) & 0x1f) << 16)
  43  #define BCM2711_DMA40_PANIC_QOS(x)     (((x) & 0x1f) << 20)
  44 +#define BCM2711_DMA40_TRANSACTIONS     BIT(25)
  45  #define BCM2711_DMA40_WAIT_FOR_WRITES  BIT(28)
  46  #define BCM2711_DMA40_DISDEBUG         BIT(29)
  47  #define BCM2711_DMA40_ABORT            BIT(30)
  48 @@ -663,30 +664,37 @@ static void bcm2835_dma_fill_cb_chain_wi
  49  static void bcm2835_dma_abort(struct bcm2835_chan *c)
  50  {
  51         void __iomem *chan_base = c->chan_base;
  52 -       long int timeout = 10000;
  53 -
  54 -       /*
  55 -        * A zero control block address means the channel is idle.
  56 -        * (The ACTIVE flag in the CS register is not a reliable indicator.)
  57 -        */
  58 -       if (!readl(chan_base + BCM2835_DMA_ADDR))
  59 -               return;
  60 +       long timeout = 100;
  61
  62         if (c->is_40bit_channel) {
  63 -               /* Halt the current DMA */
  64 -               writel(readl(chan_base + BCM2711_DMA40_CS) | BCM2711_DMA40_HALT,
  65 +               /*
  66 +                * A zero control block address means the channel is idle.
  67 +                * (The ACTIVE flag in the CS register is not a reliable indicator.)
  68 +                */
  69 +               if (!readl(chan_base + BCM2711_DMA40_CB))
  70 +                       return;
  71 +
  72 +               /* Pause the current DMA */
  73 +               writel(readl(chan_base + BCM2711_DMA40_CS) & ~BCM2711_DMA40_ACTIVE,
  74                              chan_base + BCM2711_DMA40_CS);
  75
  76 -               while ((readl(chan_base + BCM2711_DMA40_CS) & BCM2711_DMA40_HALT) && --timeout)
  77 +               /* wait for outstanding transactions to complete */
  78 +               while ((readl(chan_base + BCM2711_DMA40_CS) & BCM2711_DMA40_TRANSACTIONS) &&
  79 +                       --timeout)
  80                         cpu_relax();
  81
  82 -               /* Peripheral might be stuck and fail to halt */
  83 +               /* Peripheral might be stuck and fail to complete */
  84                 if (!timeout)
  85                         dev_err(c->vc.chan.device->dev,
  86 -                               "failed to halt dma\n");
  87 +                               "failed to complete pause on dma %d (CS:%08x)\n", c->ch,
  88 +                               readl(chan_base + BCM2711_DMA40_CS));
  89
  90 +               /* Set CS back to default state */
  91                 writel(BCM2711_DMA40_PROT, chan_base + BCM2711_DMA40_CS);
  92 -               writel(0, chan_base + BCM2711_DMA40_CB);
  93 +
  94 +               /* Reset the DMA */
  95 +               writel(readl(chan_base + BCM2711_DMA40_DEBUG) | BCM2711_DMA40_DEBUG_RESET,
  96 +                      chan_base + BCM2711_DMA40_DEBUG);
  97         } else {
  98                 /*
  99                  * A zero control block address means the channel is idle.
 100 @@ -695,36 +703,34 @@ static void bcm2835_dma_abort(struct bcm
 101                 if (!readl(chan_base + BCM2835_DMA_ADDR))
 102                         return;
 103
 104 -               /* Write 0 to the active bit - Pause the DMA */
 105 -               writel(readl(chan_base + BCM2835_DMA_CS) & ~BCM2835_DMA_ACTIVE,
 106 -                      chan_base + BCM2835_DMA_CS);
 107 -
 108 -               /* wait for DMA to be paused */
 109 -               while ((readl(chan_base + BCM2835_DMA_CS) & BCM2835_DMA_WAITING_FOR_WRITES)
 110 -                      && --timeout)
 111 -                       cpu_relax();
 112 -
 113 -               /* Peripheral might be stuck and fail to signal AXI write responses */
 114 -               if (!timeout)
 115 -                       dev_err(c->vc.chan.device->dev,
 116 -                               "failed to pause dma\n");
 117 -
 118                 /* We need to clear the next DMA block pending */
 119                 writel(0, chan_base + BCM2835_DMA_NEXTCB);
 120
 121                 /* Abort the DMA, which needs to be enabled to complete */
 122                 writel(readl(chan_base + BCM2835_DMA_CS) | BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE,
 123 -               chan_base + BCM2835_DMA_CS);
 124 +                     chan_base + BCM2835_DMA_CS);
 125
 126 -               /* wait for DMA to have been aborted */
 127 -               timeout = 10000;
 128 +               /* wait for DMA to be aborted */
 129                 while ((readl(chan_base + BCM2835_DMA_CS) & BCM2835_DMA_ABORT) && --timeout)
 130                         cpu_relax();
 131
 132 -               /* Peripheral might be stuck and fail to signal AXI write responses */
 133 -               if (!timeout)
 134 +               /* Write 0 to the active bit - Pause the DMA */
 135 +               writel(readl(chan_base + BCM2835_DMA_CS) & ~BCM2835_DMA_ACTIVE,
 136 +                      chan_base + BCM2835_DMA_CS);
 137 +
 138 +               /*
 139 +                * Peripheral might be stuck and fail to complete
 140 +                * This is expected when dreqs are enabled but not asserted
 141 +                * so only report error in non dreq case
 142 +                */
 143 +               if (!timeout && !(readl(chan_base + BCM2835_DMA_TI) &
 144 +                  (BCM2835_DMA_S_DREQ | BCM2835_DMA_D_DREQ)))
 145                         dev_err(c->vc.chan.device->dev,
 146 -                               "failed to abort dma\n");
 147 +                               "failed to complete pause on dma %d (CS:%08x)\n", c->ch,
 148 +                               readl(chan_base + BCM2835_DMA_CS));
 149 +
 150 +               /* Set CS back to default state and reset the DMA */
 151 +               writel(BCM2835_DMA_RESET, chan_base + BCM2835_DMA_CS);
 152         }
 153  }
 154