target/linux/bcm27xx/patches-5.10/950-0652-drm-vc4-Fix-pixel-wrap-issue-with-DVP-teardown.patch

   1 From 4ec54ed688271966193b572ba5b150c6a4d270fc Mon Sep 17 00:00:00 2001
   2 From: Tim Gover <tim.gover@raspberrypi.com>
   3 Date: Thu, 24 Jun 2021 17:58:05 +0100
   4 Subject: [PATCH] drm: vc4: Fix pixel-wrap issue with DVP teardown
   5
   6 Adjust the DVP enable/disable sequence to avoid a pixel getting stuck
   7 in an internal, non resettable FIFO within PixelValve when changing
   8 HDMI resolution.
   9
  10 The blank pixels features of the DVP can prevent signals back to
  11 pixelvalve causing it to not clear the FIFO. Adjust the ordering
  12 and timing of operations to ensure the clear signal makes it through to
  13 pixelvalve.
  14
  15 Signed-off-by: Tim Gover <tim.gover@raspberrypi.com>
  16 ---
  17  drivers/gpu/drm/vc4/vc4_hdmi.c | 15 ++++++++-------
  18  1 file changed, 8 insertions(+), 7 deletions(-)
  19
  20 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
  21 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
  22 @@ -610,12 +610,12 @@ static void vc4_hdmi_encoder_post_crtc_d
  23
  24         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
  25
  26 -       HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
  27 -                  VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC);
  28 +       HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
  29
  30 -       HDMI_WRITE(HDMI_VID_CTL,
  31 -                  HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
  32 +       mdelay(1);
  33
  34 +       HDMI_WRITE(HDMI_VID_CTL,
  35 +                  HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
  36         vc4_hdmi_disable_scrambling(encoder);
  37  }
  38
  39 @@ -625,12 +625,12 @@ static void vc4_hdmi_encoder_post_crtc_p
  40         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
  41         int ret;
  42
  43 +       HDMI_WRITE(HDMI_VID_CTL,
  44 +                  HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
  45 +
  46         if (vc4_hdmi->variant->phy_disable)
  47                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
  48
  49 -       HDMI_WRITE(HDMI_VID_CTL,
  50 -                  HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
  51 -
  52         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
  53         if (vc4_hdmi->bvb_req)
  54                 clk_request_done(vc4_hdmi->bvb_req);
  55 @@ -1010,6 +1010,7 @@ static void vc4_hdmi_encoder_post_crtc_e
  56
  57         HDMI_WRITE(HDMI_VID_CTL,
  58                    VC4_HD_VID_CTL_ENABLE |
  59 +                  VC4_HD_VID_CTL_CLRRGB |
  60                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
  61                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
  62                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |