1 From 3ea2bff4ed3ce74dc4303aa20f5e906e78352f6b Mon Sep 17 00:00:00 2001
2 From: John Crispin <john@phrozen.org>
3 Date: Tue, 6 Mar 2018 10:06:10 +0100
4 Subject: [PATCH 09/27] MIPS: ath79: add lots of missing registers
6 Signed-off-by: John Crispin <john@phrozen.org>
8 arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 773 ++++++++++++++++++++++++-
9 1 file changed, 771 insertions(+), 2 deletions(-)
11 diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
12 index aa3800c82332..284b4fa23e03 100644
13 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
14 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
16 #include <linux/bitops.h>
18 #define AR71XX_APB_BASE 0x18000000
19 +#define AR71XX_GE0_BASE 0x19000000
20 +#define AR71XX_GE0_SIZE 0x10000
21 +#define AR71XX_GE1_BASE 0x1a000000
22 +#define AR71XX_GE1_SIZE 0x10000
23 #define AR71XX_EHCI_BASE 0x1b000000
24 #define AR71XX_EHCI_SIZE 0x1000
25 #define AR71XX_OHCI_BASE 0x1c000000
27 #define AR71XX_PLL_SIZE 0x100
28 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
29 #define AR71XX_RESET_SIZE 0x100
30 +#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
31 +#define AR71XX_MII_SIZE 0x100
33 #define AR71XX_PCI_MEM_BASE 0x10000000
34 #define AR71XX_PCI_MEM_SIZE 0x07000000
37 #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
38 #define AR933X_UART_SIZE 0x14
39 +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
40 +#define AR933X_GMAC_SIZE 0x04
41 #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
42 #define AR933X_WMAC_SIZE 0x20000
43 #define AR933X_EHCI_BASE 0x1b000000
44 #define AR933X_EHCI_SIZE 0x1000
46 +#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
47 +#define AR934X_GMAC_SIZE 0x14
48 #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
49 #define AR934X_WMAC_SIZE 0x20000
50 #define AR934X_EHCI_BASE 0x1b000000
51 #define AR934X_EHCI_SIZE 0x200
52 +#define AR934X_NFC_BASE 0x1b000200
53 +#define AR934X_NFC_SIZE 0xb8
54 #define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
55 #define AR934X_SRIF_SIZE 0x1000
57 +#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
58 +#define QCA953X_GMAC_SIZE 0x14
59 +#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
60 +#define QCA953X_WMAC_SIZE 0x20000
61 +#define QCA953X_EHCI_BASE 0x1b000000
62 +#define QCA953X_EHCI_SIZE 0x200
63 +#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
64 +#define QCA953X_SRIF_SIZE 0x1000
66 +#define QCA953X_PCI_CFG_BASE0 0x14000000
67 +#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
68 +#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
69 +#define QCA953X_PCI_MEM_BASE0 0x10000000
70 +#define QCA953X_PCI_MEM_SIZE 0x02000000
72 #define QCA955X_PCI_MEM_BASE0 0x10000000
73 #define QCA955X_PCI_MEM_BASE1 0x12000000
74 #define QCA955X_PCI_MEM_SIZE 0x02000000
76 #define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
77 #define QCA955X_PCI_CTRL_SIZE 0x100
79 +#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
80 +#define QCA955X_GMAC_SIZE 0x40
81 #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
82 #define QCA955X_WMAC_SIZE 0x20000
83 #define QCA955X_EHCI0_BASE 0x1b000000
84 #define QCA955X_EHCI1_BASE 0x1b400000
85 #define QCA955X_EHCI_SIZE 0x1000
86 +#define QCA955X_NFC_BASE 0x1b800200
87 +#define QCA955X_NFC_SIZE 0xb8
89 +#define QCA956X_PCI_MEM_BASE1 0x12000000
90 +#define QCA956X_PCI_MEM_SIZE 0x02000000
91 +#define QCA956X_PCI_CFG_BASE1 0x16000000
92 +#define QCA956X_PCI_CFG_SIZE 0x1000
93 +#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
94 +#define QCA956X_PCI_CRP_SIZE 0x1000
95 +#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
96 +#define QCA956X_PCI_CTRL_SIZE 0x100
98 +#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
99 +#define QCA956X_WMAC_SIZE 0x20000
100 +#define QCA956X_EHCI0_BASE 0x1b000000
101 +#define QCA956X_EHCI1_BASE 0x1b400000
102 +#define QCA956X_EHCI_SIZE 0x200
103 +#define QCA956X_GMAC_SGMII_BASE (AR71XX_APB_BASE + 0x00070000)
104 +#define QCA956X_GMAC_SGMII_SIZE 0x64
105 +#define QCA956X_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
106 +#define QCA956X_PLL_SIZE 0x50
107 +#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
108 +#define QCA956X_GMAC_SIZE 0x64
113 +#define QCA956X_MAC_CFG_BASE 0xb9000000
114 +#define QCA956X_MAC_CFG_SIZE 0x64
116 +#define QCA956X_MAC_CFG1_REG 0x00
117 +#define QCA956X_MAC_CFG1_SOFT_RST BIT(31)
118 +#define QCA956X_MAC_CFG1_RX_RST BIT(19)
119 +#define QCA956X_MAC_CFG1_TX_RST BIT(18)
120 +#define QCA956X_MAC_CFG1_LOOPBACK BIT(8)
121 +#define QCA956X_MAC_CFG1_RX_EN BIT(2)
122 +#define QCA956X_MAC_CFG1_TX_EN BIT(0)
124 +#define QCA956X_MAC_CFG2_REG 0x04
125 +#define QCA956X_MAC_CFG2_IF_1000 BIT(9)
126 +#define QCA956X_MAC_CFG2_IF_10_100 BIT(8)
127 +#define QCA956X_MAC_CFG2_HUGE_FRAME_EN BIT(5)
128 +#define QCA956X_MAC_CFG2_LEN_CHECK BIT(4)
129 +#define QCA956X_MAC_CFG2_PAD_CRC_EN BIT(2)
130 +#define QCA956X_MAC_CFG2_FDX BIT(0)
132 +#define QCA956X_MAC_MII_MGMT_CFG_REG 0x20
133 +#define QCA956X_MGMT_CFG_CLK_DIV_20 0x07
135 +#define QCA956X_MAC_FIFO_CFG0_REG 0x48
136 +#define QCA956X_MAC_FIFO_CFG1_REG 0x4c
137 +#define QCA956X_MAC_FIFO_CFG2_REG 0x50
138 +#define QCA956X_MAC_FIFO_CFG3_REG 0x54
139 +#define QCA956X_MAC_FIFO_CFG4_REG 0x58
140 +#define QCA956X_MAC_FIFO_CFG5_REG 0x5c
142 +#define QCA956X_DAM_RESET_OFFSET 0xb90001bc
143 +#define QCA956X_DAM_RESET_SIZE 0x4
144 +#define QCA956X_INLINE_CHKSUM_ENG BIT(27)
149 #define AR934X_DDR_REG_FLUSH_PCIE 0xa8
150 #define AR934X_DDR_REG_FLUSH_WMAC 0xac
152 +#define QCA953X_DDR_REG_FLUSH_GE0 0x9c
153 +#define QCA953X_DDR_REG_FLUSH_GE1 0xa0
154 +#define QCA953X_DDR_REG_FLUSH_USB 0xa4
155 +#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
156 +#define QCA953X_DDR_REG_FLUSH_WMAC 0xac
162 #define AR71XX_AHB_DIV_SHIFT 20
163 #define AR71XX_AHB_DIV_MASK 0x7
165 +#define AR71XX_ETH0_PLL_SHIFT 17
166 +#define AR71XX_ETH1_PLL_SHIFT 19
168 #define AR724X_PLL_REG_CPU_CONFIG 0x00
169 -#define AR724X_PLL_REG_PCIE_CONFIG 0x18
170 +#define AR724X_PLL_REG_PCIE_CONFIG 0x10
172 +#define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS BIT(16)
173 +#define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET BIT(25)
175 #define AR724X_PLL_FB_SHIFT 0
176 #define AR724X_PLL_FB_MASK 0x3ff
178 #define AR724X_DDR_DIV_SHIFT 22
179 #define AR724X_DDR_DIV_MASK 0x3
181 +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
183 #define AR913X_PLL_REG_CPU_CONFIG 0x00
184 #define AR913X_PLL_REG_ETH_CONFIG 0x04
185 #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
187 #define AR913X_AHB_DIV_SHIFT 19
188 #define AR913X_AHB_DIV_MASK 0x1
190 +#define AR913X_ETH0_PLL_SHIFT 20
191 +#define AR913X_ETH1_PLL_SHIFT 22
193 #define AR933X_PLL_CPU_CONFIG_REG 0x00
194 #define AR933X_PLL_CLOCK_CTRL_REG 0x08
197 #define AR934X_PLL_CPU_CONFIG_REG 0x00
198 #define AR934X_PLL_DDR_CONFIG_REG 0x04
199 #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
200 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
201 +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
203 #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
204 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
206 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
207 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
209 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
211 +#define QCA953X_PLL_CPU_CONFIG_REG 0x00
212 +#define QCA953X_PLL_DDR_CONFIG_REG 0x04
213 +#define QCA953X_PLL_CLK_CTRL_REG 0x08
214 +#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
215 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
216 +#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48
218 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
219 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
220 +#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
221 +#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
222 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
223 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
224 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
225 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
227 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
228 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
229 +#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
230 +#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
231 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
232 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
233 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
234 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
236 +#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
237 +#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
238 +#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
239 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
240 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
241 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
242 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
243 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
244 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
245 +#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
246 +#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
247 +#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
249 #define QCA955X_PLL_CPU_CONFIG_REG 0x00
250 #define QCA955X_PLL_DDR_CONFIG_REG 0x04
251 #define QCA955X_PLL_CLK_CTRL_REG 0x08
252 +#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
253 +#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
254 +#define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c
256 #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
257 #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
259 #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
260 #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
262 +#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2)
263 +#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1)
264 +#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0)
266 +#define QCA956X_PLL_CPU_CONFIG_REG 0x00
267 +#define QCA956X_PLL_CPU_CONFIG1_REG 0x04
268 +#define QCA956X_PLL_DDR_CONFIG_REG 0x08
269 +#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
270 +#define QCA956X_PLL_CLK_CTRL_REG 0x10
271 +#define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG 0x28
272 +#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30
273 +#define QCA956X_PLL_ETH_SGMII_SERDES_REG 0x4c
275 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
276 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
277 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
278 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
280 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
281 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
282 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
283 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff
284 +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
285 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
287 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
288 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
289 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
290 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
292 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
293 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
294 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
295 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff
296 +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
297 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
299 +#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
300 +#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
301 +#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
302 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
303 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
304 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
305 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
306 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
307 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
308 +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20)
309 +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
310 +#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
312 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB BIT(5)
313 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1 BIT(6)
314 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL BIT(7)
315 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SHIFT 8
316 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0xf
317 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EN_PLL_TOP BIT(12)
318 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2 BIT(13)
319 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1 BIT(14)
320 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2 BIT(15)
321 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE BIT(16)
322 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EEE_ENABLE BIT(17)
323 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL BIT(18)
324 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCHCLK_SEL BIT(19)
326 +#define QCA956X_PLL_ETH_XMII_TX_INVERT BIT(1)
327 +#define QCA956X_PLL_ETH_XMII_GIGE BIT(25)
328 +#define QCA956X_PLL_ETH_XMII_RX_DELAY_SHIFT 28
329 +#define QCA956X_PLL_ETH_XMII_RX_DELAY_MASK 0x3
330 +#define QCA956X_PLL_ETH_XMII_TX_DELAY_SHIFT 26
331 +#define QCA956X_PLL_ETH_XMII_TX_DELAY_MASK 3
333 +#define QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2)
334 +#define QCA956X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1)
335 +#define QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0)
340 @@ -317,10 +542,19 @@
341 #define AR934X_RESET_REG_BOOTSTRAP 0xb0
342 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
344 +#define QCA953X_RESET_REG_RESET_MODULE 0x1c
345 +#define QCA953X_RESET_REG_BOOTSTRAP 0xb0
346 +#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
348 #define QCA955X_RESET_REG_RESET_MODULE 0x1c
349 #define QCA955X_RESET_REG_BOOTSTRAP 0xb0
350 #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
352 +#define QCA956X_RESET_REG_RESET_MODULE 0x1c
353 +#define QCA956X_RESET_REG_BOOTSTRAP 0xb0
354 +#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac
356 +#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28)
357 #define MISC_INT_ETHSW BIT(12)
358 #define MISC_INT_TIMER4 BIT(10)
359 #define MISC_INT_TIMER3 BIT(9)
360 @@ -370,16 +604,123 @@
361 #define AR913X_RESET_USB_HOST BIT(5)
362 #define AR913X_RESET_USB_PHY BIT(4)
364 +#define AR933X_RESET_GE1_MDIO BIT(23)
365 +#define AR933X_RESET_GE0_MDIO BIT(22)
366 +#define AR933X_RESET_GE1_MAC BIT(13)
367 #define AR933X_RESET_WMAC BIT(11)
368 +#define AR933X_RESET_GE0_MAC BIT(9)
369 #define AR933X_RESET_USB_HOST BIT(5)
370 #define AR933X_RESET_USB_PHY BIT(4)
371 #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
373 +#define AR934X_RESET_HOST BIT(31)
374 +#define AR934X_RESET_SLIC BIT(30)
375 +#define AR934X_RESET_HDMA BIT(29)
376 +#define AR934X_RESET_EXTERNAL BIT(28)
377 +#define AR934X_RESET_RTC BIT(27)
378 +#define AR934X_RESET_PCIE_EP_INT BIT(26)
379 +#define AR934X_RESET_CHKSUM_ACC BIT(25)
380 +#define AR934X_RESET_FULL_CHIP BIT(24)
381 +#define AR934X_RESET_GE1_MDIO BIT(23)
382 +#define AR934X_RESET_GE0_MDIO BIT(22)
383 +#define AR934X_RESET_CPU_NMI BIT(21)
384 +#define AR934X_RESET_CPU_COLD BIT(20)
385 +#define AR934X_RESET_HOST_RESET_INT BIT(19)
386 +#define AR934X_RESET_PCIE_EP BIT(18)
387 +#define AR934X_RESET_UART1 BIT(17)
388 +#define AR934X_RESET_DDR BIT(16)
389 +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
390 +#define AR934X_RESET_NANDF BIT(14)
391 +#define AR934X_RESET_GE1_MAC BIT(13)
392 +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
393 #define AR934X_RESET_USB_PHY_ANALOG BIT(11)
394 +#define AR934X_RESET_HOST_DMA_INT BIT(10)
395 +#define AR934X_RESET_GE0_MAC BIT(9)
396 +#define AR934X_RESET_ETH_SWITCH BIT(8)
397 +#define AR934X_RESET_PCIE_PHY BIT(7)
398 +#define AR934X_RESET_PCIE BIT(6)
399 #define AR934X_RESET_USB_HOST BIT(5)
400 #define AR934X_RESET_USB_PHY BIT(4)
401 #define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
403 +#define AR934X_RESET_LUT BIT(2)
404 +#define AR934X_RESET_MBOX BIT(1)
405 +#define AR934X_RESET_I2S BIT(0)
407 +#define QCA953X_RESET_USB_EXT_PWR BIT(29)
408 +#define QCA953X_RESET_EXTERNAL BIT(28)
409 +#define QCA953X_RESET_RTC BIT(27)
410 +#define QCA953X_RESET_FULL_CHIP BIT(24)
411 +#define QCA953X_RESET_GE1_MDIO BIT(23)
412 +#define QCA953X_RESET_GE0_MDIO BIT(22)
413 +#define QCA953X_RESET_CPU_NMI BIT(21)
414 +#define QCA953X_RESET_CPU_COLD BIT(20)
415 +#define QCA953X_RESET_DDR BIT(16)
416 +#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
417 +#define QCA953X_RESET_GE1_MAC BIT(13)
418 +#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12)
419 +#define QCA953X_RESET_USB_PHY_ANALOG BIT(11)
420 +#define QCA953X_RESET_GE0_MAC BIT(9)
421 +#define QCA953X_RESET_ETH_SWITCH BIT(8)
422 +#define QCA953X_RESET_PCIE_PHY BIT(7)
423 +#define QCA953X_RESET_PCIE BIT(6)
424 +#define QCA953X_RESET_USB_HOST BIT(5)
425 +#define QCA953X_RESET_USB_PHY BIT(4)
426 +#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
428 +#define QCA955X_RESET_HOST BIT(31)
429 +#define QCA955X_RESET_SLIC BIT(30)
430 +#define QCA955X_RESET_HDMA BIT(29)
431 +#define QCA955X_RESET_EXTERNAL BIT(28)
432 +#define QCA955X_RESET_RTC BIT(27)
433 +#define QCA955X_RESET_PCIE_EP_INT BIT(26)
434 +#define QCA955X_RESET_CHKSUM_ACC BIT(25)
435 +#define QCA955X_RESET_FULL_CHIP BIT(24)
436 +#define QCA955X_RESET_GE1_MDIO BIT(23)
437 +#define QCA955X_RESET_GE0_MDIO BIT(22)
438 +#define QCA955X_RESET_CPU_NMI BIT(21)
439 +#define QCA955X_RESET_CPU_COLD BIT(20)
440 +#define QCA955X_RESET_HOST_RESET_INT BIT(19)
441 +#define QCA955X_RESET_PCIE_EP BIT(18)
442 +#define QCA955X_RESET_UART1 BIT(17)
443 +#define QCA955X_RESET_DDR BIT(16)
444 +#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
445 +#define QCA955X_RESET_NANDF BIT(14)
446 +#define QCA955X_RESET_GE1_MAC BIT(13)
447 +#define QCA955X_RESET_SGMII_ANALOG BIT(12)
448 +#define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
449 +#define QCA955X_RESET_HOST_DMA_INT BIT(10)
450 +#define QCA955X_RESET_GE0_MAC BIT(9)
451 +#define QCA955X_RESET_SGMII BIT(8)
452 +#define QCA955X_RESET_PCIE_PHY BIT(7)
453 +#define QCA955X_RESET_PCIE BIT(6)
454 +#define QCA955X_RESET_USB_HOST BIT(5)
455 +#define QCA955X_RESET_USB_PHY BIT(4)
456 +#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
457 +#define QCA955X_RESET_LUT BIT(2)
458 +#define QCA955X_RESET_MBOX BIT(1)
459 +#define QCA955X_RESET_I2S BIT(0)
461 +#define QCA956X_RESET_EXTERNAL BIT(28)
462 +#define QCA956X_RESET_FULL_CHIP BIT(24)
463 +#define QCA956X_RESET_GE1_MDIO BIT(23)
464 +#define QCA956X_RESET_GE0_MDIO BIT(22)
465 +#define QCA956X_RESET_CPU_NMI BIT(21)
466 +#define QCA956X_RESET_CPU_COLD BIT(20)
467 +#define QCA956X_RESET_DMA BIT(19)
468 +#define QCA956X_RESET_DDR BIT(16)
469 +#define QCA956X_RESET_GE1_MAC BIT(13)
470 +#define QCA956X_RESET_SGMII_ANALOG BIT(12)
471 +#define QCA956X_RESET_USB_PHY_ANALOG BIT(11)
472 +#define QCA956X_RESET_GE0_MAC BIT(9)
473 +#define QCA956X_RESET_SGMII BIT(8)
474 +#define QCA956X_RESET_USB_HOST BIT(5)
475 +#define QCA956X_RESET_USB_PHY BIT(4)
476 +#define QCA956X_RESET_USBSUS_OVERRIDE BIT(3)
477 +#define QCA956X_RESET_SWITCH_ANALOG BIT(2)
478 +#define QCA956X_RESET_SWITCH BIT(0)
480 +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
481 +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
482 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
484 #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
486 #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
487 #define AR934X_BOOTSTRAP_DDR1 BIT(0)
489 +#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
490 +#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
491 +#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
492 +#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
493 +#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
494 +#define QCA953X_BOOTSTRAP_DDR1 BIT(0)
496 #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
498 +#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2)
500 #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
501 #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
502 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
504 AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
505 AR934X_PCIE_WMAC_INT_PCIE_RC3)
507 +#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
508 +#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1)
509 +#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
510 +#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
511 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4)
512 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
513 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
514 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
515 +#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
516 +#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
517 + (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
518 + QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
520 +#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
521 + (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
522 + QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
523 + QCA953X_PCIE_WMAC_INT_PCIE_RC3)
525 #define QCA955X_EXT_INT_WMAC_MISC BIT(0)
526 #define QCA955X_EXT_INT_WMAC_TX BIT(1)
527 #define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
529 QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
530 QCA955X_EXT_INT_PCIE_RC2_INT3)
532 +#define QCA956X_EXT_INT_WMAC_MISC BIT(0)
533 +#define QCA956X_EXT_INT_WMAC_TX BIT(1)
534 +#define QCA956X_EXT_INT_WMAC_RXLP BIT(2)
535 +#define QCA956X_EXT_INT_WMAC_RXHP BIT(3)
536 +#define QCA956X_EXT_INT_PCIE_RC1 BIT(4)
537 +#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5)
538 +#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6)
539 +#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7)
540 +#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8)
541 +#define QCA956X_EXT_INT_PCIE_RC2 BIT(12)
542 +#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13)
543 +#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14)
544 +#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15)
545 +#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16)
546 +#define QCA956X_EXT_INT_USB1 BIT(24)
547 +#define QCA956X_EXT_INT_USB2 BIT(28)
549 +#define QCA956X_EXT_INT_WMAC_ALL \
550 + (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
551 + QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
553 +#define QCA956X_EXT_INT_PCIE_RC1_ALL \
554 + (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
555 + QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
556 + QCA956X_EXT_INT_PCIE_RC1_INT3)
558 +#define QCA956X_EXT_INT_PCIE_RC2_ALL \
559 + (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
560 + QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
561 + QCA956X_EXT_INT_PCIE_RC2_INT3)
563 #define REV_ID_MAJOR_MASK 0xfff0
564 #define REV_ID_MAJOR_AR71XX 0x00a0
565 #define REV_ID_MAJOR_AR913X 0x00b0
567 #define REV_ID_MAJOR_AR9341 0x0120
568 #define REV_ID_MAJOR_AR9342 0x1120
569 #define REV_ID_MAJOR_AR9344 0x2120
570 +#define REV_ID_MAJOR_QCA9533 0x0140
571 +#define REV_ID_MAJOR_QCA9533_V2 0x0160
572 #define REV_ID_MAJOR_QCA9556 0x0130
573 #define REV_ID_MAJOR_QCA9558 0x1130
574 +#define REV_ID_MAJOR_TP9343 0x0150
575 +#define REV_ID_MAJOR_QCA956X 0x1150
577 #define AR71XX_REV_ID_MINOR_MASK 0x3
578 #define AR71XX_REV_ID_MINOR_AR7130 0x0
581 #define AR934X_REV_ID_REVISION_MASK 0xf
583 +#define QCA953X_REV_ID_REVISION_MASK 0xf
585 #define QCA955X_REV_ID_REVISION_MASK 0xf
587 +#define QCA956X_REV_ID_REVISION_MASK 0xf
592 @@ -521,15 +928,63 @@
593 #define AR71XX_GPIO_REG_INT_ENABLE 0x24
594 #define AR71XX_GPIO_REG_FUNC 0x28
596 +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
597 +#define AR934X_GPIO_REG_OUT_FUNC1 0x30
598 +#define AR934X_GPIO_REG_OUT_FUNC2 0x34
599 +#define AR934X_GPIO_REG_OUT_FUNC3 0x38
600 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
601 +#define AR934X_GPIO_REG_OUT_FUNC5 0x40
602 #define AR934X_GPIO_REG_FUNC 0x6c
604 +#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c
605 +#define QCA953X_GPIO_REG_OUT_FUNC1 0x30
606 +#define QCA953X_GPIO_REG_OUT_FUNC2 0x34
607 +#define QCA953X_GPIO_REG_OUT_FUNC3 0x38
608 +#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c
609 +#define QCA953X_GPIO_REG_IN_ENABLE0 0x44
610 +#define QCA953X_GPIO_REG_FUNC 0x6c
612 +#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10
613 +#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11
614 +#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9
615 +#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8
616 +#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12
617 +#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41
618 +#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42
619 +#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43
620 +#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
621 +#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
623 +#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
624 +#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
625 +#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
626 +#define QCA955X_GPIO_REG_OUT_FUNC3 0x38
627 +#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
628 +#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
629 +#define QCA955X_GPIO_REG_FUNC 0x6c
631 +#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
632 +#define QCA956X_GPIO_REG_OUT_FUNC1 0x30
633 +#define QCA956X_GPIO_REG_OUT_FUNC2 0x34
634 +#define QCA956X_GPIO_REG_OUT_FUNC3 0x38
635 +#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c
636 +#define QCA956X_GPIO_REG_OUT_FUNC5 0x40
637 +#define QCA956X_GPIO_REG_IN_ENABLE0 0x44
638 +#define QCA956X_GPIO_REG_IN_ENABLE3 0x50
639 +#define QCA956X_GPIO_REG_FUNC 0x6c
641 +#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32
642 +#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33
644 #define AR71XX_GPIO_COUNT 16
645 #define AR7240_GPIO_COUNT 18
646 #define AR7241_GPIO_COUNT 20
647 #define AR913X_GPIO_COUNT 22
648 #define AR933X_GPIO_COUNT 30
649 #define AR934X_GPIO_COUNT 23
650 +#define QCA953X_GPIO_COUNT 18
651 #define QCA955X_GPIO_COUNT 24
652 +#define QCA956X_GPIO_COUNT 23
656 @@ -552,4 +1007,318 @@
657 #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
658 #define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
660 +#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0
661 +#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4
662 +#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8
664 +#define QCA953X_SRIF_DDR_DPLL1_REG 0x240
665 +#define QCA953X_SRIF_DDR_DPLL2_REG 0x244
666 +#define QCA953X_SRIF_DDR_DPLL3_REG 0x248
668 +#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27
669 +#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
670 +#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18
671 +#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff
672 +#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
674 +#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30)
675 +#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13
676 +#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
678 +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
679 +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
680 +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
681 +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
682 +#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
683 +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
684 +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
686 +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
687 +#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
688 +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
689 +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
690 +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
691 +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
692 +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
693 +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
694 +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
695 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
696 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
697 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
698 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
699 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
700 +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
701 +#define AR724X_GPIO_FUNC_UART_EN BIT(1)
702 +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
704 +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
705 +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
706 +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
707 +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
708 +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
709 +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
710 +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
711 +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
712 +#define AR913X_GPIO_FUNC_UART_EN BIT(8)
713 +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
715 +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
716 +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
717 +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
718 +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
719 +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
720 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
721 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
722 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
723 +#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
724 +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
725 +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
726 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
727 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
728 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
729 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
730 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
731 +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
732 +#define AR933X_GPIO_FUNC_UART_EN BIT(1)
733 +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
735 +#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
736 +#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
737 +#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
738 +#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
739 +#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
740 +#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
741 +#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
742 +#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2)
743 +#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1)
745 +#define AR934X_GPIO_OUT_GPIO 0
746 +#define AR934X_GPIO_OUT_SPI_CS1 7
747 +#define AR934X_GPIO_OUT_LED_LINK0 41
748 +#define AR934X_GPIO_OUT_LED_LINK1 42
749 +#define AR934X_GPIO_OUT_LED_LINK2 43
750 +#define AR934X_GPIO_OUT_LED_LINK3 44
751 +#define AR934X_GPIO_OUT_LED_LINK4 45
752 +#define AR934X_GPIO_OUT_EXT_LNA0 46
753 +#define AR934X_GPIO_OUT_EXT_LNA1 47
755 +#define QCA955X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
756 +#define QCA955X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
757 +#define QCA955X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
758 +#define QCA955X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
759 +#define QCA955X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
760 +#define QCA955X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
761 +#define QCA955X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
762 +#define QCA955X_GPIO_FUNC_JTAG_DISABLE BIT(1)
764 +#define QCA955X_GPIO_OUT_GPIO 0
765 +#define QCA955X_MII_EXT_MDI 1
766 +#define QCA955X_SLIC_DATA_OUT 3
767 +#define QCA955X_SLIC_PCM_FS 4
768 +#define QCA955X_SLIC_PCM_CLK 5
769 +#define QCA955X_SPI_CLK 8
770 +#define QCA955X_SPI_CS_0 9
771 +#define QCA955X_SPI_CS_1 10
772 +#define QCA955X_SPI_CS_2 11
773 +#define QCA955X_SPI_MISO 12
774 +#define QCA955X_I2S_CLK 13
775 +#define QCA955X_I2S_WS 14
776 +#define QCA955X_I2S_SD 15
777 +#define QCA955X_I2S_MCK 16
778 +#define QCA955X_SPDIF_OUT 17
779 +#define QCA955X_UART1_TD 18
780 +#define QCA955X_UART1_RTS 19
781 +#define QCA955X_UART1_RD 20
782 +#define QCA955X_UART1_CTS 21
783 +#define QCA955X_UART0_SOUT 22
784 +#define QCA955X_SPDIF2_OUT 23
785 +#define QCA955X_LED_SGMII_SPEED0 24
786 +#define QCA955X_LED_SGMII_SPEED1 25
787 +#define QCA955X_LED_SGMII_DUPLEX 26
788 +#define QCA955X_LED_SGMII_LINK_UP 27
789 +#define QCA955X_SGMII_SPEED0_INVERT 28
790 +#define QCA955X_SGMII_SPEED1_INVERT 29
791 +#define QCA955X_SGMII_DUPLEX_INVERT 30
792 +#define QCA955X_SGMII_LINK_UP_INVERT 31
793 +#define QCA955X_GE1_MII_MDO 32
794 +#define QCA955X_GE1_MII_MDC 33
795 +#define QCA955X_SWCOM2 38
796 +#define QCA955X_SWCOM3 39
797 +#define QCA955X_MAC2_GPIO 40
798 +#define QCA955X_MAC3_GPIO 41
799 +#define QCA955X_ATT_LED 42
800 +#define QCA955X_PWR_LED 43
801 +#define QCA955X_TX_FRAME 44
802 +#define QCA955X_RX_CLEAR_EXTERNAL 45
803 +#define QCA955X_LED_NETWORK_EN 46
804 +#define QCA955X_LED_POWER_EN 47
805 +#define QCA955X_WMAC_GLUE_WOW 68
806 +#define QCA955X_RX_CLEAR_EXTENSION 70
807 +#define QCA955X_CP_NAND_CS1 73
808 +#define QCA955X_USB_SUSPEND 74
809 +#define QCA955X_ETH_TX_ERR 75
810 +#define QCA955X_DDR_DQ_OE 76
811 +#define QCA955X_CLKREQ_N_EP 77
812 +#define QCA955X_CLKREQ_N_RC 78
813 +#define QCA955X_CLK_OBS0 79
814 +#define QCA955X_CLK_OBS1 80
815 +#define QCA955X_CLK_OBS2 81
816 +#define QCA955X_CLK_OBS3 82
817 +#define QCA955X_CLK_OBS4 83
818 +#define QCA955X_CLK_OBS5 84
823 +#define AR71XX_MII_REG_MII0_CTRL 0x00
824 +#define AR71XX_MII_REG_MII1_CTRL 0x04
826 +#define AR71XX_MII_CTRL_IF_MASK 3
827 +#define AR71XX_MII_CTRL_SPEED_SHIFT 4
828 +#define AR71XX_MII_CTRL_SPEED_MASK 3
829 +#define AR71XX_MII_CTRL_SPEED_10 0
830 +#define AR71XX_MII_CTRL_SPEED_100 1
831 +#define AR71XX_MII_CTRL_SPEED_1000 2
833 +#define AR71XX_MII0_CTRL_IF_GMII 0
834 +#define AR71XX_MII0_CTRL_IF_MII 1
835 +#define AR71XX_MII0_CTRL_IF_RGMII 2
836 +#define AR71XX_MII0_CTRL_IF_RMII 3
838 +#define AR71XX_MII1_CTRL_IF_RGMII 0
839 +#define AR71XX_MII1_CTRL_IF_RMII 1
842 + * AR933X GMAC interface
844 +#define AR933X_GMAC_REG_ETH_CFG 0x00
846 +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
847 +#define AR933X_ETH_CFG_MII_GE0 BIT(1)
848 +#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
849 +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
850 +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
851 +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
852 +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
853 +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
854 +#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
855 +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
856 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
859 + * AR934X GMAC Interface
861 +#define AR934X_GMAC_REG_ETH_CFG 0x00
863 +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
864 +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
865 +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
866 +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
867 +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
868 +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
869 +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
870 +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
871 +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
872 +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
873 +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
874 +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
875 +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
876 +#define AR934X_ETH_CFG_RXD_DELAY BIT(14)
877 +#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3
878 +#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14
879 +#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
880 +#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
881 +#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
884 + * QCA953X GMAC Interface
886 +#define QCA953X_GMAC_REG_ETH_CFG 0x00
888 +#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6)
889 +#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7)
890 +#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9)
891 +#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
894 + * QCA955X GMAC Interface
897 +#define QCA955X_GMAC_REG_ETH_CFG 0x00
898 +#define QCA955X_GMAC_REG_SGMII_SERDES 0x18
900 +#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
901 +#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
902 +#define QCA955X_ETH_CFG_GMII_GE0 BIT(2)
903 +#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3)
904 +#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4)
905 +#define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5)
906 +#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
907 +#define QCA955X_ETH_CFG_RMII_GE0 BIT(10)
908 +#define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11)
909 +#define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12)
910 +#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3
911 +#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14
912 +#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
913 +#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3
914 +#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16
915 +#define QCA955X_ETH_CFG_TXD_DELAY_MASK 0x3
916 +#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT 18
917 +#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
918 +#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
920 +#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
921 +#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
922 +#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
924 + * QCA956X GMAC Interface
927 +#define QCA956X_GMAC_REG_ETH_CFG 0x00
928 +#define QCA956X_GMAC_REG_SGMII_RESET 0x14
929 +#define QCA956X_GMAC_REG_SGMII_SERDES 0x18
930 +#define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c
931 +#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34
932 +#define QCA956X_GMAC_REG_SGMII_DEBUG 0x58
934 +#define QCA956X_ETH_CFG_RGMII_EN BIT(0)
935 +#define QCA956X_ETH_CFG_GE0_SGMII BIT(6)
936 +#define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7)
937 +#define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8)
938 +#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9)
939 +#define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10)
940 +#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
941 +#define QCA956X_ETH_CFG_RXD_DELAY_MASK 0x3
942 +#define QCA956X_ETH_CFG_RXD_DELAY_SHIFT 14
943 +#define QCA956X_ETH_CFG_RDV_DELAY_MASK 0x3
944 +#define QCA956X_ETH_CFG_RDV_DELAY_SHIFT 16
946 +#define QCA956X_SGMII_RESET_RX_CLK_N_RESET 0x0
947 +#define QCA956X_SGMII_RESET_RX_CLK_N BIT(0)
948 +#define QCA956X_SGMII_RESET_TX_CLK_N BIT(1)
949 +#define QCA956X_SGMII_RESET_RX_125M_N BIT(2)
950 +#define QCA956X_SGMII_RESET_TX_125M_N BIT(3)
951 +#define QCA956X_SGMII_RESET_HW_RX_125M_N BIT(4)
953 +#define QCA956X_SGMII_SERDES_CDR_BW_MASK 0x3
954 +#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT 1
955 +#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK 0x7
956 +#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4
957 +#define QCA956X_SGMII_SERDES_PLL_BW BIT(8)
958 +#define QCA956X_SGMII_SERDES_VCO_FAST BIT(9)
959 +#define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10)
960 +#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
961 +#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16)
962 +#define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17)
963 +#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
964 +#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
965 +#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT 27
966 +#define QCA956X_SGMII_SERDES_VCO_REG_MASK 0xf
968 +#define QCA956X_MR_AN_CONTROL_AN_ENABLE BIT(12)
969 +#define QCA956X_MR_AN_CONTROL_PHY_RESET BIT(15)
971 +#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0
972 +#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7
974 #endif /* __ASM_MACH_AR71XX_REGS_H */
projects / openwrt / staging / rmilecki.git / blob