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ath79: ag71xx: Explicitly register mdio bus after ag71xx_hw_init() for ar7240
[openwrt/staging/rmilecki.git] / target / linux / ath79 / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/sizes.h>
15 #include <linux/of_net.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include "ag71xx.h"
19
20 #define AG71XX_DEFAULT_MSG_ENABLE \
21 (NETIF_MSG_DRV \
22 | NETIF_MSG_PROBE \
23 | NETIF_MSG_LINK \
24 | NETIF_MSG_TIMER \
25 | NETIF_MSG_IFDOWN \
26 | NETIF_MSG_IFUP \
27 | NETIF_MSG_RX_ERR \
28 | NETIF_MSG_TX_ERR)
29
30 static int ag71xx_msg_level = -1;
31
32 module_param_named(msg_level, ag71xx_msg_level, int, 0);
33 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
34
35 #define ETH_SWITCH_HEADER_LEN 2
36
37 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
38
39 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
40 {
41 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
42 }
43
44 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
45 {
46 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
47 ag->dev->name,
48 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
49 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
50 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
51
52 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
53 ag->dev->name,
54 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
55 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
56 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
57 }
58
59 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
60 {
61 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
62 ag->dev->name, label, intr,
63 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
64 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
65 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
66 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
67 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
68 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
69 }
70
71 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
72 {
73 struct ag71xx_ring *ring = &ag->tx_ring;
74 struct net_device *dev = ag->dev;
75 int ring_mask = BIT(ring->order) - 1;
76 u32 bytes_compl = 0, pkts_compl = 0;
77
78 while (ring->curr != ring->dirty) {
79 struct ag71xx_desc *desc;
80 u32 i = ring->dirty & ring_mask;
81
82 desc = ag71xx_ring_desc(ring, i);
83 if (!ag71xx_desc_empty(desc)) {
84 desc->ctrl = 0;
85 dev->stats.tx_errors++;
86 }
87
88 if (ring->buf[i].skb) {
89 bytes_compl += ring->buf[i].len;
90 pkts_compl++;
91 dev_kfree_skb_any(ring->buf[i].skb);
92 }
93 ring->buf[i].skb = NULL;
94 ring->dirty++;
95 }
96
97 /* flush descriptors */
98 wmb();
99
100 netdev_completed_queue(dev, pkts_compl, bytes_compl);
101 }
102
103 static void ag71xx_ring_tx_init(struct ag71xx *ag)
104 {
105 struct ag71xx_ring *ring = &ag->tx_ring;
106 int ring_size = BIT(ring->order);
107 int ring_mask = ring_size - 1;
108 int i;
109
110 for (i = 0; i < ring_size; i++) {
111 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
112
113 desc->next = (u32) (ring->descs_dma +
114 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
115
116 desc->ctrl = DESC_EMPTY;
117 ring->buf[i].skb = NULL;
118 }
119
120 /* flush descriptors */
121 wmb();
122
123 ring->curr = 0;
124 ring->dirty = 0;
125 netdev_reset_queue(ag->dev);
126 }
127
128 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
129 {
130 struct ag71xx_ring *ring = &ag->rx_ring;
131 int ring_size = BIT(ring->order);
132 int i;
133
134 if (!ring->buf)
135 return;
136
137 for (i = 0; i < ring_size; i++)
138 if (ring->buf[i].rx_buf) {
139 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
140 ag->rx_buf_size, DMA_FROM_DEVICE);
141 skb_free_frag(ring->buf[i].rx_buf);
142 }
143 }
144
145 static int ag71xx_buffer_size(struct ag71xx *ag)
146 {
147 return ag->rx_buf_size +
148 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
149 }
150
151 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
152 int offset,
153 void *(*alloc)(unsigned int size))
154 {
155 struct ag71xx_ring *ring = &ag->rx_ring;
156 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
157 void *data;
158
159 data = alloc(ag71xx_buffer_size(ag));
160 if (!data)
161 return false;
162
163 buf->rx_buf = data;
164 buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
165 DMA_FROM_DEVICE);
166 desc->data = (u32) buf->dma_addr + offset;
167 return true;
168 }
169
170 static int ag71xx_ring_rx_init(struct ag71xx *ag)
171 {
172 struct ag71xx_ring *ring = &ag->rx_ring;
173 int ring_size = BIT(ring->order);
174 int ring_mask = BIT(ring->order) - 1;
175 unsigned int i;
176 int ret;
177
178 ret = 0;
179 for (i = 0; i < ring_size; i++) {
180 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
181
182 desc->next = (u32) (ring->descs_dma +
183 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
184
185 DBG("ag71xx: RX desc at %p, next is %08x\n",
186 desc, desc->next);
187 }
188
189 for (i = 0; i < ring_size; i++) {
190 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
191
192 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset,
193 netdev_alloc_frag)) {
194 ret = -ENOMEM;
195 break;
196 }
197
198 desc->ctrl = DESC_EMPTY;
199 }
200
201 /* flush descriptors */
202 wmb();
203
204 ring->curr = 0;
205 ring->dirty = 0;
206
207 return ret;
208 }
209
210 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
211 {
212 struct ag71xx_ring *ring = &ag->rx_ring;
213 int ring_mask = BIT(ring->order) - 1;
214 unsigned int count;
215 int offset = ag->rx_buf_offset;
216
217 count = 0;
218 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
219 struct ag71xx_desc *desc;
220 unsigned int i;
221
222 i = ring->dirty & ring_mask;
223 desc = ag71xx_ring_desc(ring, i);
224
225 if (!ring->buf[i].rx_buf &&
226 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
227 napi_alloc_frag))
228 break;
229
230 desc->ctrl = DESC_EMPTY;
231 count++;
232 }
233
234 /* flush descriptors */
235 wmb();
236
237 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
238
239 return count;
240 }
241
242 static int ag71xx_rings_init(struct ag71xx *ag)
243 {
244 struct ag71xx_ring *tx = &ag->tx_ring;
245 struct ag71xx_ring *rx = &ag->rx_ring;
246 int ring_size = BIT(tx->order) + BIT(rx->order);
247 int tx_size = BIT(tx->order);
248
249 tx->buf = kzalloc(ring_size * sizeof(*tx->buf), GFP_KERNEL);
250 if (!tx->buf)
251 return -ENOMEM;
252
253 tx->descs_cpu = dma_alloc_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
254 &tx->descs_dma, GFP_ATOMIC);
255 if (!tx->descs_cpu) {
256 kfree(tx->buf);
257 tx->buf = NULL;
258 return -ENOMEM;
259 }
260
261 rx->buf = &tx->buf[BIT(tx->order)];
262 rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE;
263 rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE;
264
265 ag71xx_ring_tx_init(ag);
266 return ag71xx_ring_rx_init(ag);
267 }
268
269 static void ag71xx_rings_free(struct ag71xx *ag)
270 {
271 struct ag71xx_ring *tx = &ag->tx_ring;
272 struct ag71xx_ring *rx = &ag->rx_ring;
273 int ring_size = BIT(tx->order) + BIT(rx->order);
274
275 if (tx->descs_cpu)
276 dma_free_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
277 tx->descs_cpu, tx->descs_dma);
278
279 kfree(tx->buf);
280
281 tx->descs_cpu = NULL;
282 rx->descs_cpu = NULL;
283 tx->buf = NULL;
284 rx->buf = NULL;
285 }
286
287 static void ag71xx_rings_cleanup(struct ag71xx *ag)
288 {
289 ag71xx_ring_rx_clean(ag);
290 ag71xx_ring_tx_clean(ag);
291 ag71xx_rings_free(ag);
292
293 netdev_reset_queue(ag->dev);
294 }
295
296 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
297 {
298 switch (ag->speed) {
299 case SPEED_1000:
300 return "1000";
301 case SPEED_100:
302 return "100";
303 case SPEED_10:
304 return "10";
305 }
306
307 return "?";
308 }
309
310 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
311 {
312 u32 t;
313
314 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
315 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
316
317 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
318
319 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
320 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
321 }
322
323 static void ag71xx_dma_reset(struct ag71xx *ag)
324 {
325 u32 val;
326 int i;
327
328 ag71xx_dump_dma_regs(ag);
329
330 /* stop RX and TX */
331 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
332 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
333
334 /*
335 * give the hardware some time to really stop all rx/tx activity
336 * clearing the descriptors too early causes random memory corruption
337 */
338 mdelay(1);
339
340 /* clear descriptor addresses */
341 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
342 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
343
344 /* clear pending RX/TX interrupts */
345 for (i = 0; i < 256; i++) {
346 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
347 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
348 }
349
350 /* clear pending errors */
351 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
352 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
353
354 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
355 if (val)
356 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
357 ag->dev->name, val);
358
359 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
360
361 /* mask out reserved bits */
362 val &= ~0xff000000;
363
364 if (val)
365 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
366 ag->dev->name, val);
367
368 ag71xx_dump_dma_regs(ag);
369 }
370
371 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
372 MAC_CFG1_SRX | MAC_CFG1_STX)
373
374 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
375
376 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
377 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
378 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
379 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
380 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
381 FIFO_CFG4_VT)
382
383 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
384 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
385 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
386 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
387 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
388 FIFO_CFG5_17 | FIFO_CFG5_SF)
389
390 static void ag71xx_hw_stop(struct ag71xx *ag)
391 {
392 /* disable all interrupts and stop the rx/tx engine */
393 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
394 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
395 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
396 }
397
398 static void ag71xx_hw_setup(struct ag71xx *ag)
399 {
400 struct device_node *np = ag->pdev->dev.of_node;
401 u32 init = MAC_CFG1_INIT;
402
403 /* setup MAC configuration registers */
404 if (of_property_read_bool(np, "flow-control"))
405 init |= MAC_CFG1_TFC | MAC_CFG1_RFC;
406 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
407
408 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
409 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
410
411 /* setup max frame length to zero */
412 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
413
414 /* setup FIFO configuration registers */
415 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
416 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]);
417 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]);
418 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
419 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
420 }
421
422 static void ag71xx_hw_init(struct ag71xx *ag)
423 {
424 ag71xx_hw_stop(ag);
425
426 if (ag->phy_reset) {
427 reset_control_assert(ag->phy_reset);
428 msleep(50);
429 reset_control_deassert(ag->phy_reset);
430 msleep(200);
431 }
432
433 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
434 udelay(20);
435
436 reset_control_assert(ag->mac_reset);
437 msleep(100);
438 reset_control_deassert(ag->mac_reset);
439 msleep(200);
440
441 ag71xx_hw_setup(ag);
442
443 ag71xx_dma_reset(ag);
444 }
445
446 static void ag71xx_fast_reset(struct ag71xx *ag)
447 {
448 struct net_device *dev = ag->dev;
449 u32 rx_ds;
450 u32 mii_reg;
451
452 ag71xx_hw_stop(ag);
453 wmb();
454
455 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
456 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
457
458 ag71xx_tx_packets(ag, true);
459
460 reset_control_assert(ag->mac_reset);
461 udelay(10);
462 reset_control_deassert(ag->mac_reset);
463 udelay(10);
464
465 ag71xx_dma_reset(ag);
466 ag71xx_hw_setup(ag);
467 ag->tx_ring.curr = 0;
468 ag->tx_ring.dirty = 0;
469 netdev_reset_queue(ag->dev);
470
471 /* setup max frame length */
472 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
473 ag71xx_max_frame_len(ag->dev->mtu));
474
475 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
476 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
477 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
478
479 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
480 }
481
482 static void ag71xx_hw_start(struct ag71xx *ag)
483 {
484 /* start RX engine */
485 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
486
487 /* enable interrupts */
488 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
489
490 netif_wake_queue(ag->dev);
491 }
492
493 static void ath79_set_pllval(struct ag71xx *ag)
494 {
495 u32 pll_reg = ag->pllreg[1];
496 u32 pll_val;
497
498 if (!ag->pllregmap)
499 return;
500
501 switch (ag->speed) {
502 case SPEED_10:
503 pll_val = ag->plldata[2];
504 break;
505 case SPEED_100:
506 pll_val = ag->plldata[1];
507 break;
508 case SPEED_1000:
509 pll_val = ag->plldata[0];
510 break;
511 default:
512 BUG();
513 }
514
515 if (pll_val)
516 regmap_write(ag->pllregmap, pll_reg, pll_val);
517 }
518
519 static void ath79_set_pll(struct ag71xx *ag)
520 {
521 u32 pll_cfg = ag->pllreg[0];
522 u32 pll_shift = ag->pllreg[2];
523
524 if (!ag->pllregmap)
525 return;
526
527 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 2 << pll_shift);
528 udelay(100);
529
530 ath79_set_pllval(ag);
531
532 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 3 << pll_shift);
533 udelay(100);
534
535 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 0);
536 udelay(100);
537 }
538
539 static void ath79_mii_ctrl_set_speed(struct ag71xx *ag)
540 {
541 unsigned int mii_speed;
542 u32 t;
543
544 if (!ag->mii_base)
545 return;
546
547 switch (ag->speed) {
548 case SPEED_10:
549 mii_speed = AR71XX_MII_CTRL_SPEED_10;
550 break;
551 case SPEED_100:
552 mii_speed = AR71XX_MII_CTRL_SPEED_100;
553 break;
554 case SPEED_1000:
555 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
556 break;
557 default:
558 BUG();
559 }
560
561 t = __raw_readl(ag->mii_base);
562 t &= ~(AR71XX_MII_CTRL_IF_MASK);
563 t |= (mii_speed & AR71XX_MII_CTRL_IF_MASK);
564 __raw_writel(t, ag->mii_base);
565 }
566
567 static void
568 __ag71xx_link_adjust(struct ag71xx *ag, bool update)
569 {
570 struct device_node *np = ag->pdev->dev.of_node;
571 u32 cfg2;
572 u32 ifctl;
573 u32 fifo5;
574
575 if (!ag->link && update) {
576 ag71xx_hw_stop(ag);
577 netif_carrier_off(ag->dev);
578 if (netif_msg_link(ag))
579 pr_info("%s: link down\n", ag->dev->name);
580 return;
581 }
582
583 if (!of_device_is_compatible(np, "qca,ar9130-eth") &&
584 !of_device_is_compatible(np, "qca,ar7100-eth"))
585 ag71xx_fast_reset(ag);
586
587 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
588 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
589 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
590
591 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
592 ifctl &= ~(MAC_IFCTL_SPEED);
593
594 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
595 fifo5 &= ~FIFO_CFG5_BM;
596
597 switch (ag->speed) {
598 case SPEED_1000:
599 cfg2 |= MAC_CFG2_IF_1000;
600 fifo5 |= FIFO_CFG5_BM;
601 break;
602 case SPEED_100:
603 cfg2 |= MAC_CFG2_IF_10_100;
604 ifctl |= MAC_IFCTL_SPEED;
605 break;
606 case SPEED_10:
607 cfg2 |= MAC_CFG2_IF_10_100;
608 break;
609 default:
610 BUG();
611 return;
612 }
613
614 if (ag->tx_ring.desc_split) {
615 ag->fifodata[2] &= 0xffff;
616 ag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
617 }
618
619 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]);
620
621 if (update) {
622 if (of_device_is_compatible(np, "qca,ar7100-eth") ||
623 of_device_is_compatible(np, "qca,ar9130-eth")) {
624 ath79_set_pll(ag);
625 ath79_mii_ctrl_set_speed(ag);
626 } else if (of_device_is_compatible(np, "qca,ar7242-eth") ||
627 of_device_is_compatible(np, "qca,ar9340-eth") ||
628 of_device_is_compatible(np, "qca,qca9550-eth") ||
629 of_device_is_compatible(np, "qca,qca9560-eth")) {
630 ath79_set_pllval(ag);
631 }
632 }
633
634 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
635 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
636 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
637
638 if (of_device_is_compatible(np, "qca,qca9530-eth") ||
639 of_device_is_compatible(np, "qca,qca9560-eth")) {
640 /*
641 * The rx ring buffer can stall on small packets on QCA953x and
642 * QCA956x. Disabling the inline checksum engine fixes the stall.
643 * The wr, rr functions cannot be used since this hidden register
644 * is outside of the normal ag71xx register block.
645 */
646 void __iomem *dam = ioremap_nocache(0xb90001bc, 0x4);
647 if (dam) {
648 __raw_writel(__raw_readl(dam) & ~BIT(27), dam);
649 (void)__raw_readl(dam);
650 iounmap(dam);
651 }
652 }
653
654 ag71xx_hw_start(ag);
655
656 netif_carrier_on(ag->dev);
657 if (update && netif_msg_link(ag))
658 pr_info("%s: link up (%sMbps/%s duplex)\n",
659 ag->dev->name,
660 ag71xx_speed_str(ag),
661 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
662
663 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
664 ag->dev->name,
665 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
666 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
667 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
668
669 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
670 ag->dev->name,
671 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
672 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
673 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
674
675 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
676 ag->dev->name,
677 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
678 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
679 }
680
681 void ag71xx_link_adjust(struct ag71xx *ag)
682 {
683 __ag71xx_link_adjust(ag, true);
684 }
685
686 static int ag71xx_hw_enable(struct ag71xx *ag)
687 {
688 int ret;
689
690 ret = ag71xx_rings_init(ag);
691 if (ret)
692 return ret;
693
694 napi_enable(&ag->napi);
695 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
696 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
697 netif_start_queue(ag->dev);
698
699 return 0;
700 }
701
702 static void ag71xx_hw_disable(struct ag71xx *ag)
703 {
704 unsigned long flags;
705
706 spin_lock_irqsave(&ag->lock, flags);
707
708 netif_stop_queue(ag->dev);
709
710 ag71xx_hw_stop(ag);
711 ag71xx_dma_reset(ag);
712
713 napi_disable(&ag->napi);
714 del_timer_sync(&ag->oom_timer);
715
716 spin_unlock_irqrestore(&ag->lock, flags);
717
718 ag71xx_rings_cleanup(ag);
719 }
720
721 static int ag71xx_open(struct net_device *dev)
722 {
723 struct ag71xx *ag = netdev_priv(dev);
724 unsigned int max_frame_len;
725 int ret;
726
727 netif_carrier_off(dev);
728 max_frame_len = ag71xx_max_frame_len(dev->mtu);
729 ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
730
731 /* setup max frame length */
732 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
733 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
734
735 ret = ag71xx_hw_enable(ag);
736 if (ret)
737 goto err;
738
739 phy_start(ag->phy_dev);
740
741 return 0;
742
743 err:
744 ag71xx_rings_cleanup(ag);
745 return ret;
746 }
747
748 static int ag71xx_stop(struct net_device *dev)
749 {
750 struct ag71xx *ag = netdev_priv(dev);
751
752 netif_carrier_off(dev);
753 phy_stop(ag->phy_dev);
754 ag71xx_hw_disable(ag);
755
756 return 0;
757 }
758
759 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
760 {
761 int i;
762 struct ag71xx_desc *desc;
763 int ring_mask = BIT(ring->order) - 1;
764 int ndesc = 0;
765 int split = ring->desc_split;
766
767 if (!split)
768 split = len;
769
770 while (len > 0) {
771 unsigned int cur_len = len;
772
773 i = (ring->curr + ndesc) & ring_mask;
774 desc = ag71xx_ring_desc(ring, i);
775
776 if (!ag71xx_desc_empty(desc))
777 return -1;
778
779 if (cur_len > split) {
780 cur_len = split;
781
782 /*
783 * TX will hang if DMA transfers <= 4 bytes,
784 * make sure next segment is more than 4 bytes long.
785 */
786 if (len <= split + 4)
787 cur_len -= 4;
788 }
789
790 desc->data = addr;
791 addr += cur_len;
792 len -= cur_len;
793
794 if (len > 0)
795 cur_len |= DESC_MORE;
796
797 /* prevent early tx attempt of this descriptor */
798 if (!ndesc)
799 cur_len |= DESC_EMPTY;
800
801 desc->ctrl = cur_len;
802 ndesc++;
803 }
804
805 return ndesc;
806 }
807
808 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
809 struct net_device *dev)
810 {
811 struct ag71xx *ag = netdev_priv(dev);
812 struct ag71xx_ring *ring = &ag->tx_ring;
813 int ring_mask = BIT(ring->order) - 1;
814 int ring_size = BIT(ring->order);
815 struct ag71xx_desc *desc;
816 dma_addr_t dma_addr;
817 int i, n, ring_min;
818
819 if (skb->len <= 4) {
820 DBG("%s: packet len is too small\n", ag->dev->name);
821 goto err_drop;
822 }
823
824 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
825 DMA_TO_DEVICE);
826
827 i = ring->curr & ring_mask;
828 desc = ag71xx_ring_desc(ring, i);
829
830 /* setup descriptor fields */
831 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
832 if (n < 0)
833 goto err_drop_unmap;
834
835 i = (ring->curr + n - 1) & ring_mask;
836 ring->buf[i].len = skb->len;
837 ring->buf[i].skb = skb;
838
839 netdev_sent_queue(dev, skb->len);
840
841 skb_tx_timestamp(skb);
842
843 desc->ctrl &= ~DESC_EMPTY;
844 ring->curr += n;
845
846 /* flush descriptor */
847 wmb();
848
849 ring_min = 2;
850 if (ring->desc_split)
851 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
852
853 if (ring->curr - ring->dirty >= ring_size - ring_min) {
854 DBG("%s: tx queue full\n", dev->name);
855 netif_stop_queue(dev);
856 }
857
858 DBG("%s: packet injected into TX queue\n", ag->dev->name);
859
860 /* enable TX engine */
861 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
862
863 return NETDEV_TX_OK;
864
865 err_drop_unmap:
866 dma_unmap_single(&dev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
867
868 err_drop:
869 dev->stats.tx_dropped++;
870
871 dev_kfree_skb(skb);
872 return NETDEV_TX_OK;
873 }
874
875 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
876 {
877 struct ag71xx *ag = netdev_priv(dev);
878 int ret;
879
880 switch (cmd) {
881 case SIOCETHTOOL:
882 if (ag->phy_dev == NULL)
883 break;
884
885 spin_lock_irq(&ag->lock);
886 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
887 spin_unlock_irq(&ag->lock);
888 return ret;
889
890 case SIOCSIFHWADDR:
891 if (copy_from_user
892 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
893 return -EFAULT;
894 return 0;
895
896 case SIOCGIFHWADDR:
897 if (copy_to_user
898 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
899 return -EFAULT;
900 return 0;
901
902 case SIOCGMIIPHY:
903 case SIOCGMIIREG:
904 case SIOCSMIIREG:
905 if (ag->phy_dev == NULL)
906 break;
907
908 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
909
910 default:
911 break;
912 }
913
914 return -EOPNOTSUPP;
915 }
916
917 static void ag71xx_oom_timer_handler(unsigned long data)
918 {
919 struct net_device *dev = (struct net_device *) data;
920 struct ag71xx *ag = netdev_priv(dev);
921
922 napi_schedule(&ag->napi);
923 }
924
925 static void ag71xx_tx_timeout(struct net_device *dev)
926 {
927 struct ag71xx *ag = netdev_priv(dev);
928
929 if (netif_msg_tx_err(ag))
930 pr_info("%s: tx timeout\n", ag->dev->name);
931
932 schedule_delayed_work(&ag->restart_work, 1);
933 }
934
935 static void ag71xx_restart_work_func(struct work_struct *work)
936 {
937 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);
938
939 rtnl_lock();
940 ag71xx_hw_disable(ag);
941 ag71xx_hw_enable(ag);
942 if (ag->link)
943 __ag71xx_link_adjust(ag, false);
944 rtnl_unlock();
945 }
946
947 static bool ag71xx_check_dma_stuck(struct ag71xx *ag)
948 {
949 unsigned long timestamp;
950 u32 rx_sm, tx_sm, rx_fd;
951
952 timestamp = netdev_get_tx_queue(ag->dev, 0)->trans_start;
953 if (likely(time_before(jiffies, timestamp + HZ/10)))
954 return false;
955
956 if (!netif_carrier_ok(ag->dev))
957 return false;
958
959 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
960 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
961 return true;
962
963 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
964 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
965 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
966 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
967 return true;
968
969 return false;
970 }
971
972 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
973 {
974 struct ag71xx_ring *ring = &ag->tx_ring;
975 bool dma_stuck = false;
976 int ring_mask = BIT(ring->order) - 1;
977 int ring_size = BIT(ring->order);
978 int sent = 0;
979 int bytes_compl = 0;
980 int n = 0;
981
982 DBG("%s: processing TX ring\n", ag->dev->name);
983
984 while (ring->dirty + n != ring->curr) {
985 unsigned int i = (ring->dirty + n) & ring_mask;
986 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
987 struct sk_buff *skb = ring->buf[i].skb;
988
989 if (!flush && !ag71xx_desc_empty(desc)) {
990 if (ag->tx_hang_workaround &&
991 ag71xx_check_dma_stuck(ag)) {
992 schedule_delayed_work(&ag->restart_work, HZ / 2);
993 dma_stuck = true;
994 }
995 break;
996 }
997
998 if (flush)
999 desc->ctrl |= DESC_EMPTY;
1000
1001 n++;
1002 if (!skb)
1003 continue;
1004
1005 dev_kfree_skb_any(skb);
1006 ring->buf[i].skb = NULL;
1007
1008 bytes_compl += ring->buf[i].len;
1009
1010 sent++;
1011 ring->dirty += n;
1012
1013 while (n > 0) {
1014 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
1015 n--;
1016 }
1017 }
1018
1019 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
1020
1021 if (!sent)
1022 return 0;
1023
1024 ag->dev->stats.tx_bytes += bytes_compl;
1025 ag->dev->stats.tx_packets += sent;
1026
1027 netdev_completed_queue(ag->dev, sent, bytes_compl);
1028 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
1029 netif_wake_queue(ag->dev);
1030
1031 if (!dma_stuck)
1032 cancel_delayed_work(&ag->restart_work);
1033
1034 return sent;
1035 }
1036
1037 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
1038 {
1039 struct net_device *dev = ag->dev;
1040 struct ag71xx_ring *ring = &ag->rx_ring;
1041 unsigned int pktlen_mask = ag->desc_pktlen_mask;
1042 unsigned int offset = ag->rx_buf_offset;
1043 int ring_mask = BIT(ring->order) - 1;
1044 int ring_size = BIT(ring->order);
1045 struct sk_buff_head queue;
1046 struct sk_buff *skb;
1047 int done = 0;
1048
1049 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1050 dev->name, limit, ring->curr, ring->dirty);
1051
1052 skb_queue_head_init(&queue);
1053
1054 while (done < limit) {
1055 unsigned int i = ring->curr & ring_mask;
1056 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1057 int pktlen;
1058 int err = 0;
1059
1060 if (ag71xx_desc_empty(desc))
1061 break;
1062
1063 if ((ring->dirty + ring_size) == ring->curr) {
1064 ag71xx_assert(0);
1065 break;
1066 }
1067
1068 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1069
1070 pktlen = desc->ctrl & pktlen_mask;
1071 pktlen -= ETH_FCS_LEN;
1072
1073 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
1074 ag->rx_buf_size, DMA_FROM_DEVICE);
1075
1076 dev->stats.rx_packets++;
1077 dev->stats.rx_bytes += pktlen;
1078
1079 skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));
1080 if (!skb) {
1081 skb_free_frag(ring->buf[i].rx_buf);
1082 goto next;
1083 }
1084
1085 skb_reserve(skb, offset);
1086 skb_put(skb, pktlen);
1087
1088 if (err) {
1089 dev->stats.rx_dropped++;
1090 kfree_skb(skb);
1091 } else {
1092 skb->dev = dev;
1093 skb->ip_summed = CHECKSUM_NONE;
1094 __skb_queue_tail(&queue, skb);
1095 }
1096
1097 next:
1098 ring->buf[i].rx_buf = NULL;
1099 done++;
1100
1101 ring->curr++;
1102 }
1103
1104 ag71xx_ring_rx_refill(ag);
1105
1106 while ((skb = __skb_dequeue(&queue)) != NULL) {
1107 skb->protocol = eth_type_trans(skb, dev);
1108 netif_receive_skb(skb);
1109 }
1110
1111 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1112 dev->name, ring->curr, ring->dirty, done);
1113
1114 return done;
1115 }
1116
1117 static int ag71xx_poll(struct napi_struct *napi, int limit)
1118 {
1119 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1120 struct net_device *dev = ag->dev;
1121 struct ag71xx_ring *rx_ring = &ag->rx_ring;
1122 int rx_ring_size = BIT(rx_ring->order);
1123 unsigned long flags;
1124 u32 status;
1125 int tx_done;
1126 int rx_done;
1127
1128 tx_done = ag71xx_tx_packets(ag, false);
1129
1130 DBG("%s: processing RX ring\n", dev->name);
1131 rx_done = ag71xx_rx_packets(ag, limit);
1132
1133 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1134
1135 if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)
1136 goto oom;
1137
1138 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1139 if (unlikely(status & RX_STATUS_OF)) {
1140 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1141 dev->stats.rx_fifo_errors++;
1142
1143 /* restart RX */
1144 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1145 }
1146
1147 if (rx_done < limit) {
1148 if (status & RX_STATUS_PR)
1149 goto more;
1150
1151 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1152 if (status & TX_STATUS_PS)
1153 goto more;
1154
1155 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1156 dev->name, rx_done, tx_done, limit);
1157
1158 napi_complete(napi);
1159
1160 /* enable interrupts */
1161 spin_lock_irqsave(&ag->lock, flags);
1162 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1163 spin_unlock_irqrestore(&ag->lock, flags);
1164 return rx_done;
1165 }
1166
1167 more:
1168 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1169 dev->name, rx_done, tx_done, limit);
1170 return limit;
1171
1172 oom:
1173 if (netif_msg_rx_err(ag))
1174 pr_info("%s: out of memory\n", dev->name);
1175
1176 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1177 napi_complete(napi);
1178 return 0;
1179 }
1180
1181 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1182 {
1183 struct net_device *dev = dev_id;
1184 struct ag71xx *ag = netdev_priv(dev);
1185 u32 status;
1186
1187 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1188 ag71xx_dump_intr(ag, "raw", status);
1189
1190 if (unlikely(!status))
1191 return IRQ_NONE;
1192
1193 if (unlikely(status & AG71XX_INT_ERR)) {
1194 if (status & AG71XX_INT_TX_BE) {
1195 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1196 dev_err(&dev->dev, "TX BUS error\n");
1197 }
1198 if (status & AG71XX_INT_RX_BE) {
1199 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1200 dev_err(&dev->dev, "RX BUS error\n");
1201 }
1202 }
1203
1204 if (likely(status & AG71XX_INT_POLL)) {
1205 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1206 DBG("%s: enable polling mode\n", dev->name);
1207 napi_schedule(&ag->napi);
1208 }
1209
1210 ag71xx_debugfs_update_int_stats(ag, status);
1211
1212 return IRQ_HANDLED;
1213 }
1214
1215 #ifdef CONFIG_NET_POLL_CONTROLLER
1216 /*
1217 * Polling 'interrupt' - used by things like netconsole to send skbs
1218 * without having to re-enable interrupts. It's not called while
1219 * the interrupt routine is executing.
1220 */
1221 static void ag71xx_netpoll(struct net_device *dev)
1222 {
1223 disable_irq(dev->irq);
1224 ag71xx_interrupt(dev->irq, dev);
1225 enable_irq(dev->irq);
1226 }
1227 #endif
1228
1229 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1230 {
1231 struct ag71xx *ag = netdev_priv(dev);
1232
1233 dev->mtu = new_mtu;
1234 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
1235 ag71xx_max_frame_len(dev->mtu));
1236
1237 return 0;
1238 }
1239
1240 static const struct net_device_ops ag71xx_netdev_ops = {
1241 .ndo_open = ag71xx_open,
1242 .ndo_stop = ag71xx_stop,
1243 .ndo_start_xmit = ag71xx_hard_start_xmit,
1244 .ndo_do_ioctl = ag71xx_do_ioctl,
1245 .ndo_tx_timeout = ag71xx_tx_timeout,
1246 .ndo_change_mtu = ag71xx_change_mtu,
1247 .ndo_set_mac_address = eth_mac_addr,
1248 .ndo_validate_addr = eth_validate_addr,
1249 #ifdef CONFIG_NET_POLL_CONTROLLER
1250 .ndo_poll_controller = ag71xx_netpoll,
1251 #endif
1252 };
1253
1254 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
1255 {
1256 switch (mode) {
1257 case PHY_INTERFACE_MODE_MII:
1258 return "MII";
1259 case PHY_INTERFACE_MODE_GMII:
1260 return "GMII";
1261 case PHY_INTERFACE_MODE_RMII:
1262 return "RMII";
1263 case PHY_INTERFACE_MODE_RGMII:
1264 return "RGMII";
1265 case PHY_INTERFACE_MODE_SGMII:
1266 return "SGMII";
1267 default:
1268 break;
1269 }
1270
1271 return "unknown";
1272 }
1273
1274 static int ag71xx_probe(struct platform_device *pdev)
1275 {
1276 struct device_node *np = pdev->dev.of_node;
1277 struct device_node *mdio_node;
1278 struct net_device *dev;
1279 struct resource *res;
1280 struct ag71xx *ag;
1281 const void *mac_addr;
1282 u32 max_frame_len;
1283 int tx_size, err;
1284
1285 if (!np)
1286 return -ENODEV;
1287
1288 dev = alloc_etherdev(sizeof(*ag));
1289 if (!dev)
1290 return -ENOMEM;
1291
1292 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1293 if (!res)
1294 return -EINVAL;
1295
1296 err = ag71xx_setup_gmac(np);
1297 if (err)
1298 return err;
1299
1300 SET_NETDEV_DEV(dev, &pdev->dev);
1301
1302 ag = netdev_priv(dev);
1303 ag->pdev = pdev;
1304 ag->dev = dev;
1305 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1306 AG71XX_DEFAULT_MSG_ENABLE);
1307 spin_lock_init(&ag->lock);
1308
1309 ag->mac_reset = devm_reset_control_get(&pdev->dev, "mac");
1310 if (IS_ERR(ag->mac_reset)) {
1311 dev_err(&pdev->dev, "missing mac reset\n");
1312 err = PTR_ERR(ag->mac_reset);
1313 goto err_free;
1314 }
1315
1316 ag->phy_reset = devm_reset_control_get_optional(&pdev->dev, "phy");
1317
1318 if (of_property_read_u32_array(np, "fifo-data", ag->fifodata, 3)) {
1319 if (of_device_is_compatible(np, "qca,ar9130-eth") ||
1320 of_device_is_compatible(np, "qca,ar7100-eth")) {
1321 ag->fifodata[0] = 0x0fff0000;
1322 ag->fifodata[1] = 0x00001fff;
1323 } else {
1324 ag->fifodata[0] = 0x0010ffff;
1325 ag->fifodata[1] = 0x015500aa;
1326 ag->fifodata[2] = 0x01f00140;
1327 }
1328 if (of_device_is_compatible(np, "qca,ar9130-eth"))
1329 ag->fifodata[2] = 0x00780fff;
1330 else if (of_device_is_compatible(np, "qca,ar7100-eth"))
1331 ag->fifodata[2] = 0x008001ff;
1332 }
1333
1334 if (of_property_read_u32_array(np, "pll-data", ag->plldata, 3))
1335 dev_dbg(&pdev->dev, "failed to read pll-data property\n");
1336
1337 if (of_property_read_u32_array(np, "pll-reg", ag->pllreg, 3))
1338 dev_dbg(&pdev->dev, "failed to read pll-reg property\n");
1339
1340 ag->pllregmap = syscon_regmap_lookup_by_phandle(np, "pll-handle");
1341 if (IS_ERR(ag->pllregmap)) {
1342 dev_dbg(&pdev->dev, "failed to read pll-handle property\n");
1343 ag->pllregmap = NULL;
1344 }
1345
1346 ag->mac_base = devm_ioremap_nocache(&pdev->dev, res->start,
1347 res->end - res->start + 1);
1348 if (!ag->mac_base) {
1349 err = -ENOMEM;
1350 goto err_free;
1351 }
1352 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1353 if (res) {
1354 ag->mii_base = devm_ioremap_nocache(&pdev->dev, res->start,
1355 res->end - res->start + 1);
1356 if (!ag->mii_base) {
1357 err = -ENOMEM;
1358 goto err_free;
1359 }
1360 }
1361
1362 dev->irq = platform_get_irq(pdev, 0);
1363 err = devm_request_irq(&pdev->dev, dev->irq, ag71xx_interrupt,
1364 0x0, dev_name(&pdev->dev), dev);
1365 if (err) {
1366 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1367 goto err_free;
1368 }
1369
1370 dev->netdev_ops = &ag71xx_netdev_ops;
1371 dev->ethtool_ops = &ag71xx_ethtool_ops;
1372
1373 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func);
1374
1375 init_timer(&ag->oom_timer);
1376 ag->oom_timer.data = (unsigned long) dev;
1377 ag->oom_timer.function = ag71xx_oom_timer_handler;
1378
1379 tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
1380 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
1381
1382 if (of_device_is_compatible(np, "qca,ar9340-eth") ||
1383 of_device_is_compatible(np, "qca,qca9530-eth") ||
1384 of_device_is_compatible(np, "qca,qca9550-eth") ||
1385 of_device_is_compatible(np, "qca,qca9560-eth"))
1386 ag->desc_pktlen_mask = SZ_16K - 1;
1387 else
1388 ag->desc_pktlen_mask = SZ_4K - 1;
1389
1390 if (ag->desc_pktlen_mask == SZ_16K - 1 &&
1391 !of_device_is_compatible(np, "qca,qca9550-eth") &&
1392 !of_device_is_compatible(np, "qca,qca9560-eth"))
1393 max_frame_len = ag->desc_pktlen_mask;
1394 else
1395 max_frame_len = 1540;
1396
1397 dev->min_mtu = 68;
1398 dev->max_mtu = max_frame_len - ag71xx_max_frame_len(0);
1399
1400 if (of_device_is_compatible(np, "qca,ar7240-eth"))
1401 ag->tx_hang_workaround = 1;
1402
1403 ag->rx_buf_offset = NET_SKB_PAD;
1404 if (!of_device_is_compatible(np, "qca,ar7100-eth") &&
1405 !of_device_is_compatible(np, "qca,ar9130-eth"))
1406 ag->rx_buf_offset += NET_IP_ALIGN;
1407
1408 if (of_device_is_compatible(np, "qca,ar7100-eth")) {
1409 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1410 tx_size *= AG71XX_TX_RING_DS_PER_PKT;
1411 }
1412 ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
1413
1414 ag->stop_desc = dmam_alloc_coherent(&pdev->dev,
1415 sizeof(struct ag71xx_desc),
1416 &ag->stop_desc_dma, GFP_KERNEL);
1417 if (!ag->stop_desc)
1418 goto err_free;
1419
1420 ag->stop_desc->data = 0;
1421 ag->stop_desc->ctrl = 0;
1422 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1423
1424 mac_addr = of_get_mac_address(np);
1425 if (mac_addr)
1426 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
1427 if (!mac_addr || !is_valid_ether_addr(dev->dev_addr)) {
1428 dev_err(&pdev->dev, "invalid MAC address, using random address\n");
1429 eth_random_addr(dev->dev_addr);
1430 }
1431
1432 ag->phy_if_mode = of_get_phy_mode(np);
1433 if (ag->phy_if_mode < 0) {
1434 dev_err(&pdev->dev, "missing phy-mode property in DT\n");
1435 err = ag->phy_if_mode;
1436 goto err_free;
1437 }
1438
1439 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1440
1441 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);
1442 ag71xx_hw_init(ag);
1443
1444 if(!of_device_is_compatible(np, "simple-mfd")) {
1445 mdio_node = of_get_child_by_name(np, "mdio-bus");
1446 if(!IS_ERR(mdio_node))
1447 of_platform_device_create(mdio_node, NULL, NULL);
1448 }
1449
1450 err = ag71xx_phy_connect(ag);
1451 if (err)
1452 goto err_free;
1453
1454 err = ag71xx_debugfs_init(ag);
1455 if (err)
1456 goto err_phy_disconnect;
1457
1458 platform_set_drvdata(pdev, dev);
1459
1460 err = register_netdev(dev);
1461 if (err) {
1462 dev_err(&pdev->dev, "unable to register net device\n");
1463 platform_set_drvdata(pdev, NULL);
1464 ag71xx_debugfs_exit(ag);
1465 goto err_phy_disconnect;
1466 }
1467
1468 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1469 dev->name, (unsigned long) ag->mac_base, dev->irq,
1470 ag71xx_get_phy_if_mode_name(ag->phy_if_mode));
1471
1472 return 0;
1473
1474 err_phy_disconnect:
1475 ag71xx_phy_disconnect(ag);
1476 err_free:
1477 free_netdev(dev);
1478 return err;
1479 }
1480
1481 static int ag71xx_remove(struct platform_device *pdev)
1482 {
1483 struct net_device *dev = platform_get_drvdata(pdev);
1484 struct ag71xx *ag;
1485
1486 if (!dev)
1487 return 0;
1488
1489 ag = netdev_priv(dev);
1490 ag71xx_debugfs_exit(ag);
1491 ag71xx_phy_disconnect(ag);
1492 unregister_netdev(dev);
1493 free_irq(dev->irq, dev);
1494 iounmap(ag->mac_base);
1495 kfree(dev);
1496 platform_set_drvdata(pdev, NULL);
1497
1498 return 0;
1499 }
1500
1501 static const struct of_device_id ag71xx_match[] = {
1502 { .compatible = "qca,ar7100-eth" },
1503 { .compatible = "qca,ar7240-eth" },
1504 { .compatible = "qca,ar7241-eth" },
1505 { .compatible = "qca,ar7242-eth" },
1506 { .compatible = "qca,ar9130-eth" },
1507 { .compatible = "qca,ar9330-eth" },
1508 { .compatible = "qca,ar9340-eth" },
1509 { .compatible = "qca,qca9530-eth" },
1510 { .compatible = "qca,qca9550-eth" },
1511 { .compatible = "qca,qca9560-eth" },
1512 {}
1513 };
1514
1515 static struct platform_driver ag71xx_driver = {
1516 .probe = ag71xx_probe,
1517 .remove = ag71xx_remove,
1518 .driver = {
1519 .name = AG71XX_DRV_NAME,
1520 .of_match_table = ag71xx_match,
1521 }
1522 };
1523
1524 static int __init ag71xx_module_init(void)
1525 {
1526 int ret;
1527
1528 ret = ag71xx_debugfs_root_init();
1529 if (ret)
1530 goto err_out;
1531
1532 ret = platform_driver_register(&ag71xx_driver);
1533 if (ret)
1534 goto err_debugfs_exit;
1535
1536 return 0;
1537
1538 err_debugfs_exit:
1539 ag71xx_debugfs_root_exit();
1540 err_out:
1541 return ret;
1542 }
1543
1544 static void __exit ag71xx_module_exit(void)
1545 {
1546 platform_driver_unregister(&ag71xx_driver);
1547 ag71xx_debugfs_root_exit();
1548 }
1549
1550 module_init(ag71xx_module_init);
1551 module_exit(ag71xx_module_exit);
1552
1553 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1554 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1555 MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
1556 MODULE_LICENSE("GPL v2");
1557 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
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