ath79: define switch reset-gpios for D-Link DIR-842
[openwrt/staging/dedeckeh.git] / target / linux / ath79 / dts / qca9563_dlink_dir-842-c.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5
6 #include "qca956x.dtsi"
7
8 / {
9 chosen {
10 bootargs = "console=ttyS0,115200n8";
11 };
12
13 keys {
14 compatible = "gpio-keys";
15
16 wps {
17 linux,code = <KEY_WPS_BUTTON>;
18 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
19 debounce-interval = <60>;
20 };
21
22 reset {
23 linux,code = <KEY_RESTART>;
24 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
25 debounce-interval = <60>;
26 };
27 };
28 };
29
30 &uart {
31 status = "okay";
32 };
33
34 &pcie {
35 status = "okay";
36 };
37
38 &spi {
39 status = "okay";
40 num-cs = <1>;
41
42 flash@0 {
43 compatible = "jedec,spi-nor";
44 reg = <0>;
45 spi-max-frequency = <30000000>;
46
47 partitions {
48 compatible = "fixed-partitions";
49 #address-cells = <1>;
50 #size-cells = <1>;
51
52 partition@0 {
53 label = "u-boot";
54 reg = <0x000000 0x40000>;
55 read-only;
56 };
57
58 partition@40000 {
59 label = "u-boot-env";
60 reg = <0x040000 0x10000>;
61 read-only;
62 };
63
64 partition@50000 {
65 label = "devdata";
66 reg = <0x050000 0x10000>;
67 read-only;
68 };
69
70 partition@60000 {
71 label = "devconf";
72 reg = <0x060000 0x10000>;
73 read-only;
74 };
75
76 partition@70000 {
77 label = "misc";
78 reg = <0x070000 0x10000>;
79 read-only;
80 };
81
82 partition@80000 {
83 compatible = "seama";
84 label = "firmware";
85 reg = <0x080000 0xf50000>;
86 };
87
88 art: partition@fd0000 {
89 label = "art";
90 reg = <0xfd0000 0x010000>;
91 read-only;
92 };
93
94 partition@fe0000 {
95 label = "reserved";
96 reg = <0xfe0000 0x20000>;
97 read-only;
98 };
99 };
100 };
101 };
102
103 &mdio0 {
104 status = "okay";
105
106 phy-mask = <0>;
107
108 phy0: ethernet-phy@0 {
109 reg = <0>;
110 qca,mib-poll-interval = <500>;
111 reset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
112
113 qca,ar8327-initvals = <
114 0x04 0x00080080 /* PORT0 PAD MODE CTRL */
115 0x10 0x81000080 /* POWER_ON_STRIP */
116 0x50 0xcc35cc35 /* LED_CTRL0 */
117 0x54 0xcb37cb37 /* LED_CTRL1 */
118 0x58 0x00000000 /* LED_CTRL2 */
119 0x5c 0x00f3cf00 /* LED_CTRL3 */
120 0x7c 0x0000007e /* PORT0_STATUS */
121 >;
122 };
123 };
124
125 &eth0 {
126 status = "okay";
127
128 pll-data = <0x03000101 0x00000101 0x00001919>;
129
130 phy-mode = "sgmii";
131 phy-handle = <&phy0>;
132 };
133
134 &wmac {
135 status = "okay";
136
137 qca,no-eeprom;
138 };