ath79: enable UART in SoC DTSI files
[openwrt/staging/jow.git] / target / linux / ath79 / dts / qca9558_dlink_dap-2695-a1.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "qca955x.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "dlink,dap-2695-a1", "qca,qca9558";
10 model = "D-link DAP-2695-A1";
11
12 aliases {
13 led-boot = &led_power_red;
14 led-failsafe = &led_power_red;
15 led-running = &led_power_green;
16 led-upgrade = &led_power_red;
17 };
18
19 leds {
20 compatible = "gpio-leds";
21
22 led_power_green: power_green {
23 label = "green:power";
24 gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
25 default-state = "on";
26 };
27
28 led_power_red: power_red {
29 label = "red:power";
30 gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
31 };
32
33 wifi2g {
34 label = "green:wifi2g";
35 gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
36 linux,default-trigger = "phy1tpt";
37 };
38 };
39
40 keys {
41 compatible = "gpio-keys";
42
43 reset {
44 label = "reset";
45 linux,code = <KEY_RESTART>;
46 gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
47 };
48 };
49 };
50
51 &spi {
52 status = "okay";
53
54 flash@0 {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 compatible = "mx25l12805d";
58 reg = <0>;
59 spi-max-frequency = <25000000>;
60
61 partitions {
62 compatible = "fixed-partitions";
63 #address-cells = <1>;
64 #size-cells = <1>;
65
66 partition@0 {
67 label = "u-boot";
68 reg = <0x000000 0x040000>;
69 read-only;
70 };
71
72 partition@40000 {
73 label = "bdcfg";
74 reg = <0x040000 0x010000>;
75 read-only;
76 };
77
78 partition@50000 {
79 label = "rgdb";
80 reg = <0x050000 0x010000>;
81 read-only;
82 };
83
84 partition@60000 {
85 label = "langpack";
86 reg = <0x060000 0x010000>;
87 read-only;
88 };
89
90 partition@70000 {
91 compatible = "wrg";
92 label = "firmware";
93 reg = <0x070000 0xf00000>;
94 };
95
96 partition@f70000 {
97 label = "captival";
98 reg = <0xf70000 0x070000>;
99 read-only;
100 };
101
102 partition@fe0000 {
103 label = "certificate";
104 reg = <0xfe0000 0x010000>;
105 read-only;
106 };
107
108 art: partition@ff0000 {
109 label = "art";
110 reg = <0xff0000 0x010000>;
111 read-only;
112 };
113 };
114 };
115 };
116
117 &mdio0 {
118 status = "okay";
119
120 phy0: ethernet-phy@0 {
121 reg = <0>;
122
123 qca,ar8327-initvals = <
124 0x04 0x07600000 /* PORT0_PAD_CTRL */
125 0x0c 0x00080080 /* PORT6_PAD_CTRL */
126 0x7c 0x0000007e /* PORT0_STATUS */
127 0x94 0x0000007e /* PORT6_STATUS */
128 >;
129 };
130 };
131
132 &eth0 {
133 status = "okay";
134
135 phy-handle = <&phy0>;
136 pll-data = <0x56000000 0x00000101 0x00001616>;
137
138 fixed-link {
139 speed = <1000>;
140 full-duplex;
141 };
142 };
143
144 &eth1 {
145 status = "okay";
146
147 phy-mask = <0>;
148 pll-data = <0x03000101 0x00000101 0x00001616>;
149
150 fixed-link {
151 speed = <1000>;
152 full-duplex;
153 };
154 };
155
156 &pcie0 {
157 status = "okay";
158 };
159
160 &wmac {
161 status = "okay";
162
163 qca,no-eeprom;
164 };