ath79: enable UART in SoC DTSI files
[openwrt/staging/jow.git] / target / linux / ath79 / dts / qca953x.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "ath79.dtsi"
4
5 / {
6 compatible = "qca,qca9530";
7
8 #address-cells = <1>;
9 #size-cells = <1>;
10
11 chosen {
12 bootargs = "console=ttyS0,115200n8";
13 };
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "mips,mips24Kc";
22 clocks = <&pll ATH79_CLK_CPU>;
23 reg = <0>;
24 };
25 };
26
27 extosc: ref {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-output-names = "ref";
31 clock-frequency = <25000000>;
32 };
33
34 ahb {
35 apb {
36 ddr_ctrl: memory-controller@18000000 {
37 compatible = "qca,qca9530-ddr-controller",
38 "qca,ar7240-ddr-controller";
39 reg = <0x18000000 0x128>;
40
41 #qca,ddr-wb-channel-cells = <1>;
42 };
43
44 uart: uart@18020000 {
45 compatible = "ns16550a";
46 reg = <0x18020000 0x20>;
47
48 interrupts = <3>;
49
50 clocks = <&pll ATH79_CLK_REF>;
51 clock-names = "uart";
52
53 reg-io-width = <4>;
54 reg-shift = <2>;
55 no-loopback-test;
56 };
57
58 usb_phy: usb-phy@18030000 {
59 compatible = "qca,ar7200-usb-phy";
60 reg = <0x18030000 0x100>;
61 #phy-cells = <0>;
62
63 reset-names = "usb-phy", "usb-suspend-override";
64 resets = <&rst 4>, <&rst 3>;
65
66 status = "disabled";
67 };
68
69 gpio: gpio@18040000 {
70 compatible = "qca,qca9530-gpio",
71 "qca,ar9340-gpio";
72 reg = <0x18040000 0x28>;
73
74 interrupts = <2>;
75 ngpios = <20>;
76
77 gpio-controller;
78 #gpio-cells = <2>;
79
80 interrupt-controller;
81 #interrupt-cells = <2>;
82 };
83
84 pinmux: pinmux@1804002c {
85 compatible = "pinctrl-single";
86
87 reg = <0x1804002c 0x48>;
88
89 #size-cells = <0>;
90
91 pinctrl-single,bit-per-mux;
92 pinctrl-single,register-width = <32>;
93 pinctrl-single,function-mask = <0x1>;
94 #pinctrl-cells = <2>;
95
96 jtag_disable_pins: pinmux_jtag_disable_pins {
97 pinctrl-single,bits = <0x40 0x2 0x2>;
98 };
99 };
100
101 pll: pll-controller@18050000 {
102 compatible = "qca,qca9530-pll", "syscon";
103 reg = <0x18050000 0x48>;
104
105 #clock-cells = <1>;
106 clock-output-names = "cpu", "ddr", "ahb";
107 clocks = <&extosc>;
108 };
109
110 wdt: wdt@18060008 {
111 compatible = "qca,qca9530-wdt", "qca,ar7130-wdt";
112 reg = <0x18060008 0x8>;
113
114 interrupts = <4>;
115
116 clocks = <&pll ATH79_CLK_AHB>;
117 clock-names = "wdt";
118 };
119
120 rst: reset-controller@1806001c {
121 compatible = "qca,qca9530-reset",
122 "qca,ar7100-reset";
123 reg = <0x1806001c 0xac>;
124
125 #reset-cells = <1>;
126
127 intc2: interrupt-controller {
128 compatible = "qca,ar9340-intc";
129
130 interrupt-parent = <&cpuintc>;
131 interrupts = <2>;
132
133 interrupt-controller;
134 #interrupt-cells = <1>;
135
136 qca,int-status-addr = <0xac>;
137 qca,pending-bits = <0xf>, /* wmac */
138 <0x1f0>; /* pcie rc1 */
139
140 qca,ddr-wb-channel-interrupts = <0>, <1>;
141 qca,ddr-wb-channels = <&ddr_ctrl 4>, <&ddr_ctrl 3>;
142 };
143 };
144 };
145
146 gmac: gmac@18070000 {
147 compatible = "qca,ar9330-gmac";
148 reg = <0x18070000 0x4>;
149 };
150
151 pcie0: pcie-controller@180c0000 {
152 compatible = "qcom,ar7240-pci";
153 #address-cells = <3>;
154 #size-cells = <2>;
155 bus-range = <0x0 0x0>;
156 reg = <0x180c0000 0x1000>, /* CRP */
157 <0x180f0000 0x100>, /* CTRL */
158 <0x14000000 0x1000>; /* CFG */
159 reg-names = "crp_base", "ctrl_base", "cfg_base";
160 ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000 /* pci memory */
161 0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
162 interrupt-parent = <&intc2>;
163 interrupts = <1>;
164
165 device_type = "pci";
166
167 resets = <&rst 6>, <&rst 7>;
168 reset-names = "hc", "phy";
169
170 interrupt-controller;
171 #interrupt-cells = <1>;
172
173 interrupt-map-mask = <0 0 0 1>;
174 interrupt-map = <0 0 0 0 &pcie0 0>;
175 status = "disabled";
176 };
177
178 wmac: wmac@18100000 {
179 compatible = "qca,qca9530-wmac";
180 reg = <0x18100000 0x20000>;
181
182 interrupt-parent = <&intc2>;
183 interrupts = <0>;
184
185 status = "disabled";
186 };
187
188 usb0: usb@1b000000 {
189 compatible = "generic-ehci";
190 reg = <0x1b000000 0x1000>;
191
192 interrupts = <3>;
193 resets = <&rst 5>;
194 reset-names = "usb-host";
195 dr_mode = "host";
196
197 has-transaction-translator;
198 caps-offset = <0x100>;
199
200 phy-names = "usb-phy";
201 phys = <&usb_phy>;
202
203 status = "disabled";
204 };
205
206 spi: spi@1f000000 {
207 compatible = "qca,ar934x-spi";
208 reg = <0x1f000000 0x1c>;
209
210 clocks = <&pll ATH79_CLK_AHB>;
211
212 status = "disabled";
213
214 #address-cells = <1>;
215 #size-cells = <0>;
216 };
217 };
218 };
219
220 &cpuintc {
221 qca,ddr-wb-channel-interrupts = <3>, <4>, <5>;
222 qca,ddr-wb-channels = <&ddr_ctrl 2>, <&ddr_ctrl 0>,
223 <&ddr_ctrl 1>;
224 };
225
226 &eth0 {
227 compatible = "qca,qca9530-eth", "syscon";
228 pll-data = <0x82000101 0x80000101 0x80001313>;
229 reg = <0x19000000 0x200
230 0x18070000 0x4>;
231 pll-reg = <0x4 0x2c 17>;
232 pll-handle = <&pll>;
233
234 reset-names = "mac";
235 resets = <&rst 9>;
236 };
237
238 &mdio1 {
239 status = "okay";
240 resets = <&rst 23>;
241 reset-names = "mdio";
242 builtin-switch;
243
244 builtin_switch: switch0@1f {
245 compatible = "qca,ar8229";
246
247 reg = <0x1f>;
248 resets = <&rst 8>;
249 reset-names = "switch";
250 phy-mode = "gmii";
251 qca,phy4-mii-enable;
252 qca,mib-poll-interval = <500>;
253
254 mdio-bus {
255 #address-cells = <1>;
256 #size-cells = <0>;
257
258 swphy0: ethernet-phy@0 {
259 reg = <0>;
260 phy-mode = "mii";
261 };
262
263 swphy4: ethernet-phy@4 {
264 reg = <4>;
265 phy-mode = "mii";
266 };
267 };
268 };
269 };
270
271 &eth1 {
272 status = "okay";
273
274 compatible = "qca,qca9530-eth", "syscon";
275 resets = <&rst 13>;
276 reset-names = "mac";
277
278 phy-mode = "gmii";
279
280 fixed-link {
281 speed = <1000>;
282 full-duplex;
283 };
284 };