target/linux/ath79/dts/ar934x.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "ath79.dtsi"
   4
   5 / {
   6         compatible = "qca,ar9340";
   7
   8         #address-cells = <1>;
   9         #size-cells = <1>;
  10
  11         aliases {
  12                 serial0 = &uart;
  13         };
  14
  15         chosen {
  16                 bootargs = "console=ttyS0,115200";
  17         };
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 cpu@0 {
  24                         device_type = "cpu";
  25                         compatible = "mips,mips74Kc";
  26                         clocks = <&pll ATH79_CLK_CPU>;
  27                         reg = <0>;
  28                 };
  29         };
  30
  31         clocks {
  32                 #address-cells = <1>;
  33                 #size-cells = <1>;
  34                 ranges;
  35
  36                 ref: ref {
  37                         #clock-cells = <0>;
  38                         compatible = "fixed-clock";
  39                         clock-output-names = "ref";
  40                 };
  41         };
  42
  43         ahb: ahb {
  44                 compatible = "simple-bus";
  45                 ranges;
  46
  47                 #address-cells = <1>;
  48                 #size-cells = <1>;
  49
  50                 apb: apb {
  51                         compatible = "simple-bus";
  52                         ranges;
  53
  54                         #address-cells = <1>;
  55                         #size-cells = <1>;
  56
  57                         ddr_ctrl: memory-controller@18000000 {
  58                                 compatible = "qca,ar9340-ddr-controller",
  59                                                 "qca,ar7240-ddr-controller";
  60                                 reg = <0x18000000 0x12c>;
  61
  62                                 #qca,ddr-wb-channel-cells = <1>;
  63                         };
  64
  65                         uart: uart@18020000 {
  66                                 compatible = "ns16550a";
  67                                 reg = <0x18020000 0x2c>;
  68
  69                                 interrupts = <3>;
  70
  71                                 clocks = <&pll ATH79_CLK_REF>;
  72                                 clock-names = "uart";
  73
  74                                 reg-io-width = <4>;
  75                                 reg-shift = <2>;
  76                                 no-loopback-test;
  77                         };
  78
  79                         gpio: gpio@18040000 {
  80                                 compatible = "qca,ar9340-gpio";
  81                                 reg = <0x18040000 0x2c>;
  82
  83                                 interrupts = <2>;
  84                                 ngpios = <23>;
  85
  86                                 gpio-controller;
  87                                 #gpio-cells = <2>;
  88
  89                                 interrupt-controller;
  90                                 #interrupt-cells = <2>;
  91                         };
  92
  93                         pinmux: pinmux@1804002c {
  94                                 compatible = "pinctrl-single";
  95
  96                                 reg = <0x1804002c 0x44>;
  97
  98                                 #size-cells = <0>;
  99
 100                                 pinctrl-single,bit-per-mux;
 101                                 pinctrl-single,register-width = <32>;
 102                                 pinctrl-single,function-mask = <0x1>;
 103                                 #pinctrl-cells = <2>;
 104
 105                                 jtag_disable_pins: pinmux_jtag_disable_pins {
 106                                         pinctrl-single,bits = <0x40 0x2 0x2>;
 107                                 };
 108                         };
 109
 110                         pll: pll-controller@18050000 {
 111                                 compatible = "qca,ar9340-pll", "syscon";
 112                                 reg = <0x18050000 0x4c>;
 113
 114                                 #clock-cells = <1>;
 115                                 clocks = <&ref>;
 116                                 clock-names = "ref";
 117                                 clock-output-names = "cpu", "ddr", "ahb";
 118                         };
 119
 120                         wdt: wdt@18060008 {
 121                                 compatible = "qca,ar9340-wdt", "qca,ar7130-wdt";
 122                                 reg = <0x18060008 0x8>;
 123
 124                                 interrupts = <4>;
 125
 126                                 clocks = <&pll ATH79_CLK_AHB>;
 127                                 clock-names = "wdt";
 128                         };
 129
 130                         rst: reset-controller@1806001c {
 131                                 compatible = "qca,ar9340-reset", "qca,ar7100-reset";
 132                                 reg = <0x1806001c 0x4>;
 133
 134                                 #reset-cells = <1>;
 135                         };
 136
 137                         hs_uart: uart@18500000 {
 138                                 compatible = "qca,ar9330-uart";
 139                                 reg = <0x18500000 0x14>;
 140
 141                                 interrupts = <6>;
 142                                 interrupt-parent = <&miscintc>;
 143
 144                                 clocks = <&pll ATH79_CLK_UART1>;
 145                                 clock-names = "uart";
 146
 147                                 status = "disabled";
 148                         };
 149                 };
 150
 151                 gmac: gmac@18070000 {
 152                         compatible = "qca,ar9340-gmac";
 153                         reg = <0x18070000 0x14>;
 154                 };
 155
 156                 wmac: wmac@18100000 {
 157                         compatible = "qca,ar9340-wmac";
 158                         reg = <0x18100000 0x20000>;
 159
 160                         status = "disabled";
 161                 };
 162
 163                 usb: usb@1b000000 {
 164                         compatible = "generic-ehci";
 165                         reg = <0x1b000000 0x1d8>;
 166
 167                         interrupts = <3>;
 168                         resets = <&rst 5>;
 169                         reset-names = "usb-host";
 170
 171                         has-transaction-translator;
 172                         caps-offset = <0x100>;
 173
 174                         phy-names = "usb-phy";
 175                         phys = <&usb_phy>;
 176
 177                         status = "disabled";
 178                 };
 179
 180                 nand: nand@1b000200 {
 181                         compatible = "qca,ar934x-nand";
 182                         reg = <0x1b000200 0xb8>;
 183
 184                         interrupts = <21>;
 185                         interrupt-parent = <&miscintc>;
 186
 187                         resets = <&rst 14>;
 188                         reset-names = "nand";
 189
 190                         nand-ecc-mode = "hw";
 191
 192                         #address-cells = <1>;
 193                         #size-cells = <0>;
 194
 195                         status = "disabled";
 196                 };
 197
 198                 spi: spi@1f000000 {
 199                         compatible = "qca,ar934x-spi";
 200                         reg = <0x1f000000 0x1c>;
 201
 202                         clocks = <&pll ATH79_CLK_AHB>;
 203
 204                         #address-cells = <1>;
 205                         #size-cells = <0>;
 206
 207                         status = "disabled";
 208                 };
 209         };
 210
 211         usb_phy: usb-phy {
 212                 compatible = "qca,ar9340-usb-phy", "qca,ar7200-usb-phy";
 213
 214                 reset-names = "usb-phy-analog", "usb-phy", "usb-suspend-override";
 215                 resets = <&rst 11>, <&rst 4>, <&rst 3>;
 216
 217                 #phy-cells = <0>;
 218
 219                 status = "disabled";
 220         };
 221 };
 222
 223 &mdio0 {
 224         compatible = "qca,ar9340-mdio";
 225 };
 226
 227 &eth0 {
 228         compatible = "qca,ar9340-eth", "syscon";
 229
 230         pll-data = <0x16000000 0x00000101 0x00001616>;
 231         pll-reg = <0x4 0x2c 17>;
 232         pll-handle = <&pll>;
 233         resets = <&rst 9>, <&rst 22>;
 234         reset-names = "mac", "mdio";
 235         clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
 236         clock-names = "eth", "mdio";
 237 };
 238
 239 &mdio1 {
 240         status = "okay";
 241
 242         compatible = "qca,ar9340-mdio";
 243         resets = <&rst 23>;
 244         reset-names = "mdio";
 245         builtin-switch;
 246
 247         builtin_switch: switch0@1f {
 248                 compatible = "qca,ar8229";
 249
 250                 reg = <0x1f>;
 251                 resets = <&rst 8>;
 252                 reset-names = "switch";
 253                 phy-mode = "gmii";
 254                 qca,mib-poll-interval = <500>;
 255                 qca,phy4-mii-enable;
 256
 257                 mdio-bus {
 258                         #address-cells = <1>;
 259                         #size-cells = <0>;
 260
 261                         swphy0: ethernet-phy@0 {
 262                                 reg = <0>;
 263                                 phy-mode = "mii";
 264                         };
 265
 266                         swphy4: ethernet-phy@4 {
 267                                 reg = <4>;
 268                                 phy-mode = "mii";
 269                         };
 270                 };
 271         };
 272 };
 273
 274 &eth1 {
 275         compatible = "qca,ar9340-eth", "syscon";
 276
 277         resets = <&rst 13>;
 278         reset-names = "mac";
 279         clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
 280         clock-names = "eth", "mdio";
 281         phy-mode = "gmii";
 282
 283         fixed-link {
 284                 speed = <1000>;
 285                 full-duplex;
 286         };
 287 };