ath79: enable UART in SoC DTSI files
[openwrt/staging/jow.git] / target / linux / ath79 / dts / ar9344_engenius_exx600.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "ar9344.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/mtd/partitions/uimage.h>
8
9 / {
10 aliases {
11 label-mac-device = &eth0;
12 led-boot = &led_power;
13 led-failsafe = &led_power;
14 led-running = &led_power;
15 led-upgrade = &led_power;
16 };
17
18 keys {
19 compatible = "gpio-keys";
20
21 reset {
22 label = "reset";
23 gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
24 debounce-interval = <60>;
25 linux,code = <KEY_RESTART>;
26 };
27 };
28
29 ath9k-leds {
30 compatible = "gpio-leds";
31
32 wifi2g {
33 label = "blue:wifi2g";
34 gpios = <&ath9k 0 GPIO_ACTIVE_LOW>;
35 linux,default-trigger = "phy1tpt";
36 };
37 };
38
39 virtual_flash {
40 compatible = "mtd-concat";
41
42 devices = <&fwconcat0 &fwconcat1>;
43
44 partitions {
45 compatible = "fixed-partitions";
46 #address-cells = <1>;
47 #size-cells = <1>;
48
49 partition@0 {
50 compatible = "openwrt,uimage", "denx,uimage";
51 openwrt,ih-magic = <IH_MAGIC_OKLI>;
52 label = "firmware";
53 reg = <0x0 0x0>;
54 };
55 };
56 };
57 };
58
59 &ref {
60 clock-frequency = <40000000>;
61 };
62
63 &spi {
64 status = "okay";
65
66 flash@0 {
67 compatible = "jedec,spi-nor";
68 reg = <0>;
69 spi-max-frequency = <40000000>;
70
71 partitions {
72 compatible = "fixed-partitions";
73 #address-cells = <1>;
74 #size-cells = <1>;
75
76 partition@0 {
77 label = "u-boot";
78 reg = <0x000000 0x040000>;
79 read-only;
80 };
81
82 partition@40000 {
83 label = "u-boot-env";
84 reg = <0x040000 0x010000>;
85 };
86
87 partition@50000 {
88 label = "custom";
89 reg = <0x050000 0x050000>;
90 read-only;
91 };
92
93 partition@a0000 {
94 label = "loader";
95 reg = <0x0a0000 0x010000>;
96 read-only;
97 };
98
99 fwconcat1: partition@b0000 {
100 label = "fwconcat1";
101 reg = <0x0b0000 0x170000>;
102 };
103
104 partition@220000 {
105 label = "fakeroot";
106 reg = <0x220000 0x010000>;
107 read-only;
108 };
109
110 fwconcat0: partition@230000 {
111 label = "fwconcat0";
112 reg = <0x230000 0xbc0000>;
113 };
114
115 partition@df0000 {
116 label = "failsafe";
117 reg = <0xdf0000 0x200000>;
118 read-only;
119 };
120
121 art: partition@ff0000 {
122 label = "art";
123 reg = <0xff0000 0x010000>;
124 read-only;
125 };
126 };
127 };
128 };
129
130 &mdio0 {
131 status = "okay";
132
133 phy0: ethernet-phy@0 {
134 reg = <0>;
135 eee-broken-100tx;
136 eee-broken-1000t;
137 };
138 };
139
140 &eth0 {
141 status = "okay";
142
143 phy-handle = <&phy0>;
144 phy-mode = "rgmii-id";
145
146 pll-data = <0x02000000 0x00000101 0x00001313>;
147
148 gmac-config {
149 device = <&gmac>;
150 rgmii-gmac0 = <1>;
151 rxdv-delay = <3>;
152 rxd-delay = <3>;
153 };
154 };
155
156 &pcie {
157 status = "okay";
158
159 ath9k: wifi@0,0,0 {
160 compatible = "pci168c,0030";
161 reg = <0x0 0 0 0 0>;
162 qca,disable-5ghz;
163 qca,no-eeprom;
164 #gpio-cells = <2>;
165 gpio-controller;
166 };
167 };
168
169 &wmac {
170 status = "okay";
171
172 qca,disable-2ghz;
173
174 mtd-cal-data = <&art 0x1000>;
175 };