projects / openwrt / staging / blogic.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ar71xx: allow to use large ethernet frames on AR934x SoCs
[openwrt/staging/blogic.git] / target / linux / ar71xx / files / arch / mips / ath79 / dev-eth.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23 #include <linux/sizes.h>
24
25 #include <asm/mach-ath79/ath79.h>
26 #include <asm/mach-ath79/ar71xx_regs.h>
27 #include <asm/mach-ath79/irq.h>
28
29 #include "common.h"
30 #include "dev-eth.h"
31
32 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
33
34 static struct resource ath79_mdio0_resources[] = {
35 {
36 .name = "mdio_base",
37 .flags = IORESOURCE_MEM,
38 .start = AR71XX_GE0_BASE,
39 .end = AR71XX_GE0_BASE + 0x200 - 1,
40 }
41 };
42
43 struct ag71xx_mdio_platform_data ath79_mdio0_data;
44
45 struct platform_device ath79_mdio0_device = {
46 .name = "ag71xx-mdio",
47 .id = 0,
48 .resource = ath79_mdio0_resources,
49 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
50 .dev = {
51 .platform_data = &ath79_mdio0_data,
52 },
53 };
54
55 static struct resource ath79_mdio1_resources[] = {
56 {
57 .name = "mdio_base",
58 .flags = IORESOURCE_MEM,
59 .start = AR71XX_GE1_BASE,
60 .end = AR71XX_GE1_BASE + 0x200 - 1,
61 }
62 };
63
64 struct ag71xx_mdio_platform_data ath79_mdio1_data;
65
66 struct platform_device ath79_mdio1_device = {
67 .name = "ag71xx-mdio",
68 .id = 1,
69 .resource = ath79_mdio1_resources,
70 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
71 .dev = {
72 .platform_data = &ath79_mdio1_data,
73 },
74 };
75
76 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
77 {
78 void __iomem *base;
79 u32 t;
80
81 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
82
83 t = __raw_readl(base + cfg_reg);
84 t &= ~(3 << shift);
85 t |= (2 << shift);
86 __raw_writel(t, base + cfg_reg);
87 udelay(100);
88
89 __raw_writel(pll_val, base + pll_reg);
90
91 t |= (3 << shift);
92 __raw_writel(t, base + cfg_reg);
93 udelay(100);
94
95 t &= ~(3 << shift);
96 __raw_writel(t, base + cfg_reg);
97 udelay(100);
98
99 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
100 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
101
102 iounmap(base);
103 }
104
105 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
106 unsigned int mii_if)
107 {
108 void __iomem *base;
109 u32 t;
110
111 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
112
113 t = __raw_readl(base + reg);
114 t &= ~(AR71XX_MII_CTRL_IF_MASK);
115 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
116 __raw_writel(t, base + reg);
117
118 iounmap(base);
119 }
120
121 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
122 {
123 void __iomem *base;
124 unsigned int mii_speed;
125 u32 t;
126
127 switch (speed) {
128 case SPEED_10:
129 mii_speed = AR71XX_MII_CTRL_SPEED_10;
130 break;
131 case SPEED_100:
132 mii_speed = AR71XX_MII_CTRL_SPEED_100;
133 break;
134 case SPEED_1000:
135 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
136 break;
137 default:
138 BUG();
139 }
140
141 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
142
143 t = __raw_readl(base + reg);
144 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
145 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
146 __raw_writel(t, base + reg);
147
148 iounmap(base);
149 }
150
151 static unsigned long ar934x_get_mdio_ref_clock(void)
152 {
153 void __iomem *base;
154 unsigned long ret;
155 u32 t;
156
157 base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
158
159 ret = 0;
160 t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
161 if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
162 ret = 100 * 1000 * 1000;
163 } else {
164 struct clk *clk;
165
166 clk = clk_get(NULL, "ref");
167 if (!IS_ERR(clk))
168 ret = clk_get_rate(clk);
169 }
170
171 iounmap(base);
172
173 return ret;
174 }
175
176 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
177 {
178 struct platform_device *mdio_dev;
179 struct ag71xx_mdio_platform_data *mdio_data;
180 unsigned int max_id;
181
182 if (ath79_soc == ATH79_SOC_AR9341 ||
183 ath79_soc == ATH79_SOC_AR9342 ||
184 ath79_soc == ATH79_SOC_AR9344 ||
185 ath79_soc == ATH79_SOC_QCA9556 ||
186 ath79_soc == ATH79_SOC_QCA9558)
187 max_id = 1;
188 else
189 max_id = 0;
190
191 if (id > max_id) {
192 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
193 return;
194 }
195
196 switch (ath79_soc) {
197 case ATH79_SOC_AR7241:
198 case ATH79_SOC_AR9330:
199 case ATH79_SOC_AR9331:
200 mdio_dev = &ath79_mdio1_device;
201 mdio_data = &ath79_mdio1_data;
202 break;
203
204 case ATH79_SOC_AR9341:
205 case ATH79_SOC_AR9342:
206 case ATH79_SOC_AR9344:
207 case ATH79_SOC_QCA9556:
208 case ATH79_SOC_QCA9558:
209 if (id == 0) {
210 mdio_dev = &ath79_mdio0_device;
211 mdio_data = &ath79_mdio0_data;
212 } else {
213 mdio_dev = &ath79_mdio1_device;
214 mdio_data = &ath79_mdio1_data;
215 }
216 break;
217
218 case ATH79_SOC_AR7242:
219 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
220 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
221 AR71XX_ETH0_PLL_SHIFT);
222 /* fall through */
223 default:
224 mdio_dev = &ath79_mdio0_device;
225 mdio_data = &ath79_mdio0_data;
226 break;
227 }
228
229 mdio_data->phy_mask = phy_mask;
230
231 switch (ath79_soc) {
232 case ATH79_SOC_AR7240:
233 mdio_data->is_ar7240 = 1;
234 /* fall through */
235 case ATH79_SOC_AR7241:
236 mdio_data->builtin_switch = 1;
237 break;
238
239 case ATH79_SOC_AR9330:
240 mdio_data->is_ar9330 = 1;
241 /* fall through */
242 case ATH79_SOC_AR9331:
243 mdio_data->builtin_switch = 1;
244 break;
245
246 case ATH79_SOC_AR9341:
247 case ATH79_SOC_AR9342:
248 case ATH79_SOC_AR9344:
249 if (id == 1) {
250 mdio_data->builtin_switch = 1;
251 mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
252 mdio_data->mdio_clock = 6250000;
253 }
254 mdio_data->is_ar934x = 1;
255 break;
256
257 case ATH79_SOC_QCA9558:
258 if (id == 1)
259 mdio_data->builtin_switch = 1;
260 mdio_data->is_ar934x = 1;
261 break;
262
263 case ATH79_SOC_QCA9556:
264 mdio_data->is_ar934x = 1;
265 break;
266
267 default:
268 break;
269 }
270
271 platform_device_register(mdio_dev);
272 }
273
274 struct ath79_eth_pll_data ath79_eth0_pll_data;
275 struct ath79_eth_pll_data ath79_eth1_pll_data;
276
277 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
278 {
279 struct ath79_eth_pll_data *pll_data;
280 u32 pll_val;
281
282 switch (mac) {
283 case 0:
284 pll_data = &ath79_eth0_pll_data;
285 break;
286 case 1:
287 pll_data = &ath79_eth1_pll_data;
288 break;
289 default:
290 BUG();
291 }
292
293 switch (speed) {
294 case SPEED_10:
295 pll_val = pll_data->pll_10;
296 break;
297 case SPEED_100:
298 pll_val = pll_data->pll_100;
299 break;
300 case SPEED_1000:
301 pll_val = pll_data->pll_1000;
302 break;
303 default:
304 BUG();
305 }
306
307 return pll_val;
308 }
309
310 static void ath79_set_speed_ge0(int speed)
311 {
312 u32 val = ath79_get_eth_pll(0, speed);
313
314 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
315 val, AR71XX_ETH0_PLL_SHIFT);
316 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
317 }
318
319 static void ath79_set_speed_ge1(int speed)
320 {
321 u32 val = ath79_get_eth_pll(1, speed);
322
323 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
324 val, AR71XX_ETH1_PLL_SHIFT);
325 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
326 }
327
328 static void ar7242_set_speed_ge0(int speed)
329 {
330 u32 val = ath79_get_eth_pll(0, speed);
331 void __iomem *base;
332
333 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
334 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
335 iounmap(base);
336 }
337
338 static void ar91xx_set_speed_ge0(int speed)
339 {
340 u32 val = ath79_get_eth_pll(0, speed);
341
342 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
343 val, AR913X_ETH0_PLL_SHIFT);
344 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
345 }
346
347 static void ar91xx_set_speed_ge1(int speed)
348 {
349 u32 val = ath79_get_eth_pll(1, speed);
350
351 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
352 val, AR913X_ETH1_PLL_SHIFT);
353 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
354 }
355
356 static void ar934x_set_speed_ge0(int speed)
357 {
358 void __iomem *base;
359 u32 val = ath79_get_eth_pll(0, speed);
360
361 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
362 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
363 iounmap(base);
364 }
365
366 static void qca955x_set_speed_xmii(int speed)
367 {
368 void __iomem *base;
369 u32 val = ath79_get_eth_pll(0, speed);
370
371 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
372 __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
373 iounmap(base);
374 }
375
376 static void qca955x_set_speed_sgmii(int speed)
377 {
378 void __iomem *base;
379 u32 val = ath79_get_eth_pll(1, speed);
380
381 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
382 __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
383 iounmap(base);
384 }
385
386 static void ath79_set_speed_dummy(int speed)
387 {
388 }
389
390 static void ath79_ddr_no_flush(void)
391 {
392 }
393
394 static void ath79_ddr_flush_ge0(void)
395 {
396 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
397 }
398
399 static void ath79_ddr_flush_ge1(void)
400 {
401 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
402 }
403
404 static void ar724x_ddr_flush_ge0(void)
405 {
406 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
407 }
408
409 static void ar724x_ddr_flush_ge1(void)
410 {
411 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
412 }
413
414 static void ar91xx_ddr_flush_ge0(void)
415 {
416 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
417 }
418
419 static void ar91xx_ddr_flush_ge1(void)
420 {
421 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
422 }
423
424 static void ar933x_ddr_flush_ge0(void)
425 {
426 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
427 }
428
429 static void ar933x_ddr_flush_ge1(void)
430 {
431 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
432 }
433
434 static struct resource ath79_eth0_resources[] = {
435 {
436 .name = "mac_base",
437 .flags = IORESOURCE_MEM,
438 .start = AR71XX_GE0_BASE,
439 .end = AR71XX_GE0_BASE + 0x200 - 1,
440 }, {
441 .name = "mac_irq",
442 .flags = IORESOURCE_IRQ,
443 .start = ATH79_CPU_IRQ(4),
444 .end = ATH79_CPU_IRQ(4),
445 },
446 };
447
448 struct ag71xx_platform_data ath79_eth0_data = {
449 .reset_bit = AR71XX_RESET_GE0_MAC,
450 };
451
452 struct platform_device ath79_eth0_device = {
453 .name = "ag71xx",
454 .id = 0,
455 .resource = ath79_eth0_resources,
456 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
457 .dev = {
458 .platform_data = &ath79_eth0_data,
459 },
460 };
461
462 static struct resource ath79_eth1_resources[] = {
463 {
464 .name = "mac_base",
465 .flags = IORESOURCE_MEM,
466 .start = AR71XX_GE1_BASE,
467 .end = AR71XX_GE1_BASE + 0x200 - 1,
468 }, {
469 .name = "mac_irq",
470 .flags = IORESOURCE_IRQ,
471 .start = ATH79_CPU_IRQ(5),
472 .end = ATH79_CPU_IRQ(5),
473 },
474 };
475
476 struct ag71xx_platform_data ath79_eth1_data = {
477 .reset_bit = AR71XX_RESET_GE1_MAC,
478 };
479
480 struct platform_device ath79_eth1_device = {
481 .name = "ag71xx",
482 .id = 1,
483 .resource = ath79_eth1_resources,
484 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
485 .dev = {
486 .platform_data = &ath79_eth1_data,
487 },
488 };
489
490 struct ag71xx_switch_platform_data ath79_switch_data;
491
492 #define AR71XX_PLL_VAL_1000 0x00110000
493 #define AR71XX_PLL_VAL_100 0x00001099
494 #define AR71XX_PLL_VAL_10 0x00991099
495
496 #define AR724X_PLL_VAL_1000 0x00110000
497 #define AR724X_PLL_VAL_100 0x00001099
498 #define AR724X_PLL_VAL_10 0x00991099
499
500 #define AR7242_PLL_VAL_1000 0x16000000
501 #define AR7242_PLL_VAL_100 0x00000101
502 #define AR7242_PLL_VAL_10 0x00001616
503
504 #define AR913X_PLL_VAL_1000 0x1a000000
505 #define AR913X_PLL_VAL_100 0x13000a44
506 #define AR913X_PLL_VAL_10 0x00441099
507
508 #define AR933X_PLL_VAL_1000 0x00110000
509 #define AR933X_PLL_VAL_100 0x00001099
510 #define AR933X_PLL_VAL_10 0x00991099
511
512 #define AR934X_PLL_VAL_1000 0x16000000
513 #define AR934X_PLL_VAL_100 0x00000101
514 #define AR934X_PLL_VAL_10 0x00001616
515
516 static void __init ath79_init_eth_pll_data(unsigned int id)
517 {
518 struct ath79_eth_pll_data *pll_data;
519 u32 pll_10, pll_100, pll_1000;
520
521 switch (id) {
522 case 0:
523 pll_data = &ath79_eth0_pll_data;
524 break;
525 case 1:
526 pll_data = &ath79_eth1_pll_data;
527 break;
528 default:
529 BUG();
530 }
531
532 switch (ath79_soc) {
533 case ATH79_SOC_AR7130:
534 case ATH79_SOC_AR7141:
535 case ATH79_SOC_AR7161:
536 pll_10 = AR71XX_PLL_VAL_10;
537 pll_100 = AR71XX_PLL_VAL_100;
538 pll_1000 = AR71XX_PLL_VAL_1000;
539 break;
540
541 case ATH79_SOC_AR7240:
542 case ATH79_SOC_AR7241:
543 pll_10 = AR724X_PLL_VAL_10;
544 pll_100 = AR724X_PLL_VAL_100;
545 pll_1000 = AR724X_PLL_VAL_1000;
546 break;
547
548 case ATH79_SOC_AR7242:
549 pll_10 = AR7242_PLL_VAL_10;
550 pll_100 = AR7242_PLL_VAL_100;
551 pll_1000 = AR7242_PLL_VAL_1000;
552 break;
553
554 case ATH79_SOC_AR9130:
555 case ATH79_SOC_AR9132:
556 pll_10 = AR913X_PLL_VAL_10;
557 pll_100 = AR913X_PLL_VAL_100;
558 pll_1000 = AR913X_PLL_VAL_1000;
559 break;
560
561 case ATH79_SOC_AR9330:
562 case ATH79_SOC_AR9331:
563 pll_10 = AR933X_PLL_VAL_10;
564 pll_100 = AR933X_PLL_VAL_100;
565 pll_1000 = AR933X_PLL_VAL_1000;
566 break;
567
568 case ATH79_SOC_AR9341:
569 case ATH79_SOC_AR9342:
570 case ATH79_SOC_AR9344:
571 case ATH79_SOC_QCA9556:
572 case ATH79_SOC_QCA9558:
573 pll_10 = AR934X_PLL_VAL_10;
574 pll_100 = AR934X_PLL_VAL_100;
575 pll_1000 = AR934X_PLL_VAL_1000;
576 break;
577
578 default:
579 BUG();
580 }
581
582 if (!pll_data->pll_10)
583 pll_data->pll_10 = pll_10;
584
585 if (!pll_data->pll_100)
586 pll_data->pll_100 = pll_100;
587
588 if (!pll_data->pll_1000)
589 pll_data->pll_1000 = pll_1000;
590 }
591
592 static int __init ath79_setup_phy_if_mode(unsigned int id,
593 struct ag71xx_platform_data *pdata)
594 {
595 unsigned int mii_if;
596
597 switch (id) {
598 case 0:
599 switch (ath79_soc) {
600 case ATH79_SOC_AR7130:
601 case ATH79_SOC_AR7141:
602 case ATH79_SOC_AR7161:
603 case ATH79_SOC_AR9130:
604 case ATH79_SOC_AR9132:
605 switch (pdata->phy_if_mode) {
606 case PHY_INTERFACE_MODE_MII:
607 mii_if = AR71XX_MII0_CTRL_IF_MII;
608 break;
609 case PHY_INTERFACE_MODE_GMII:
610 mii_if = AR71XX_MII0_CTRL_IF_GMII;
611 break;
612 case PHY_INTERFACE_MODE_RGMII:
613 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
614 break;
615 case PHY_INTERFACE_MODE_RMII:
616 mii_if = AR71XX_MII0_CTRL_IF_RMII;
617 break;
618 default:
619 return -EINVAL;
620 }
621 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
622 break;
623
624 case ATH79_SOC_AR7240:
625 case ATH79_SOC_AR7241:
626 case ATH79_SOC_AR9330:
627 case ATH79_SOC_AR9331:
628 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
629 break;
630
631 case ATH79_SOC_AR7242:
632 /* FIXME */
633
634 case ATH79_SOC_AR9341:
635 case ATH79_SOC_AR9342:
636 case ATH79_SOC_AR9344:
637 switch (pdata->phy_if_mode) {
638 case PHY_INTERFACE_MODE_MII:
639 case PHY_INTERFACE_MODE_GMII:
640 case PHY_INTERFACE_MODE_RGMII:
641 case PHY_INTERFACE_MODE_RMII:
642 break;
643 default:
644 return -EINVAL;
645 }
646 break;
647
648 case ATH79_SOC_QCA9556:
649 case ATH79_SOC_QCA9558:
650 switch (pdata->phy_if_mode) {
651 case PHY_INTERFACE_MODE_MII:
652 case PHY_INTERFACE_MODE_RGMII:
653 case PHY_INTERFACE_MODE_SGMII:
654 break;
655 default:
656 return -EINVAL;
657 }
658 break;
659
660 default:
661 BUG();
662 }
663 break;
664 case 1:
665 switch (ath79_soc) {
666 case ATH79_SOC_AR7130:
667 case ATH79_SOC_AR7141:
668 case ATH79_SOC_AR7161:
669 case ATH79_SOC_AR9130:
670 case ATH79_SOC_AR9132:
671 switch (pdata->phy_if_mode) {
672 case PHY_INTERFACE_MODE_RMII:
673 mii_if = AR71XX_MII1_CTRL_IF_RMII;
674 break;
675 case PHY_INTERFACE_MODE_RGMII:
676 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
677 break;
678 default:
679 return -EINVAL;
680 }
681 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
682 break;
683
684 case ATH79_SOC_AR7240:
685 case ATH79_SOC_AR7241:
686 case ATH79_SOC_AR9330:
687 case ATH79_SOC_AR9331:
688 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
689 break;
690
691 case ATH79_SOC_AR7242:
692 /* FIXME */
693
694 case ATH79_SOC_AR9341:
695 case ATH79_SOC_AR9342:
696 case ATH79_SOC_AR9344:
697 switch (pdata->phy_if_mode) {
698 case PHY_INTERFACE_MODE_MII:
699 case PHY_INTERFACE_MODE_GMII:
700 break;
701 default:
702 return -EINVAL;
703 }
704 break;
705
706 case ATH79_SOC_QCA9556:
707 case ATH79_SOC_QCA9558:
708 switch (pdata->phy_if_mode) {
709 case PHY_INTERFACE_MODE_MII:
710 case PHY_INTERFACE_MODE_RGMII:
711 case PHY_INTERFACE_MODE_SGMII:
712 break;
713 default:
714 return -EINVAL;
715 }
716 break;
717
718 default:
719 BUG();
720 }
721 break;
722 }
723
724 return 0;
725 }
726
727 void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
728 {
729 void __iomem *base;
730 u32 t;
731
732 base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
733
734 t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
735 t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
736 if (mac)
737 t |= AR933X_ETH_CFG_SW_PHY_SWAP;
738 if (mdio)
739 t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
740 __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
741
742 iounmap(base);
743 }
744
745 void __init ath79_setup_ar934x_eth_cfg(u32 mask)
746 {
747 void __iomem *base;
748 u32 t;
749
750 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
751
752 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
753
754 t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
755 AR934X_ETH_CFG_MII_GMAC0 |
756 AR934X_ETH_CFG_GMII_GMAC0 |
757 AR934X_ETH_CFG_SW_ONLY_MODE |
758 AR934X_ETH_CFG_SW_PHY_SWAP);
759
760 t |= mask;
761
762 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
763 /* flush write */
764 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
765
766 iounmap(base);
767 }
768
769 static int ath79_eth_instance __initdata;
770 void __init ath79_register_eth(unsigned int id)
771 {
772 struct platform_device *pdev;
773 struct ag71xx_platform_data *pdata;
774 int err;
775
776 if (id > 1) {
777 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
778 return;
779 }
780
781 ath79_init_eth_pll_data(id);
782
783 if (id == 0)
784 pdev = &ath79_eth0_device;
785 else
786 pdev = &ath79_eth1_device;
787
788 pdata = pdev->dev.platform_data;
789
790 pdata->max_frame_len = 1540;
791 pdata->desc_pktlen_mask = 0xfff;
792
793 err = ath79_setup_phy_if_mode(id, pdata);
794 if (err) {
795 printk(KERN_ERR
796 "ar71xx: invalid PHY interface mode for GE%u\n", id);
797 return;
798 }
799
800 switch (ath79_soc) {
801 case ATH79_SOC_AR7130:
802 if (id == 0) {
803 pdata->ddr_flush = ath79_ddr_flush_ge0;
804 pdata->set_speed = ath79_set_speed_ge0;
805 } else {
806 pdata->ddr_flush = ath79_ddr_flush_ge1;
807 pdata->set_speed = ath79_set_speed_ge1;
808 }
809 break;
810
811 case ATH79_SOC_AR7141:
812 case ATH79_SOC_AR7161:
813 if (id == 0) {
814 pdata->ddr_flush = ath79_ddr_flush_ge0;
815 pdata->set_speed = ath79_set_speed_ge0;
816 } else {
817 pdata->ddr_flush = ath79_ddr_flush_ge1;
818 pdata->set_speed = ath79_set_speed_ge1;
819 }
820 pdata->has_gbit = 1;
821 break;
822
823 case ATH79_SOC_AR7242:
824 if (id == 0) {
825 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
826 AR71XX_RESET_GE0_PHY;
827 pdata->ddr_flush = ar724x_ddr_flush_ge0;
828 pdata->set_speed = ar7242_set_speed_ge0;
829 } else {
830 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
831 AR71XX_RESET_GE1_PHY;
832 pdata->ddr_flush = ar724x_ddr_flush_ge1;
833 pdata->set_speed = ath79_set_speed_dummy;
834 }
835 pdata->has_gbit = 1;
836 pdata->is_ar724x = 1;
837
838 if (!pdata->fifo_cfg1)
839 pdata->fifo_cfg1 = 0x0010ffff;
840 if (!pdata->fifo_cfg2)
841 pdata->fifo_cfg2 = 0x015500aa;
842 if (!pdata->fifo_cfg3)
843 pdata->fifo_cfg3 = 0x01f00140;
844 break;
845
846 case ATH79_SOC_AR7241:
847 if (id == 0)
848 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
849 else
850 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
851 /* fall through */
852 case ATH79_SOC_AR7240:
853 if (id == 0) {
854 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
855 pdata->ddr_flush = ar724x_ddr_flush_ge0;
856 pdata->set_speed = ath79_set_speed_dummy;
857
858 pdata->phy_mask = BIT(4);
859 } else {
860 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
861 pdata->ddr_flush = ar724x_ddr_flush_ge1;
862 pdata->set_speed = ath79_set_speed_dummy;
863
864 pdata->speed = SPEED_1000;
865 pdata->duplex = DUPLEX_FULL;
866 pdata->switch_data = &ath79_switch_data;
867
868 ath79_switch_data.phy_poll_mask |= BIT(4);
869 }
870 pdata->has_gbit = 1;
871 pdata->is_ar724x = 1;
872 if (ath79_soc == ATH79_SOC_AR7240)
873 pdata->is_ar7240 = 1;
874
875 if (!pdata->fifo_cfg1)
876 pdata->fifo_cfg1 = 0x0010ffff;
877 if (!pdata->fifo_cfg2)
878 pdata->fifo_cfg2 = 0x015500aa;
879 if (!pdata->fifo_cfg3)
880 pdata->fifo_cfg3 = 0x01f00140;
881 break;
882
883 case ATH79_SOC_AR9130:
884 if (id == 0) {
885 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
886 pdata->set_speed = ar91xx_set_speed_ge0;
887 } else {
888 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
889 pdata->set_speed = ar91xx_set_speed_ge1;
890 }
891 pdata->is_ar91xx = 1;
892 break;
893
894 case ATH79_SOC_AR9132:
895 if (id == 0) {
896 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
897 pdata->set_speed = ar91xx_set_speed_ge0;
898 } else {
899 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
900 pdata->set_speed = ar91xx_set_speed_ge1;
901 }
902 pdata->is_ar91xx = 1;
903 pdata->has_gbit = 1;
904 break;
905
906 case ATH79_SOC_AR9330:
907 case ATH79_SOC_AR9331:
908 if (id == 0) {
909 pdata->reset_bit = AR933X_RESET_GE0_MAC |
910 AR933X_RESET_GE0_MDIO;
911 pdata->ddr_flush = ar933x_ddr_flush_ge0;
912 pdata->set_speed = ath79_set_speed_dummy;
913
914 pdata->phy_mask = BIT(4);
915 } else {
916 pdata->reset_bit = AR933X_RESET_GE1_MAC |
917 AR933X_RESET_GE1_MDIO;
918 pdata->ddr_flush = ar933x_ddr_flush_ge1;
919 pdata->set_speed = ath79_set_speed_dummy;
920
921 pdata->speed = SPEED_1000;
922 pdata->duplex = DUPLEX_FULL;
923 pdata->switch_data = &ath79_switch_data;
924
925 ath79_switch_data.phy_poll_mask |= BIT(4);
926 }
927
928 pdata->has_gbit = 1;
929 pdata->is_ar724x = 1;
930
931 if (!pdata->fifo_cfg1)
932 pdata->fifo_cfg1 = 0x0010ffff;
933 if (!pdata->fifo_cfg2)
934 pdata->fifo_cfg2 = 0x015500aa;
935 if (!pdata->fifo_cfg3)
936 pdata->fifo_cfg3 = 0x01f00140;
937 break;
938
939 case ATH79_SOC_AR9341:
940 case ATH79_SOC_AR9342:
941 case ATH79_SOC_AR9344:
942 if (id == 0) {
943 pdata->reset_bit = AR934X_RESET_GE0_MAC |
944 AR934X_RESET_GE0_MDIO;
945 pdata->set_speed = ar934x_set_speed_ge0;
946 } else {
947 pdata->reset_bit = AR934X_RESET_GE1_MAC |
948 AR934X_RESET_GE1_MDIO;
949 pdata->set_speed = ath79_set_speed_dummy;
950
951 pdata->switch_data = &ath79_switch_data;
952
953 /* reset the built-in switch */
954 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
955 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
956 }
957
958 pdata->ddr_flush = ath79_ddr_no_flush;
959 pdata->has_gbit = 1;
960 pdata->is_ar724x = 1;
961
962 pdata->max_frame_len = SZ_16K - 1;
963 pdata->desc_pktlen_mask = SZ_16K - 1;
964
965 if (!pdata->fifo_cfg1)
966 pdata->fifo_cfg1 = 0x0010ffff;
967 if (!pdata->fifo_cfg2)
968 pdata->fifo_cfg2 = 0x015500aa;
969 if (!pdata->fifo_cfg3)
970 pdata->fifo_cfg3 = 0x01f00140;
971 break;
972
973 case ATH79_SOC_QCA9556:
974 case ATH79_SOC_QCA9558:
975 if (id == 0) {
976 pdata->reset_bit = QCA955X_RESET_GE0_MAC |
977 QCA955X_RESET_GE0_MDIO;
978 pdata->set_speed = qca955x_set_speed_xmii;
979 } else {
980 pdata->reset_bit = QCA955X_RESET_GE1_MAC |
981 QCA955X_RESET_GE1_MDIO;
982 pdata->set_speed = qca955x_set_speed_sgmii;
983 }
984
985 pdata->ddr_flush = ath79_ddr_no_flush;
986 pdata->has_gbit = 1;
987 pdata->is_ar724x = 1;
988
989 if (!pdata->fifo_cfg1)
990 pdata->fifo_cfg1 = 0x0010ffff;
991 if (!pdata->fifo_cfg2)
992 pdata->fifo_cfg2 = 0x015500aa;
993 if (!pdata->fifo_cfg3)
994 pdata->fifo_cfg3 = 0x01f00140;
995 break;
996
997 default:
998 BUG();
999 }
1000
1001 switch (pdata->phy_if_mode) {
1002 case PHY_INTERFACE_MODE_GMII:
1003 case PHY_INTERFACE_MODE_RGMII:
1004 case PHY_INTERFACE_MODE_SGMII:
1005 if (!pdata->has_gbit) {
1006 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
1007 id);
1008 return;
1009 }
1010 /* fallthrough */
1011 default:
1012 break;
1013 }
1014
1015 if (!is_valid_ether_addr(pdata->mac_addr)) {
1016 random_ether_addr(pdata->mac_addr);
1017 printk(KERN_DEBUG
1018 "ar71xx: using random MAC address for eth%d\n",
1019 ath79_eth_instance);
1020 }
1021
1022 if (pdata->mii_bus_dev == NULL) {
1023 switch (ath79_soc) {
1024 case ATH79_SOC_AR9341:
1025 case ATH79_SOC_AR9342:
1026 case ATH79_SOC_AR9344:
1027 if (id == 0)
1028 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1029 else
1030 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1031 break;
1032
1033 case ATH79_SOC_AR7241:
1034 case ATH79_SOC_AR9330:
1035 case ATH79_SOC_AR9331:
1036 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1037 break;
1038
1039 case ATH79_SOC_QCA9556:
1040 case ATH79_SOC_QCA9558:
1041 /* don't assign any MDIO device by default */
1042 break;
1043
1044 default:
1045 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1046 break;
1047 }
1048 }
1049
1050 /* Reset the device */
1051 ath79_device_reset_set(pdata->reset_bit);
1052 mdelay(100);
1053
1054 ath79_device_reset_clear(pdata->reset_bit);
1055 mdelay(100);
1056
1057 platform_device_register(pdev);
1058 ath79_eth_instance++;
1059 }
1060
1061 void __init ath79_set_mac_base(unsigned char *mac)
1062 {
1063 memcpy(ath79_mac_base, mac, ETH_ALEN);
1064 }
1065
1066 void __init ath79_parse_ascii_mac(char *mac_str, u8 *mac)
1067 {
1068 int t;
1069
1070 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1071 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1072
1073 if (t != ETH_ALEN)
1074 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1075 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1076
1077 if (t != ETH_ALEN || !is_valid_ether_addr(mac)) {
1078 memset(mac, 0, ETH_ALEN);
1079 printk(KERN_DEBUG "ar71xx: invalid mac address \"%s\"\n",
1080 mac_str);
1081 }
1082 }
1083
1084 static void __init ath79_set_mac_base_ascii(char *str)
1085 {
1086 u8 mac[ETH_ALEN];
1087
1088 ath79_parse_ascii_mac(str, mac);
1089 ath79_set_mac_base(mac);
1090 }
1091
1092 static int __init ath79_ethaddr_setup(char *str)
1093 {
1094 ath79_set_mac_base_ascii(str);
1095 return 1;
1096 }
1097 __setup("ethaddr=", ath79_ethaddr_setup);
1098
1099 static int __init ath79_kmac_setup(char *str)
1100 {
1101 ath79_set_mac_base_ascii(str);
1102 return 1;
1103 }
1104 __setup("kmac=", ath79_kmac_setup);
1105
1106 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
1107 int offset)
1108 {
1109 int t;
1110
1111 if (!dst)
1112 return;
1113
1114 if (!src || !is_valid_ether_addr(src)) {
1115 memset(dst, '\0', ETH_ALEN);
1116 return;
1117 }
1118
1119 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1120 t += offset;
1121
1122 dst[0] = src[0];
1123 dst[1] = src[1];
1124 dst[2] = src[2];
1125 dst[3] = (t >> 16) & 0xff;
1126 dst[4] = (t >> 8) & 0xff;
1127 dst[5] = t & 0xff;
1128 }
1129
1130 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
1131 {
1132 int i;
1133
1134 if (!dst)
1135 return;
1136
1137 if (!src || !is_valid_ether_addr(src)) {
1138 memset(dst, '\0', ETH_ALEN);
1139 return;
1140 }
1141
1142 for (i = 0; i < ETH_ALEN; i++)
1143 dst[i] = src[i];
1144 dst[0] |= 0x02;
1145 }
John Crispins staging tree