projects / openwrt / staging / blogic.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ar71xx: fold patch 622-MIPS-ath79-add-support-for-QCA956x-ethernet.patch into files/
[openwrt/staging/blogic.git] / target / linux / ar71xx / files / arch / mips / ath79 / dev-eth.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23 #include <linux/sizes.h>
24
25 #include <asm/mach-ath79/ath79.h>
26 #include <asm/mach-ath79/ar71xx_regs.h>
27 #include <asm/mach-ath79/irq.h>
28
29 #include "common.h"
30 #include "dev-eth.h"
31
32 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
33
34 static struct resource ath79_mdio0_resources[] = {
35 {
36 .name = "mdio_base",
37 .flags = IORESOURCE_MEM,
38 .start = AR71XX_GE0_BASE,
39 .end = AR71XX_GE0_BASE + 0x200 - 1,
40 }
41 };
42
43 struct ag71xx_mdio_platform_data ath79_mdio0_data;
44
45 struct platform_device ath79_mdio0_device = {
46 .name = "ag71xx-mdio",
47 .id = 0,
48 .resource = ath79_mdio0_resources,
49 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
50 .dev = {
51 .platform_data = &ath79_mdio0_data,
52 },
53 };
54
55 static struct resource ath79_mdio1_resources[] = {
56 {
57 .name = "mdio_base",
58 .flags = IORESOURCE_MEM,
59 .start = AR71XX_GE1_BASE,
60 .end = AR71XX_GE1_BASE + 0x200 - 1,
61 }
62 };
63
64 struct ag71xx_mdio_platform_data ath79_mdio1_data;
65
66 struct platform_device ath79_mdio1_device = {
67 .name = "ag71xx-mdio",
68 .id = 1,
69 .resource = ath79_mdio1_resources,
70 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
71 .dev = {
72 .platform_data = &ath79_mdio1_data,
73 },
74 };
75
76 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
77 {
78 void __iomem *base;
79 u32 t;
80
81 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
82
83 t = __raw_readl(base + cfg_reg);
84 t &= ~(3 << shift);
85 t |= (2 << shift);
86 __raw_writel(t, base + cfg_reg);
87 udelay(100);
88
89 __raw_writel(pll_val, base + pll_reg);
90
91 t |= (3 << shift);
92 __raw_writel(t, base + cfg_reg);
93 udelay(100);
94
95 t &= ~(3 << shift);
96 __raw_writel(t, base + cfg_reg);
97 udelay(100);
98
99 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
100 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
101
102 iounmap(base);
103 }
104
105 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
106 unsigned int mii_if)
107 {
108 void __iomem *base;
109 u32 t;
110
111 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
112
113 t = __raw_readl(base + reg);
114 t &= ~(AR71XX_MII_CTRL_IF_MASK);
115 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
116 __raw_writel(t, base + reg);
117
118 iounmap(base);
119 }
120
121 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
122 {
123 void __iomem *base;
124 unsigned int mii_speed;
125 u32 t;
126
127 switch (speed) {
128 case SPEED_10:
129 mii_speed = AR71XX_MII_CTRL_SPEED_10;
130 break;
131 case SPEED_100:
132 mii_speed = AR71XX_MII_CTRL_SPEED_100;
133 break;
134 case SPEED_1000:
135 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
136 break;
137 default:
138 BUG();
139 }
140
141 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
142
143 t = __raw_readl(base + reg);
144 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
145 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
146 __raw_writel(t, base + reg);
147
148 iounmap(base);
149 }
150
151 static unsigned long ar934x_get_mdio_ref_clock(void)
152 {
153 void __iomem *base;
154 unsigned long ret;
155 u32 t;
156
157 base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
158
159 ret = 0;
160 t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
161 if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
162 ret = 100 * 1000 * 1000;
163 } else {
164 struct clk *clk;
165
166 clk = clk_get(NULL, "ref");
167 if (!IS_ERR(clk))
168 ret = clk_get_rate(clk);
169 }
170
171 iounmap(base);
172
173 return ret;
174 }
175
176 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
177 {
178 struct platform_device *mdio_dev;
179 struct ag71xx_mdio_platform_data *mdio_data;
180 unsigned int max_id;
181
182 if (ath79_soc == ATH79_SOC_AR9341 ||
183 ath79_soc == ATH79_SOC_AR9342 ||
184 ath79_soc == ATH79_SOC_AR9344 ||
185 ath79_soc == ATH79_SOC_QCA9556 ||
186 ath79_soc == ATH79_SOC_QCA9558)
187 max_id = 1;
188 else
189 max_id = 0;
190
191 if (id > max_id) {
192 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
193 return;
194 }
195
196 switch (ath79_soc) {
197 case ATH79_SOC_AR7241:
198 case ATH79_SOC_AR9330:
199 case ATH79_SOC_AR9331:
200 case ATH79_SOC_QCA9533:
201 case ATH79_SOC_TP9343:
202 mdio_dev = &ath79_mdio1_device;
203 mdio_data = &ath79_mdio1_data;
204 break;
205
206 case ATH79_SOC_AR9341:
207 case ATH79_SOC_AR9342:
208 case ATH79_SOC_AR9344:
209 case ATH79_SOC_QCA9556:
210 case ATH79_SOC_QCA9558:
211 case ATH79_SOC_QCA956X:
212 if (id == 0) {
213 mdio_dev = &ath79_mdio0_device;
214 mdio_data = &ath79_mdio0_data;
215 } else {
216 mdio_dev = &ath79_mdio1_device;
217 mdio_data = &ath79_mdio1_data;
218 }
219 break;
220
221 case ATH79_SOC_AR7242:
222 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
223 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
224 AR71XX_ETH0_PLL_SHIFT);
225 /* fall through */
226 default:
227 mdio_dev = &ath79_mdio0_device;
228 mdio_data = &ath79_mdio0_data;
229 break;
230 }
231
232 mdio_data->phy_mask = phy_mask;
233
234 switch (ath79_soc) {
235 case ATH79_SOC_AR7240:
236 mdio_data->is_ar7240 = 1;
237 /* fall through */
238 case ATH79_SOC_AR7241:
239 mdio_data->builtin_switch = 1;
240 break;
241
242 case ATH79_SOC_AR9330:
243 mdio_data->is_ar9330 = 1;
244 /* fall through */
245 case ATH79_SOC_AR9331:
246 mdio_data->builtin_switch = 1;
247 break;
248
249 case ATH79_SOC_AR9341:
250 case ATH79_SOC_AR9342:
251 case ATH79_SOC_AR9344:
252 if (id == 1) {
253 mdio_data->builtin_switch = 1;
254 mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
255 mdio_data->mdio_clock = 6250000;
256 }
257 mdio_data->is_ar934x = 1;
258 break;
259
260 case ATH79_SOC_QCA9533:
261 case ATH79_SOC_TP9343:
262 mdio_data->builtin_switch = 1;
263 break;
264
265 case ATH79_SOC_QCA9556:
266 case ATH79_SOC_QCA9558:
267 mdio_data->is_ar934x = 1;
268 break;
269
270 case ATH79_SOC_QCA956X:
271 if (id == 1)
272 mdio_data->builtin_switch = 1;
273 break;
274
275 default:
276 break;
277 }
278
279 platform_device_register(mdio_dev);
280 }
281
282 struct ath79_eth_pll_data ath79_eth0_pll_data;
283 struct ath79_eth_pll_data ath79_eth1_pll_data;
284
285 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
286 {
287 struct ath79_eth_pll_data *pll_data;
288 u32 pll_val;
289
290 switch (mac) {
291 case 0:
292 pll_data = &ath79_eth0_pll_data;
293 break;
294 case 1:
295 pll_data = &ath79_eth1_pll_data;
296 break;
297 default:
298 BUG();
299 }
300
301 switch (speed) {
302 case SPEED_10:
303 pll_val = pll_data->pll_10;
304 break;
305 case SPEED_100:
306 pll_val = pll_data->pll_100;
307 break;
308 case SPEED_1000:
309 pll_val = pll_data->pll_1000;
310 break;
311 default:
312 BUG();
313 }
314
315 return pll_val;
316 }
317
318 static void ath79_set_speed_ge0(int speed)
319 {
320 u32 val = ath79_get_eth_pll(0, speed);
321
322 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
323 val, AR71XX_ETH0_PLL_SHIFT);
324 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
325 }
326
327 static void ath79_set_speed_ge1(int speed)
328 {
329 u32 val = ath79_get_eth_pll(1, speed);
330
331 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
332 val, AR71XX_ETH1_PLL_SHIFT);
333 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
334 }
335
336 static void ar7242_set_speed_ge0(int speed)
337 {
338 u32 val = ath79_get_eth_pll(0, speed);
339 void __iomem *base;
340
341 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
342 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
343 iounmap(base);
344 }
345
346 static void ar91xx_set_speed_ge0(int speed)
347 {
348 u32 val = ath79_get_eth_pll(0, speed);
349
350 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
351 val, AR913X_ETH0_PLL_SHIFT);
352 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
353 }
354
355 static void ar91xx_set_speed_ge1(int speed)
356 {
357 u32 val = ath79_get_eth_pll(1, speed);
358
359 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
360 val, AR913X_ETH1_PLL_SHIFT);
361 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
362 }
363
364 static void ar934x_set_speed_ge0(int speed)
365 {
366 void __iomem *base;
367 u32 val = ath79_get_eth_pll(0, speed);
368
369 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
370 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
371 iounmap(base);
372 }
373
374 static void qca955x_set_speed_xmii(int speed)
375 {
376 void __iomem *base;
377 u32 val = ath79_get_eth_pll(0, speed);
378
379 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
380 __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
381 iounmap(base);
382 }
383
384 static void qca955x_set_speed_sgmii(int speed)
385 {
386 void __iomem *base;
387 u32 val = ath79_get_eth_pll(1, speed);
388
389 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
390 __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
391 iounmap(base);
392 }
393
394 static void qca956x_set_speed_sgmii(int speed)
395 {
396 void __iomem *base;
397 u32 val = ath79_get_eth_pll(0, speed);
398
399 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
400 __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
401 iounmap(base);
402 }
403
404 static void ath79_set_speed_dummy(int speed)
405 {
406 }
407
408 static void ath79_ddr_no_flush(void)
409 {
410 }
411
412 static void ath79_ddr_flush_ge0(void)
413 {
414 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
415 }
416
417 static void ath79_ddr_flush_ge1(void)
418 {
419 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
420 }
421
422 static void ar724x_ddr_flush_ge0(void)
423 {
424 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
425 }
426
427 static void ar724x_ddr_flush_ge1(void)
428 {
429 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
430 }
431
432 static void ar91xx_ddr_flush_ge0(void)
433 {
434 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
435 }
436
437 static void ar91xx_ddr_flush_ge1(void)
438 {
439 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
440 }
441
442 static void ar933x_ddr_flush_ge0(void)
443 {
444 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
445 }
446
447 static void ar933x_ddr_flush_ge1(void)
448 {
449 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
450 }
451
452 static struct resource ath79_eth0_resources[] = {
453 {
454 .name = "mac_base",
455 .flags = IORESOURCE_MEM,
456 .start = AR71XX_GE0_BASE,
457 .end = AR71XX_GE0_BASE + 0x200 - 1,
458 }, {
459 .name = "mac_irq",
460 .flags = IORESOURCE_IRQ,
461 .start = ATH79_CPU_IRQ(4),
462 .end = ATH79_CPU_IRQ(4),
463 },
464 };
465
466 struct ag71xx_platform_data ath79_eth0_data = {
467 .reset_bit = AR71XX_RESET_GE0_MAC,
468 };
469
470 struct platform_device ath79_eth0_device = {
471 .name = "ag71xx",
472 .id = 0,
473 .resource = ath79_eth0_resources,
474 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
475 .dev = {
476 .platform_data = &ath79_eth0_data,
477 },
478 };
479
480 static struct resource ath79_eth1_resources[] = {
481 {
482 .name = "mac_base",
483 .flags = IORESOURCE_MEM,
484 .start = AR71XX_GE1_BASE,
485 .end = AR71XX_GE1_BASE + 0x200 - 1,
486 }, {
487 .name = "mac_irq",
488 .flags = IORESOURCE_IRQ,
489 .start = ATH79_CPU_IRQ(5),
490 .end = ATH79_CPU_IRQ(5),
491 },
492 };
493
494 struct ag71xx_platform_data ath79_eth1_data = {
495 .reset_bit = AR71XX_RESET_GE1_MAC,
496 };
497
498 struct platform_device ath79_eth1_device = {
499 .name = "ag71xx",
500 .id = 1,
501 .resource = ath79_eth1_resources,
502 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
503 .dev = {
504 .platform_data = &ath79_eth1_data,
505 },
506 };
507
508 struct ag71xx_switch_platform_data ath79_switch_data;
509
510 #define AR71XX_PLL_VAL_1000 0x00110000
511 #define AR71XX_PLL_VAL_100 0x00001099
512 #define AR71XX_PLL_VAL_10 0x00991099
513
514 #define AR724X_PLL_VAL_1000 0x00110000
515 #define AR724X_PLL_VAL_100 0x00001099
516 #define AR724X_PLL_VAL_10 0x00991099
517
518 #define AR7242_PLL_VAL_1000 0x16000000
519 #define AR7242_PLL_VAL_100 0x00000101
520 #define AR7242_PLL_VAL_10 0x00001616
521
522 #define AR913X_PLL_VAL_1000 0x1a000000
523 #define AR913X_PLL_VAL_100 0x13000a44
524 #define AR913X_PLL_VAL_10 0x00441099
525
526 #define AR933X_PLL_VAL_1000 0x00110000
527 #define AR933X_PLL_VAL_100 0x00001099
528 #define AR933X_PLL_VAL_10 0x00991099
529
530 #define AR934X_PLL_VAL_1000 0x16000000
531 #define AR934X_PLL_VAL_100 0x00000101
532 #define AR934X_PLL_VAL_10 0x00001616
533
534 #define QCA956X_PLL_VAL_1000 0x03000000
535 #define QCA956X_PLL_VAL_100 0x00000101
536 #define QCA956X_PLL_VAL_10 0x00001919
537
538 static void __init ath79_init_eth_pll_data(unsigned int id)
539 {
540 struct ath79_eth_pll_data *pll_data;
541 u32 pll_10, pll_100, pll_1000;
542
543 switch (id) {
544 case 0:
545 pll_data = &ath79_eth0_pll_data;
546 break;
547 case 1:
548 pll_data = &ath79_eth1_pll_data;
549 break;
550 default:
551 BUG();
552 }
553
554 switch (ath79_soc) {
555 case ATH79_SOC_AR7130:
556 case ATH79_SOC_AR7141:
557 case ATH79_SOC_AR7161:
558 pll_10 = AR71XX_PLL_VAL_10;
559 pll_100 = AR71XX_PLL_VAL_100;
560 pll_1000 = AR71XX_PLL_VAL_1000;
561 break;
562
563 case ATH79_SOC_AR7240:
564 case ATH79_SOC_AR7241:
565 pll_10 = AR724X_PLL_VAL_10;
566 pll_100 = AR724X_PLL_VAL_100;
567 pll_1000 = AR724X_PLL_VAL_1000;
568 break;
569
570 case ATH79_SOC_AR7242:
571 pll_10 = AR7242_PLL_VAL_10;
572 pll_100 = AR7242_PLL_VAL_100;
573 pll_1000 = AR7242_PLL_VAL_1000;
574 break;
575
576 case ATH79_SOC_AR9130:
577 case ATH79_SOC_AR9132:
578 pll_10 = AR913X_PLL_VAL_10;
579 pll_100 = AR913X_PLL_VAL_100;
580 pll_1000 = AR913X_PLL_VAL_1000;
581 break;
582
583 case ATH79_SOC_AR9330:
584 case ATH79_SOC_AR9331:
585 pll_10 = AR933X_PLL_VAL_10;
586 pll_100 = AR933X_PLL_VAL_100;
587 pll_1000 = AR933X_PLL_VAL_1000;
588 break;
589
590 case ATH79_SOC_AR9341:
591 case ATH79_SOC_AR9342:
592 case ATH79_SOC_AR9344:
593 case ATH79_SOC_QCA9533:
594 case ATH79_SOC_QCA9556:
595 case ATH79_SOC_QCA9558:
596 case ATH79_SOC_TP9343:
597 pll_10 = AR934X_PLL_VAL_10;
598 pll_100 = AR934X_PLL_VAL_100;
599 pll_1000 = AR934X_PLL_VAL_1000;
600 break;
601
602 case ATH79_SOC_QCA956X:
603 pll_10 = QCA956X_PLL_VAL_10;
604 pll_100 = QCA956X_PLL_VAL_100;
605 pll_1000 = QCA956X_PLL_VAL_1000;
606 break;
607
608 default:
609 BUG();
610 }
611
612 if (!pll_data->pll_10)
613 pll_data->pll_10 = pll_10;
614
615 if (!pll_data->pll_100)
616 pll_data->pll_100 = pll_100;
617
618 if (!pll_data->pll_1000)
619 pll_data->pll_1000 = pll_1000;
620 }
621
622 static int __init ath79_setup_phy_if_mode(unsigned int id,
623 struct ag71xx_platform_data *pdata)
624 {
625 unsigned int mii_if;
626
627 switch (id) {
628 case 0:
629 switch (ath79_soc) {
630 case ATH79_SOC_AR7130:
631 case ATH79_SOC_AR7141:
632 case ATH79_SOC_AR7161:
633 case ATH79_SOC_AR9130:
634 case ATH79_SOC_AR9132:
635 switch (pdata->phy_if_mode) {
636 case PHY_INTERFACE_MODE_MII:
637 mii_if = AR71XX_MII0_CTRL_IF_MII;
638 break;
639 case PHY_INTERFACE_MODE_GMII:
640 mii_if = AR71XX_MII0_CTRL_IF_GMII;
641 break;
642 case PHY_INTERFACE_MODE_RGMII:
643 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
644 break;
645 case PHY_INTERFACE_MODE_RMII:
646 mii_if = AR71XX_MII0_CTRL_IF_RMII;
647 break;
648 default:
649 return -EINVAL;
650 }
651 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
652 break;
653
654 case ATH79_SOC_AR7240:
655 case ATH79_SOC_AR7241:
656 case ATH79_SOC_AR9330:
657 case ATH79_SOC_AR9331:
658 case ATH79_SOC_QCA9533:
659 case ATH79_SOC_TP9343:
660 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
661 break;
662
663 case ATH79_SOC_AR7242:
664 /* FIXME */
665
666 case ATH79_SOC_AR9341:
667 case ATH79_SOC_AR9342:
668 case ATH79_SOC_AR9344:
669 switch (pdata->phy_if_mode) {
670 case PHY_INTERFACE_MODE_MII:
671 case PHY_INTERFACE_MODE_GMII:
672 case PHY_INTERFACE_MODE_RGMII:
673 case PHY_INTERFACE_MODE_RMII:
674 break;
675 default:
676 return -EINVAL;
677 }
678 break;
679
680 case ATH79_SOC_QCA9556:
681 case ATH79_SOC_QCA9558:
682 case ATH79_SOC_QCA956X:
683 switch (pdata->phy_if_mode) {
684 case PHY_INTERFACE_MODE_MII:
685 case PHY_INTERFACE_MODE_RGMII:
686 case PHY_INTERFACE_MODE_SGMII:
687 break;
688 default:
689 return -EINVAL;
690 }
691 break;
692
693 default:
694 BUG();
695 }
696 break;
697 case 1:
698 switch (ath79_soc) {
699 case ATH79_SOC_AR7130:
700 case ATH79_SOC_AR7141:
701 case ATH79_SOC_AR7161:
702 case ATH79_SOC_AR9130:
703 case ATH79_SOC_AR9132:
704 switch (pdata->phy_if_mode) {
705 case PHY_INTERFACE_MODE_RMII:
706 mii_if = AR71XX_MII1_CTRL_IF_RMII;
707 break;
708 case PHY_INTERFACE_MODE_RGMII:
709 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
710 break;
711 default:
712 return -EINVAL;
713 }
714 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
715 break;
716
717 case ATH79_SOC_AR7240:
718 case ATH79_SOC_AR7241:
719 case ATH79_SOC_AR9330:
720 case ATH79_SOC_AR9331:
721 case ATH79_SOC_QCA956X:
722 case ATH79_SOC_TP9343:
723 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
724 break;
725
726 case ATH79_SOC_AR7242:
727 /* FIXME */
728
729 case ATH79_SOC_AR9341:
730 case ATH79_SOC_AR9342:
731 case ATH79_SOC_AR9344:
732 case ATH79_SOC_QCA9533:
733 switch (pdata->phy_if_mode) {
734 case PHY_INTERFACE_MODE_MII:
735 case PHY_INTERFACE_MODE_GMII:
736 break;
737 default:
738 return -EINVAL;
739 }
740 break;
741
742 case ATH79_SOC_QCA9556:
743 case ATH79_SOC_QCA9558:
744 switch (pdata->phy_if_mode) {
745 case PHY_INTERFACE_MODE_MII:
746 case PHY_INTERFACE_MODE_RGMII:
747 case PHY_INTERFACE_MODE_SGMII:
748 break;
749 default:
750 return -EINVAL;
751 }
752 break;
753
754 default:
755 BUG();
756 }
757 break;
758 }
759
760 return 0;
761 }
762
763 void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
764 {
765 void __iomem *base;
766 u32 t;
767
768 base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
769
770 t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
771 t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
772 if (mac)
773 t |= AR933X_ETH_CFG_SW_PHY_SWAP;
774 if (mdio)
775 t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
776 __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
777
778 iounmap(base);
779 }
780
781 void __init ath79_setup_ar934x_eth_cfg(u32 mask)
782 {
783 void __iomem *base;
784 u32 t;
785
786 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
787
788 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
789
790 t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
791 AR934X_ETH_CFG_MII_GMAC0 |
792 AR934X_ETH_CFG_GMII_GMAC0 |
793 AR934X_ETH_CFG_SW_ONLY_MODE |
794 AR934X_ETH_CFG_SW_PHY_SWAP);
795
796 t |= mask;
797
798 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
799 /* flush write */
800 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
801
802 iounmap(base);
803 }
804
805 void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd,
806 unsigned int rxdv)
807 {
808 void __iomem *base;
809 u32 t;
810
811 rxd &= AR934X_ETH_CFG_RXD_DELAY_MASK;
812 rxdv &= AR934X_ETH_CFG_RDV_DELAY_MASK;
813
814 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
815
816 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
817
818 t &= ~(AR934X_ETH_CFG_RXD_DELAY_MASK << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
819 AR934X_ETH_CFG_RDV_DELAY_MASK << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
820
821 t |= (rxd << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
822 rxdv << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
823
824 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
825 /* flush write */
826 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
827
828 iounmap(base);
829 }
830
831 void __init ath79_setup_qca955x_eth_cfg(u32 mask)
832 {
833 void __iomem *base;
834 u32 t;
835
836 base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
837
838 t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
839
840 t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
841
842 t |= mask;
843
844 __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
845
846 iounmap(base);
847 }
848
849 static int ath79_eth_instance __initdata;
850 void __init ath79_register_eth(unsigned int id)
851 {
852 struct platform_device *pdev;
853 struct ag71xx_platform_data *pdata;
854 int err;
855
856 if (id > 1) {
857 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
858 return;
859 }
860
861 ath79_init_eth_pll_data(id);
862
863 if (id == 0)
864 pdev = &ath79_eth0_device;
865 else
866 pdev = &ath79_eth1_device;
867
868 pdata = pdev->dev.platform_data;
869
870 pdata->max_frame_len = 1540;
871 pdata->desc_pktlen_mask = 0xfff;
872
873 err = ath79_setup_phy_if_mode(id, pdata);
874 if (err) {
875 printk(KERN_ERR
876 "ar71xx: invalid PHY interface mode for GE%u\n", id);
877 return;
878 }
879
880 switch (ath79_soc) {
881 case ATH79_SOC_AR7130:
882 if (id == 0) {
883 pdata->ddr_flush = ath79_ddr_flush_ge0;
884 pdata->set_speed = ath79_set_speed_ge0;
885 } else {
886 pdata->ddr_flush = ath79_ddr_flush_ge1;
887 pdata->set_speed = ath79_set_speed_ge1;
888 }
889 break;
890
891 case ATH79_SOC_AR7141:
892 case ATH79_SOC_AR7161:
893 if (id == 0) {
894 pdata->ddr_flush = ath79_ddr_flush_ge0;
895 pdata->set_speed = ath79_set_speed_ge0;
896 } else {
897 pdata->ddr_flush = ath79_ddr_flush_ge1;
898 pdata->set_speed = ath79_set_speed_ge1;
899 }
900 pdata->has_gbit = 1;
901 break;
902
903 case ATH79_SOC_AR7242:
904 if (id == 0) {
905 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
906 AR71XX_RESET_GE0_PHY;
907 pdata->ddr_flush = ar724x_ddr_flush_ge0;
908 pdata->set_speed = ar7242_set_speed_ge0;
909 } else {
910 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
911 AR71XX_RESET_GE1_PHY;
912 pdata->ddr_flush = ar724x_ddr_flush_ge1;
913 pdata->set_speed = ath79_set_speed_dummy;
914 }
915 pdata->has_gbit = 1;
916 pdata->is_ar724x = 1;
917
918 if (!pdata->fifo_cfg1)
919 pdata->fifo_cfg1 = 0x0010ffff;
920 if (!pdata->fifo_cfg2)
921 pdata->fifo_cfg2 = 0x015500aa;
922 if (!pdata->fifo_cfg3)
923 pdata->fifo_cfg3 = 0x01f00140;
924 break;
925
926 case ATH79_SOC_AR7241:
927 if (id == 0)
928 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
929 else
930 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
931 /* fall through */
932 case ATH79_SOC_AR7240:
933 if (id == 0) {
934 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
935 pdata->ddr_flush = ar724x_ddr_flush_ge0;
936 pdata->set_speed = ath79_set_speed_dummy;
937
938 pdata->phy_mask = BIT(4);
939 } else {
940 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
941 pdata->ddr_flush = ar724x_ddr_flush_ge1;
942 pdata->set_speed = ath79_set_speed_dummy;
943
944 pdata->speed = SPEED_1000;
945 pdata->duplex = DUPLEX_FULL;
946 pdata->switch_data = &ath79_switch_data;
947
948 ath79_switch_data.phy_poll_mask |= BIT(4);
949 }
950 pdata->has_gbit = 1;
951 pdata->is_ar724x = 1;
952 if (ath79_soc == ATH79_SOC_AR7240)
953 pdata->is_ar7240 = 1;
954
955 if (!pdata->fifo_cfg1)
956 pdata->fifo_cfg1 = 0x0010ffff;
957 if (!pdata->fifo_cfg2)
958 pdata->fifo_cfg2 = 0x015500aa;
959 if (!pdata->fifo_cfg3)
960 pdata->fifo_cfg3 = 0x01f00140;
961 break;
962
963 case ATH79_SOC_AR9130:
964 if (id == 0) {
965 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
966 pdata->set_speed = ar91xx_set_speed_ge0;
967 } else {
968 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
969 pdata->set_speed = ar91xx_set_speed_ge1;
970 }
971 pdata->is_ar91xx = 1;
972 break;
973
974 case ATH79_SOC_AR9132:
975 if (id == 0) {
976 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
977 pdata->set_speed = ar91xx_set_speed_ge0;
978 } else {
979 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
980 pdata->set_speed = ar91xx_set_speed_ge1;
981 }
982 pdata->is_ar91xx = 1;
983 pdata->has_gbit = 1;
984 break;
985
986 case ATH79_SOC_AR9330:
987 case ATH79_SOC_AR9331:
988 if (id == 0) {
989 pdata->reset_bit = AR933X_RESET_GE0_MAC |
990 AR933X_RESET_GE0_MDIO;
991 pdata->ddr_flush = ar933x_ddr_flush_ge0;
992 pdata->set_speed = ath79_set_speed_dummy;
993
994 pdata->phy_mask = BIT(4);
995 } else {
996 pdata->reset_bit = AR933X_RESET_GE1_MAC |
997 AR933X_RESET_GE1_MDIO;
998 pdata->ddr_flush = ar933x_ddr_flush_ge1;
999 pdata->set_speed = ath79_set_speed_dummy;
1000
1001 pdata->speed = SPEED_1000;
1002 pdata->has_gbit = 1;
1003 pdata->duplex = DUPLEX_FULL;
1004 pdata->switch_data = &ath79_switch_data;
1005
1006 ath79_switch_data.phy_poll_mask |= BIT(4);
1007 }
1008
1009 pdata->is_ar724x = 1;
1010
1011 if (!pdata->fifo_cfg1)
1012 pdata->fifo_cfg1 = 0x0010ffff;
1013 if (!pdata->fifo_cfg2)
1014 pdata->fifo_cfg2 = 0x015500aa;
1015 if (!pdata->fifo_cfg3)
1016 pdata->fifo_cfg3 = 0x01f00140;
1017 break;
1018
1019 case ATH79_SOC_AR9341:
1020 case ATH79_SOC_AR9342:
1021 case ATH79_SOC_AR9344:
1022 case ATH79_SOC_QCA9533:
1023 if (id == 0) {
1024 pdata->reset_bit = AR934X_RESET_GE0_MAC |
1025 AR934X_RESET_GE0_MDIO;
1026 pdata->set_speed = ar934x_set_speed_ge0;
1027 } else {
1028 pdata->reset_bit = AR934X_RESET_GE1_MAC |
1029 AR934X_RESET_GE1_MDIO;
1030 pdata->set_speed = ath79_set_speed_dummy;
1031
1032 pdata->switch_data = &ath79_switch_data;
1033
1034 /* reset the built-in switch */
1035 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
1036 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
1037 }
1038
1039 pdata->ddr_flush = ath79_ddr_no_flush;
1040 pdata->has_gbit = 1;
1041 pdata->is_ar724x = 1;
1042
1043 pdata->max_frame_len = SZ_16K - 1;
1044 pdata->desc_pktlen_mask = SZ_16K - 1;
1045
1046 if (!pdata->fifo_cfg1)
1047 pdata->fifo_cfg1 = 0x0010ffff;
1048 if (!pdata->fifo_cfg2)
1049 pdata->fifo_cfg2 = 0x015500aa;
1050 if (!pdata->fifo_cfg3)
1051 pdata->fifo_cfg3 = 0x01f00140;
1052 break;
1053
1054 case ATH79_SOC_TP9343:
1055 if (id == 0) {
1056 pdata->reset_bit = AR933X_RESET_GE0_MAC |
1057 AR933X_RESET_GE0_MDIO;
1058 pdata->set_speed = ath79_set_speed_dummy;
1059
1060 if (!pdata->phy_mask)
1061 pdata->phy_mask = BIT(4);
1062 } else {
1063 pdata->reset_bit = AR933X_RESET_GE1_MAC |
1064 AR933X_RESET_GE1_MDIO;
1065 pdata->set_speed = ath79_set_speed_dummy;
1066
1067 pdata->speed = SPEED_1000;
1068 pdata->duplex = DUPLEX_FULL;
1069 pdata->switch_data = &ath79_switch_data;
1070
1071 ath79_switch_data.phy_poll_mask |= BIT(4);
1072 }
1073
1074 pdata->ddr_flush = ath79_ddr_no_flush;
1075 pdata->has_gbit = 1;
1076 pdata->is_ar724x = 1;
1077
1078 if (!pdata->fifo_cfg1)
1079 pdata->fifo_cfg1 = 0x0010ffff;
1080 if (!pdata->fifo_cfg2)
1081 pdata->fifo_cfg2 = 0x015500aa;
1082 if (!pdata->fifo_cfg3)
1083 pdata->fifo_cfg3 = 0x01f00140;
1084 break;
1085
1086 case ATH79_SOC_QCA9556:
1087 case ATH79_SOC_QCA9558:
1088 if (id == 0) {
1089 pdata->reset_bit = QCA955X_RESET_GE0_MAC |
1090 QCA955X_RESET_GE0_MDIO;
1091 pdata->set_speed = qca955x_set_speed_xmii;
1092 } else {
1093 pdata->reset_bit = QCA955X_RESET_GE1_MAC |
1094 QCA955X_RESET_GE1_MDIO;
1095 pdata->set_speed = qca955x_set_speed_sgmii;
1096 }
1097
1098 pdata->ddr_flush = ath79_ddr_no_flush;
1099 pdata->has_gbit = 1;
1100 pdata->is_ar724x = 1;
1101
1102 /*
1103 * Limit the maximum frame length to 4095 bytes.
1104 * Although the documentation says that the hardware
1105 * limit is 16383 bytes but that does not work in
1106 * practice. It seems that the hardware only updates
1107 * the lowest 12 bits of the packet length field
1108 * in the RX descriptor.
1109 */
1110 pdata->max_frame_len = SZ_4K - 1;
1111 pdata->desc_pktlen_mask = SZ_16K - 1;
1112
1113 if (!pdata->fifo_cfg1)
1114 pdata->fifo_cfg1 = 0x0010ffff;
1115 if (!pdata->fifo_cfg2)
1116 pdata->fifo_cfg2 = 0x015500aa;
1117 if (!pdata->fifo_cfg3)
1118 pdata->fifo_cfg3 = 0x01f00140;
1119 break;
1120
1121 case ATH79_SOC_QCA956X:
1122 if (id == 0) {
1123 pdata->reset_bit = QCA955X_RESET_GE0_MAC |
1124 QCA955X_RESET_GE0_MDIO;
1125 if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
1126 pdata->set_speed = qca956x_set_speed_sgmii;
1127 else
1128 /* FIXME */
1129 pdata->set_speed = ath79_set_speed_dummy;
1130 } else {
1131 pdata->reset_bit = QCA955X_RESET_GE1_MAC |
1132 QCA955X_RESET_GE1_MDIO;
1133 /* FIXME */
1134 pdata->set_speed = ath79_set_speed_dummy;
1135 }
1136
1137 pdata->ddr_flush = ath79_ddr_no_flush;
1138 pdata->has_gbit = 1;
1139 pdata->is_ar724x = 1;
1140
1141 if (!pdata->fifo_cfg1)
1142 pdata->fifo_cfg1 = 0x0010ffff;
1143 if (!pdata->fifo_cfg2)
1144 pdata->fifo_cfg2 = 0x015500aa;
1145 if (!pdata->fifo_cfg3)
1146 pdata->fifo_cfg3 = 0x01f00140;
1147 break;
1148
1149 default:
1150 BUG();
1151 }
1152
1153 switch (pdata->phy_if_mode) {
1154 case PHY_INTERFACE_MODE_GMII:
1155 case PHY_INTERFACE_MODE_RGMII:
1156 case PHY_INTERFACE_MODE_SGMII:
1157 if (!pdata->has_gbit) {
1158 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
1159 id);
1160 return;
1161 }
1162 /* fallthrough */
1163 default:
1164 break;
1165 }
1166
1167 if (!is_valid_ether_addr(pdata->mac_addr)) {
1168 random_ether_addr(pdata->mac_addr);
1169 printk(KERN_DEBUG
1170 "ar71xx: using random MAC address for eth%d\n",
1171 ath79_eth_instance);
1172 }
1173
1174 if (pdata->mii_bus_dev == NULL) {
1175 switch (ath79_soc) {
1176 case ATH79_SOC_AR9341:
1177 case ATH79_SOC_AR9342:
1178 case ATH79_SOC_AR9344:
1179 if (id == 0)
1180 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1181 else
1182 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1183 break;
1184
1185 case ATH79_SOC_AR7241:
1186 case ATH79_SOC_AR9330:
1187 case ATH79_SOC_AR9331:
1188 case ATH79_SOC_QCA9533:
1189 case ATH79_SOC_TP9343:
1190 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1191 break;
1192
1193 case ATH79_SOC_QCA9556:
1194 case ATH79_SOC_QCA9558:
1195 /* don't assign any MDIO device by default */
1196 break;
1197
1198 default:
1199 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1200 break;
1201 }
1202 }
1203
1204 /* Reset the device */
1205 ath79_device_reset_set(pdata->reset_bit);
1206 msleep(100);
1207
1208 ath79_device_reset_clear(pdata->reset_bit);
1209 msleep(100);
1210
1211 platform_device_register(pdev);
1212 ath79_eth_instance++;
1213 }
1214
1215 void __init ath79_set_mac_base(unsigned char *mac)
1216 {
1217 memcpy(ath79_mac_base, mac, ETH_ALEN);
1218 }
1219
1220 void __init ath79_parse_ascii_mac(char *mac_str, u8 *mac)
1221 {
1222 int t;
1223
1224 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1225 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1226
1227 if (t != ETH_ALEN)
1228 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1229 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1230
1231 if (t != ETH_ALEN || !is_valid_ether_addr(mac)) {
1232 memset(mac, 0, ETH_ALEN);
1233 printk(KERN_DEBUG "ar71xx: invalid mac address \"%s\"\n",
1234 mac_str);
1235 }
1236 }
1237
1238 static void __init ath79_set_mac_base_ascii(char *str)
1239 {
1240 u8 mac[ETH_ALEN];
1241
1242 ath79_parse_ascii_mac(str, mac);
1243 ath79_set_mac_base(mac);
1244 }
1245
1246 static int __init ath79_ethaddr_setup(char *str)
1247 {
1248 ath79_set_mac_base_ascii(str);
1249 return 1;
1250 }
1251 __setup("ethaddr=", ath79_ethaddr_setup);
1252
1253 static int __init ath79_kmac_setup(char *str)
1254 {
1255 ath79_set_mac_base_ascii(str);
1256 return 1;
1257 }
1258 __setup("kmac=", ath79_kmac_setup);
1259
1260 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
1261 int offset)
1262 {
1263 int t;
1264
1265 if (!dst)
1266 return;
1267
1268 if (!src || !is_valid_ether_addr(src)) {
1269 memset(dst, '\0', ETH_ALEN);
1270 return;
1271 }
1272
1273 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1274 t += offset;
1275
1276 dst[0] = src[0];
1277 dst[1] = src[1];
1278 dst[2] = src[2];
1279 dst[3] = (t >> 16) & 0xff;
1280 dst[4] = (t >> 8) & 0xff;
1281 dst[5] = t & 0xff;
1282 }
1283
1284 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
1285 {
1286 int i;
1287
1288 if (!dst)
1289 return;
1290
1291 if (!src || !is_valid_ether_addr(src)) {
1292 memset(dst, '\0', ETH_ALEN);
1293 return;
1294 }
1295
1296 for (i = 0; i < ETH_ALEN; i++)
1297 dst[i] = src[i];
1298 dst[0] |= 0x02;
1299 }
John Crispins staging tree