target/linux/amazon-2.6/files/include/asm-mips/amazon/amazon_tpe.h

   1 #ifndef AMAZON_TPE_H
   2 #define AMAZON_TPE_H
   3 #include <linux/atm.h>
   4 #include <linux/atmdev.h>
   5 #include <linux/netdevice.h>
   6 #include <linux/ioctl.h>
   7
   8 #ifdef CONFIG_IFX_ATM_MIB
   9 /* For ATM-MIB lists */
  10 #include <linux/list.h>
  11 #endif
  12 #include <asm/amazon/atm_mib.h>
  13
  14 /* CBM Queue arranagement
  15  * Q0: free cells pool
  16  * Q1~ Q15: upstream queues
  17  * Q16: QAM downstream
  18  * Q17~Q31: downstream queues
  19  */
  20 #define AMAZON_ATM_MAX_QUEUE_NUM        32
  21 #define AMAZON_ATM_PORT_NUM             2
  22 #define AMAZON_ATM_FREE_CELLS           4000
  23 #define AMAZON_ATM_MAX_VCC_NUM          (AMAZON_ATM_MAX_QUEUE_NUM/2 - 1)
  24 #define AMAZON_AAL0_SDU                 (ATM_AAL0_SDU+4)                                //one more word for status
  25 #define CBM_RX_OFFSET                   16                                              //offset from the same q for tx
  26 #define AMAZON_ATM_OAM_Q_ID             16
  27 #define AMAZON_ATM_RM_Q_ID              16
  28 #define AMAZON_ATM_OTHER_Q_ID           16
  29 #define CBM_DEFAULT_Q_OFFSET            1
  30 #define HTUTIMEOUT                      0xffff//timeoutofhtutocbm
  31 #define QSB_WFQ_NONUBR_MAX              0x3f00
  32 #define QSB_WFQ_UBR_BYPASS              0x3fff
  33 #define QSB_TP_TS_MAX                   65472
  34 #define QSB_TAUS_MAX                    64512
  35 #define QSB_GCR_MIN                     18
  36 #define HTU_RAM_ACCESS_MAX              1024//maxium time for HTU RAM access
  37
  38 #define SWIE_LOCK               1
  39 #define PROC_ATM                1
  40 #define PROC_MIB                2
  41 #define PROC_VCC                3
  42 #define PROC_AAL5               4
  43 #define PROC_CBM                5
  44 #define PROC_HTU                6
  45 #define PROC_QSB                7
  46 #define PROC_SWIE               8
  47
  48 /***************** internal data structure ********************/
  49 typedef int (*push_back_t)(struct atm_vcc *vcc,struct sk_buff *skb,int err) ;
  50 /* Device private data */
  51 typedef struct{
  52         u8      padding_byte;
  53         u32     tx_max_sdu;
  54         u32     rx_max_sdu;
  55         u32     cnt_cpy;                //no. of packets that need a copy due to alignment
  56 }amazon_aal5_dev_t;
  57
  58 typedef struct{
  59         u32     max_q_off;              //maxium queues used in real scenario
  60         u32     nrt_thr;
  61         u32     clp0_thr;
  62         u32     clp1_thr;
  63         u32     free_cell_cnt;
  64 #ifdef CONFIG_USE_VENUS
  65         u8 *    qd_addr_free;   //to work around a bug, bit15 of QDOFF address should be 1
  66 #endif
  67         u8 *    qd_addr;
  68         u8 *    mem_addr;
  69         u8      allocated;
  70 }amazon_cbm_dev_t;
  71
  72 typedef struct{
  73
  74 }amazon_htu_dev_t;
  75
  76 typedef struct{
  77         u32     tau;                    //cell delay variation due to concurrency(?)
  78         u32     tstepc;                 //time step, all legal values are 1,2,4
  79         u32     sbl;                    //scheduler burse length (for PHY)
  80 }amazon_qsb_dev_t;
  81
  82 typedef struct{
  83         u32     qid;                    //QID of the current extraction queue
  84         struct semaphore in_sem;        // Software-Insertion semaphore
  85         volatile long   lock;           //lock that avoids race contions between SWIN and SWEX
  86         wait_queue_head_t sleep;        //wait queue for SWIE and SWEX
  87         u32 sw;                 //status word
  88 }amazon_swie_dev_t;
  89
  90 //AAL5 MIB Counter
  91 typedef struct{
  92         u32     tx,rx;                  //number AAL5 CPCS PDU from/to higher-layer
  93         u32     tx_err,rx_err;          //ifInErrors and ifOutErros
  94         u32     tx_drop,rx_drop;        //discarded received packets due to mm shortage
  95         u32     htu_unp;                //number of unknown received cells
  96         u32     rx_cnt_h;               //number of octets received, high 32 bits
  97         u32     rx_cnt_l;               //number of octets received, low 32 bits
  98         u32     tx_cnt_h;               //number of octets transmitted, high 32 bits
  99         u32     tx_cnt_l;               //number of octets transmitted, low 32 bits
 100         u32     tx_ppd;                 //number of cells for AAL5 upstream PPD discards
 101         u64     rx_cells;               //number of cells for downstream
 102         u64     tx_cells;               //number of cells for upstream
 103         u32     rx_err_cells;           //number of cells dropped due to uncorrectable HEC errors
 104 }amazon_mib_counter_t;
 105
 106
 107
 108 typedef enum {QS_PKT,QS_LEN,QS_ERR,QS_HW_DROP,QS_SW_DROP,QS_MAX} qs_t;
 109 //queue statics no. of packet received / sent
 110 //queue statics no. of bytes received / sent
 111 //queue statics no. of packets with error
 112 //queue statics no. of packets dropped by hw
 113 //queue statics no. of packets dropped by sw
 114
 115 typedef struct{
 116         push_back_t push;               //call back function
 117         struct atm_vcc * vcc;           //opened vcc
 118         struct timeval access_time;     //time when last F4/F5 user cells arrive
 119         int     free;                   //whether this queue is occupied, 0: occupied, 1: free
 120         u32     aal5VccCrcErrors;       //MIB counter
 121         u32     aal5VccOverSizedSDUs;   //MIB counter
 122
 123 #if defined(AMAZON_ATM_DEBUG) || defined (CONFIG_IFX_ATM_MIB)
 124         u32     qs[QS_MAX];
 125 #endif
 126 }amazon_atm_queue_t;
 127
 128
 129 typedef struct{
 130         int     enable;         //enable / disable
 131         u32     max_conn;       //maximum number of connections per port
 132         u32     tx_max_cr;      //Remaining cellrate for this device for tx direction
 133         u32     tx_rem_cr;      //Remaining cellrate for this device for tx direction
 134         u32     tx_cur_cr;      //Current cellrate for this device for tx direction
 135 }amazon_atm_port_t;
 136
 137 typedef struct{
 138         amazon_aal5_dev_t       aal5;
 139         amazon_cbm_dev_t        cbm;
 140         amazon_htu_dev_t        htu;
 141         amazon_qsb_dev_t        qsb;
 142         amazon_swie_dev_t       swie;
 143         amazon_mib_counter_t    mib_counter;
 144         amazon_atm_queue_t      queues[AMAZON_ATM_MAX_QUEUE_NUM];
 145         amazon_atm_port_t       ports[AMAZON_ATM_PORT_NUM];
 146         atomic_t                dma_tx_free_0;//TX_CH0 has availabe descriptors
 147 } amazon_atm_dev_t;
 148
 149 struct oam_last_activity{
 150         u8                      vpi;    //vpi for this connection
 151         u16                     vci;    //vci for t his connection
 152         struct timeval          stamp;  //time when last F4/F5 user cells arrive
 153         struct oam_last_activity * next;//for link list purpose
 154 };
 155
 156 typedef union{
 157 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 158         struct{
 159                 u32     tprs            :16;
 160                 u32     twfq            :14;
 161                 u32     vbr             :1;
 162                 u32     reserved        :1;
 163         }bit;
 164         u32 w0;
 165 #else
 166         struct{
 167                 u32     reserved        :1;
 168                 u32     vbr             :1;
 169                 u32     twfq            :14;
 170                 u32     tprs            :16;
 171         }bit;
 172         u32 w0;
 173 #endif
 174
 175 }qsb_qptl_t;
 176
 177 typedef union{
 178 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 179         struct{
 180                 u32     ts              :16;
 181                 u32     taus            :16;
 182         }bit;
 183         u32 w0;
 184 #else
 185         struct{
 186                 u32     taus            :16;
 187                 u32     ts              :16;
 188         }bit;
 189         u32 w0;
 190 #endif
 191 }qsb_qvpt_t;
 192
 193
 194
 195 struct amazon_atm_cell_header {
 196 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 197         struct{
 198                 u32 clp         :1;     // Cell Loss Priority
 199                 u32 pti         :3;     // Payload Type Identifier
 200                 u32 vci         :16;    // Virtual Channel Identifier
 201                 u32 vpi         :8;     // Vitual Path Identifier
 202                 u32 gfc         :4;     // Generic Flow Control
 203                 }bit;
 204 #else
 205         struct{
 206                 u32 gfc         :4;     // Generic Flow Control
 207                 u32 vpi         :8;     // Vitual Path Identifier
 208                 u32 vci         :16;    // Virtual Channel Identifier
 209                 u32 pti         :3;     // Payload Type Identifier
 210                 u32 clp         :1;     // Cell Loss Priority
 211                 }bit;
 212 #endif
 213 };
 214
 215
 216 /************************ Function Declarations **************************/
 217 amazon_atm_dev_t *      amazon_atm_create(void);
 218 int     amazon_atm_open(struct atm_vcc *vcc,push_back_t);
 219 int     amazon_atm_send(struct atm_vcc *vcc,struct sk_buff *skb);
 220 int     amazon_atm_send_oam(struct atm_vcc *vcc,void *cell, int flags);
 221 void    amazon_atm_close(struct atm_vcc *vcc);
 222 void    amazon_atm_cleanup(void);
 223 const struct oam_last_activity* get_oam_time_stamp(void);
 224
 225 //mib-related
 226 int amazon_atm_cell_mib(atm_cell_ifEntry_t * to,u32 itf);
 227 int amazon_atm_aal5_mib(atm_aal5_ifEntry_t * to);
 228 int amazon_atm_vcc_mib(struct atm_vcc *vcc,atm_aal5_vcc_t * to);
 229 int amazon_atm_vcc_mib_x(int vpi, int vci,atm_aal5_vcc_t* to);
 230
 231 #define AMAZON_WRITE_REGISTER_L(data,addr)      do{ *((volatile u32*)(addr)) = (u32)(data); wmb();} while (0)
 232 #define AMAZON_READ_REGISTER_L(addr)    (*((volatile u32*)(addr)))
 233 /******************************* ioctl stuff****************************************/
 234 #define NUM(dev)    (MINOR(dev) & 0xf)
 235 /*
 236  * Ioctl definitions
 237  */
 238 /* Use 'o' as magic number */
 239 #define AMAZON_ATM_IOC_MAGIC  'o'
 240 /* MIB_CELL: get atm cell level mib counter
 241  * MIB_AAL5: get aal5 mib counter
 242  * MIB_VCC: get vcc mib counter
 243  */
 244 typedef struct{
 245         int vpi;
 246         int vci;
 247         atm_aal5_vcc_t mib_vcc;
 248 }atm_aal5_vcc_x_t;
 249 #define AMAZON_ATM_MIB_CELL             _IOWR(AMAZON_ATM_IOC_MAGIC,  0, atm_cell_ifEntry_t)
 250 #define AMAZON_ATM_MIB_AAL5             _IOWR(AMAZON_ATM_IOC_MAGIC,  1, atm_aal5_ifEntry_t)
 251 #define AMAZON_ATM_MIB_VCC              _IOWR(AMAZON_ATM_IOC_MAGIC,  2, atm_aal5_vcc_x_t)
 252 #define AMAZON_ATM_IOC_MAXNR    3
 253
 254 //sockopt
 255 #define SO_AMAZON_ATM_MIB_VCC           __SO_ENCODE(SOL_ATM,5,atm_aal5_vcc_t)
 256
 257 #endif // AMAZON_TPE_H
 258