1 --- a/drivers/spi/Kconfig
2 +++ b/drivers/spi/Kconfig
3 @@ -307,6 +307,12 @@ config SPI_DLN2
4 This driver can also be built as a module. If so, the module
5 will be called spi-dln2.
7 +config SPI_AIROHA_EN7523
8 + bool "Airoha EN7523 SPI controller support"
9 + depends on ARCH_AIROHA
11 + This enables SPI controller support for the Airoha EN7523 SoC.
14 tristate "Cirrus Logic EP93xx SPI controller"
15 depends on ARCH_EP93XX || COMPILE_TEST
16 --- a/drivers/spi/Makefile
17 +++ b/drivers/spi/Makefile
18 @@ -45,6 +45,7 @@ obj-$(CONFIG_SPI_DW_BT1) += spi-dw-bt1.
19 obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
20 obj-$(CONFIG_SPI_DW_PCI) += spi-dw-pci.o
21 obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o
22 +obj-$(CONFIG_SPI_AIROHA_EN7523) += spi-en7523.o
23 obj-$(CONFIG_SPI_FALCON) += spi-falcon.o
24 obj-$(CONFIG_SPI_FSI) += spi-fsi.o
25 obj-$(CONFIG_SPI_FSL_CPM) += spi-fsl-cpm.o
27 +++ b/drivers/spi/spi-en7523.c
29 +// SPDX-License-Identifier: GPL-2.0
31 +#include <linux/module.h>
32 +#include <linux/platform_device.h>
33 +#include <linux/mod_devicetable.h>
34 +#include <linux/spi/spi.h>
37 +#define ENSPI_READ_IDLE_EN 0x0004
38 +#define ENSPI_MTX_MODE_TOG 0x0014
39 +#define ENSPI_RDCTL_FSM 0x0018
40 +#define ENSPI_MANUAL_EN 0x0020
41 +#define ENSPI_MANUAL_OPFIFO_EMPTY 0x0024
42 +#define ENSPI_MANUAL_OPFIFO_WDATA 0x0028
43 +#define ENSPI_MANUAL_OPFIFO_FULL 0x002C
44 +#define ENSPI_MANUAL_OPFIFO_WR 0x0030
45 +#define ENSPI_MANUAL_DFIFO_FULL 0x0034
46 +#define ENSPI_MANUAL_DFIFO_WDATA 0x0038
47 +#define ENSPI_MANUAL_DFIFO_EMPTY 0x003C
48 +#define ENSPI_MANUAL_DFIFO_RD 0x0040
49 +#define ENSPI_MANUAL_DFIFO_RDATA 0x0044
50 +#define ENSPI_IER 0x0090
51 +#define ENSPI_NFI2SPI_EN 0x0130
53 +// TODO not in spi block
54 +#define ENSPI_CLOCK_DIVIDER ((void __iomem *)0x1fa201c4)
66 +#define OP_OS2IS 0x10
67 +#define OP_OS2ID 0x11
68 +#define OP_OS2IQ 0x12
69 +#define OP_OD2IS 0x13
70 +#define OP_OD2ID 0x14
71 +#define OP_OD2IQ 0x15
72 +#define OP_OQ2IS 0x16
73 +#define OP_OQ2ID 0x17
74 +#define OP_OQ2IQ 0x18
75 +#define OP_OSNIS 0x19
76 +#define OP_ODNID 0x1A
78 +#define MATRIX_MODE_AUTO 1
79 +#define CONF_MTX_MODE_AUTO 0
80 +#define MANUALEN_AUTO 0
81 +#define MATRIX_MODE_MANUAL 0
82 +#define CONF_MTX_MODE_MANUAL 9
83 +#define MANUALEN_MANUAL 1
85 +#define _ENSPI_MAX_XFER 0x1ff
87 +#define REG(x) (iobase + x)
90 +static void __iomem *iobase;
93 +static void opfifo_write(u32 cmd, u32 len)
95 + u32 tmp = ((cmd & 0x1f) << 9) | (len & 0x1ff);
97 + writel(tmp, REG(ENSPI_MANUAL_OPFIFO_WDATA));
99 + /* Wait for room in OPFIFO */
100 + while (readl(REG(ENSPI_MANUAL_OPFIFO_FULL)))
103 + /* Shift command into OPFIFO */
104 + writel(1, REG(ENSPI_MANUAL_OPFIFO_WR));
106 + /* Wait for command to finish */
107 + while (!readl(REG(ENSPI_MANUAL_OPFIFO_EMPTY)))
111 +static void set_cs(int state)
114 + opfifo_write(OP_CSH, 1);
116 + opfifo_write(OP_CSL, 1);
119 +static void manual_begin_cmd(void)
121 + /* Disable read idle state */
122 + writel(0, REG(ENSPI_READ_IDLE_EN));
124 + /* Wait for FSM to reach idle state */
125 + while (readl(REG(ENSPI_RDCTL_FSM)))
128 + /* Set SPI core to manual mode */
129 + writel(CONF_MTX_MODE_MANUAL, REG(ENSPI_MTX_MODE_TOG));
130 + writel(MANUALEN_MANUAL, REG(ENSPI_MANUAL_EN));
133 +static void manual_end_cmd(void)
135 + /* Set SPI core to auto mode */
136 + writel(CONF_MTX_MODE_AUTO, REG(ENSPI_MTX_MODE_TOG));
137 + writel(MANUALEN_AUTO, REG(ENSPI_MANUAL_EN));
139 + /* Enable read idle state */
140 + writel(1, REG(ENSPI_READ_IDLE_EN));
143 +static void dfifo_read(u8 *buf, int len)
147 + for (i = 0; i < len; i++) {
148 + /* Wait for requested data to show up in DFIFO */
149 + while (readl(REG(ENSPI_MANUAL_DFIFO_EMPTY)))
151 + buf[i] = readl(REG(ENSPI_MANUAL_DFIFO_RDATA));
152 + /* Queue up next byte */
153 + writel(1, REG(ENSPI_MANUAL_DFIFO_RD));
157 +static void dfifo_write(const u8 *buf, int len)
161 + for (i = 0; i < len; i++) {
162 + /* Wait for room in DFIFO */
163 + while (readl(REG(ENSPI_MANUAL_DFIFO_FULL)))
165 + writel(buf[i], REG(ENSPI_MANUAL_DFIFO_WDATA));
170 +static void set_spi_clock_speed(int freq_mhz)
174 + tmp = readl(ENSPI_CLOCK_DIVIDER);
176 + writel(tmp, ENSPI_CLOCK_DIVIDER);
178 + val = (400 / (freq_mhz * 2));
179 + tmp |= (val << 8) | 1;
180 + writel(tmp, ENSPI_CLOCK_DIVIDER);
184 +static void init_hw(void)
186 + /* Disable manual/auto mode clash interrupt */
187 + writel(0, REG(ENSPI_IER));
189 + // TODO via clk framework
190 + // set_spi_clock_speed(50);
193 + writel(0, REG(ENSPI_NFI2SPI_EN));
196 +static int xfer_read(struct spi_transfer *xfer)
199 + uint8_t *buf = xfer->rx_buf;
201 + switch (xfer->rx_nbits) {
202 + case SPI_NBITS_SINGLE:
205 + case SPI_NBITS_DUAL:
208 + case SPI_NBITS_QUAD:
213 + opfifo_write(opcode, xfer->len);
214 + dfifo_read(buf, xfer->len);
219 +static int xfer_write(struct spi_transfer *xfer, int next_xfer_is_rx)
222 + const uint8_t *buf = xfer->tx_buf;
224 + if (next_xfer_is_rx) {
225 + /* need to use Ox2Ix opcode to set the core to input afterwards */
226 + switch (xfer->tx_nbits) {
227 + case SPI_NBITS_SINGLE:
230 + case SPI_NBITS_DUAL:
233 + case SPI_NBITS_QUAD:
238 + switch (xfer->tx_nbits) {
239 + case SPI_NBITS_SINGLE:
242 + case SPI_NBITS_DUAL:
245 + case SPI_NBITS_QUAD:
251 + opfifo_write(opcode, xfer->len);
252 + dfifo_write(buf, xfer->len);
257 +size_t max_transfer_size(struct spi_device *spi)
259 + return _ENSPI_MAX_XFER;
262 +int transfer_one_message(struct spi_controller *ctrl, struct spi_message *msg)
264 + struct spi_transfer *xfer;
265 + int next_xfer_is_rx = 0;
267 + manual_begin_cmd();
269 + list_for_each_entry(xfer, &msg->transfers, transfer_list) {
270 + if (xfer->tx_buf) {
271 + if (!list_is_last(&xfer->transfer_list, &msg->transfers)
272 + && list_next_entry(xfer, transfer_list)->rx_buf != NULL)
273 + next_xfer_is_rx = 1;
275 + next_xfer_is_rx = 0;
276 + msg->actual_length += xfer_write(xfer, next_xfer_is_rx);
277 + } else if (xfer->rx_buf) {
278 + msg->actual_length += xfer_read(xfer);
285 + spi_finalize_current_message(ctrl);
290 +static int spi_probe(struct platform_device *pdev)
292 + struct spi_controller *ctrl;
295 + ctrl = devm_spi_alloc_master(&pdev->dev, 0);
297 + dev_err(&pdev->dev, "Error allocating SPI controller\n");
301 + iobase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
302 + if (IS_ERR(iobase)) {
303 + dev_err(&pdev->dev, "Could not map SPI register address");
309 + ctrl->dev.of_node = pdev->dev.of_node;
310 + ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX;
311 + ctrl->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL;
312 + ctrl->max_transfer_size = max_transfer_size;
313 + ctrl->transfer_one_message = transfer_one_message;
314 + err = devm_spi_register_controller(&pdev->dev, ctrl);
316 + dev_err(&pdev->dev, "Could not register SPI controller\n");
323 +static const struct of_device_id spi_of_ids[] = {
324 + { .compatible = "airoha,en7523-spi" },
327 +MODULE_DEVICE_TABLE(of, spi_of_ids);
329 +static struct platform_driver spi_driver = {
330 + .probe = spi_probe,
332 + .name = "airoha-en7523-spi",
333 + .of_match_table = spi_of_ids,
337 +module_platform_driver(spi_driver);
339 +MODULE_LICENSE("GPL v2");
340 +MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
341 +MODULE_DESCRIPTION("Airoha EN7523 SPI driver");