plat/rpi/rpi4/rpi4_bl31_setup.c

   1 /*
   2  * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <assert.h>
   8
   9 #include <libfdt.h>
  10
  11 #include <platform_def.h>
  12 #include <common/bl_common.h>
  13 #include <lib/mmio.h>
  14 #include <lib/xlat_tables/xlat_mmu_helpers.h>
  15 #include <lib/xlat_tables/xlat_tables_defs.h>
  16 #include <plat/common/platform.h>
  17
  18 #include <drivers/arm/gicv2.h>
  19
  20 #include <rpi_shared.h>
  21
  22 static const gicv2_driver_data_t rpi4_gic_data = {
  23         .gicd_base = RPI4_GIC_GICD_BASE,
  24         .gicc_base = RPI4_GIC_GICC_BASE,
  25 };
  26
  27 /*
  28  * To be filled by the code below. At the moment BL32 is not supported.
  29  * In the future these might be passed down from BL2.
  30  */
  31 static entry_point_info_t bl32_image_ep_info;
  32 static entry_point_info_t bl33_image_ep_info;
  33
  34 /*******************************************************************************
  35  * Return a pointer to the 'entry_point_info' structure of the next image for
  36  * the security state specified. BL33 corresponds to the non-secure image type
  37  * while BL32 corresponds to the secure image type. A NULL pointer is returned
  38  * if the image does not exist.
  39  ******************************************************************************/
  40 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
  41 {
  42         entry_point_info_t *next_image_info;
  43
  44         assert(sec_state_is_valid(type) != 0);
  45
  46         next_image_info = (type == NON_SECURE)
  47                         ? &bl33_image_ep_info : &bl32_image_ep_info;
  48
  49         /* None of the images can have 0x0 as the entrypoint. */
  50         if (next_image_info->pc) {
  51                 return next_image_info;
  52         } else {
  53                 return NULL;
  54         }
  55 }
  56
  57 static void ldelay(register_t delay)
  58 {
  59         __asm__ volatile (
  60                 "1:\tcbz %0, 2f\n\t"
  61                 "sub %0, %0, #1\n\t"
  62                 "b 1b\n"
  63                 "2:"
  64                 : "=&r" (delay) : "0" (delay)
  65         );
  66 }
  67
  68 /*******************************************************************************
  69  * Perform any BL31 early platform setup. Here is an opportunity to copy
  70  * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before
  71  * they are lost (potentially). This needs to be done before the MMU is
  72  * initialized so that the memory layout can be used while creating page
  73  * tables. BL2 has flushed this information to memory, so we are guaranteed
  74  * to pick up good data.
  75  ******************************************************************************/
  76 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
  77                                 u_register_t arg2, u_register_t arg3)
  78
  79 {
  80         uint32_t div_reg;
  81
  82         /*
  83          * LOCAL_CONTROL:
  84          * Bit 9 clear: Increment by 1 (vs. 2).
  85          * Bit 8 clear: Timer source is 19.2MHz crystal (vs. APB).
  86          */
  87         mmio_write_32(RPI4_LOCAL_CONTROL_BASE_ADDRESS, 0);
  88
  89         /* LOCAL_PRESCALER; divide-by (0x80000000 / register_val) == 1 */
  90         mmio_write_32(RPI4_LOCAL_CONTROL_PRESCALER, 0x80000000);
  91
  92         /* Early GPU firmware revisions need a little break here. */
  93         ldelay(100000);
  94
  95         /*
  96          * Initialize the console to provide early debug support.
  97          * Different GPU firmware revisions set up the VPU divider differently,
  98          * so read the actual divider register to learn the UART base clock
  99          * rate. The divider is encoded as a 12.12 fixed point number, but we
 100          * just care about the integer part of it.
 101          */
 102         div_reg = mmio_read_32(RPI4_CLOCK_BASE + RPI4_VPU_CLOCK_DIVIDER);
 103         div_reg = (div_reg >> 12) & 0xfff;
 104         if (div_reg == 0)
 105                 div_reg = 1;
 106         rpi3_console_init(PLAT_RPI4_VPU_CLK_RATE / div_reg);
 107
 108 #if RPI3_DIRECT_LINUX_BOOT
 109         bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
 110         bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
 111                                           DISABLE_ALL_EXCEPTIONS);
 112         SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
 113
 114 # if RPI3_BL33_IN_AARCH32
 115         /*
 116          * According to the file ``Documentation/arm/Booting`` of the Linux
 117          * kernel tree, Linux expects:
 118          * r0 = 0
 119          * r1 = machine type number, optional in DT-only platforms (~0 if so)
 120          * r2 = Physical address of the device tree blob
 121          */
 122         VERBOSE("rpi4: Preparing to boot 32-bit Linux kernel\n");
 123         bl33_image_ep_info.args.arg0 = 0U;
 124         bl33_image_ep_info.args.arg1 = ~0U;
 125         bl33_image_ep_info.args.arg2 = (u_register_t) RPI3_PRELOADED_DTB_BASE;
 126 # else
 127         /*
 128          * According to the file ``Documentation/arm64/booting.txt`` of the
 129          * Linux kernel tree, Linux expects the physical address of the device
 130          * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
 131          * must be 0.
 132          */
 133         VERBOSE("rpi4: Preparing to boot 64-bit Linux kernel\n");
 134         bl33_image_ep_info.args.arg0 = (u_register_t) RPI3_PRELOADED_DTB_BASE;
 135         bl33_image_ep_info.args.arg1 = 0ULL;
 136         bl33_image_ep_info.args.arg2 = 0ULL;
 137         bl33_image_ep_info.args.arg3 = 0ULL;
 138 # endif /* RPI3_BL33_IN_AARCH32 */
 139 #endif /* RPI3_DIRECT_LINUX_BOOT */
 140 }
 141
 142 void bl31_plat_arch_setup(void)
 143 {
 144         rpi3_setup_page_tables(BL31_BASE, BL31_END - BL31_BASE,
 145                                BL_CODE_BASE, BL_CODE_END,
 146                                BL_RO_DATA_BASE, BL_RO_DATA_END
 147 #if USE_COHERENT_MEM
 148                                , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END
 149 #endif
 150                               );
 151
 152         enable_mmu_el3(0);
 153 }
 154
 155 void bl31_platform_setup(void)
 156 {
 157         /* Configure the interrupt controller */
 158         gicv2_driver_init(&rpi4_gic_data);
 159         gicv2_distif_init();
 160         gicv2_pcpu_distif_init();
 161         gicv2_cpuif_enable();
 162 }