plat/amlogic/g12a/g12a_def.h

   1 /*
   2  * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef G12A_DEF_H
   8 #define G12A_DEF_H
   9
  10 #include <lib/utils_def.h>
  11
  12 /*******************************************************************************
  13  * System oscillator
  14  ******************************************************************************/
  15 #define AML_OSC24M_CLK_IN_HZ                    ULL(24000000) /* 24 MHz */
  16
  17 /*******************************************************************************
  18  * Memory regions
  19  ******************************************************************************/
  20 #define AML_HDCP_RX_BASE                        UL(0xFFE0D000)
  21 #define AML_HDCP_RX_SIZE                        UL(0x00002000)
  22
  23 #define AML_HDCP_TX_BASE                        UL(0xFFE01000)
  24 #define AML_HDCP_TX_SIZE                        UL(0x00001000)
  25
  26 #define AML_NS_SHARE_MEM_BASE                   UL(0x05000000)
  27 #define AML_NS_SHARE_MEM_SIZE                   UL(0x00100000)
  28
  29 #define AML_SEC_SHARE_MEM_BASE                  UL(0x05200000)
  30 #define AML_SEC_SHARE_MEM_SIZE                  UL(0x00100000)
  31
  32 #define AML_GIC_DEVICE_BASE                     UL(0xFFC00000)
  33 #define AML_GIC_DEVICE_SIZE                     UL(0x00008000)
  34
  35 #define AML_NSDRAM0_BASE                        UL(0x01000000)
  36 #define AML_NSDRAM0_SIZE                        UL(0x0F000000)
  37
  38 #define BL31_BASE                               UL(0x05100000)
  39 #define BL31_SIZE                               UL(0x00100000)
  40 #define BL31_LIMIT                              (BL31_BASE + BL31_SIZE)
  41
  42 /* Shared memory used for SMC services */
  43 #define AML_SHARE_MEM_INPUT_BASE                UL(0x050FE000)
  44 #define AML_SHARE_MEM_OUTPUT_BASE               UL(0x050FF000)
  45
  46 #define AML_SEC_DEVICE0_BASE                    UL(0xFFD00000)
  47 #define AML_SEC_DEVICE0_SIZE                    UL(0x00026000)
  48
  49 #define AML_SEC_DEVICE1_BASE                    UL(0xFF800000)
  50 #define AML_SEC_DEVICE1_SIZE                    UL(0x0000A000)
  51
  52 #define AML_TZRAM_BASE                          UL(0xFFFA0000)
  53 #define AML_TZRAM_SIZE                          UL(0x00048000)
  54
  55 /* Mailboxes */
  56 #define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD        UL(0xFFFE7800)
  57 #define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD        UL(0xFFFE7A00)
  58 #define AML_PSCI_MAILBOX_BASE                   UL(0xFFFE7F00)
  59
  60 #define AML_SEC_DEVICE2_BASE                    UL(0xFF620000)
  61 #define AML_SEC_DEVICE2_SIZE                    UL(0x00028000)
  62
  63 /*******************************************************************************
  64  * GIC-400 and interrupt handling related constants
  65  ******************************************************************************/
  66 #define AML_GICD_BASE                           UL(0xFFC01000)
  67 #define AML_GICC_BASE                           UL(0xFFC02000)
  68
  69 #define IRQ_SEC_PHY_TIMER                       29
  70
  71 #define IRQ_SEC_SGI_0                           8
  72 #define IRQ_SEC_SGI_1                           9
  73 #define IRQ_SEC_SGI_2                           10
  74 #define IRQ_SEC_SGI_3                           11
  75 #define IRQ_SEC_SGI_4                           12
  76 #define IRQ_SEC_SGI_5                           13
  77 #define IRQ_SEC_SGI_6                           14
  78 #define IRQ_SEC_SGI_7                           15
  79 #define IRQ_SEC_SGI_8                           16
  80
  81 /*******************************************************************************
  82  * UART definitions
  83  ******************************************************************************/
  84 #define AML_UART0_AO_BASE                       UL(0xFF803000)
  85 #define AML_UART0_AO_CLK_IN_HZ                  AML_OSC24M_CLK_IN_HZ
  86 #define AML_UART_BAUDRATE                       U(115200)
  87
  88 /*******************************************************************************
  89  * Memory-mapped I/O Registers
  90  ******************************************************************************/
  91 #define AML_AO_TIMESTAMP_CNTL                   UL(0xFF8000B4)
  92
  93 #define AML_SYS_CPU_CFG7                        UL(0xFF634664)
  94
  95 #define AML_AO_RTI_STATUS_REG3                  UL(0xFF80001C)
  96 #define AML_AO_RTI_SCP_STAT                     UL(0xFF80023C)
  97 #define AML_AO_RTI_SCP_READY_OFF                U(0x14)
  98 #define AML_A0_RTI_SCP_READY_MASK               U(3)
  99 #define AML_AO_RTI_SCP_IS_READY(v)                                      \
 100         ((((v) >> AML_AO_RTI_SCP_READY_OFF) &                           \
 101         AML_A0_RTI_SCP_READY_MASK) == AML_A0_RTI_SCP_READY_MASK)
 102
 103 #define AML_HIU_MAILBOX_SET_0                   UL(0xFF63C404)
 104 #define AML_HIU_MAILBOX_STAT_0                  UL(0xFF63C408)
 105 #define AML_HIU_MAILBOX_CLR_0                   UL(0xFF63C40C)
 106 #define AML_HIU_MAILBOX_SET_3                   UL(0xFF63C428)
 107 #define AML_HIU_MAILBOX_STAT_3                  UL(0xFF63C42C)
 108 #define AML_HIU_MAILBOX_CLR_3                   UL(0xFF63C430)
 109
 110 #define AML_SHA_DMA_BASE                        UL(0xFF63E000)
 111 #define AML_SHA_DMA_DESC                        (AML_SHA_DMA_BASE + 0x08)
 112 #define AML_SHA_DMA_STATUS                      (AML_SHA_DMA_BASE + 0x28)
 113
 114 /*******************************************************************************
 115  * System Monitor Call IDs and arguments
 116  ******************************************************************************/
 117 #define AML_SM_GET_SHARE_MEM_INPUT_BASE         U(0x82000020)
 118 #define AML_SM_GET_SHARE_MEM_OUTPUT_BASE        U(0x82000021)
 119
 120 #define AML_SM_EFUSE_READ                       U(0x82000030)
 121 #define AML_SM_EFUSE_USER_MAX                   U(0x82000033)
 122
 123 #define AML_SM_JTAG_ON                          U(0x82000040)
 124 #define AML_SM_JTAG_OFF                         U(0x82000041)
 125 #define AML_SM_GET_CHIP_ID                      U(0x82000044)
 126
 127 #define AML_JTAG_STATE_ON                       U(0)
 128 #define AML_JTAG_STATE_OFF                      U(1)
 129
 130 #define AML_JTAG_M3_AO                          U(0)
 131 #define AML_JTAG_M3_EE                          U(1)
 132 #define AML_JTAG_A53_AO                         U(2)
 133 #define AML_JTAG_A53_EE                         U(3)
 134
 135 #endif /* G12A_DEF_H */