projects / openwrt / staging / noltari.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
mac80211: clean and submit a bunch of rt2x00 patches
[openwrt/staging/noltari.git] / package / kernel / mac80211 / patches / rt2x00 / 985-rt2x00-add-RXIQ-calibration.patch
1 From 38b78ba60f6759968b19fe183a344a8612fef694 Mon Sep 17 00:00:00 2001
2 From: Daniel Golle <daniel@makrotopia.org>
3 Date: Mon, 8 Jan 2018 13:43:56 +0100
4 Subject: [PATCH 07/16] rt2x00: add RXIQ calibration for MT7620
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8 To: linux-wireless@vger.kernel.org,
9 Stanislaw Gruszka <stf_xl@wp.pl>,
10 Helmut Schaa <helmut.schaa@googlemail.com>
11 Cc: Kalle Valo <kvalo@kernel.org>,
12 David S. Miller <davem@davemloft.net>,
13 Eric Dumazet <edumazet@google.com>,
14 Jakub Kicinski <kuba@kernel.org>,
15 Paolo Abeni <pabeni@redhat.com>,
16 Johannes Berg <johannes.berg@intel.com>
17
18 From: Tomislav Požega <pozega.tomislav@gmail.com>
19
20 Add RXIQ calibration found in mtk driver. With old openwrt builds this
21 gets us ~8Mbps more of RX bandwidth (test with iPA/eLNA layout).
22
23 Signed-off-by: Tomislav Požega <pozega.tomislav@gmail.com>
24 ---
25 .../net/wireless/ralink/rt2x00/rt2800lib.c | 384 ++++++++++++++++++
26 1 file changed, 384 insertions(+)
27
28 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
29 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
30 @@ -8696,6 +8696,389 @@ static void rt2800_rxdcoc_calibration(st
31 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, saverfb0r2);
32 }
33
34 +static u32 rt2800_do_sqrt_accumulation(u32 si)
35 +{
36 + u32 root, root_pre, bit;
37 + char i;
38 +
39 + bit = 1 << 15;
40 + root = 0;
41 + for (i = 15; i >= 0; i = i - 1) {
42 + root_pre = root + bit;
43 + if ((root_pre * root_pre) <= si)
44 + root = root_pre;
45 + bit = bit >> 1;
46 + }
47 +
48 + return root;
49 +}
50 +
51 +static void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev)
52 +{
53 + u8 rfb0r1, rfb0r2, rfb0r42;
54 + u8 rfb4r0, rfb4r19;
55 + u8 rfb5r3, rfb5r4, rfb5r17, rfb5r18, rfb5r19, rfb5r20;
56 + u8 rfb6r0, rfb6r19;
57 + u8 rfb7r3, rfb7r4, rfb7r17, rfb7r18, rfb7r19, rfb7r20;
58 +
59 + u8 bbp1, bbp4;
60 + u8 bbpr241, bbpr242;
61 + u32 i;
62 + u8 ch_idx;
63 + u8 bbpval;
64 + u8 rfval, vga_idx = 0;
65 + int mi = 0, mq = 0, si = 0, sq = 0, riq = 0;
66 + int sigma_i, sigma_q, r_iq, g_rx;
67 + int g_imb;
68 + int ph_rx;
69 + u32 savemacsysctrl = 0;
70 + u32 orig_RF_CONTROL0 = 0;
71 + u32 orig_RF_BYPASS0 = 0;
72 + u32 orig_RF_CONTROL1 = 0;
73 + u32 orig_RF_BYPASS1 = 0;
74 + u32 orig_RF_CONTROL3 = 0;
75 + u32 orig_RF_BYPASS3 = 0;
76 + u32 macstatus, bbpval1 = 0;
77 + u8 rf_vga_table[] = {0x20, 0x21, 0x22, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f};
78 +
79 + savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
80 + orig_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
81 + orig_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
82 + orig_RF_CONTROL1 = rt2800_register_read(rt2x00dev, RF_CONTROL1);
83 + orig_RF_BYPASS1 = rt2800_register_read(rt2x00dev, RF_BYPASS1);
84 + orig_RF_CONTROL3 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
85 + orig_RF_BYPASS3 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
86 +
87 + bbp1 = rt2800_bbp_read(rt2x00dev, 1);
88 + bbp4 = rt2800_bbp_read(rt2x00dev, 4);
89 +
90 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x0);
91 +
92 + for (i = 0; i < 10000; i++) {
93 + macstatus = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
94 + if (macstatus & 0x3)
95 + usleep_range(50, 100);
96 + else
97 + break;
98 + }
99 +
100 + if (i == 10000)
101 + rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
102 +
103 + bbpval = bbp4 & (~0x18);
104 + bbpval = bbp4 | 0x00;
105 + rt2800_bbp_write(rt2x00dev, 4, bbpval);
106 +
107 + bbpval = rt2800_bbp_read(rt2x00dev, 21);
108 + bbpval = bbpval | 1;
109 + rt2800_bbp_write(rt2x00dev, 21, bbpval);
110 + bbpval = bbpval & 0xfe;
111 + rt2800_bbp_write(rt2x00dev, 21, bbpval);
112 +
113 + rt2800_register_write(rt2x00dev, RF_CONTROL1, 0x00000202);
114 + rt2800_register_write(rt2x00dev, RF_BYPASS1, 0x00000303);
115 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
116 + rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0101);
117 + else
118 + rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0000);
119 +
120 + rt2800_register_write(rt2x00dev, RF_BYPASS3, 0xf1f1);
121 +
122 + rfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
123 + rfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
124 + rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
125 + rfb4r0 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
126 + rfb4r19 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 19);
127 + rfb5r3 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
128 + rfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
129 + rfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
130 + rfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
131 + rfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
132 + rfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
133 +
134 + rfb6r0 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
135 + rfb6r19 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 19);
136 + rfb7r3 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
137 + rfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
138 + rfb7r17 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
139 + rfb7r18 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
140 + rfb7r19 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
141 + rfb7r20 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
142 +
143 + rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x87);
144 + rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0x27);
145 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x38);
146 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x38);
147 + rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x80);
148 + rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0xC1);
149 + rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x60);
150 + rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
151 +
152 + rt2800_bbp_write(rt2x00dev, 23, 0x0);
153 + rt2800_bbp_write(rt2x00dev, 24, 0x0);
154 +
155 + rt2800_bbp_dcoc_write(rt2x00dev, 5, 0x0);
156 +
157 + bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
158 + bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
159 +
160 + rt2800_bbp_write(rt2x00dev, 241, 0x10);
161 + rt2800_bbp_write(rt2x00dev, 242, 0x84);
162 + rt2800_bbp_write(rt2x00dev, 244, 0x31);
163 +
164 + bbpval = rt2800_bbp_dcoc_read(rt2x00dev, 3);
165 + bbpval = bbpval & (~0x7);
166 + rt2800_bbp_dcoc_write(rt2x00dev, 3, bbpval);
167 +
168 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
169 + udelay(1);
170 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
171 + usleep_range(1, 200);
172 + rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003376);
173 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
174 + udelay(1);
175 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
176 + rt2800_bbp_write(rt2x00dev, 23, 0x06);
177 + rt2800_bbp_write(rt2x00dev, 24, 0x06);
178 + } else {
179 + rt2800_bbp_write(rt2x00dev, 23, 0x02);
180 + rt2800_bbp_write(rt2x00dev, 24, 0x02);
181 + }
182 +
183 + for (ch_idx = 0; ch_idx < 2; ch_idx = ch_idx + 1) {
184 + if (ch_idx == 0) {
185 + rfval = rfb0r1 & (~0x3);
186 + rfval = rfb0r1 | 0x1;
187 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
188 + rfval = rfb0r2 & (~0x33);
189 + rfval = rfb0r2 | 0x11;
190 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
191 + rfval = rfb0r42 & (~0x50);
192 + rfval = rfb0r42 | 0x10;
193 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
194 +
195 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
196 + udelay(1);
197 +
198 + bbpval = bbp1 & (~0x18);
199 + bbpval = bbpval | 0x00;
200 + rt2800_bbp_write(rt2x00dev, 1, bbpval);
201 +
202 + rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x00);
203 + } else {
204 + rfval = rfb0r1 & (~0x3);
205 + rfval = rfb0r1 | 0x2;
206 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
207 + rfval = rfb0r2 & (~0x33);
208 + rfval = rfb0r2 | 0x22;
209 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
210 + rfval = rfb0r42 & (~0x50);
211 + rfval = rfb0r42 | 0x40;
212 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
213 +
214 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002006);
215 + udelay(1);
216 +
217 + bbpval = bbp1 & (~0x18);
218 + bbpval = bbpval | 0x08;
219 + rt2800_bbp_write(rt2x00dev, 1, bbpval);
220 +
221 + rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x01);
222 + }
223 + usleep_range(500, 1500);
224 +
225 + vga_idx = 0;
226 + while (vga_idx < 11) {
227 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, rf_vga_table[vga_idx]);
228 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, rf_vga_table[vga_idx]);
229 +
230 + rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x93);
231 +
232 + for (i = 0; i < 10000; i++) {
233 + bbpval = rt2800_bbp_read(rt2x00dev, 159);
234 + if ((bbpval & 0xff) == 0x93)
235 + usleep_range(50, 100);
236 + else
237 + break;
238 + }
239 +
240 + if ((bbpval & 0xff) == 0x93) {
241 + rt2x00_warn(rt2x00dev, "Fatal Error: Calibration doesn't finish");
242 + goto restore_value;
243 + }
244 +
245 + for (i = 0; i < 5; i++) {
246 + u32 bbptemp = 0;
247 + u8 value = 0;
248 + int result = 0;
249 +
250 + rt2800_bbp_write(rt2x00dev, 158, 0x1e);
251 + rt2800_bbp_write(rt2x00dev, 159, i);
252 + rt2800_bbp_write(rt2x00dev, 158, 0x22);
253 + value = rt2800_bbp_read(rt2x00dev, 159);
254 + bbptemp = bbptemp + (value << 24);
255 + rt2800_bbp_write(rt2x00dev, 158, 0x21);
256 + value = rt2800_bbp_read(rt2x00dev, 159);
257 + bbptemp = bbptemp + (value << 16);
258 + rt2800_bbp_write(rt2x00dev, 158, 0x20);
259 + value = rt2800_bbp_read(rt2x00dev, 159);
260 + bbptemp = bbptemp + (value << 8);
261 + rt2800_bbp_write(rt2x00dev, 158, 0x1f);
262 + value = rt2800_bbp_read(rt2x00dev, 159);
263 + bbptemp = bbptemp + value;
264 +
265 + if (i < 2 && (bbptemp & 0x800000))
266 + result = (bbptemp & 0xffffff) - 0x1000000;
267 + else if (i == 4)
268 + result = bbptemp;
269 + else
270 + result = bbptemp;
271 +
272 + if (i == 0)
273 + mi = result / 4096;
274 + else if (i == 1)
275 + mq = result / 4096;
276 + else if (i == 2)
277 + si = bbptemp / 4096;
278 + else if (i == 3)
279 + sq = bbptemp / 4096;
280 + else
281 + riq = result / 4096;
282 + }
283 +
284 + bbpval1 = si - mi * mi;
285 + rt2x00_dbg(rt2x00dev,
286 + "RXIQ si=%d, sq=%d, riq=%d, bbpval %d, vga_idx %d",
287 + si, sq, riq, bbpval1, vga_idx);
288 +
289 + if (bbpval1 >= (100 * 100))
290 + break;
291 +
292 + if (bbpval1 <= 100)
293 + vga_idx = vga_idx + 9;
294 + else if (bbpval1 <= 158)
295 + vga_idx = vga_idx + 8;
296 + else if (bbpval1 <= 251)
297 + vga_idx = vga_idx + 7;
298 + else if (bbpval1 <= 398)
299 + vga_idx = vga_idx + 6;
300 + else if (bbpval1 <= 630)
301 + vga_idx = vga_idx + 5;
302 + else if (bbpval1 <= 1000)
303 + vga_idx = vga_idx + 4;
304 + else if (bbpval1 <= 1584)
305 + vga_idx = vga_idx + 3;
306 + else if (bbpval1 <= 2511)
307 + vga_idx = vga_idx + 2;
308 + else
309 + vga_idx = vga_idx + 1;
310 + }
311 +
312 + sigma_i = rt2800_do_sqrt_accumulation(100 * (si - mi * mi));
313 + sigma_q = rt2800_do_sqrt_accumulation(100 * (sq - mq * mq));
314 + r_iq = 10 * (riq - (mi * mq));
315 +
316 + rt2x00_dbg(rt2x00dev, "Sigma_i=%d, Sigma_q=%d, R_iq=%d", sigma_i, sigma_q, r_iq);
317 +
318 + if (sigma_i <= 1400 && sigma_i >= 1000 &&
319 + (sigma_i - sigma_q) <= 112 &&
320 + (sigma_i - sigma_q) >= -112 &&
321 + mi <= 32 && mi >= -32 &&
322 + mq <= 32 && mq >= -32) {
323 + r_iq = 10 * (riq - (mi * mq));
324 + rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n",
325 + sigma_i, sigma_q, r_iq);
326 +
327 + g_rx = (1000 * sigma_q) / sigma_i;
328 + g_imb = ((-2) * 128 * (1000 - g_rx)) / (1000 + g_rx);
329 + ph_rx = (r_iq * 2292) / (sigma_i * sigma_q);
330 +
331 + if (ph_rx > 20 || ph_rx < -20) {
332 + ph_rx = 0;
333 + rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
334 + }
335 +
336 + if (g_imb > 12 || g_imb < -12) {
337 + g_imb = 0;
338 + rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
339 + }
340 + } else {
341 + g_imb = 0;
342 + ph_rx = 0;
343 + rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n",
344 + sigma_i, sigma_q, r_iq);
345 + rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
346 + }
347 +
348 + if (ch_idx == 0) {
349 + rt2800_bbp_write(rt2x00dev, 158, 0x37);
350 + rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
351 + rt2800_bbp_write(rt2x00dev, 158, 0x35);
352 + rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
353 + } else {
354 + rt2800_bbp_write(rt2x00dev, 158, 0x55);
355 + rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
356 + rt2800_bbp_write(rt2x00dev, 158, 0x53);
357 + rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
358 + }
359 + }
360 +
361 +restore_value:
362 + rt2800_bbp_write(rt2x00dev, 158, 0x3);
363 + bbpval = rt2800_bbp_read(rt2x00dev, 159);
364 + rt2800_bbp_write(rt2x00dev, 159, (bbpval | 0x07));
365 +
366 + rt2800_bbp_write(rt2x00dev, 158, 0x00);
367 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
368 + rt2800_bbp_write(rt2x00dev, 1, bbp1);
369 + rt2800_bbp_write(rt2x00dev, 4, bbp4);
370 + rt2800_bbp_write(rt2x00dev, 241, bbpr241);
371 + rt2800_bbp_write(rt2x00dev, 242, bbpr242);
372 +
373 + rt2800_bbp_write(rt2x00dev, 244, 0x00);
374 + bbpval = rt2800_bbp_read(rt2x00dev, 21);
375 + bbpval |= 0x1;
376 + rt2800_bbp_write(rt2x00dev, 21, bbpval);
377 + usleep_range(10, 200);
378 + bbpval &= 0xfe;
379 + rt2800_bbp_write(rt2x00dev, 21, bbpval);
380 +
381 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfb0r1);
382 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfb0r2);
383 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
384 +
385 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, rfb4r0);
386 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 19, rfb4r19);
387 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rfb5r3);
388 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rfb5r4);
389 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rfb5r17);
390 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, rfb5r18);
391 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, rfb5r19);
392 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, rfb5r20);
393 +
394 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, rfb6r0);
395 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 19, rfb6r19);
396 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, rfb7r3);
397 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, rfb7r4);
398 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, rfb7r17);
399 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, rfb7r18);
400 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, rfb7r19);
401 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, rfb7r20);
402 +
403 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
404 + udelay(1);
405 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
406 + udelay(1);
407 + rt2800_register_write(rt2x00dev, RF_CONTROL0, orig_RF_CONTROL0);
408 + udelay(1);
409 + rt2800_register_write(rt2x00dev, RF_BYPASS0, orig_RF_BYPASS0);
410 + rt2800_register_write(rt2x00dev, RF_CONTROL1, orig_RF_CONTROL1);
411 + rt2800_register_write(rt2x00dev, RF_BYPASS1, orig_RF_BYPASS1);
412 + rt2800_register_write(rt2x00dev, RF_CONTROL3, orig_RF_CONTROL3);
413 + rt2800_register_write(rt2x00dev, RF_BYPASS3, orig_RF_BYPASS3);
414 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
415 +}
416 +
417 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
418 bool set_bw, bool is_ht40)
419 {
420 @@ -9308,6 +9691,7 @@ static void rt2800_init_rfcsr_6352(struc
421 rt2800_rxdcoc_calibration(rt2x00dev);
422 rt2800_bw_filter_calibration(rt2x00dev, true);
423 rt2800_bw_filter_calibration(rt2x00dev, false);
424 + rt2800_rxiq_calibration(rt2x00dev);
425 }
426
427 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
Staging tree of Alvaro Fernandez Rojas