package/kernel/mac80211/patches/321-ath9k-ar9271_hw_pa_cal-use-proper-makroses.patch

   1 From: Oleksij Rempel <linux@rempel-privat.de>
   2 Date: Sun, 22 Mar 2015 19:29:48 +0100
   3 Subject: [PATCH] ath9k: ar9271_hw_pa_cal: use proper makroses.
   4
   5 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
   6 Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
   7 ---
   8
   9 --- a/drivers/net/wireless/ath/ath9k/ar9002_calib.c
  10 +++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
  11 @@ -443,33 +443,30 @@ static void ar9271_hw_pa_cal(struct ath_
  12         for (i = 0; i < ARRAY_SIZE(regList); i++)
  13                 regList[i][1] = REG_READ(ah, regList[i][0]);
  14
  15 -       regVal = REG_READ(ah, AR9285_AN_RF2G6);
  16 -       regVal &= (~(0x1));
  17 -       REG_WRITE(ah, AR9285_AN_RF2G6, regVal);
  18 -       regVal = REG_READ(ah, 0x9808);
  19 -       regVal |= (0x1 << 27);
  20 -       REG_WRITE(ah, 0x9808, regVal);
  21 -
  22 +       /* 7834, b1=0 */
  23 +       REG_CLR_BIT(ah, AR9285_AN_RF2G6, 1 << 0);
  24 +       /* 9808, b27=1 */
  25 +       REG_SET_BIT(ah, 0x9808, 1 << 27);
  26         /* 786c,b23,1, pwddac=1 */
  27 -       REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
  28 +       REG_SET_BIT(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC);
  29         /* 7854, b5,1, pdrxtxbb=1 */
  30 -       REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
  31 +       REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1);
  32         /* 7854, b7,1, pdv2i=1 */
  33 -       REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
  34 +       REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I);
  35         /* 7854, b8,1, pddacinterface=1 */
  36 -       REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
  37 +       REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF);
  38         /* 7824,b12,0, offcal=0 */
  39 -       REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
  40 +       REG_CLR_BIT(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL);
  41         /* 7838, b1,0, pwddb=0 */
  42 -       REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
  43 +       REG_CLR_BIT(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB);
  44         /* 7820,b11,0, enpacal=0 */
  45 -       REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
  46 +       REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL);
  47         /* 7820,b25,1, pdpadrv1=0 */
  48 -       REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
  49 +       REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1);
  50         /* 7820,b24,0, pdpadrv2=0 */
  51 -       REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
  52 +       REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2);
  53         /* 7820,b23,0, pdpaout=0 */
  54 -       REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
  55 +       REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT);
  56         /* 783c,b14-16,7, padrvgn2tab_0=7 */
  57         REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
  58         /*
  59 @@ -516,15 +513,13 @@ static void ar9271_hw_pa_cal(struct ath_
  60                 ah->pacal_info.prev_offset = regVal;
  61         }
  62
  63 -       ENABLE_REGWRITE_BUFFER(ah);
  64
  65 -       regVal = REG_READ(ah, AR_AN_RF2G1_CH1);
  66 -       regVal |= 0x1;
  67 -       REG_WRITE(ah, AR_AN_RF2G1_CH1, regVal);
  68 -       regVal = REG_READ(ah, 0x9808);
  69 -       regVal &= (~(0x1 << 27));
  70 -       REG_WRITE(ah, 0x9808, regVal);
  71 +       /* 7834, b1=1 */
  72 +       REG_SET_BIT(ah, AR9285_AN_RF2G6, 1 << 0);
  73 +       /* 9808, b27=0 */
  74 +       REG_CLR_BIT(ah, 0x9808, 1 << 27);
  75
  76 +       ENABLE_REGWRITE_BUFFER(ah);
  77         for (i = 0; i < ARRAY_SIZE(regList); i++)
  78                 REG_WRITE(ah, regList[i][0], regList[i][1]);
  79