1 /******************************************************************************
3 ** FILE NAME : ifxmips_ptm_adsl.c
9 ** DESCRIPTION : PTM driver common source file (core functions for Danube/
11 ** COPYRIGHT : Copyright (c) 2006
12 ** Infineon Technologies AG
13 ** Am Campeon 1-12, 85579 Neubiberg, Germany
15 ** This program is free software; you can redistribute it and/or modify
16 ** it under the terms of the GNU General Public License as published by
17 ** the Free Software Foundation; either version 2 of the License, or
18 ** (at your option) any later version.
21 ** $Date $Author $Comment
22 ** 07 JUL 2009 Xu Liang Init Version
23 *******************************************************************************/
28 * ####################################
30 * ####################################
36 #include <linux/version.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/types.h>
40 #include <linux/errno.h>
41 #include <linux/proc_fs.h>
42 #include <linux/init.h>
43 #include <linux/ioctl.h>
44 #include <linux/etherdevice.h>
45 #include <linux/interrupt.h>
46 #include <linux/netdevice.h>
50 * Chip Specific Head File
52 #include "ifxmips_ptm_adsl.h"
55 #include <lantiq_soc.h>
58 * ####################################
59 * Kernel Version Adaption
60 * ####################################
62 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11)
63 #define MODULE_PARM_ARRAY(a, b) module_param_array(a, int, NULL, 0)
64 #define MODULE_PARM(a, b) module_param(a, int, 0)
66 #define MODULE_PARM_ARRAY(a, b) MODULE_PARM(a, b)
72 * ####################################
73 * Parameters to Configure PPE
74 * ####################################
77 static int write_desc_delay
= 0x20; /* Write descriptor delay */
79 static int rx_max_packet_size
= ETH_MAX_FRAME_LENGTH
;
80 /* Max packet size for RX */
82 static int dma_rx_descriptor_length
= 24; /* Number of descriptors per DMA RX channel */
83 static int dma_tx_descriptor_length
= 24; /* Number of descriptors per DMA TX channel */
85 static int eth_efmtc_crc_cfg
= 0x03100710; /* default: tx_eth_crc_check: 1, tx_tc_crc_check: 1, tx_tc_crc_len = 16 */
86 /* rx_eth_crc_present: 1, rx_eth_crc_check: 1, rx_tc_crc_check: 1, rx_tc_crc_len = 16 */
88 MODULE_PARM(write_desc_delay
, "i");
89 MODULE_PARM_DESC(write_desc_delay
, "PPE core clock cycles between descriptor write and effectiveness in external RAM");
91 MODULE_PARM(rx_max_packet_size
, "i");
92 MODULE_PARM_DESC(rx_max_packet_size
, "Max packet size in byte for downstream ethernet frames");
94 MODULE_PARM(dma_rx_descriptor_length
, "i");
95 MODULE_PARM_DESC(dma_rx_descriptor_length
, "Number of descriptor assigned to DMA RX channel (>16)");
96 MODULE_PARM(dma_tx_descriptor_length
, "i");
97 MODULE_PARM_DESC(dma_tx_descriptor_length
, "Number of descriptor assigned to DMA TX channel (>16)");
99 MODULE_PARM(eth_efmtc_crc_cfg
, "i");
100 MODULE_PARM_DESC(eth_efmtc_crc_cfg
, "Configuration for PTM TX/RX ethernet/efm-tc CRC");
105 * ####################################
107 * ####################################
111 #define DUMP_SKB_LEN ~0
116 * ####################################
118 * ####################################
124 static void ptm_setup(struct net_device
*, int);
125 static struct net_device_stats
*ptm_get_stats(struct net_device
*);
126 static int ptm_open(struct net_device
*);
127 static int ptm_stop(struct net_device
*);
128 static unsigned int ptm_poll(int, unsigned int);
129 static int ptm_napi_poll(struct napi_struct
*, int);
130 static int ptm_hard_start_xmit(struct sk_buff
*, struct net_device
*);
131 static int ptm_ioctl(struct net_device
*, struct ifreq
*, int);
132 static void ptm_tx_timeout(struct net_device
*);
137 static INLINE
void adsl_led_flash(void);
140 * buffer manage functions
142 static INLINE
struct sk_buff
* alloc_skb_rx(void);
143 //static INLINE struct sk_buff* alloc_skb_tx(unsigned int);
144 static INLINE
struct sk_buff
*get_skb_rx_pointer(unsigned int);
145 static INLINE
int get_tx_desc(unsigned int, unsigned int *);
148 * Mailbox handler and signal function
150 static INLINE
int mailbox_rx_irq_handler(unsigned int);
151 static irqreturn_t
mailbox_irq_handler(int, void *);
152 static INLINE
void mailbox_signal(unsigned int, int);
153 #ifdef CONFIG_IFX_PTM_RX_TASKLET
154 static void do_ptm_tasklet(unsigned long);
160 #if defined(DEBUG_DUMP_SKB) && DEBUG_DUMP_SKB
161 static void dump_skb(struct sk_buff
*, u32
, char *, int, int, int);
163 #define dump_skb(skb, len, title, port, ch, is_tx) do {} while (0)
165 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
166 static void skb_swap(struct sk_buff
*);
168 #define skb_swap(skb) do {} while (0)
172 * Proc File Functions
174 static INLINE
void proc_file_create(void);
175 static INLINE
void proc_file_delete(void);
176 static int proc_read_version(char *, char **, off_t
, int, int *, void *);
177 static int proc_read_wanmib(char *, char **, off_t
, int, int *, void *);
178 static int proc_write_wanmib(struct file
*, const char *, unsigned long, void *);
179 #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
180 static int proc_read_genconf(char *, char **, off_t
, int, int *, void *);
182 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
183 static int proc_read_dbg(char *, char **, off_t
, int, int *, void *);
184 static int proc_write_dbg(struct file
*, const char *, unsigned long, void *);
188 * Proc Help Functions
190 static INLINE
int stricmp(const char *, const char *);
191 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
192 static INLINE
int strincmp(const char *, const char *, int);
194 static INLINE
int ifx_ptm_version(char *);
197 * Init & clean-up functions
199 static INLINE
void check_parameters(void);
200 static INLINE
int init_priv_data(void);
201 static INLINE
void clear_priv_data(void);
202 static INLINE
void init_tables(void);
207 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
208 extern int ifx_mei_atm_showtime_check(int *is_showtime
, struct port_cell_info
*port_cell
, void **xdata_addr
);
210 static inline int ifx_mei_atm_showtime_check(int *is_showtime
, struct port_cell_info
*port_cell
, void **xdata_addr
)
212 if ( is_showtime
!= NULL
)
221 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
222 extern int (*ifx_mei_atm_showtime_enter
)(struct port_cell_info
*, void *);
223 extern int (*ifx_mei_atm_showtime_exit
)(void);
225 int (*ifx_mei_atm_showtime_enter
)(struct port_cell_info
*, void *) = NULL
;
226 EXPORT_SYMBOL(ifx_mei_atm_showtime_enter
);
227 int (*ifx_mei_atm_showtime_exit
)(void) = NULL
;
228 EXPORT_SYMBOL(ifx_mei_atm_showtime_exit
);
234 * ####################################
236 * ####################################
239 static struct ptm_priv_data g_ptm_priv_data
;
241 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32)
242 static struct net_device_ops g_ptm_netdev_ops
= {
243 .ndo_get_stats
= ptm_get_stats
,
244 .ndo_open
= ptm_open
,
245 .ndo_stop
= ptm_stop
,
246 .ndo_start_xmit
= ptm_hard_start_xmit
,
247 .ndo_validate_addr
= eth_validate_addr
,
248 .ndo_set_mac_address
= eth_mac_addr
,
249 .ndo_change_mtu
= eth_change_mtu
,
250 .ndo_do_ioctl
= ptm_ioctl
,
251 .ndo_tx_timeout
= ptm_tx_timeout
,
255 static struct net_device
*g_net_dev
[2] = {0};
256 static char *g_net_dev_name
[2] = {"ptm0", "ptmfast0"};
258 #ifdef CONFIG_IFX_PTM_RX_TASKLET
259 static struct tasklet_struct g_ptm_tasklet
[] = {
260 {NULL
, 0, ATOMIC_INIT(0), do_ptm_tasklet
, 0},
261 {NULL
, 0, ATOMIC_INIT(0), do_ptm_tasklet
, 1},
265 unsigned int ifx_ptm_dbg_enable
= DBG_ENABLE_MASK_ERR
;
267 static struct proc_dir_entry
* g_ptm_dir
= NULL
;
269 static int g_showtime
= 0;
274 * ####################################
276 * ####################################
279 static void ptm_setup(struct net_device
*dev
, int ndev
)
281 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
282 netif_carrier_off(dev
);
285 /* hook network operations */
286 dev
->netdev_ops
= &g_ptm_netdev_ops
;
287 netif_napi_add(dev
, &g_ptm_priv_data
.itf
[ndev
].napi
, ptm_napi_poll
, 25);
288 dev
->watchdog_timeo
= ETH_WATCHDOG_TIMEOUT
;
290 dev
->dev_addr
[0] = 0x00;
291 dev
->dev_addr
[1] = 0x20;
292 dev
->dev_addr
[2] = 0xda;
293 dev
->dev_addr
[3] = 0x86;
294 dev
->dev_addr
[4] = 0x23;
295 dev
->dev_addr
[5] = 0x75 + ndev
;
298 static struct net_device_stats
*ptm_get_stats(struct net_device
*dev
)
302 for ( ndev
= 0; ndev
< ARRAY_SIZE(g_net_dev
) && g_net_dev
[ndev
] != dev
; ndev
++ );
303 ASSERT(ndev
>= 0 && ndev
< ARRAY_SIZE(g_net_dev
), "ndev = %d (wrong value)", ndev
);
305 g_ptm_priv_data
.itf
[ndev
].stats
.rx_errors
= WAN_MIB_TABLE
[ndev
].wrx_tccrc_err_pdu
+ WAN_MIB_TABLE
[ndev
].wrx_ethcrc_err_pdu
;
306 g_ptm_priv_data
.itf
[ndev
].stats
.rx_dropped
= WAN_MIB_TABLE
[ndev
].wrx_nodesc_drop_pdu
+ WAN_MIB_TABLE
[ndev
].wrx_len_violation_drop_pdu
+ (WAN_MIB_TABLE
[ndev
].wrx_correct_pdu
- g_ptm_priv_data
.itf
[ndev
].stats
.rx_packets
);
308 return &g_ptm_priv_data
.itf
[ndev
].stats
;
311 static int ptm_open(struct net_device
*dev
)
315 for ( ndev
= 0; ndev
< ARRAY_SIZE(g_net_dev
) && g_net_dev
[ndev
] != dev
; ndev
++ );
316 ASSERT(ndev
>= 0 && ndev
< ARRAY_SIZE(g_net_dev
), "ndev = %d (wrong value)", ndev
);
318 napi_enable(&g_ptm_priv_data
.itf
[ndev
].napi
);
320 IFX_REG_W32_MASK(0, 1 << ndev
, MBOX_IGU1_IER
);
322 netif_start_queue(dev
);
327 static int ptm_stop(struct net_device
*dev
)
331 for ( ndev
= 0; ndev
< ARRAY_SIZE(g_net_dev
) && g_net_dev
[ndev
] != dev
; ndev
++ );
332 ASSERT(ndev
>= 0 && ndev
< ARRAY_SIZE(g_net_dev
), "ndev = %d (wrong value)", ndev
);
334 IFX_REG_W32_MASK((1 << ndev
) | (1 << (ndev
+ 16)), 0, MBOX_IGU1_IER
);
336 napi_disable(&g_ptm_priv_data
.itf
[ndev
].napi
);
338 netif_stop_queue(dev
);
343 static unsigned int ptm_poll(int ndev
, unsigned int work_to_do
)
345 unsigned int work_done
= 0;
347 ASSERT(ndev
>= 0 && ndev
< ARRAY_SIZE(g_net_dev
), "ndev = %d (wrong value)", ndev
);
349 while ( work_done
< work_to_do
&& WRX_DMA_CHANNEL_CONFIG(ndev
)->vlddes
> 0 ) {
350 if ( mailbox_rx_irq_handler(ndev
) < 0 )
358 static int ptm_napi_poll(struct napi_struct
*napi
, int budget
)
361 unsigned int work_done
;
363 for ( ndev
= 0; ndev
< ARRAY_SIZE(g_net_dev
) && g_net_dev
[ndev
] != napi
->dev
; ndev
++ );
365 work_done
= ptm_poll(ndev
, budget
);
368 if ( !netif_running(napi
->dev
) ) {
374 if ( WRX_DMA_CHANNEL_CONFIG(ndev
)->vlddes
== 0 ) {
376 IFX_REG_W32_MASK(0, 1 << ndev
, MBOX_IGU1_ISRC
);
378 if ( WRX_DMA_CHANNEL_CONFIG(ndev
)->vlddes
== 0 ) {
380 IFX_REG_W32_MASK(0, 1 << ndev
, MBOX_IGU1_IER
);
389 static int ptm_hard_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
394 register struct tx_descriptor reg_desc
= {0};
396 for ( ndev
= 0; ndev
< ARRAY_SIZE(g_net_dev
) && g_net_dev
[ndev
] != dev
; ndev
++ );
397 ASSERT(ndev
>= 0 && ndev
< ARRAY_SIZE(g_net_dev
), "ndev = %d (wrong value)", ndev
);
400 err("not in showtime");
401 goto PTM_HARD_START_XMIT_FAIL
;
404 /* allocate descriptor */
405 desc_base
= get_tx_desc(ndev
, &f_full
);
407 dev
->trans_start
= jiffies
;
408 netif_stop_queue(dev
);
410 IFX_REG_W32_MASK(0, 1 << (ndev
+ 16), MBOX_IGU1_ISRC
);
411 IFX_REG_W32_MASK(0, 1 << (ndev
+ 16), MBOX_IGU1_IER
);
414 goto PTM_HARD_START_XMIT_FAIL
;
416 if ( g_ptm_priv_data
.itf
[ndev
].tx_skb
[desc_base
] != NULL
)
417 dev_kfree_skb_any(g_ptm_priv_data
.itf
[ndev
].tx_skb
[desc_base
]);
418 g_ptm_priv_data
.itf
[ndev
].tx_skb
[desc_base
] = skb
;
420 reg_desc
.dataptr
= (unsigned int)skb
->data
>> 2;
421 reg_desc
.datalen
= skb
->len
< ETH_ZLEN
? ETH_ZLEN
: skb
->len
;
422 reg_desc
.byteoff
= (unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1);
425 reg_desc
.sop
= reg_desc
.eop
= 1;
427 /* write discriptor to memory and write back cache */
428 g_ptm_priv_data
.itf
[ndev
].tx_desc
[desc_base
] = reg_desc
;
429 dma_cache_wback((unsigned long)skb
->data
, skb
->len
);
432 dump_skb(skb
, DUMP_SKB_LEN
, (char *)__func__
, ndev
, ndev
, 1);
434 if ( (ifx_ptm_dbg_enable
& DBG_ENABLE_MASK_MAC_SWAP
) ) {
438 g_ptm_priv_data
.itf
[ndev
].stats
.tx_packets
++;
439 g_ptm_priv_data
.itf
[ndev
].stats
.tx_bytes
+= reg_desc
.datalen
;
441 dev
->trans_start
= jiffies
;
442 mailbox_signal(ndev
, 1);
448 PTM_HARD_START_XMIT_FAIL
:
449 dev_kfree_skb_any(skb
);
450 g_ptm_priv_data
.itf
[ndev
].stats
.tx_dropped
++;
454 static int ptm_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
458 for ( ndev
= 0; ndev
< ARRAY_SIZE(g_net_dev
) && g_net_dev
[ndev
] != dev
; ndev
++ );
459 ASSERT(ndev
>= 0 && ndev
< ARRAY_SIZE(g_net_dev
), "ndev = %d (wrong value)", ndev
);
463 case IFX_PTM_MIB_CW_GET
:
464 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifRxNoIdleCodewords
= WAN_MIB_TABLE
[ndev
].wrx_nonidle_cw
;
465 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifRxIdleCodewords
= WAN_MIB_TABLE
[ndev
].wrx_idle_cw
;
466 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifRxCodingViolation
= WAN_MIB_TABLE
[ndev
].wrx_err_cw
;
467 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifTxNoIdleCodewords
= 0;
468 ((PTM_CW_IF_ENTRY_T
*)ifr
->ifr_data
)->ifTxIdleCodewords
= 0;
470 case IFX_PTM_MIB_FRAME_GET
:
471 ((PTM_FRAME_MIB_T
*)ifr
->ifr_data
)->RxCorrect
= WAN_MIB_TABLE
[ndev
].wrx_correct_pdu
;
472 ((PTM_FRAME_MIB_T
*)ifr
->ifr_data
)->TC_CrcError
= WAN_MIB_TABLE
[ndev
].wrx_tccrc_err_pdu
;
473 ((PTM_FRAME_MIB_T
*)ifr
->ifr_data
)->RxDropped
= WAN_MIB_TABLE
[ndev
].wrx_nodesc_drop_pdu
+ WAN_MIB_TABLE
[ndev
].wrx_len_violation_drop_pdu
;
474 ((PTM_FRAME_MIB_T
*)ifr
->ifr_data
)->TxSend
= WAN_MIB_TABLE
[ndev
].wtx_total_pdu
;
476 case IFX_PTM_CFG_GET
:
477 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxEthCrcPresent
= CFG_ETH_EFMTC_CRC
->rx_eth_crc_present
;
478 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxEthCrcCheck
= CFG_ETH_EFMTC_CRC
->rx_eth_crc_check
;
479 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcCheck
= CFG_ETH_EFMTC_CRC
->rx_tc_crc_check
;
480 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcLen
= CFG_ETH_EFMTC_CRC
->rx_tc_crc_len
;
481 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxEthCrcGen
= CFG_ETH_EFMTC_CRC
->tx_eth_crc_gen
;
482 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcGen
= CFG_ETH_EFMTC_CRC
->tx_tc_crc_gen
;
483 ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcLen
= CFG_ETH_EFMTC_CRC
->tx_tc_crc_len
;
485 case IFX_PTM_CFG_SET
:
486 CFG_ETH_EFMTC_CRC
->rx_eth_crc_present
= ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxEthCrcPresent
? 1 : 0;
487 CFG_ETH_EFMTC_CRC
->rx_eth_crc_check
= ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxEthCrcCheck
? 1 : 0;
488 if ( ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcCheck
&& (((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcLen
== 16 || ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcLen
== 32) )
490 CFG_ETH_EFMTC_CRC
->rx_tc_crc_check
= 1;
491 CFG_ETH_EFMTC_CRC
->rx_tc_crc_len
= ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->RxTcCrcLen
;
495 CFG_ETH_EFMTC_CRC
->rx_tc_crc_check
= 0;
496 CFG_ETH_EFMTC_CRC
->rx_tc_crc_len
= 0;
498 CFG_ETH_EFMTC_CRC
->tx_eth_crc_gen
= ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxEthCrcGen
? 1 : 0;
499 if ( ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcGen
&& (((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcLen
== 16 || ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcLen
== 32) )
501 CFG_ETH_EFMTC_CRC
->tx_tc_crc_gen
= 1;
502 CFG_ETH_EFMTC_CRC
->tx_tc_crc_len
= ((IFX_PTM_CFG_T
*)ifr
->ifr_data
)->TxTcCrcLen
;
506 CFG_ETH_EFMTC_CRC
->tx_tc_crc_gen
= 0;
507 CFG_ETH_EFMTC_CRC
->tx_tc_crc_len
= 0;
517 static void ptm_tx_timeout(struct net_device
*dev
)
521 for ( ndev
= 0; ndev
< ARRAY_SIZE(g_net_dev
) && g_net_dev
[ndev
] != dev
; ndev
++ );
522 ASSERT(ndev
>= 0 && ndev
< ARRAY_SIZE(g_net_dev
), "ndev = %d (wrong value)", ndev
);
524 /* disable TX irq, release skb when sending new packet */
525 IFX_REG_W32_MASK(1 << (ndev
+ 16), 0, MBOX_IGU1_IER
);
527 /* wake up TX queue */
528 netif_wake_queue(dev
);
533 static INLINE
void adsl_led_flash(void)
537 static INLINE
struct sk_buff
* alloc_skb_rx(void)
541 /* allocate memroy including trailer and padding */
542 skb
= dev_alloc_skb(rx_max_packet_size
+ RX_HEAD_MAC_ADDR_ALIGNMENT
+ DATA_BUFFER_ALIGNMENT
);
544 /* must be burst length alignment and reserve two more bytes for MAC address alignment */
545 if ( ((unsigned int)skb
->data
& (DATA_BUFFER_ALIGNMENT
- 1)) != 0 )
546 skb_reserve(skb
, ~((unsigned int)skb
->data
+ (DATA_BUFFER_ALIGNMENT
- 1)) & (DATA_BUFFER_ALIGNMENT
- 1));
547 /* pub skb in reserved area "skb->data - 4" */
548 *((struct sk_buff
**)skb
->data
- 1) = skb
;
550 /* write back and invalidate cache */
551 dma_cache_wback_inv((unsigned long)skb
->data
- sizeof(skb
), sizeof(skb
));
552 /* invalidate cache */
553 dma_cache_inv((unsigned long)skb
->data
, (unsigned int)skb
->end
- (unsigned int)skb
->data
);
560 static INLINE
struct sk_buff
* alloc_skb_tx(unsigned int size
)
564 /* allocate memory including padding */
565 size
= (size
+ DATA_BUFFER_ALIGNMENT
- 1) & ~(DATA_BUFFER_ALIGNMENT
- 1);
566 skb
= dev_alloc_skb(size
+ DATA_BUFFER_ALIGNMENT
);
567 /* must be burst length alignment */
569 skb_reserve(skb
, ~((unsigned int)skb
->data
+ (DATA_BUFFER_ALIGNMENT
- 1)) & (DATA_BUFFER_ALIGNMENT
- 1));
574 static INLINE
struct sk_buff
*get_skb_rx_pointer(unsigned int dataptr
)
576 unsigned int skb_dataptr
;
579 skb_dataptr
= ((dataptr
- 1) << 2) | KSEG1
;
580 skb
= *(struct sk_buff
**)skb_dataptr
;
582 ASSERT((unsigned int)skb
>= KSEG0
, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb
, dataptr
);
583 ASSERT(((unsigned int)skb
->data
| KSEG1
) == ((dataptr
<< 2) | KSEG1
), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb
, (unsigned int)skb
->data
, dataptr
);
588 static INLINE
int get_tx_desc(unsigned int itf
, unsigned int *f_full
)
591 struct ptm_itf
*p_itf
= &g_ptm_priv_data
.itf
[itf
];
593 // assume TX is serial operation
594 // no protection provided
598 if ( p_itf
->tx_desc
[p_itf
->tx_desc_pos
].own
== 0 ) {
599 desc_base
= p_itf
->tx_desc_pos
;
600 if ( ++(p_itf
->tx_desc_pos
) == dma_tx_descriptor_length
)
601 p_itf
->tx_desc_pos
= 0;
602 if ( p_itf
->tx_desc
[p_itf
->tx_desc_pos
].own
== 0 )
609 static INLINE
int mailbox_rx_irq_handler(unsigned int ch
) // return: < 0 - descriptor not available, 0 - received one packet
611 unsigned int ndev
= ch
;
613 struct sk_buff
*new_skb
;
614 volatile struct rx_descriptor
*desc
;
615 struct rx_descriptor reg_desc
;
618 desc
= &g_ptm_priv_data
.itf
[ndev
].rx_desc
[g_ptm_priv_data
.itf
[ndev
].rx_desc_pos
];
619 if ( desc
->own
|| !desc
->c
) // if PP32 hold descriptor or descriptor not completed
621 if ( ++g_ptm_priv_data
.itf
[ndev
].rx_desc_pos
== dma_rx_descriptor_length
)
622 g_ptm_priv_data
.itf
[ndev
].rx_desc_pos
= 0;
625 skb
= get_skb_rx_pointer(reg_desc
.dataptr
);
627 if ( !reg_desc
.err
) {
628 new_skb
= alloc_skb_rx();
629 if ( new_skb
!= NULL
) {
630 skb_reserve(skb
, reg_desc
.byteoff
);
631 skb_put(skb
, reg_desc
.datalen
);
633 dump_skb(skb
, DUMP_SKB_LEN
, (char *)__func__
, ndev
, ndev
, 0);
635 // parse protocol header
636 skb
->dev
= g_net_dev
[ndev
];
637 skb
->protocol
= eth_type_trans(skb
, skb
->dev
);
639 g_net_dev
[ndev
]->last_rx
= jiffies
;
641 netif_rx_ret
= netif_receive_skb(skb
);
643 if ( netif_rx_ret
!= NET_RX_DROP
) {
644 g_ptm_priv_data
.itf
[ndev
].stats
.rx_packets
++;
645 g_ptm_priv_data
.itf
[ndev
].stats
.rx_bytes
+= reg_desc
.datalen
;
648 reg_desc
.dataptr
= ((unsigned int)new_skb
->data
>> 2) & 0x0FFFFFFF;
649 reg_desc
.byteoff
= RX_HEAD_MAC_ADDR_ALIGNMENT
;
655 reg_desc
.datalen
= rx_max_packet_size
;
663 mailbox_signal(ndev
, 0);
670 static irqreturn_t
mailbox_irq_handler(int irq
, void *dev_id
)
675 isr
= IFX_REG_R32(MBOX_IGU1_ISR
);
676 IFX_REG_W32(isr
, MBOX_IGU1_ISRC
);
677 isr
&= IFX_REG_R32(MBOX_IGU1_IER
);
679 while ( (i
= __fls(isr
)) >= 0 ) {
684 IFX_REG_W32_MASK(1 << i
, 0, MBOX_IGU1_IER
);
686 if ( i
< MAX_ITF_NUMBER
)
687 netif_wake_queue(g_net_dev
[i
]);
691 #ifdef CONFIG_IFX_PTM_RX_INTERRUPT
692 while ( WRX_DMA_CHANNEL_CONFIG(i
)->vlddes
> 0 )
693 mailbox_rx_irq_handler(i
);
695 IFX_REG_W32_MASK(1 << i
, 0, MBOX_IGU1_IER
);
696 napi_schedule(&g_ptm_priv_data
.itf
[i
].napi
);
704 static INLINE
void mailbox_signal(unsigned int itf
, int is_tx
)
709 while ( MBOX_IGU3_ISR_ISR(itf
+ 16) && count
> 0 )
711 IFX_REG_W32(MBOX_IGU3_ISRS_SET(itf
+ 16), MBOX_IGU3_ISRS
);
714 while ( MBOX_IGU3_ISR_ISR(itf
) && count
> 0 )
716 IFX_REG_W32(MBOX_IGU3_ISRS_SET(itf
), MBOX_IGU3_ISRS
);
719 ASSERT(count
!= 0, "MBOX_IGU3_ISR = 0x%08x", IFX_REG_R32(MBOX_IGU3_ISR
));
722 #ifdef CONFIG_IFX_PTM_RX_TASKLET
723 static void do_ptm_tasklet(unsigned long arg
)
725 unsigned int work_to_do
= 25;
726 unsigned int work_done
= 0;
728 ASSERT(arg
>= 0 && arg
< ARRAY_SIZE(g_net_dev
), "arg = %lu (wrong value)", arg
);
730 while ( work_done
< work_to_do
&& WRX_DMA_CHANNEL_CONFIG(arg
)->vlddes
> 0 ) {
731 if ( mailbox_rx_irq_handler(arg
) < 0 )
738 if ( !netif_running(g_net_dev
[arg
]) )
742 if ( WRX_DMA_CHANNEL_CONFIG(arg
)->vlddes
== 0 ) {
744 IFX_REG_W32_MASK(0, 1 << arg
, MBOX_IGU1_ISRC
);
746 if ( WRX_DMA_CHANNEL_CONFIG(arg
)->vlddes
== 0 ) {
747 IFX_REG_W32_MASK(0, 1 << arg
, MBOX_IGU1_IER
);
753 tasklet_schedule(&g_ptm_tasklet
[arg
]);
757 #if defined(DEBUG_DUMP_SKB) && DEBUG_DUMP_SKB
758 static void dump_skb(struct sk_buff
*skb
, u32 len
, char *title
, int port
, int ch
, int is_tx
)
762 if ( !(ifx_ptm_dbg_enable
& (is_tx
? DBG_ENABLE_MASK_DUMP_SKB_TX
: DBG_ENABLE_MASK_DUMP_SKB_RX
)) )
765 if ( skb
->len
< len
)
768 if ( len
> rx_max_packet_size
) {
769 printk("too big data length: skb = %08x, skb->data = %08x, skb->len = %d\n", (u32
)skb
, (u32
)skb
->data
, skb
->len
);
774 printk("%s (port %d, ch %d)\n", title
, port
, ch
);
776 printk("%s\n", title
);
777 printk(" skb->data = %08X, skb->tail = %08X, skb->len = %d\n", (u32
)skb
->data
, (u32
)skb
->tail
, (int)skb
->len
);
778 for ( i
= 1; i
<= len
; i
++ ) {
780 printk(" %4d:", i
- 1);
781 printk(" %02X", (int)(*((char*)skb
->data
+ i
- 1) & 0xFF));
785 if ( (i
- 1) % 16 != 0 )
790 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
791 static void skb_swap(struct sk_buff
*skb
)
793 unsigned char tmp
[8];
794 unsigned char *p
= skb
->data
;
796 if ( !(p
[0] & 0x01) ) { // bypass broadcast/multicast
800 memcpy(p
+ 6, tmp
, 6);
804 while ( p
[0] == 0x81 && p
[1] == 0x00 )
808 if ( p
[0] == 0x08 && p
[1] == 0x00 ) {
812 memcpy(p
+ 4, tmp
, 4);
816 dma_cache_wback((unsigned long)skb
->data
, (unsigned long)p
- (unsigned long)skb
->data
);
821 static INLINE
void proc_file_create(void)
823 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
824 struct proc_dir_entry
*res
;
826 g_ptm_dir
= proc_mkdir("driver/ifx_ptm", NULL
);
828 create_proc_read_entry("version",
834 res
= create_proc_entry("wanmib",
838 res
->read_proc
= proc_read_wanmib
;
839 res
->write_proc
= proc_write_wanmib
;
842 #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
843 create_proc_read_entry("genconf",
850 create_proc_read_entry("regs",
853 ifx_ptm_proc_read_regs
,
858 res
= create_proc_entry("dbg",
862 res
->read_proc
= proc_read_dbg
;
863 res
->write_proc
= proc_write_dbg
;
868 static INLINE
void proc_file_delete(void)
870 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
871 remove_proc_entry("dbg", g_ptm_dir
);
874 #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
876 remove_proc_entry("regs", g_ptm_dir
);
879 remove_proc_entry("genconf", g_ptm_dir
);
882 remove_proc_entry("wanmib", g_ptm_dir
);
884 remove_proc_entry("version", g_ptm_dir
);
886 remove_proc_entry("driver/ifx_ptm", NULL
);
889 static int proc_read_version(char *buf
, char **start
, off_t offset
, int count
, int *eof
, void *data
)
893 len
+= ifx_ptm_version(buf
+ len
);
895 if ( offset
>= len
) {
900 *start
= buf
+ offset
;
901 if ( (len
-= offset
) > count
)
907 static int proc_read_wanmib(char *page
, char **start
, off_t off
, int count
, int *eof
, void *data
)
916 for ( i
= 0; i
< ARRAY_SIZE(title
); i
++ ) {
917 len
+= sprintf(page
+ off
+ len
, title
[i
]);
918 len
+= sprintf(page
+ off
+ len
, " wrx_correct_pdu = %d\n", WAN_MIB_TABLE
[i
].wrx_correct_pdu
);
919 len
+= sprintf(page
+ off
+ len
, " wrx_correct_pdu_bytes = %d\n", WAN_MIB_TABLE
[i
].wrx_correct_pdu_bytes
);
920 len
+= sprintf(page
+ off
+ len
, " wrx_tccrc_err_pdu = %d\n", WAN_MIB_TABLE
[i
].wrx_tccrc_err_pdu
);
921 len
+= sprintf(page
+ off
+ len
, " wrx_tccrc_err_pdu_bytes = %d\n", WAN_MIB_TABLE
[i
].wrx_tccrc_err_pdu_bytes
);
922 len
+= sprintf(page
+ off
+ len
, " wrx_ethcrc_err_pdu = %d\n", WAN_MIB_TABLE
[i
].wrx_ethcrc_err_pdu
);
923 len
+= sprintf(page
+ off
+ len
, " wrx_ethcrc_err_pdu_bytes = %d\n", WAN_MIB_TABLE
[i
].wrx_ethcrc_err_pdu_bytes
);
924 len
+= sprintf(page
+ off
+ len
, " wrx_nodesc_drop_pdu = %d\n", WAN_MIB_TABLE
[i
].wrx_nodesc_drop_pdu
);
925 len
+= sprintf(page
+ off
+ len
, " wrx_len_violation_drop_pdu = %d\n", WAN_MIB_TABLE
[i
].wrx_len_violation_drop_pdu
);
926 len
+= sprintf(page
+ off
+ len
, " wrx_idle_bytes = %d\n", WAN_MIB_TABLE
[i
].wrx_idle_bytes
);
927 len
+= sprintf(page
+ off
+ len
, " wrx_nonidle_cw = %d\n", WAN_MIB_TABLE
[i
].wrx_nonidle_cw
);
928 len
+= sprintf(page
+ off
+ len
, " wrx_idle_cw = %d\n", WAN_MIB_TABLE
[i
].wrx_idle_cw
);
929 len
+= sprintf(page
+ off
+ len
, " wrx_err_cw = %d\n", WAN_MIB_TABLE
[i
].wrx_err_cw
);
930 len
+= sprintf(page
+ off
+ len
, " wtx_total_pdu = %d\n", WAN_MIB_TABLE
[i
].wtx_total_pdu
);
931 len
+= sprintf(page
+ off
+ len
, " wtx_total_bytes = %d\n", WAN_MIB_TABLE
[i
].wtx_total_bytes
);
939 static int proc_write_wanmib(struct file
*file
, const char *buf
, unsigned long count
, void *data
)
947 len
= count
< sizeof(str
) ? count
: sizeof(str
) - 1;
948 rlen
= len
- copy_from_user(str
, buf
, len
);
949 while ( rlen
&& str
[rlen
- 1] <= ' ' )
952 for ( p
= str
; *p
&& *p
<= ' '; p
++, rlen
-- );
956 if ( stricmp(p
, "clear") == 0 || stricmp(p
, "clean") == 0 ) {
957 for ( i
= 0; i
< 2; i
++ )
958 memset((void*)&WAN_MIB_TABLE
[i
], 0, sizeof(WAN_MIB_TABLE
[i
]));
964 #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
966 static int proc_read_genconf(char *page
, char **start
, off_t off
, int count
, int *eof
, void *data
)
969 int len_max
= off
+ count
;
976 pstr
= *start
= page
;
980 llen
+= sprintf(str
+ llen
, "CFG_WAN_WRDES_DELAY (0x%08X): %d\n", (unsigned int)CFG_WAN_WRDES_DELAY
, IFX_REG_R32(CFG_WAN_WRDES_DELAY
));
981 llen
+= sprintf(str
+ llen
, "CFG_WRX_DMACH_ON (0x%08X):", (unsigned int)CFG_WRX_DMACH_ON
);
982 for ( i
= 0, bit
= 1; i
< MAX_RX_DMA_CHANNEL_NUMBER
; i
++, bit
<<= 1 )
983 llen
+= sprintf(str
+ llen
, " %d - %s", i
, (IFX_REG_R32(CFG_WRX_DMACH_ON
) & bit
) ? "on " : "off");
984 llen
+= sprintf(str
+ llen
, "\n");
985 llen
+= sprintf(str
+ llen
, "CFG_WTX_DMACH_ON (0x%08X):", (unsigned int)CFG_WTX_DMACH_ON
);
986 for ( i
= 0, bit
= 1; i
< MAX_TX_DMA_CHANNEL_NUMBER
; i
++, bit
<<= 1 )
987 llen
+= sprintf(str
+ llen
, " %d - %s", i
, (IFX_REG_R32(CFG_WTX_DMACH_ON
) & bit
) ? "on " : "off");
988 llen
+= sprintf(str
+ llen
, "\n");
989 llen
+= sprintf(str
+ llen
, "CFG_WRX_LOOK_BITTH (0x%08X): %d\n", (unsigned int)CFG_WRX_LOOK_BITTH
, IFX_REG_R32(CFG_WRX_LOOK_BITTH
));
990 llen
+= sprintf(str
+ llen
, "CFG_ETH_EFMTC_CRC (0x%08X): rx_tc_crc_len - %2d, rx_tc_crc_check - %s\n", (unsigned int)CFG_ETH_EFMTC_CRC
, CFG_ETH_EFMTC_CRC
->rx_tc_crc_len
, CFG_ETH_EFMTC_CRC
->rx_tc_crc_check
? " on" : "off");
991 llen
+= sprintf(str
+ llen
, " rx_eth_crc_check - %s, rx_eth_crc_present - %s\n", CFG_ETH_EFMTC_CRC
->rx_eth_crc_check
? " on" : "off", CFG_ETH_EFMTC_CRC
->rx_eth_crc_present
? " on" : "off");
992 llen
+= sprintf(str
+ llen
, " tx_tc_crc_len - %2d, tx_tc_crc_gen - %s\n", CFG_ETH_EFMTC_CRC
->tx_tc_crc_len
, CFG_ETH_EFMTC_CRC
->tx_tc_crc_gen
? " on" : "off");
993 llen
+= sprintf(str
+ llen
, " tx_eth_crc_gen - %s\n", CFG_ETH_EFMTC_CRC
->tx_eth_crc_gen
? " on" : "off");
995 llen
+= sprintf(str
+ llen
, "RX Port:\n");
996 for ( i
= 0; i
< MAX_RX_DMA_CHANNEL_NUMBER
; i
++ )
997 llen
+= sprintf(str
+ llen
, " %d (0x%08X). mfs - %5d, dmach - %d, local_state - %d, partner_state - %d\n", i
, (unsigned int)WRX_PORT_CONFIG(i
), WRX_PORT_CONFIG(i
)->mfs
, WRX_PORT_CONFIG(i
)->dmach
, WRX_PORT_CONFIG(i
)->local_state
, WRX_PORT_CONFIG(i
)->partner_state
);
998 llen
+= sprintf(str
+ llen
, "RX DMA Channel:\n");
999 for ( i
= 0; i
< MAX_RX_DMA_CHANNEL_NUMBER
; i
++ )
1000 llen
+= sprintf(str
+ llen
, " %d (0x%08X). desba - 0x%08X (0x%08X), deslen - %d, vlddes - %d\n", i
, (unsigned int)WRX_DMA_CHANNEL_CONFIG(i
), WRX_DMA_CHANNEL_CONFIG(i
)->desba
, ((unsigned int)WRX_DMA_CHANNEL_CONFIG(i
)->desba
<< 2) | KSEG1
, WRX_DMA_CHANNEL_CONFIG(i
)->deslen
, WRX_DMA_CHANNEL_CONFIG(i
)->vlddes
);
1002 llen
+= sprintf(str
+ llen
, "TX Port:\n");
1003 for ( i
= 0; i
< MAX_TX_DMA_CHANNEL_NUMBER
; i
++ )
1004 llen
+= sprintf(str
+ llen
, " %d (0x%08X). tx_cwth2 - %d, tx_cwth1 - %d\n", i
, (unsigned int)WTX_PORT_CONFIG(i
), WTX_PORT_CONFIG(i
)->tx_cwth2
, WTX_PORT_CONFIG(i
)->tx_cwth1
);
1005 llen
+= sprintf(str
+ llen
, "TX DMA Channel:\n");
1006 for ( i
= 0; i
< MAX_TX_DMA_CHANNEL_NUMBER
; i
++ )
1007 llen
+= sprintf(str
+ llen
, " %d (0x%08X). desba - 0x%08X (0x%08X), deslen - %d, vlddes - %d\n", i
, (unsigned int)WTX_DMA_CHANNEL_CONFIG(i
), WTX_DMA_CHANNEL_CONFIG(i
)->desba
, ((unsigned int)WTX_DMA_CHANNEL_CONFIG(i
)->desba
<< 2) | KSEG1
, WTX_DMA_CHANNEL_CONFIG(i
)->deslen
, WTX_DMA_CHANNEL_CONFIG(i
)->vlddes
);
1009 if ( len
<= off
&& len
+ llen
> off
)
1011 memcpy(pstr
, str
+ off
- len
, len
+ llen
- off
);
1012 pstr
+= len
+ llen
- off
;
1014 else if ( len
> off
)
1016 memcpy(pstr
, str
, llen
);
1020 if ( len
>= len_max
)
1021 goto PROC_READ_GENCONF_OVERRUN_END
;
1027 PROC_READ_GENCONF_OVERRUN_END
:
1028 return len
- llen
- off
;
1031 #endif // defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
1033 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
1035 static int proc_read_dbg(char *page
, char **start
, off_t off
, int count
, int *eof
, void *data
)
1039 len
+= sprintf(page
+ off
+ len
, "error print - %s\n", (ifx_ptm_dbg_enable
& DBG_ENABLE_MASK_ERR
) ? "enabled" : "disabled");
1040 len
+= sprintf(page
+ off
+ len
, "debug print - %s\n", (ifx_ptm_dbg_enable
& DBG_ENABLE_MASK_DEBUG_PRINT
) ? "enabled" : "disabled");
1041 len
+= sprintf(page
+ off
+ len
, "assert - %s\n", (ifx_ptm_dbg_enable
& DBG_ENABLE_MASK_ASSERT
) ? "enabled" : "disabled");
1042 len
+= sprintf(page
+ off
+ len
, "dump rx skb - %s\n", (ifx_ptm_dbg_enable
& DBG_ENABLE_MASK_DUMP_SKB_RX
) ? "enabled" : "disabled");
1043 len
+= sprintf(page
+ off
+ len
, "dump tx skb - %s\n", (ifx_ptm_dbg_enable
& DBG_ENABLE_MASK_DUMP_SKB_TX
) ? "enabled" : "disabled");
1044 len
+= sprintf(page
+ off
+ len
, "mac swap - %s\n", (ifx_ptm_dbg_enable
& DBG_ENABLE_MASK_MAC_SWAP
) ? "enabled" : "disabled");
1051 static int proc_write_dbg(struct file
*file
, const char *buf
, unsigned long count
, void *data
)
1053 static const char *dbg_enable_mask_str
[] = {
1072 static const int dbg_enable_mask_str_len
[] = {
1083 unsigned int dbg_enable_mask
[] = {
1084 DBG_ENABLE_MASK_ERR
,
1085 DBG_ENABLE_MASK_DEBUG_PRINT
,
1086 DBG_ENABLE_MASK_ASSERT
,
1087 DBG_ENABLE_MASK_DUMP_SKB_RX
,
1088 DBG_ENABLE_MASK_DUMP_SKB_TX
,
1089 DBG_ENABLE_MASK_DUMP_INIT
,
1090 DBG_ENABLE_MASK_DUMP_QOS
,
1091 DBG_ENABLE_MASK_MAC_SWAP
,
1103 len
= count
< sizeof(str
) ? count
: sizeof(str
) - 1;
1104 rlen
= len
- copy_from_user(str
, buf
, len
);
1105 while ( rlen
&& str
[rlen
- 1] <= ' ' )
1108 for ( p
= str
; *p
&& *p
<= ' '; p
++, rlen
-- );
1112 // debugging feature for enter/leave showtime
1113 if ( strincmp(p
, "enter", 5) == 0 && ifx_mei_atm_showtime_enter
!= NULL
)
1114 ifx_mei_atm_showtime_enter(NULL
, NULL
);
1115 else if ( strincmp(p
, "leave", 5) == 0 && ifx_mei_atm_showtime_exit
!= NULL
)
1116 ifx_mei_atm_showtime_exit();
1118 if ( strincmp(p
, "enable", 6) == 0 ) {
1122 else if ( strincmp(p
, "disable", 7) == 0 ) {
1126 else if ( strincmp(p
, "help", 4) == 0 || *p
== '?' ) {
1127 printk("echo <enable/disable> [err/dbg/assert/rx/tx/init/qos/swap/all] > /proc/driver/ifx_ptm/dbg\n");
1133 ifx_ptm_dbg_enable
|= DBG_ENABLE_MASK_ALL
& ~DBG_ENABLE_MASK_MAC_SWAP
;
1135 ifx_ptm_dbg_enable
&= ~DBG_ENABLE_MASK_ALL
| DBG_ENABLE_MASK_MAC_SWAP
;
1139 for ( i
= 0; i
< ARRAY_SIZE(dbg_enable_mask_str
); i
++ )
1140 if ( strincmp(p
, dbg_enable_mask_str
[i
], dbg_enable_mask_str_len
[i
]) == 0 ) {
1142 ifx_ptm_dbg_enable
|= dbg_enable_mask
[i
>> 1];
1144 ifx_ptm_dbg_enable
&= ~dbg_enable_mask
[i
>> 1];
1145 p
+= dbg_enable_mask_str_len
[i
];
1148 } while ( i
< ARRAY_SIZE(dbg_enable_mask_str
) );
1155 #endif // defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
1157 static INLINE
int stricmp(const char *p1
, const char *p2
)
1161 while ( *p1
&& *p2
)
1163 c1
= *p1
>= 'A' && *p1
<= 'Z' ? *p1
+ 'a' - 'A' : *p1
;
1164 c2
= *p2
>= 'A' && *p2
<= 'Z' ? *p2
+ 'a' - 'A' : *p2
;
1174 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
1175 static INLINE
int strincmp(const char *p1
, const char *p2
, int n
)
1179 while ( n
&& *p1
&& *p2
)
1181 c1
= *p1
>= 'A' && *p1
<= 'Z' ? *p1
+ 'a' - 'A' : *p1
;
1182 c2
= *p2
>= 'A' && *p2
<= 'Z' ? *p2
+ 'a' - 'A' : *p2
;
1190 return n
? *p1
- *p2
: c1
;
1194 static INLINE
int ifx_ptm_version(char *buf
)
1197 unsigned int major
, minor
;
1199 ifx_ptm_get_fw_ver(&major
, &minor
);
1201 len
+= sprintf(buf
+ len
, "PTM %d.%d.%d", IFX_PTM_VER_MAJOR
, IFX_PTM_VER_MID
, IFX_PTM_VER_MINOR
);
1202 len
+= sprintf(buf
+ len
, " PTM (E1) firmware version %d.%d\n", major
, minor
);
1207 static INLINE
void check_parameters(void)
1209 /* There is a delay between PPE write descriptor and descriptor is */
1210 /* really stored in memory. Host also has this delay when writing */
1211 /* descriptor. So PPE will use this value to determine if the write */
1212 /* operation makes effect. */
1213 if ( write_desc_delay
< 0 )
1214 write_desc_delay
= 0;
1216 /* Because of the limitation of length field in descriptors, the packet */
1217 /* size could not be larger than 64K minus overhead size. */
1218 if ( rx_max_packet_size
< ETH_MIN_FRAME_LENGTH
)
1219 rx_max_packet_size
= ETH_MIN_FRAME_LENGTH
;
1220 else if ( rx_max_packet_size
> 65536 - 1 )
1221 rx_max_packet_size
= 65536 - 1;
1223 if ( dma_rx_descriptor_length
< 2 )
1224 dma_rx_descriptor_length
= 2;
1225 if ( dma_tx_descriptor_length
< 2 )
1226 dma_tx_descriptor_length
= 2;
1229 static INLINE
int init_priv_data(void)
1233 struct rx_descriptor rx_desc
= {0};
1234 struct sk_buff
*skb
;
1235 volatile struct rx_descriptor
*p_rx_desc
;
1236 volatile struct tx_descriptor
*p_tx_desc
;
1237 struct sk_buff
**ppskb
;
1239 // clear ptm private data structure
1240 memset(&g_ptm_priv_data
, 0, sizeof(g_ptm_priv_data
));
1242 // allocate memory for RX descriptors
1243 p
= kzalloc(MAX_ITF_NUMBER
* dma_rx_descriptor_length
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
, GFP_KERNEL
);
1246 dma_cache_inv((unsigned long)p
, MAX_ITF_NUMBER
* dma_rx_descriptor_length
* sizeof(struct rx_descriptor
) + DESC_ALIGNMENT
);
1247 g_ptm_priv_data
.rx_desc_base
= p
;
1248 //p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1250 // allocate memory for TX descriptors
1251 p
= kzalloc(MAX_ITF_NUMBER
* dma_tx_descriptor_length
* sizeof(struct tx_descriptor
) + DESC_ALIGNMENT
, GFP_KERNEL
);
1254 dma_cache_inv((unsigned long)p
, MAX_ITF_NUMBER
* dma_tx_descriptor_length
* sizeof(struct tx_descriptor
) + DESC_ALIGNMENT
);
1255 g_ptm_priv_data
.tx_desc_base
= p
;
1257 // allocate memroy for TX skb pointers
1258 p
= kzalloc(MAX_ITF_NUMBER
* dma_tx_descriptor_length
* sizeof(struct sk_buff
*) + 4, GFP_KERNEL
);
1261 dma_cache_wback_inv((unsigned long)p
, MAX_ITF_NUMBER
* dma_tx_descriptor_length
* sizeof(struct sk_buff
*) + 4);
1262 g_ptm_priv_data
.tx_skb_base
= p
;
1264 p_rx_desc
= (volatile struct rx_descriptor
*)((((unsigned int)g_ptm_priv_data
.rx_desc_base
+ DESC_ALIGNMENT
- 1) & ~(DESC_ALIGNMENT
- 1)) | KSEG1
);
1265 p_tx_desc
= (volatile struct tx_descriptor
*)((((unsigned int)g_ptm_priv_data
.tx_desc_base
+ DESC_ALIGNMENT
- 1) & ~(DESC_ALIGNMENT
- 1)) | KSEG1
);
1266 ppskb
= (struct sk_buff
**)(((unsigned int)g_ptm_priv_data
.tx_skb_base
+ 3) & ~3);
1267 for ( i
= 0; i
< MAX_ITF_NUMBER
; i
++ ) {
1268 g_ptm_priv_data
.itf
[i
].rx_desc
= &p_rx_desc
[i
* dma_rx_descriptor_length
];
1269 g_ptm_priv_data
.itf
[i
].tx_desc
= &p_tx_desc
[i
* dma_tx_descriptor_length
];
1270 g_ptm_priv_data
.itf
[i
].tx_skb
= &ppskb
[i
* dma_tx_descriptor_length
];
1277 rx_desc
.byteoff
= RX_HEAD_MAC_ADDR_ALIGNMENT
;
1280 rx_desc
.datalen
= rx_max_packet_size
;
1281 for ( i
= 0; i
< MAX_ITF_NUMBER
* dma_rx_descriptor_length
; i
++ ) {
1282 skb
= alloc_skb_rx();
1285 rx_desc
.dataptr
= ((unsigned int)skb
->data
>> 2) & 0x0FFFFFFF;
1286 p_rx_desc
[i
] = rx_desc
;
1292 static INLINE
void clear_priv_data(void)
1295 struct sk_buff
*skb
;
1297 for ( i
= 0; i
< MAX_ITF_NUMBER
; i
++ ) {
1298 if ( g_ptm_priv_data
.itf
[i
].tx_skb
!= NULL
) {
1299 for ( j
= 0; j
< dma_tx_descriptor_length
; j
++ )
1300 if ( g_ptm_priv_data
.itf
[i
].tx_skb
[j
] != NULL
)
1301 dev_kfree_skb_any(g_ptm_priv_data
.itf
[i
].tx_skb
[j
]);
1303 if ( g_ptm_priv_data
.itf
[i
].rx_desc
!= NULL
) {
1304 for ( j
= 0; j
< dma_rx_descriptor_length
; j
++ ) {
1305 if ( g_ptm_priv_data
.itf
[i
].rx_desc
[j
].sop
|| g_ptm_priv_data
.itf
[i
].rx_desc
[j
].eop
) { // descriptor initialized
1306 skb
= get_skb_rx_pointer(g_ptm_priv_data
.itf
[i
].rx_desc
[j
].dataptr
);
1307 dev_kfree_skb_any(skb
);
1313 if ( g_ptm_priv_data
.rx_desc_base
!= NULL
)
1314 kfree(g_ptm_priv_data
.rx_desc_base
);
1316 if ( g_ptm_priv_data
.tx_desc_base
!= NULL
)
1317 kfree(g_ptm_priv_data
.tx_desc_base
);
1319 if ( g_ptm_priv_data
.tx_skb_base
!= NULL
)
1320 kfree(g_ptm_priv_data
.tx_skb_base
);
1323 static INLINE
void init_tables(void)
1326 volatile unsigned int *p
;
1327 struct wrx_dma_channel_config rx_config
= {0};
1328 struct wtx_dma_channel_config tx_config
= {0};
1329 struct wrx_port_cfg_status rx_port_cfg
= { 0 };
1330 struct wtx_port_cfg tx_port_cfg
= { 0 };
1335 IFX_REG_W32(CDM_CFG_RAM1_SET(0x00) | CDM_CFG_RAM0_SET(0x00), CDM_CFG
); // CDM block 1 must be data memory and mapped to 0x5000 (dword addr)
1336 p
= CDM_DATA_MEMORY(0, 0); // Clear CDM block 1
1337 for ( i
= 0; i
< CDM_DATA_MEMORY_DWLEN
; i
++, p
++ )
1343 IFX_REG_W32(write_desc_delay
, CFG_WAN_WRDES_DELAY
);
1344 IFX_REG_W32((1 << MAX_RX_DMA_CHANNEL_NUMBER
) - 1, CFG_WRX_DMACH_ON
);
1345 IFX_REG_W32((1 << MAX_TX_DMA_CHANNEL_NUMBER
) - 1, CFG_WTX_DMACH_ON
);
1347 IFX_REG_W32(8, CFG_WRX_LOOK_BITTH
); // WAN RX EFM-TC Looking Threshold
1349 IFX_REG_W32(eth_efmtc_crc_cfg
, CFG_ETH_EFMTC_CRC
);
1352 * WRX DMA Channel Configuration Table
1354 rx_config
.deslen
= dma_rx_descriptor_length
;
1355 rx_port_cfg
.mfs
= ETH_MAX_FRAME_LENGTH
;
1356 rx_port_cfg
.local_state
= 0; // looking for sync
1357 rx_port_cfg
.partner_state
= 0; // parter receiver is out of sync
1359 for ( i
= 0; i
< MAX_RX_DMA_CHANNEL_NUMBER
; i
++ ) {
1360 rx_config
.desba
= ((unsigned int)g_ptm_priv_data
.itf
[i
].rx_desc
>> 2) & 0x0FFFFFFF;
1361 *WRX_DMA_CHANNEL_CONFIG(i
) = rx_config
;
1363 rx_port_cfg
.dmach
= i
;
1364 *WRX_PORT_CONFIG(i
) = rx_port_cfg
;
1368 * WTX DMA Channel Configuration Table
1370 tx_config
.deslen
= dma_tx_descriptor_length
;
1371 tx_port_cfg
.tx_cwth1
= 5;
1372 tx_port_cfg
.tx_cwth2
= 4;
1374 for ( i
= 0; i
< MAX_TX_DMA_CHANNEL_NUMBER
; i
++ ) {
1375 tx_config
.desba
= ((unsigned int)g_ptm_priv_data
.itf
[i
].tx_desc
>> 2) & 0x0FFFFFFF;
1376 *WTX_DMA_CHANNEL_CONFIG(i
) = tx_config
;
1378 *WTX_PORT_CONFIG(i
) = tx_port_cfg
;
1385 * ####################################
1387 * ####################################
1390 static int ptm_showtime_enter(struct port_cell_info
*port_cell
, void *xdata_addr
)
1396 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ )
1397 netif_carrier_on(g_net_dev
[i
]);
1399 printk("enter showtime\n");
1404 static int ptm_showtime_exit(void)
1411 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ )
1412 netif_carrier_off(g_net_dev
[i
]);
1416 printk("leave showtime\n");
1424 * ####################################
1426 * ####################################
1431 * Initialize global variables, PP32, comunication structures, register IRQ
1432 * and register device.
1437 * else --- failure, usually it is negative value of error code
1439 static int ifx_ptm_init(void)
1442 struct port_cell_info port_cell
= {0};
1443 void *xdata_addr
= NULL
;
1449 ret
= init_priv_data();
1451 err("INIT_PRIV_DATA_FAIL");
1452 goto INIT_PRIV_DATA_FAIL
;
1455 ifx_ptm_init_chip();
1458 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ ) {
1459 g_net_dev
[i
] = alloc_netdev(0, g_net_dev_name
[i
], NET_NAME_UNKNOWN
, ether_setup
);
1460 if ( g_net_dev
[i
] == NULL
)
1461 goto ALLOC_NETDEV_FAIL
;
1462 ptm_setup(g_net_dev
[i
], i
);
1465 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ ) {
1466 ret
= register_netdev(g_net_dev
[i
]);
1468 goto REGISTER_NETDEV_FAIL
;
1471 /* register interrupt handler */
1472 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0)
1473 ret
= request_irq(PPE_MAILBOX_IGU1_INT
, mailbox_irq_handler
, 0, "ptm_mailbox_isr", &g_ptm_priv_data
);
1475 ret
= request_irq(PPE_MAILBOX_IGU1_INT
, mailbox_irq_handler
, IRQF_DISABLED
, "ptm_mailbox_isr", &g_ptm_priv_data
);
1478 if ( ret
== -EBUSY
) {
1479 err("IRQ may be occupied by other driver, please reconfig to disable it.");
1482 err("request_irq fail");
1484 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL
;
1486 disable_irq(PPE_MAILBOX_IGU1_INT
);
1488 ret
= ifx_pp32_start(0);
1490 err("ifx_pp32_start fail!");
1491 goto PP32_START_FAIL
;
1493 IFX_REG_W32(0, MBOX_IGU1_IER
);
1494 IFX_REG_W32(~0, MBOX_IGU1_ISRC
);
1496 enable_irq(PPE_MAILBOX_IGU1_INT
);
1501 port_cell
.port_num
= 1;
1502 ifx_mei_atm_showtime_check(&g_showtime
, &port_cell
, &xdata_addr
);
1504 ifx_mei_atm_showtime_enter
= ptm_showtime_enter
;
1505 ifx_mei_atm_showtime_exit
= ptm_showtime_exit
;
1507 ifx_ptm_version(ver_str
);
1508 printk(KERN_INFO
"%s", ver_str
);
1510 printk("ifxmips_ptm: PTM init succeed\n");
1515 free_irq(PPE_MAILBOX_IGU1_INT
, &g_ptm_priv_data
);
1516 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL
:
1517 i
= ARRAY_SIZE(g_net_dev
);
1518 REGISTER_NETDEV_FAIL
:
1520 unregister_netdev(g_net_dev
[i
]);
1521 i
= ARRAY_SIZE(g_net_dev
);
1524 free_netdev(g_net_dev
[i
]);
1525 g_net_dev
[i
] = NULL
;
1527 INIT_PRIV_DATA_FAIL
:
1529 printk("ifxmips_ptm: PTM init failed\n");
1535 * Release memory, free IRQ, and deregister device.
1541 static void __exit
ifx_ptm_exit(void)
1545 ifx_mei_atm_showtime_enter
= NULL
;
1546 ifx_mei_atm_showtime_exit
= NULL
;
1553 free_irq(PPE_MAILBOX_IGU1_INT
, &g_ptm_priv_data
);
1555 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ )
1556 unregister_netdev(g_net_dev
[i
]);
1558 for ( i
= 0; i
< ARRAY_SIZE(g_net_dev
); i
++ ) {
1559 free_netdev(g_net_dev
[i
]);
1560 g_net_dev
[i
] = NULL
;
1563 ifx_ptm_uninit_chip();
1568 module_init(ifx_ptm_init
);
1569 module_exit(ifx_ptm_exit
);