package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch

   1 --- /dev/null
   2 +++ b/configs/mt7622_ubnt_unifi-6-lr_defconfig
   3 @@ -0,0 +1,147 @@
   4 +CONFIG_ARM=y
   5 +CONFIG_POSITION_INDEPENDENT=y
   6 +CONFIG_ARCH_MEDIATEK=y
   7 +CONFIG_TARGET_MT7622=y
   8 +CONFIG_SYS_TEXT_BASE=0x41e00000
   9 +CONFIG_SYS_MALLOC_F_LEN=0x4000
  10 +CONFIG_SYS_LOAD_ADDR=0x40080000
  11 +CONFIG_USE_DEFAULT_ENV_FILE=y
  12 +CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:128k(bl2),640k(fip),64k(u-boot-env),256k(factory),64k(eeprom),15232k(recovery),-(firmware)"
  13 +CONFIG_ENV_IS_IN_MTD=y
  14 +CONFIG_ENV_MTD_NAME="nor0"
  15 +CONFIG_ENV_SIZE_REDUND=0x4000
  16 +CONFIG_ENV_SIZE=0x4000
  17 +CONFIG_ENV_OFFSET=0xc0000
  18 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
  19 +CONFIG_BOARD_LATE_INIT=y
  20 +CONFIG_RESET_BUTTON_SETTLE_DELAY=400
  21 +CONFIG_BOOTP_SEND_HOSTNAME=y
  22 +CONFIG_DEFAULT_ENV_FILE="ubnt_unifi-6-lr_env"
  23 +CONFIG_DEBUG_UART_BASE=0x11002000
  24 +CONFIG_DEBUG_UART_CLOCK=25000000
  25 +CONFIG_DEFAULT_DEVICE_TREE="mt7622-ubnt-unifi-6-lr"
  26 +CONFIG_DEBUG_UART=y
  27 +CONFIG_SMBIOS_PRODUCT_NAME=""
  28 +CONFIG_AUTOBOOT_KEYED=y
  29 +CONFIG_BOOTDELAY=30
  30 +CONFIG_AUTOBOOT_MENU_SHOW=y
  31 +CONFIG_CFB_CONSOLE_ANSI=y
  32 +CONFIG_BUTTON=y
  33 +CONFIG_BUTTON_GPIO=y
  34 +CONFIG_GPIO_HOG=y
  35 +CONFIG_CMD_ENV_FLAGS=y
  36 +CONFIG_FIT=y
  37 +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
  38 +CONFIG_LOGLEVEL=7
  39 +CONFIG_LOG=y
  40 +CONFIG_DEFAULT_FDT_FILE="mt7622-ubnt-unifi-6-lr"
  41 +CONFIG_SYS_PROMPT="MT7622> "
  42 +# CONFIG_LEGACY_IMAGE_FORMAT is not set
  43 +# CONFIG_BOOTM_PLAN9 is not set
  44 +# CONFIG_BOOTM_RTEMS is not set
  45 +# CONFIG_BOOTM_VXWORKS is not set
  46 +# CONFIG_EFI is not set
  47 +# CONFIG_EFI_LOADER is not set
  48 +CONFIG_CMD_BOOTMENU=y
  49 +# CONFIG_CMD_BOOTEFI is not set
  50 +CONFIG_CMD_BOOTP=y
  51 +CONFIG_CMD_BUTTON=y
  52 +CONFIG_CMD_CDP=y
  53 +CONFIG_CMD_DHCP=y
  54 +CONFIG_CMD_DNS=y
  55 +CONFIG_CMD_ECHO=y
  56 +# CONFIG_CMD_ELF is not set
  57 +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
  58 +CONFIG_CMD_ENV_READMEM=y
  59 +CONFIG_CMD_ERASEENV=y
  60 +CONFIG_CMD_GPIO=y
  61 +CONFIG_CMD_HASH=y
  62 +CONFIG_CMD_ITEST=y
  63 +CONFIG_CMD_LED=y
  64 +CONFIG_CMD_LINK_LOCAL=y
  65 +# CONFIG_CMD_MBR is not set
  66 +CONFIG_CMD_MTD=y
  67 +CONFIG_CMD_MTDPARTS=y
  68 +# CONFIG_CMD_PCI is not set
  69 +CONFIG_CMD_SF_TEST=y
  70 +CONFIG_CMD_PING=y
  71 +CONFIG_CMD_PXE=y
  72 +CONFIG_CMD_SMC=y
  73 +CONFIG_CMD_TFTPBOOT=y
  74 +CONFIG_CMD_TFTPSRV=y
  75 +# CONFIG_CMD_UNLZ4 is not set
  76 +CONFIG_CMD_ASKENV=y
  77 +CONFIG_CMD_PSTORE=y
  78 +CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
  79 +CONFIG_CMD_RARP=y
  80 +CONFIG_CMD_SETEXPR=y
  81 +CONFIG_CMD_SLEEP=y
  82 +CONFIG_CMD_SOURCE=y
  83 +CONFIG_CMD_UUID=y
  84 +CONFIG_DISPLAY_CPUINFO=y
  85 +CONFIG_DM_ETH=y
  86 +CONFIG_DM_ETH_PHY=y
  87 +CONFIG_DM_GPIO=y
  88 +CONFIG_DM_MDIO=y
  89 +CONFIG_DM_MTD=y
  90 +CONFIG_DM_REGULATOR=y
  91 +CONFIG_DM_REGULATOR_FIXED=y
  92 +CONFIG_DM_REGULATOR_GPIO=y
  93 +# CONFIG_DM_MMC is not set
  94 +CONFIG_DM_SERIAL=y
  95 +CONFIG_DM_SPI=y
  96 +CONFIG_DM_SPI_FLASH=y
  97 +CONFIG_HUSH_PARSER=y
  98 +# CONFIG_PARTITION_UUIDS is not set
  99 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 100 +# CONFIG_LED is not set
 101 +# CONFIG_LZ4 is not set
 102 +CONFIG_VERSION_VARIABLE=y
 103 +CONFIG_NETCONSOLE=y
 104 +CONFIG_REGMAP=y
 105 +CONFIG_SYSCON=y
 106 +CONFIG_CLK=y
 107 +CONFIG_PHY=y
 108 +CONFIG_PHY_FIXED=y
 109 +CONFIG_PHYLIB_10G=y
 110 +CONFIG_PHY_AQUANTIA=y
 111 +CONFIG_PHY_ADDR_ENABLE=y
 112 +CONFIG_PHY_ADDR=8
 113 +CONFIG_MEDIATEK_ETH=y
 114 +CONFIG_MTD=y
 115 +# CONFIG_MMC is not set
 116 +CONFIG_PINCTRL=y
 117 +CONFIG_PINCONF=y
 118 +CONFIG_PINCTRL_MT7622=y
 119 +CONFIG_POWER_DOMAIN=y
 120 +CONFIG_PRE_CONSOLE_BUFFER=y
 121 +CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
 122 +CONFIG_MTK_POWER_DOMAIN=y
 123 +CONFIG_RAM=y
 124 +CONFIG_MTK_SERIAL=y
 125 +CONFIG_SPI=y
 126 +CONFIG_MTK_SNFI_SPI=y
 127 +CONFIG_MTK_SNOR=y
 128 +CONFIG_SYSRESET_WATCHDOG=y
 129 +CONFIG_WDT_MTK=y
 130 +CONFIG_HEXDUMP=y
 131 +CONFIG_RANDOM_UUID=y
 132 +CONFIG_REGEX=y
 133 +CONFIG_SPI_FLASH=y
 134 +CONFIG_SPI_FLASH_BAR=y
 135 +CONFIG_SPI_FLASH_MTD=y
 136 +CONFIG_SPI_FLASH_UNLOCK_ALL=y
 137 +CONFIG_SPI_FLASH_EON=y
 138 +CONFIG_SPI_FLASH_GIGADEVICE=y
 139 +CONFIG_SPI_FLASH_MACRONIX=y
 140 +CONFIG_SPI_FLASH_SPANSION=y
 141 +CONFIG_SPI_FLASH_STMICRO=y
 142 +CONFIG_SPI_FLASH_SST=y
 143 +CONFIG_SPI_FLASH_WINBOND=y
 144 +CONFIG_SPI_FLASH_XMC=y
 145 +CONFIG_SPI_FLASH_USE_4K_SECTORS=y
 146 +CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 147 +CONFIG_USE_IPADDR=y
 148 +CONFIG_IPADDR="192.168.1.1"
 149 +CONFIG_USE_SERVERIP=y
 150 +CONFIG_SERVERIP="192.168.1.254"
 151 --- /dev/null
 152 +++ b/arch/arm/dts/mt7622-ubnt-unifi-6-lr.dts
 153 @@ -0,0 +1,188 @@
 154 +// SPDX-License-Identifier: GPL-2.0
 155 +/*
 156 + * Copyright (c) 2019 MediaTek Inc.
 157 + * Author: Sam Shih <sam.shih@mediatek.com>
 158 + */
 159 +
 160 +/dts-v1/;
 161 +#include "mt7622.dtsi"
 162 +#include "mt7622-u-boot.dtsi"
 163 +
 164 +/ {
 165 +       #address-cells = <1>;
 166 +       #size-cells = <1>;
 167 +       model = "mt7622-ubnt-unifi-6-lr";
 168 +       compatible = "mediatek,mt7622", "ubnt,unifi-6-lr";
 169 +
 170 +       chosen {
 171 +               stdout-path = &uart0;
 172 +               tick-timer = &timer0;
 173 +       };
 174 +
 175 +       aliases {
 176 +               spi0 = &snor;
 177 +       };
 178 +
 179 +       gpio-keys {
 180 +               compatible = "gpio-keys";
 181 +               u-boot,dm-pre-reloc;
 182 +
 183 +               reset {
 184 +                       label = "reset";
 185 +                       gpios = <&gpio 62 GPIO_ACTIVE_LOW>;
 186 +                       u-boot,dm-pre-reloc;
 187 +               };
 188 +       };
 189 +
 190 +       memory@40000000 {
 191 +               device_type = "memory";
 192 +               reg = <0x40000000 0x20000000>;
 193 +       };
 194 +
 195 +       reg_1p8v: regulator-1p8v {
 196 +               compatible = "regulator-fixed";
 197 +               regulator-name = "fixed-1.8V";
 198 +               regulator-min-microvolt = <1800000>;
 199 +               regulator-max-microvolt = <1800000>;
 200 +               regulator-boot-on;
 201 +               regulator-always-on;
 202 +       };
 203 +
 204 +       reg_3p3v: regulator-3p3v {
 205 +               compatible = "regulator-fixed";
 206 +               regulator-name = "fixed-3.3V";
 207 +               regulator-min-microvolt = <3300000>;
 208 +               regulator-max-microvolt = <3300000>;
 209 +               regulator-boot-on;
 210 +               regulator-always-on;
 211 +       };
 212 +
 213 +       reg_5v: regulator-5v {
 214 +               compatible = "regulator-fixed";
 215 +               regulator-name = "fixed-5V";
 216 +               regulator-min-microvolt = <5000000>;
 217 +               regulator-max-microvolt = <5000000>;
 218 +               regulator-boot-on;
 219 +               regulator-always-on;
 220 +       };
 221 +};
 222 +
 223 +&pcie {
 224 +       pinctrl-names = "default";
 225 +       pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
 226 +       status = "okay";
 227 +
 228 +       pcie@0,0 {
 229 +               status = "okay";
 230 +       };
 231 +
 232 +       pcie@1,0 {
 233 +               status = "okay";
 234 +       };
 235 +};
 236 +
 237 +&pinctrl {
 238 +       eth_pins: eth-pins {
 239 +               mux {
 240 +                       function = "eth";
 241 +                       groups = "mdc_mdio", "rgmii_via_gmac2";
 242 +               };
 243 +       };
 244 +
 245 +       pcie0_pins: pcie0-pins {
 246 +               mux {
 247 +                       function = "pcie";
 248 +                       groups = "pcie0_pad_perst",
 249 +                                "pcie0_1_waken",
 250 +                                "pcie0_1_clkreq";
 251 +               };
 252 +       };
 253 +
 254 +       pcie1_pins: pcie1-pins {
 255 +               mux {
 256 +                       function = "pcie";
 257 +                       groups = "pcie1_pad_perst",
 258 +                                "pcie1_0_waken",
 259 +                                "pcie1_0_clkreq";
 260 +               };
 261 +       };
 262 +
 263 +       snfi_pins: snfi-pins {
 264 +               mux {
 265 +                       function = "flash";
 266 +                       groups = "snfi";
 267 +               };
 268 +       };
 269 +
 270 +       snor_pins: snor-pins {
 271 +               mux {
 272 +                       function = "flash";
 273 +                       groups = "spi_nor";
 274 +               };
 275 +       };
 276 +
 277 +       uart0_pins: uart0 {
 278 +               mux {
 279 +                       function = "uart";
 280 +                       groups = "uart0_0_tx_rx" ;
 281 +               };
 282 +       };
 283 +
 284 +       watchdog_pins: watchdog-default {
 285 +               mux {
 286 +                       function = "watchdog";
 287 +                       groups = "watchdog";
 288 +               };
 289 +       };
 290 +};
 291 +
 292 +&snor {
 293 +       pinctrl-names = "default";
 294 +       pinctrl-0 = <&snor_pins>;
 295 +       status = "okay";
 296 +
 297 +       spi-flash@0 {
 298 +               compatible = "jedec,spi-nor";
 299 +               reg = <0>;
 300 +               spi-tx-bus-width = <1>;
 301 +               spi-rx-bus-width = <4>;
 302 +               u-boot,dm-pre-reloc;
 303 +       };
 304 +};
 305 +
 306 +&uart0 {
 307 +       mediatek,force-highspeed;
 308 +       status = "okay";
 309 +};
 310 +
 311 +&watchdog {
 312 +       pinctrl-names = "default";
 313 +       pinctrl-0 = <&watchdog_pins>;
 314 +       status = "okay";
 315 +};
 316 +
 317 +&eth {
 318 +       status = "okay";
 319 +       pinctrl-names = "default";
 320 +       pinctrl-0 = <&eth_pins>;
 321 +
 322 +       mediatek,gmac-id = <0>;
 323 +       phy-mode = "sgmii";
 324 +       phy-handle = <&gphy>;
 325 +
 326 +       fixed-link {
 327 +               speed = <1000>;
 328 +               full-duplex;
 329 +       };
 330 +
 331 +       mdio-bus {
 332 +               #address-cells = <1>;
 333 +               #size-cells = <0>;
 334 +
 335 +               gphy: ethernet-phy@8 {
 336 +                       /* Marvell AQRate AQR112W - no driver */
 337 +                       compatible = "ethernet-phy-ieee802.3-c45";
 338 +                       reg = <0x8>;
 339 +               };
 340 +       };
 341 +};
 342 --- a/arch/arm/dts/Makefile
 343 +++ b/arch/arm/dts/Makefile
 344 @@ -1286,6 +1286,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
 345         mt7623a-unielec-u7623-02-emmc.dtb \
 346         mt7622-bananapi-bpi-r64.dtb \
 347         mt7622-linksys-e8450-ubi.dtb \
 348 +       mt7622-ubnt-unifi-6-lr.dtb \
 349         mt7623n-bananapi-bpi-r2.dtb \
 350         mt7629-rfb.dtb \
 351         mt7981-rfb.dtb \
 352 --- /dev/null
 353 +++ b/ubnt_unifi-6-lr_env
 354 @@ -0,0 +1,50 @@
 355 +ethaddr_factory=mtd read nor0 $loadaddr 0x110000 0x10000 && env readmem -b ethaddr $loadaddr 0x6 ; setenv ethaddr_factory
 356 +ipaddr=192.168.1.1
 357 +serverip=192.168.1.254
 358 +loadaddr=0x48000000
 359 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_nor ; fi
 360 +bootdelay=0
 361 +bootfile=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v1-ubootmod-initramfs-recovery.itb
 362 +bootfile_bl2=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v1-ubootmod-preloader.bin
 363 +bootfile_fip=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v1-ubootmod-bl31-uboot.fip
 364 +bootfile_upg=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v1-ubootmod-squashfs-sysupgrade.itb
 365 +bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
 366 +bootmenu_default=0
 367 +bootmenu_delay=0
 368 +bootmenu_title=      \e[0;34m( ( ( \e[1;39mOpenWrt\e[0;34m ) ) )\e[0m
 369 +bootmenu_0=Initialize environment.=run _firstboot
 370 +bootmenu_0d=Run default boot command.=run boot_default
 371 +bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
 372 +bootmenu_2=Boot production system from flash.=run boot_production ; run bootmenu_confirm_return
 373 +bootmenu_3=Boot recovery system from flash.=run boot_recovery ; run bootmenu_confirm_return
 374 +bootmenu_4=Load production system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
 375 +bootmenu_5=Load recovery system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return
 376 +bootmenu_6=\e[31mLoad BL31+U-Boot FIP via TFTP then write to flash.\e[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return
 377 +bootmenu_7=\e[31mLoad BL2 preloader via TFTP then write to flash.\e[0m=run boot_tftp_write_preloader ; run bootmenu_confirm_return
 378 +bootmenu_8=Reboot.=reset
 379 +bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
 380 +boot_first=if button reset ; then run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu
 381 +boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever
 382 +boot_production=run nor_read_production && bootm $loadaddr
 383 +boot_recovery=run nor_read_recovery ; bootm $loadaddr
 384 +boot_serial_write_fip=loadx $loadaddr 115200 && run boot_write_fip
 385 +boot_serial_write_preloader=loadx $loadaddr 115200 && run boot_write_preloader
 386 +boot_tftp_forever=while true ; do run boot_tftp_recovery ; sleep 1 ; done
 387 +boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run nor_write_production ; if env exists noboot ; then else bootm $loadaddr ; fi
 388 +boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run nor_write_recovery ; if env exists noboot ; then else bootm $loadaddr ; fi
 389 +boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr
 390 +boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip
 391 +boot_tftp_write_preloader=tftpboot $loadaddr $bootfile_bl2 && run boot_write_preloader
 392 +boot_nor=run boot_production ; run boot_recovery
 393 +boot_write_fip=mtd erase nor0 0x20000 0x80000 && mtd write nor0 $loadaddr 0x20000 0x80000
 394 +boot_write_preloader=mtd erase nor0 0x0 0x20000 && mtd write nor0 $loadaddr 0x0 0x20000
 395 +reset_factory=mtd erase nor0 0xc0000 0x10000 && reset
 396 +nor_read_production=mtd read nor0 $loadaddr 0x1000000 0x1000 && imsz $loadaddr image_size && mtd read nor0 $loadaddr 0x1000000 $image_size
 397 +nor_read_recovery=mtd read nor0 $loadaddr 0x120000 0x1000 && imsz $loadaddr image_size && mtd read nor0 $loadaddr 0x120000 $image_size
 398 +nor_pad_size=imsz $loadaddr image_size ; setexpr image_eb 0x$image_size / 0x1000 ; setexpr tmp1 0x$image_size % 0x1000 ; test 0x$tmp1 -gt 0 && setexpr image_eb 0x$image_eb + 1 ; setexpr image_eb 0x$image_eb * 0x1000
 399 +nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0x3000000 && mtd erase nor0 0x1000000 0x$image_eb && mtd write nor0 $loadaddr 0x1000000 $filesize
 400 +nor_write_recovery=run nor_pad_size ; test 0x$image_eb -le 0xee0000 && mtd erase nor0 0x120000 0x$image_eb && mtd write nor0 $loadaddr 0x120000 $filesize
 401 +_init_env=setenv _init_env ; saveenv
 402 +_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run _init_env ; run boot_first
 403 +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
 404 +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title       \e[33m$ver\e[0m"
 405 --- a/common/board_r.c
 406 +++ b/common/board_r.c
 407 @@ -66,6 +66,7 @@
 408  #include <asm-generic/gpio.h>
 409  #include <efi_loader.h>
 410  #include <relocate.h>
 411 +#include <spi_flash.h>
 412
 413  DECLARE_GLOBAL_DATA_PTR;
 414
 415 @@ -412,6 +413,20 @@ static int initr_onenand(void)
 416  }
 417  #endif
 418
 419 +#if defined(CONFIG_SPI_FLASH)
 420 +/* probe SPI FLASH */
 421 +static int initr_spiflash(void)
 422 +{
 423 +       struct udevice *new;
 424 +
 425 +spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS,
 426 +                       CONFIG_SF_DEFAULT_CS,
 427 +                       &new);
 428 +
 429 +       return 0;
 430 +}
 431 +#endif
 432 +
 433  #ifdef CONFIG_MMC
 434  static int initr_mmc(void)
 435  {
 436 @@ -720,6 +735,9 @@ static init_fnc_t init_sequence_r[] = {
 437  #ifdef CONFIG_NMBM_MTD
 438         initr_nmbm,
 439  #endif
 440 +#ifdef CONFIG_SPI_FLASH
 441 +       initr_spiflash,
 442 +#endif
 443  #ifdef CONFIG_MMC
 444         initr_mmc,
 445  #endif