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358461a2b706741024b3273fe6ff70d1f0869bf9
[openwrt/staging/pepe2k.git] / package / boot / uboot-mediatek / patches / 100-22-mtd-spi-nand-backport-from-upstream-kernel.patch
1 From a3c5878599d530330027412eb8be12f816ac215c Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Wed, 27 Jul 2022 16:36:13 +0800
4 Subject: [PATCH 57/71] mtd: spi-nand: backport from upstream kernel
5
6 Backport new features from upstream kernel
7
8 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
9 ---
10 drivers/mtd/nand/spi/Kconfig | 8 +
11 drivers/mtd/nand/spi/core.c | 101 ++++++----
12 drivers/mtd/nand/spi/gigadevice.c | 322 ++++++++++++++++++++++++++----
13 drivers/mtd/nand/spi/macronix.c | 173 +++++++++++++---
14 drivers/mtd/nand/spi/micron.c | 50 ++---
15 drivers/mtd/nand/spi/toshiba.c | 66 +++---
16 drivers/mtd/nand/spi/winbond.c | 171 +++++++++++++---
17 include/linux/mtd/spinand.h | 86 +++++---
18 8 files changed, 753 insertions(+), 224 deletions(-)
19
20 --- a/drivers/mtd/nand/spi/Kconfig
21 +++ b/drivers/mtd/nand/spi/Kconfig
22 @@ -5,3 +5,11 @@ menuconfig MTD_SPI_NAND
23 select SPI_MEM
24 help
25 This is the framework for the SPI NAND device drivers.
26 +
27 +config MTD_SPI_NAND_W25N01KV
28 + tristate "Winbond W25N01KV Support"
29 + select MTD_SPI_NAND
30 + default n
31 + help
32 + Winbond W25N01KV share the same ID with W25N01GV. However, they have
33 + different attributes.
34 --- a/drivers/mtd/nand/spi/core.c
35 +++ b/drivers/mtd/nand/spi/core.c
36 @@ -17,6 +17,7 @@
37 #include <linux/mtd/spinand.h>
38 #include <linux/of.h>
39 #include <linux/slab.h>
40 +#include <linux/string.h>
41 #include <linux/spi/spi.h>
42 #include <linux/spi/spi-mem.h>
43 #else
44 @@ -451,10 +452,11 @@ out:
45 return status & STATUS_BUSY ? -ETIMEDOUT : 0;
46 }
47
48 -static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf)
49 +static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr,
50 + u8 ndummy, u8 *buf)
51 {
52 - struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf,
53 - SPINAND_MAX_ID_LEN);
54 + struct spi_mem_op op = SPINAND_READID_OP(
55 + naddr, ndummy, spinand->scratchbuf, SPINAND_MAX_ID_LEN);
56 int ret;
57
58 ret = spi_mem_exec_op(spinand->slave, &op);
59 @@ -464,18 +466,6 @@ static int spinand_read_id_op(struct spi
60 return ret;
61 }
62
63 -static int spinand_reset_op(struct spinand_device *spinand)
64 -{
65 - struct spi_mem_op op = SPINAND_RESET_OP;
66 - int ret;
67 -
68 - ret = spi_mem_exec_op(spinand->slave, &op);
69 - if (ret)
70 - return ret;
71 -
72 - return spinand_wait(spinand, NULL);
73 -}
74 -
75 static int spinand_lock_block(struct spinand_device *spinand, u8 lock)
76 {
77 return spinand_write_reg_op(spinand, REG_BLOCK_LOCK, lock);
78 @@ -836,24 +826,63 @@ static const struct spinand_manufacturer
79 &winbond_spinand_manufacturer,
80 };
81
82 -static int spinand_manufacturer_detect(struct spinand_device *spinand)
83 +static int spinand_manufacturer_match(struct spinand_device *spinand,
84 + enum spinand_readid_method rdid_method)
85 {
86 + u8 *id = spinand->id.data;
87 unsigned int i;
88 int ret;
89
90 for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) {
91 - ret = spinand_manufacturers[i]->ops->detect(spinand);
92 - if (ret > 0) {
93 - spinand->manufacturer = spinand_manufacturers[i];
94 - return 0;
95 - } else if (ret < 0) {
96 - return ret;
97 - }
98 + const struct spinand_manufacturer *manufacturer =
99 + spinand_manufacturers[i];
100 +
101 + if (id[0] != manufacturer->id)
102 + continue;
103 +
104 + ret = spinand_match_and_init(spinand,
105 + manufacturer->chips,
106 + manufacturer->nchips,
107 + rdid_method);
108 + if (ret < 0)
109 + continue;
110 +
111 + spinand->manufacturer = manufacturer;
112 + return 0;
113 }
114
115 return -ENOTSUPP;
116 }
117
118 +static int spinand_id_detect(struct spinand_device *spinand)
119 +{
120 + u8 *id = spinand->id.data;
121 + int ret;
122 +
123 + ret = spinand_read_id_op(spinand, 0, 0, id);
124 + if (ret)
125 + return ret;
126 + ret = spinand_manufacturer_match(spinand, SPINAND_READID_METHOD_OPCODE);
127 + if (!ret)
128 + return 0;
129 +
130 + ret = spinand_read_id_op(spinand, 1, 0, id);
131 + if (ret)
132 + return ret;
133 + ret = spinand_manufacturer_match(spinand,
134 + SPINAND_READID_METHOD_OPCODE_ADDR);
135 + if (!ret)
136 + return 0;
137 +
138 + ret = spinand_read_id_op(spinand, 0, 1, id);
139 + if (ret)
140 + return ret;
141 + ret = spinand_manufacturer_match(spinand,
142 + SPINAND_READID_METHOD_OPCODE_DUMMY);
143 +
144 + return ret;
145 +}
146 +
147 static int spinand_manufacturer_init(struct spinand_device *spinand)
148 {
149 if (spinand->manufacturer->ops->init)
150 @@ -909,9 +938,9 @@ spinand_select_op_variant(struct spinand
151 * @spinand: SPI NAND object
152 * @table: SPI NAND device description table
153 * @table_size: size of the device description table
154 + * @rdid_method: read id method to match
155 *
156 - * Should be used by SPI NAND manufacturer drivers when they want to find a
157 - * match between a device ID retrieved through the READ_ID command and an
158 + * Match between a device ID retrieved through the READ_ID command and an
159 * entry in the SPI NAND description table. If a match is found, the spinand
160 * object will be initialized with information provided by the matching
161 * spinand_info entry.
162 @@ -920,8 +949,10 @@ spinand_select_op_variant(struct spinand
163 */
164 int spinand_match_and_init(struct spinand_device *spinand,
165 const struct spinand_info *table,
166 - unsigned int table_size, u8 devid)
167 + unsigned int table_size,
168 + enum spinand_readid_method rdid_method)
169 {
170 + u8 *id = spinand->id.data;
171 struct nand_device *nand = spinand_to_nand(spinand);
172 unsigned int i;
173
174 @@ -929,13 +960,17 @@ int spinand_match_and_init(struct spinan
175 const struct spinand_info *info = &table[i];
176 const struct spi_mem_op *op;
177
178 - if (devid != info->devid)
179 + if (rdid_method != info->devid.method)
180 + continue;
181 +
182 + if (memcmp(id + 1, info->devid.id, info->devid.len))
183 continue;
184
185 nand->memorg = table[i].memorg;
186 nand->eccreq = table[i].eccreq;
187 spinand->eccinfo = table[i].eccinfo;
188 spinand->flags = table[i].flags;
189 + spinand->id.len = 1 + table[i].devid.len;
190 spinand->select_target = table[i].select_target;
191
192 op = spinand_select_op_variant(spinand,
193 @@ -967,17 +1002,7 @@ static int spinand_detect(struct spinand
194 struct nand_device *nand = spinand_to_nand(spinand);
195 int ret;
196
197 - ret = spinand_reset_op(spinand);
198 - if (ret)
199 - return ret;
200 -
201 - ret = spinand_read_id_op(spinand, spinand->id.data);
202 - if (ret)
203 - return ret;
204 -
205 - spinand->id.len = SPINAND_MAX_ID_LEN;
206 -
207 - ret = spinand_manufacturer_detect(spinand);
208 + ret = spinand_id_detect(spinand);
209 if (ret) {
210 dev_err(spinand->slave->dev, "unknown raw ID %02x %02x %02x %02x\n",
211 spinand->id.data[0], spinand->id.data[1],
212 --- a/drivers/mtd/nand/spi/gigadevice.c
213 +++ b/drivers/mtd/nand/spi/gigadevice.c
214 @@ -22,8 +22,13 @@
215
216 #define GD5FXGQXXEXXG_REG_STATUS2 0xf0
217
218 +#define GD5FXGQ4UXFXXG_STATUS_ECC_MASK (7 << 4)
219 +#define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS (0 << 4)
220 +#define GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS (1 << 4)
221 +#define GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR (7 << 4)
222 +
223 /* Q4 devices, QUADIO: Dummy bytes valid for 1 and 2 GBit variants */
224 -static SPINAND_OP_VARIANTS(gd5fxgq4_read_cache_variants,
225 +static SPINAND_OP_VARIANTS(read_cache_variants,
226 SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
227 SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
228 SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
229 @@ -31,8 +36,17 @@ static SPINAND_OP_VARIANTS(gd5fxgq4_read
230 SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
231 SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
232
233 -/* Q5 devices, QUADIO: Dummy bytes only valid for 1 GBit variants */
234 -static SPINAND_OP_VARIANTS(gd5f1gq5_read_cache_variants,
235 +static SPINAND_OP_VARIANTS(read_cache_variants_f,
236 + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
237 + SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(0, 1, NULL, 0),
238 + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
239 + SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(0, 1, NULL, 0),
240 + SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
241 + SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
242 +
243 +/* For Q5 devices, QUADIO use different dummy byte settings */
244 +/* Q5 1Gb */
245 +static SPINAND_OP_VARIANTS(dummy2_read_cache_variants,
246 SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
247 SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
248 SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
249 @@ -40,6 +54,15 @@ static SPINAND_OP_VARIANTS(gd5f1gq5_read
250 SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
251 SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
252
253 +/* Q5 2Gb & 4Gb */
254 +static SPINAND_OP_VARIANTS(dummy4_read_cache_variants,
255 + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
256 + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
257 + SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
258 + SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
259 + SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
260 + SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
261 +
262 static SPINAND_OP_VARIANTS(write_cache_variants,
263 SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
264 SPINAND_PROG_LOAD(true, 0, NULL, 0));
265 @@ -48,7 +71,65 @@ static SPINAND_OP_VARIANTS(update_cache_
266 SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
267 SPINAND_PROG_LOAD(false, 0, NULL, 0));
268
269 -static int gd5fxgqxxexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
270 +static int gd5fxgq4xa_ooblayout_ecc(struct mtd_info *mtd, int section,
271 + struct mtd_oob_region *region)
272 +{
273 + if (section > 3)
274 + return -ERANGE;
275 +
276 + region->offset = (16 * section) + 8;
277 + region->length = 8;
278 +
279 + return 0;
280 +}
281 +
282 +static int gd5fxgq4xa_ooblayout_free(struct mtd_info *mtd, int section,
283 + struct mtd_oob_region *region)
284 +{
285 + if (section > 3)
286 + return -ERANGE;
287 +
288 + if (section) {
289 + region->offset = 16 * section;
290 + region->length = 8;
291 + } else {
292 + /* section 0 has one byte reserved for bad block mark */
293 + region->offset = 1;
294 + region->length = 7;
295 + }
296 + return 0;
297 +}
298 +
299 +static const struct mtd_ooblayout_ops gd5fxgq4xa_ooblayout = {
300 + .ecc = gd5fxgq4xa_ooblayout_ecc,
301 + .rfree = gd5fxgq4xa_ooblayout_free,
302 +};
303 +
304 +static int gd5fxgq4xa_ecc_get_status(struct spinand_device *spinand,
305 + u8 status)
306 +{
307 + switch (status & STATUS_ECC_MASK) {
308 + case STATUS_ECC_NO_BITFLIPS:
309 + return 0;
310 +
311 + case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS:
312 + /* 1-7 bits are flipped. return the maximum. */
313 + return 7;
314 +
315 + case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS:
316 + return 8;
317 +
318 + case STATUS_ECC_UNCOR_ERROR:
319 + return -EBADMSG;
320 +
321 + default:
322 + break;
323 + }
324 +
325 + return -EINVAL;
326 +}
327 +
328 +static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
329 struct mtd_oob_region *region)
330 {
331 if (section)
332 @@ -60,7 +141,7 @@ static int gd5fxgqxxexxg_ooblayout_ecc(s
333 return 0;
334 }
335
336 -static int gd5fxgqxxexxg_ooblayout_free(struct mtd_info *mtd, int section,
337 +static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section,
338 struct mtd_oob_region *region)
339 {
340 if (section)
341 @@ -73,7 +154,13 @@ static int gd5fxgqxxexxg_ooblayout_free(
342 return 0;
343 }
344
345 -static int gd5fxgq4xexxg_ecc_get_status(struct spinand_device *spinand,
346 +/* Valid for Q4/Q5 and Q6 (untested) devices */
347 +static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = {
348 + .ecc = gd5fxgqx_variant2_ooblayout_ecc,
349 + .rfree = gd5fxgqx_variant2_ooblayout_free,
350 +};
351 +
352 +static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
353 u8 status)
354 {
355 u8 status2;
356 @@ -152,59 +239,214 @@ static int gd5fxgq5xexxg_ecc_get_status(
357 return -EINVAL;
358 }
359
360 -static const struct mtd_ooblayout_ops gd5fxgqxxexxg_ooblayout = {
361 - .ecc = gd5fxgqxxexxg_ooblayout_ecc,
362 - .rfree = gd5fxgqxxexxg_ooblayout_free,
363 +static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand,
364 + u8 status)
365 +{
366 + switch (status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) {
367 + case GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS:
368 + return 0;
369 +
370 + case GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS:
371 + return 3;
372 +
373 + case GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR:
374 + return -EBADMSG;
375 +
376 + default: /* (2 << 4) through (6 << 4) are 4-8 corrected errors */
377 + return ((status & GD5FXGQ4UXFXXG_STATUS_ECC_MASK) >> 4) + 2;
378 + }
379 +
380 + return -EINVAL;
381 +}
382 +
383 +static int esmt_1_ooblayout_ecc(struct mtd_info *mtd, int section,
384 + struct mtd_oob_region *region)
385 +{
386 + if (section > 3)
387 + return -ERANGE;
388 +
389 + region->offset = (16 * section) + 8;
390 + region->length = 8;
391 +
392 + return 0;
393 +}
394 +
395 +static int esmt_1_ooblayout_free(struct mtd_info *mtd, int section,
396 + struct mtd_oob_region *region)
397 +{
398 + if (section > 3)
399 + return -ERANGE;
400 +
401 + region->offset = (16 * section) + 2;
402 + region->length = 6;
403 +
404 + return 0;
405 +}
406 +
407 +static const struct mtd_ooblayout_ops esmt_1_ooblayout = {
408 + .ecc = esmt_1_ooblayout_ecc,
409 + .rfree = esmt_1_ooblayout_free,
410 };
411
412 static const struct spinand_info gigadevice_spinand_table[] = {
413 - SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
414 - NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
415 + SPINAND_INFO("F50L1G41LB",
416 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01),
417 + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
418 NAND_ECCREQ(8, 512),
419 - SPINAND_INFO_OP_VARIANTS(&gd5fxgq4_read_cache_variants,
420 + SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
421 &write_cache_variants,
422 &update_cache_variants),
423 0,
424 - SPINAND_ECCINFO(&gd5fxgqxxexxg_ooblayout,
425 - gd5fxgq4xexxg_ecc_get_status)),
426 - SPINAND_INFO("GD5F1GQ5UExxG", 0x51,
427 + SPINAND_ECCINFO(&esmt_1_ooblayout, NULL)),
428 + SPINAND_INFO("GD5F1GQ4xA",
429 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1),
430 + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
431 + NAND_ECCREQ(8, 512),
432 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
433 + &write_cache_variants,
434 + &update_cache_variants),
435 + SPINAND_HAS_QE_BIT,
436 + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
437 + gd5fxgq4xa_ecc_get_status)),
438 + SPINAND_INFO("GD5F2GQ4xA",
439 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf2),
440 + NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
441 + NAND_ECCREQ(8, 512),
442 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
443 + &write_cache_variants,
444 + &update_cache_variants),
445 + SPINAND_HAS_QE_BIT,
446 + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
447 + gd5fxgq4xa_ecc_get_status)),
448 + SPINAND_INFO("GD5F4GQ4xA",
449 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf4),
450 + NAND_MEMORG(1, 2048, 64, 64, 4096, 1, 1, 1),
451 + NAND_ECCREQ(8, 512),
452 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
453 + &write_cache_variants,
454 + &update_cache_variants),
455 + SPINAND_HAS_QE_BIT,
456 + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
457 + gd5fxgq4xa_ecc_get_status)),
458 + SPINAND_INFO("GD5F1GQ4UExxG",
459 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd1),
460 + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
461 + NAND_ECCREQ(8, 512),
462 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
463 + &write_cache_variants,
464 + &update_cache_variants),
465 + SPINAND_HAS_QE_BIT,
466 + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
467 + gd5fxgq4uexxg_ecc_get_status)),
468 + SPINAND_INFO("GD5F1GQ4UFxxG",
469 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
470 + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
471 + NAND_ECCREQ(8, 512),
472 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
473 + &write_cache_variants,
474 + &update_cache_variants),
475 + SPINAND_HAS_QE_BIT,
476 + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
477 + gd5fxgq4ufxxg_ecc_get_status)),
478 + SPINAND_INFO("GD5F1GQ5UExxG",
479 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
480 NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
481 NAND_ECCREQ(4, 512),
482 - SPINAND_INFO_OP_VARIANTS(&gd5f1gq5_read_cache_variants,
483 + SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
484 &write_cache_variants,
485 &update_cache_variants),
486 - 0,
487 - SPINAND_ECCINFO(&gd5fxgqxxexxg_ooblayout,
488 + SPINAND_HAS_QE_BIT,
489 + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
490 + gd5fxgq5xexxg_ecc_get_status)),
491 + SPINAND_INFO("GD5F2GQ5UExxG",
492 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52),
493 + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
494 + NAND_ECCREQ(4, 512),
495 + SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
496 + &write_cache_variants,
497 + &update_cache_variants),
498 + SPINAND_HAS_QE_BIT,
499 + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
500 + gd5fxgq5xexxg_ecc_get_status)),
501 + SPINAND_INFO("GD5F4GQ6UExxG",
502 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x55),
503 + NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
504 + NAND_ECCREQ(4, 512),
505 + SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
506 + &write_cache_variants,
507 + &update_cache_variants),
508 + SPINAND_HAS_QE_BIT,
509 + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
510 + gd5fxgq5xexxg_ecc_get_status)),
511 + SPINAND_INFO("GD5F1GM7UExxG",
512 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x91),
513 + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
514 + NAND_ECCREQ(8, 512),
515 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
516 + &write_cache_variants,
517 + &update_cache_variants),
518 + SPINAND_HAS_QE_BIT,
519 + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
520 + gd5fxgq4uexxg_ecc_get_status)),
521 + SPINAND_INFO("GD5F2GM7UExxG",
522 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x92),
523 + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
524 + NAND_ECCREQ(8, 512),
525 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
526 + &write_cache_variants,
527 + &update_cache_variants),
528 + SPINAND_HAS_QE_BIT,
529 + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
530 + gd5fxgq4uexxg_ecc_get_status)),
531 + SPINAND_INFO("GD5F4GM8UExxG",
532 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x95),
533 + NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
534 + NAND_ECCREQ(8, 512),
535 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
536 + &write_cache_variants,
537 + &update_cache_variants),
538 + SPINAND_HAS_QE_BIT,
539 + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
540 + gd5fxgq4uexxg_ecc_get_status)),
541 + SPINAND_INFO("GD5F1GQ5UExxH",
542 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x31),
543 + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
544 + NAND_ECCREQ(4, 512),
545 + SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants,
546 + &write_cache_variants,
547 + &update_cache_variants),
548 + SPINAND_HAS_QE_BIT,
549 + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
550 + gd5fxgq5xexxg_ecc_get_status)),
551 + SPINAND_INFO("GD5F2GQ5UExxH",
552 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32),
553 + NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
554 + NAND_ECCREQ(4, 512),
555 + SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
556 + &write_cache_variants,
557 + &update_cache_variants),
558 + SPINAND_HAS_QE_BIT,
559 + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
560 + gd5fxgq5xexxg_ecc_get_status)),
561 + SPINAND_INFO("GD5F4GQ6UExxH",
562 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
563 + NAND_MEMORG(1, 2048, 64, 64, 4096, 1, 1, 1),
564 + NAND_ECCREQ(4, 512),
565 + SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants,
566 + &write_cache_variants,
567 + &update_cache_variants),
568 + SPINAND_HAS_QE_BIT,
569 + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
570 gd5fxgq5xexxg_ecc_get_status)),
571 };
572
573 -static int gigadevice_spinand_detect(struct spinand_device *spinand)
574 -{
575 - u8 *id = spinand->id.data;
576 - int ret;
577 -
578 - /*
579 - * For GD NANDs, There is an address byte needed to shift in before IDs
580 - * are read out, so the first byte in raw_id is dummy.
581 - */
582 - if (id[1] != SPINAND_MFR_GIGADEVICE)
583 - return 0;
584 -
585 - ret = spinand_match_and_init(spinand, gigadevice_spinand_table,
586 - ARRAY_SIZE(gigadevice_spinand_table),
587 - id[2]);
588 - if (ret)
589 - return ret;
590 -
591 - return 1;
592 -}
593 -
594 static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
595 - .detect = gigadevice_spinand_detect,
596 };
597
598 const struct spinand_manufacturer gigadevice_spinand_manufacturer = {
599 .id = SPINAND_MFR_GIGADEVICE,
600 .name = "GigaDevice",
601 + .chips = gigadevice_spinand_table,
602 + .nchips = ARRAY_SIZE(gigadevice_spinand_table),
603 .ops = &gigadevice_spinand_manuf_ops,
604 };
605 --- a/drivers/mtd/nand/spi/macronix.c
606 +++ b/drivers/mtd/nand/spi/macronix.c
607 @@ -105,7 +105,8 @@ static int mx35lf1ge4ab_ecc_get_status(s
608 }
609
610 static const struct spinand_info macronix_spinand_table[] = {
611 - SPINAND_INFO("MX35LF1GE4AB", 0x12,
612 + SPINAND_INFO("MX35LF1GE4AB",
613 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x12),
614 NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
615 NAND_ECCREQ(4, 512),
616 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
617 @@ -114,7 +115,8 @@ static const struct spinand_info macroni
618 SPINAND_HAS_QE_BIT,
619 SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
620 mx35lf1ge4ab_ecc_get_status)),
621 - SPINAND_INFO("MX35LF2GE4AB", 0x22,
622 + SPINAND_INFO("MX35LF2GE4AB",
623 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x22),
624 NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),
625 NAND_ECCREQ(4, 512),
626 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
627 @@ -122,7 +124,96 @@ static const struct spinand_info macroni
628 &update_cache_variants),
629 SPINAND_HAS_QE_BIT,
630 SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
631 - SPINAND_INFO("MX35UF4GE4AD", 0xb7,
632 + SPINAND_INFO("MX35LF2GE4AD",
633 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x26),
634 + NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
635 + NAND_ECCREQ(8, 512),
636 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
637 + &write_cache_variants,
638 + &update_cache_variants),
639 + SPINAND_HAS_QE_BIT,
640 + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
641 + mx35lf1ge4ab_ecc_get_status)),
642 + SPINAND_INFO("MX35LF4GE4AD",
643 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x37),
644 + NAND_MEMORG(1, 4096, 128, 64, 2048, 1, 1, 1),
645 + NAND_ECCREQ(8, 512),
646 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
647 + &write_cache_variants,
648 + &update_cache_variants),
649 + SPINAND_HAS_QE_BIT,
650 + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
651 + mx35lf1ge4ab_ecc_get_status)),
652 + SPINAND_INFO("MX35LF1G24AD",
653 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
654 + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
655 + NAND_ECCREQ(8, 512),
656 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
657 + &write_cache_variants,
658 + &update_cache_variants),
659 + SPINAND_HAS_QE_BIT,
660 + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
661 + SPINAND_INFO("MX35LF2G24AD",
662 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
663 + NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
664 + NAND_ECCREQ(8, 512),
665 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
666 + &write_cache_variants,
667 + &update_cache_variants),
668 + SPINAND_HAS_QE_BIT,
669 + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
670 + SPINAND_INFO("MX35LF4G24AD",
671 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
672 + NAND_MEMORG(1, 4096, 256, 64, 2048, 2, 1, 1),
673 + NAND_ECCREQ(8, 512),
674 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
675 + &write_cache_variants,
676 + &update_cache_variants),
677 + SPINAND_HAS_QE_BIT,
678 + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
679 + SPINAND_INFO("MX31LF1GE4BC",
680 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x1e),
681 + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
682 + NAND_ECCREQ(8, 512),
683 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
684 + &write_cache_variants,
685 + &update_cache_variants),
686 + SPINAND_HAS_QE_BIT,
687 + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
688 + mx35lf1ge4ab_ecc_get_status)),
689 + SPINAND_INFO("MX31UF1GE4BC",
690 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9e),
691 + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
692 + NAND_ECCREQ(8, 512),
693 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
694 + &write_cache_variants,
695 + &update_cache_variants),
696 + SPINAND_HAS_QE_BIT,
697 + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
698 + mx35lf1ge4ab_ecc_get_status)),
699 +
700 + SPINAND_INFO("MX35LF2G14AC",
701 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x20),
702 + NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),
703 + NAND_ECCREQ(4, 512),
704 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
705 + &write_cache_variants,
706 + &update_cache_variants),
707 + SPINAND_HAS_QE_BIT,
708 + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
709 + mx35lf1ge4ab_ecc_get_status)),
710 + SPINAND_INFO("MX35UF4G24AD",
711 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb5),
712 + NAND_MEMORG(1, 4096, 256, 64, 2048, 2, 1, 1),
713 + NAND_ECCREQ(8, 512),
714 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
715 + &write_cache_variants,
716 + &update_cache_variants),
717 + SPINAND_HAS_QE_BIT,
718 + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
719 + mx35lf1ge4ab_ecc_get_status)),
720 + SPINAND_INFO("MX35UF4GE4AD",
721 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xb7),
722 NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
723 NAND_ECCREQ(8, 512),
724 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
725 @@ -131,7 +222,28 @@ static const struct spinand_info macroni
726 SPINAND_HAS_QE_BIT,
727 SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
728 mx35lf1ge4ab_ecc_get_status)),
729 - SPINAND_INFO("MX35UF2GE4AD", 0xa6,
730 + SPINAND_INFO("MX35UF2G14AC",
731 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa0),
732 + NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),
733 + NAND_ECCREQ(4, 512),
734 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
735 + &write_cache_variants,
736 + &update_cache_variants),
737 + SPINAND_HAS_QE_BIT,
738 + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
739 + mx35lf1ge4ab_ecc_get_status)),
740 + SPINAND_INFO("MX35UF2G24AD",
741 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa4),
742 + NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
743 + NAND_ECCREQ(8, 512),
744 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
745 + &write_cache_variants,
746 + &update_cache_variants),
747 + SPINAND_HAS_QE_BIT,
748 + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
749 + mx35lf1ge4ab_ecc_get_status)),
750 + SPINAND_INFO("MX35UF2GE4AD",
751 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa6),
752 NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
753 NAND_ECCREQ(8, 512),
754 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
755 @@ -140,16 +252,28 @@ static const struct spinand_info macroni
756 SPINAND_HAS_QE_BIT,
757 SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
758 mx35lf1ge4ab_ecc_get_status)),
759 - SPINAND_INFO("MX35UF2GE4AC", 0xa2,
760 + SPINAND_INFO("MX35UF2GE4AC",
761 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xa2),
762 NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
763 NAND_ECCREQ(4, 512),
764 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
765 + &write_cache_variants,
766 + &update_cache_variants),
767 + SPINAND_HAS_QE_BIT,
768 + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
769 + mx35lf1ge4ab_ecc_get_status)),
770 + SPINAND_INFO("MX35UF1G14AC",
771 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x90),
772 + NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
773 + NAND_ECCREQ(4, 512),
774 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
775 &write_cache_variants,
776 &update_cache_variants),
777 SPINAND_HAS_QE_BIT,
778 SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
779 mx35lf1ge4ab_ecc_get_status)),
780 - SPINAND_INFO("MX35UF1GE4AD", 0x96,
781 + SPINAND_INFO("MX35UF1G24AD",
782 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x94),
783 NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
784 NAND_ECCREQ(8, 512),
785 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
786 @@ -158,7 +282,18 @@ static const struct spinand_info macroni
787 SPINAND_HAS_QE_BIT,
788 SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
789 mx35lf1ge4ab_ecc_get_status)),
790 - SPINAND_INFO("MX35UF1GE4AC", 0x92,
791 + SPINAND_INFO("MX35UF1GE4AD",
792 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x96),
793 + NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
794 + NAND_ECCREQ(8, 512),
795 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
796 + &write_cache_variants,
797 + &update_cache_variants),
798 + SPINAND_HAS_QE_BIT,
799 + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
800 + mx35lf1ge4ab_ecc_get_status)),
801 + SPINAND_INFO("MX35UF1GE4AC",
802 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
803 NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
804 NAND_ECCREQ(4, 512),
805 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
806 @@ -170,33 +305,13 @@ static const struct spinand_info macroni
807
808 };
809
810 -static int macronix_spinand_detect(struct spinand_device *spinand)
811 -{
812 - u8 *id = spinand->id.data;
813 - int ret;
814 -
815 - /*
816 - * Macronix SPI NAND read ID needs a dummy byte, so the first byte in
817 - * raw_id is garbage.
818 - */
819 - if (id[1] != SPINAND_MFR_MACRONIX)
820 - return 0;
821 -
822 - ret = spinand_match_and_init(spinand, macronix_spinand_table,
823 - ARRAY_SIZE(macronix_spinand_table),
824 - id[2]);
825 - if (ret)
826 - return ret;
827 -
828 - return 1;
829 -}
830 -
831 static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = {
832 - .detect = macronix_spinand_detect,
833 };
834
835 const struct spinand_manufacturer macronix_spinand_manufacturer = {
836 .id = SPINAND_MFR_MACRONIX,
837 .name = "Macronix",
838 + .chips = macronix_spinand_table,
839 + .nchips = ARRAY_SIZE(macronix_spinand_table),
840 .ops = &macronix_spinand_manuf_ops,
841 };
842 --- a/drivers/mtd/nand/spi/micron.c
843 +++ b/drivers/mtd/nand/spi/micron.c
844 @@ -120,7 +120,8 @@ static int micron_8_ecc_get_status(struc
845
846 static const struct spinand_info micron_spinand_table[] = {
847 /* M79A 2Gb 3.3V */
848 - SPINAND_INFO("MT29F2G01ABAGD", 0x24,
849 + SPINAND_INFO("MT29F2G01ABAGD",
850 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
851 NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
852 NAND_ECCREQ(8, 512),
853 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
854 @@ -130,7 +131,8 @@ static const struct spinand_info micron_
855 SPINAND_ECCINFO(&micron_8_ooblayout,
856 micron_8_ecc_get_status)),
857 /* M79A 2Gb 1.8V */
858 - SPINAND_INFO("MT29F2G01ABBGD", 0x25,
859 + SPINAND_INFO("MT29F2G01ABBGD",
860 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
861 NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
862 NAND_ECCREQ(8, 512),
863 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
864 @@ -140,7 +142,8 @@ static const struct spinand_info micron_
865 SPINAND_ECCINFO(&micron_8_ooblayout,
866 micron_8_ecc_get_status)),
867 /* M78A 1Gb 3.3V */
868 - SPINAND_INFO("MT29F1G01ABAFD", 0x14,
869 + SPINAND_INFO("MT29F1G01ABAFD",
870 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
871 NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
872 NAND_ECCREQ(8, 512),
873 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
874 @@ -150,7 +153,8 @@ static const struct spinand_info micron_
875 SPINAND_ECCINFO(&micron_8_ooblayout,
876 micron_8_ecc_get_status)),
877 /* M78A 1Gb 1.8V */
878 - SPINAND_INFO("MT29F1G01ABAFD", 0x15,
879 + SPINAND_INFO("MT29F1G01ABAFD",
880 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
881 NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
882 NAND_ECCREQ(8, 512),
883 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
884 @@ -160,7 +164,8 @@ static const struct spinand_info micron_
885 SPINAND_ECCINFO(&micron_8_ooblayout,
886 micron_8_ecc_get_status)),
887 /* M79A 4Gb 3.3V */
888 - SPINAND_INFO("MT29F4G01ADAGD", 0x36,
889 + SPINAND_INFO("MT29F4G01ADAGD",
890 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36),
891 NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 2),
892 NAND_ECCREQ(8, 512),
893 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
894 @@ -171,7 +176,8 @@ static const struct spinand_info micron_
895 micron_8_ecc_get_status),
896 SPINAND_SELECT_TARGET(micron_select_target)),
897 /* M70A 4Gb 3.3V */
898 - SPINAND_INFO("MT29F4G01ABAFD", 0x34,
899 + SPINAND_INFO("MT29F4G01ABAFD",
900 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34),
901 NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
902 NAND_ECCREQ(8, 512),
903 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
904 @@ -181,7 +187,8 @@ static const struct spinand_info micron_
905 SPINAND_ECCINFO(&micron_8_ooblayout,
906 micron_8_ecc_get_status)),
907 /* M70A 4Gb 1.8V */
908 - SPINAND_INFO("MT29F4G01ABBFD", 0x35,
909 + SPINAND_INFO("MT29F4G01ABBFD",
910 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
911 NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
912 NAND_ECCREQ(8, 512),
913 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
914 @@ -191,7 +198,8 @@ static const struct spinand_info micron_
915 SPINAND_ECCINFO(&micron_8_ooblayout,
916 micron_8_ecc_get_status)),
917 /* M70A 8Gb 3.3V */
918 - SPINAND_INFO("MT29F8G01ADAFD", 0x46,
919 + SPINAND_INFO("MT29F8G01ADAFD",
920 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46),
921 NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2),
922 NAND_ECCREQ(8, 512),
923 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
924 @@ -202,7 +210,8 @@ static const struct spinand_info micron_
925 micron_8_ecc_get_status),
926 SPINAND_SELECT_TARGET(micron_select_target)),
927 /* M70A 8Gb 1.8V */
928 - SPINAND_INFO("MT29F8G01ADBFD", 0x47,
929 + SPINAND_INFO("MT29F8G01ADBFD",
930 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47),
931 NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 2),
932 NAND_ECCREQ(8, 512),
933 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
934 @@ -214,26 +223,6 @@ static const struct spinand_info micron_
935 SPINAND_SELECT_TARGET(micron_select_target)),
936 };
937
938 -static int micron_spinand_detect(struct spinand_device *spinand)
939 -{
940 - u8 *id = spinand->id.data;
941 - int ret;
942 -
943 - /*
944 - * Micron SPI NAND read ID need a dummy byte,
945 - * so the first byte in raw_id is dummy.
946 - */
947 - if (id[1] != SPINAND_MFR_MICRON)
948 - return 0;
949 -
950 - ret = spinand_match_and_init(spinand, micron_spinand_table,
951 - ARRAY_SIZE(micron_spinand_table), id[2]);
952 - if (ret)
953 - return ret;
954 -
955 - return 1;
956 -}
957 -
958 static int micron_spinand_init(struct spinand_device *spinand)
959 {
960 /*
961 @@ -248,12 +237,13 @@ static int micron_spinand_init(struct sp
962 }
963
964 static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {
965 - .detect = micron_spinand_detect,
966 .init = micron_spinand_init,
967 };
968
969 const struct spinand_manufacturer micron_spinand_manufacturer = {
970 .id = SPINAND_MFR_MICRON,
971 .name = "Micron",
972 + .chips = micron_spinand_table,
973 + .nchips = ARRAY_SIZE(micron_spinand_table),
974 .ops = &micron_spinand_manuf_ops,
975 };
976 --- a/drivers/mtd/nand/spi/toshiba.c
977 +++ b/drivers/mtd/nand/spi/toshiba.c
978 @@ -111,7 +111,8 @@ static int tx58cxgxsxraix_ecc_get_status
979
980 static const struct spinand_info toshiba_spinand_table[] = {
981 /* 3.3V 1Gb (1st generation) */
982 - SPINAND_INFO("TC58CVG0S3HRAIG", 0xC2,
983 + SPINAND_INFO("TC58CVG0S3HRAIG",
984 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xC2),
985 NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
986 NAND_ECCREQ(8, 512),
987 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
988 @@ -121,7 +122,8 @@ static const struct spinand_info toshiba
989 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
990 tx58cxgxsxraix_ecc_get_status)),
991 /* 3.3V 2Gb (1st generation) */
992 - SPINAND_INFO("TC58CVG1S3HRAIG", 0xCB,
993 + SPINAND_INFO("TC58CVG1S3HRAIG",
994 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCB),
995 NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
996 NAND_ECCREQ(8, 512),
997 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
998 @@ -131,7 +133,8 @@ static const struct spinand_info toshiba
999 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
1000 tx58cxgxsxraix_ecc_get_status)),
1001 /* 3.3V 4Gb (1st generation) */
1002 - SPINAND_INFO("TC58CVG2S0HRAIG", 0xCD,
1003 + SPINAND_INFO("TC58CVG2S0HRAIG",
1004 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xCD),
1005 NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
1006 NAND_ECCREQ(8, 512),
1007 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
1008 @@ -141,7 +144,8 @@ static const struct spinand_info toshiba
1009 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
1010 tx58cxgxsxraix_ecc_get_status)),
1011 /* 1.8V 1Gb (1st generation) */
1012 - SPINAND_INFO("TC58CYG0S3HRAIG", 0xB2,
1013 + SPINAND_INFO("TC58CYG0S3HRAIG",
1014 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xB2),
1015 NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
1016 NAND_ECCREQ(8, 512),
1017 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
1018 @@ -151,7 +155,8 @@ static const struct spinand_info toshiba
1019 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
1020 tx58cxgxsxraix_ecc_get_status)),
1021 /* 1.8V 2Gb (1st generation) */
1022 - SPINAND_INFO("TC58CYG1S3HRAIG", 0xBB,
1023 + SPINAND_INFO("TC58CYG1S3HRAIG",
1024 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBB),
1025 NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
1026 NAND_ECCREQ(8, 512),
1027 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
1028 @@ -161,7 +166,8 @@ static const struct spinand_info toshiba
1029 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
1030 tx58cxgxsxraix_ecc_get_status)),
1031 /* 1.8V 4Gb (1st generation) */
1032 - SPINAND_INFO("TC58CYG2S0HRAIG", 0xBD,
1033 + SPINAND_INFO("TC58CYG2S0HRAIG",
1034 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBD),
1035 NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
1036 NAND_ECCREQ(8, 512),
1037 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
1038 @@ -176,7 +182,8 @@ static const struct spinand_info toshiba
1039 * QE_BIT.
1040 */
1041 /* 3.3V 1Gb (2nd generation) */
1042 - SPINAND_INFO("TC58CVG0S3HRAIJ", 0xE2,
1043 + SPINAND_INFO("TC58CVG0S3HRAIJ",
1044 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE2),
1045 NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
1046 NAND_ECCREQ(8, 512),
1047 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
1048 @@ -186,7 +193,8 @@ static const struct spinand_info toshiba
1049 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
1050 tx58cxgxsxraix_ecc_get_status)),
1051 /* 3.3V 2Gb (2nd generation) */
1052 - SPINAND_INFO("TC58CVG1S3HRAIJ", 0xEB,
1053 + SPINAND_INFO("TC58CVG1S3HRAIJ",
1054 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xEB),
1055 NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
1056 NAND_ECCREQ(8, 512),
1057 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
1058 @@ -196,7 +204,8 @@ static const struct spinand_info toshiba
1059 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
1060 tx58cxgxsxraix_ecc_get_status)),
1061 /* 3.3V 4Gb (2nd generation) */
1062 - SPINAND_INFO("TC58CVG2S0HRAIJ", 0xED,
1063 + SPINAND_INFO("TC58CVG2S0HRAIJ",
1064 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xED),
1065 NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
1066 NAND_ECCREQ(8, 512),
1067 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
1068 @@ -206,7 +215,8 @@ static const struct spinand_info toshiba
1069 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
1070 tx58cxgxsxraix_ecc_get_status)),
1071 /* 3.3V 8Gb (2nd generation) */
1072 - SPINAND_INFO("TH58CVG3S0HRAIJ", 0xE4,
1073 + SPINAND_INFO("TH58CVG3S0HRAIJ",
1074 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4),
1075 NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
1076 NAND_ECCREQ(8, 512),
1077 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
1078 @@ -216,7 +226,8 @@ static const struct spinand_info toshiba
1079 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
1080 tx58cxgxsxraix_ecc_get_status)),
1081 /* 1.8V 1Gb (2nd generation) */
1082 - SPINAND_INFO("TC58CYG0S3HRAIJ", 0xD2,
1083 + SPINAND_INFO("TC58CYG0S3HRAIJ",
1084 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD2),
1085 NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
1086 NAND_ECCREQ(8, 512),
1087 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
1088 @@ -226,7 +237,8 @@ static const struct spinand_info toshiba
1089 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
1090 tx58cxgxsxraix_ecc_get_status)),
1091 /* 1.8V 2Gb (2nd generation) */
1092 - SPINAND_INFO("TC58CYG1S3HRAIJ", 0xDB,
1093 + SPINAND_INFO("TC58CYG1S3HRAIJ",
1094 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDB),
1095 NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
1096 NAND_ECCREQ(8, 512),
1097 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
1098 @@ -236,7 +248,8 @@ static const struct spinand_info toshiba
1099 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
1100 tx58cxgxsxraix_ecc_get_status)),
1101 /* 1.8V 4Gb (2nd generation) */
1102 - SPINAND_INFO("TC58CYG2S0HRAIJ", 0xDD,
1103 + SPINAND_INFO("TC58CYG2S0HRAIJ",
1104 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xDD),
1105 NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
1106 NAND_ECCREQ(8, 512),
1107 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
1108 @@ -246,7 +259,8 @@ static const struct spinand_info toshiba
1109 SPINAND_ECCINFO(&tx58cxgxsxraix_ooblayout,
1110 tx58cxgxsxraix_ecc_get_status)),
1111 /* 1.8V 8Gb (2nd generation) */
1112 - SPINAND_INFO("TH58CYG3S0HRAIJ", 0xD4,
1113 + SPINAND_INFO("TH58CYG3S0HRAIJ",
1114 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4),
1115 NAND_MEMORG(1, 4096, 256, 64, 4096, 1, 1, 1),
1116 NAND_ECCREQ(8, 512),
1117 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
1118 @@ -257,33 +271,13 @@ static const struct spinand_info toshiba
1119 tx58cxgxsxraix_ecc_get_status)),
1120 };
1121
1122 -static int toshiba_spinand_detect(struct spinand_device *spinand)
1123 -{
1124 - u8 *id = spinand->id.data;
1125 - int ret;
1126 -
1127 - /*
1128 - * Toshiba SPI NAND read ID needs a dummy byte,
1129 - * so the first byte in id is garbage.
1130 - */
1131 - if (id[1] != SPINAND_MFR_TOSHIBA)
1132 - return 0;
1133 -
1134 - ret = spinand_match_and_init(spinand, toshiba_spinand_table,
1135 - ARRAY_SIZE(toshiba_spinand_table),
1136 - id[2]);
1137 - if (ret)
1138 - return ret;
1139 -
1140 - return 1;
1141 -}
1142 -
1143 static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = {
1144 - .detect = toshiba_spinand_detect,
1145 };
1146
1147 const struct spinand_manufacturer toshiba_spinand_manufacturer = {
1148 .id = SPINAND_MFR_TOSHIBA,
1149 .name = "Toshiba",
1150 + .chips = toshiba_spinand_table,
1151 + .nchips = ARRAY_SIZE(toshiba_spinand_table),
1152 .ops = &toshiba_spinand_manuf_ops,
1153 };
1154 --- a/drivers/mtd/nand/spi/winbond.c
1155 +++ b/drivers/mtd/nand/spi/winbond.c
1156 @@ -19,6 +19,25 @@
1157
1158 #define WINBOND_CFG_BUF_READ BIT(3)
1159
1160 +#define W25N02_N04KV_STATUS_ECC_MASK (3 << 4)
1161 +#define W25N02_N04KV_STATUS_ECC_NO_BITFLIPS (0 << 4)
1162 +#define W25N02_N04KV_STATUS_ECC_1_4_BITFLIPS (1 << 4)
1163 +#define W25N02_N04KV_STATUS_ECC_5_8_BITFLIPS (3 << 4)
1164 +#define W25N02_N04KV_STATUS_ECC_UNCOR_ERROR (2 << 4)
1165 +
1166 +#define W25N01_M02GV_STATUS_ECC_MASK (3 << 4)
1167 +#define W25N01_M02GV_STATUS_ECC_NO_BITFLIPS (0 << 4)
1168 +#define W25N01_M02GV_STATUS_ECC_1_BITFLIPS (1 << 4)
1169 +#define W25N01_M02GV_STATUS_ECC_UNCOR_ERROR (2 << 4)
1170 +
1171 +#if IS_ENABLED(CONFIG_MTD_SPI_NAND_W25N01KV)
1172 +#define W25N01KV_STATUS_ECC_MASK (3 << 4)
1173 +#define W25N01KV_STATUS_ECC_NO_BITFLIPS (0 << 4)
1174 +#define W25N01KV_STATUS_ECC_1_3_BITFLIPS (1 << 4)
1175 +#define W25N01KV_STATUS_ECC_4_BITFLIPS (3 << 4)
1176 +#define W25N01KV_STATUS_ECC_UNCOR_ERROR (2 << 4)
1177 +#endif
1178 +
1179 static SPINAND_OP_VARIANTS(read_cache_variants,
1180 SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
1181 SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
1182 @@ -35,6 +54,35 @@ static SPINAND_OP_VARIANTS(update_cache_
1183 SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
1184 SPINAND_PROG_LOAD(false, 0, NULL, 0));
1185
1186 +static int w25n02kv_n04kv_ooblayout_ecc(struct mtd_info *mtd, int section,
1187 + struct mtd_oob_region *region)
1188 +{
1189 + if (section > 3)
1190 + return -ERANGE;
1191 +
1192 + region->offset = (16 * section) + 64;
1193 + region->length = 16;
1194 +
1195 + return 0;
1196 +}
1197 +
1198 +static int w25n02kv_n04kv_ooblayout_free(struct mtd_info *mtd, int section,
1199 + struct mtd_oob_region *region)
1200 +{
1201 + if (section > 3)
1202 + return -ERANGE;
1203 +
1204 + region->offset = (16 * section) + 2;
1205 + region->length = 14;
1206 +
1207 + return 0;
1208 +}
1209 +
1210 +static const struct mtd_ooblayout_ops w25n02kv_n04kv_ooblayout = {
1211 + .ecc = w25n02kv_n04kv_ooblayout_ecc,
1212 + .rfree = w25n02kv_n04kv_ooblayout_free,
1213 +};
1214 +
1215 static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
1216 struct mtd_oob_region *region)
1217 {
1218 @@ -78,8 +126,63 @@ static int w25m02gv_select_target(struct
1219 return spi_mem_exec_op(spinand->slave, &op);
1220 }
1221
1222 +#if IS_ENABLED(CONFIG_MTD_SPI_NAND_W25N01KV)
1223 +static int w25n01kv_ecc_get_status(struct spinand_device *spinand,
1224 + u8 status)
1225 +{
1226 + switch (status & W25N01KV_STATUS_ECC_MASK) {
1227 + case W25N01KV_STATUS_ECC_NO_BITFLIPS:
1228 + return 0;
1229 +
1230 + case W25N01KV_STATUS_ECC_1_3_BITFLIPS:
1231 + return 3;
1232 +
1233 + case W25N01KV_STATUS_ECC_4_BITFLIPS:
1234 + return 4;
1235 +
1236 + case W25N01KV_STATUS_ECC_UNCOR_ERROR:
1237 + return -EBADMSG;
1238 +
1239 + default:
1240 + break;
1241 + }
1242 +
1243 + return -EINVAL;
1244 +}
1245 +#endif
1246 +
1247 +static int w25n02kv_n04kv_ecc_get_status(struct spinand_device *spinand,
1248 + u8 status)
1249 +{
1250 + switch (status & W25N02_N04KV_STATUS_ECC_MASK) {
1251 + case W25N02_N04KV_STATUS_ECC_NO_BITFLIPS:
1252 + return 0;
1253 +
1254 + case W25N02_N04KV_STATUS_ECC_1_4_BITFLIPS:
1255 + return 3;
1256 +
1257 + case W25N02_N04KV_STATUS_ECC_5_8_BITFLIPS:
1258 + return 4;
1259 +
1260 + /* W25N02_N04KV_use internal 8bit ECC algorithm.
1261 + * But the ECC strength is 4 bit requried.
1262 + * Return 3 if the bit bit flip count less than 5.
1263 + * Return 4 if the bit bit flip count more than 5 to 8.
1264 + */
1265 +
1266 + case W25N02_N04KV_STATUS_ECC_UNCOR_ERROR:
1267 + return -EBADMSG;
1268 +
1269 + default:
1270 + break;
1271 + }
1272 +
1273 + return -EINVAL;
1274 +}
1275 +
1276 static const struct spinand_info winbond_spinand_table[] = {
1277 - SPINAND_INFO("W25M02GV", 0xAB,
1278 + SPINAND_INFO("W25M02GV",
1279 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab, 0x21),
1280 NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 2),
1281 NAND_ECCREQ(1, 512),
1282 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
1283 @@ -88,7 +191,19 @@ static const struct spinand_info winbond
1284 0,
1285 SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
1286 SPINAND_SELECT_TARGET(w25m02gv_select_target)),
1287 - SPINAND_INFO("W25N01GV", 0xAA,
1288 +#if IS_ENABLED(CONFIG_MTD_SPI_NAND_W25N01KV)
1289 + SPINAND_INFO("W25N01KV",
1290 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21),
1291 + NAND_MEMORG(1, 2048, 96, 64, 1024, 1, 1, 1),
1292 + NAND_ECCREQ(4, 512),
1293 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
1294 + &write_cache_variants,
1295 + &update_cache_variants),
1296 + 0,
1297 + SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout, w25n01kv_ecc_get_status)),
1298 +#else
1299 + SPINAND_INFO("W25N01GV",
1300 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21),
1301 NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
1302 NAND_ECCREQ(1, 512),
1303 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
1304 @@ -96,32 +211,31 @@ static const struct spinand_info winbond
1305 &update_cache_variants),
1306 0,
1307 SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)),
1308 -};
1309 -
1310 -/**
1311 - * winbond_spinand_detect - initialize device related part in spinand_device
1312 - * struct if it is a Winbond device.
1313 - * @spinand: SPI NAND device structure
1314 - */
1315 -static int winbond_spinand_detect(struct spinand_device *spinand)
1316 -{
1317 - u8 *id = spinand->id.data;
1318 - int ret;
1319 -
1320 - /*
1321 - * Winbond SPI NAND read ID need a dummy byte,
1322 - * so the first byte in raw_id is dummy.
1323 +#endif
1324 + SPINAND_INFO("W25N02KV",
1325 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
1326 + NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
1327 + NAND_ECCREQ(4, 512),
1328 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
1329 + &write_cache_variants,
1330 + &update_cache_variants),
1331 + 0,
1332 + SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout,
1333 + w25n02kv_n04kv_ecc_get_status)),
1334 + /* W25N04KV has 2-die(lun), however, it can select die automatically.
1335 + * Treat it as single die here and double block size.
1336 */
1337 - if (id[1] != SPINAND_MFR_WINBOND)
1338 - return 0;
1339 -
1340 - ret = spinand_match_and_init(spinand, winbond_spinand_table,
1341 - ARRAY_SIZE(winbond_spinand_table), id[2]);
1342 - if (ret)
1343 - return ret;
1344 -
1345 - return 1;
1346 -}
1347 + SPINAND_INFO("W25N04KV",
1348 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23),
1349 + NAND_MEMORG(1, 2048, 128, 64, 4096, 2, 1, 1),
1350 + NAND_ECCREQ(4, 512),
1351 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
1352 + &write_cache_variants,
1353 + &update_cache_variants),
1354 + 0,
1355 + SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout,
1356 + w25n02kv_n04kv_ecc_get_status)),
1357 +};
1358
1359 static int winbond_spinand_init(struct spinand_device *spinand)
1360 {
1361 @@ -142,12 +256,13 @@ static int winbond_spinand_init(struct s
1362 }
1363
1364 static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = {
1365 - .detect = winbond_spinand_detect,
1366 .init = winbond_spinand_init,
1367 };
1368
1369 const struct spinand_manufacturer winbond_spinand_manufacturer = {
1370 .id = SPINAND_MFR_WINBOND,
1371 .name = "Winbond",
1372 + .chips = winbond_spinand_table,
1373 + .nchips = ARRAY_SIZE(winbond_spinand_table),
1374 .ops = &winbond_spinand_manuf_ops,
1375 };
1376 --- a/include/linux/mtd/spinand.h
1377 +++ b/include/linux/mtd/spinand.h
1378 @@ -39,15 +39,15 @@
1379 SPI_MEM_OP_NO_DUMMY, \
1380 SPI_MEM_OP_NO_DATA)
1381
1382 -#define SPINAND_READID_OP(ndummy, buf, len) \
1383 +#define SPINAND_READID_OP(naddr, ndummy, buf, len) \
1384 SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \
1385 - SPI_MEM_OP_NO_ADDR, \
1386 + SPI_MEM_OP_ADDR(naddr, 0, 1), \
1387 SPI_MEM_OP_DUMMY(ndummy, 1), \
1388 SPI_MEM_OP_DATA_IN(len, buf, 1))
1389
1390 #define SPINAND_SET_FEATURE_OP(reg, valptr) \
1391 SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \
1392 - SPI_MEM_OP_ADDR(1, reg, 1), \
1393 + SPI_MEM_OP_ADDR(1, reg, 1), \
1394 SPI_MEM_OP_NO_DUMMY, \
1395 SPI_MEM_OP_DATA_OUT(1, valptr, 1))
1396
1397 @@ -75,18 +75,36 @@
1398 SPI_MEM_OP_DUMMY(ndummy, 1), \
1399 SPI_MEM_OP_DATA_IN(len, buf, 1))
1400
1401 +#define SPINAND_PAGE_READ_FROM_CACHE_OP_3A(fast, addr, ndummy, buf, len)\
1402 + SPI_MEM_OP(SPI_MEM_OP_CMD(fast ? 0x0b : 0x03, 1), \
1403 + SPI_MEM_OP_ADDR(3, addr, 1), \
1404 + SPI_MEM_OP_DUMMY(ndummy, 1), \
1405 + SPI_MEM_OP_DATA_IN(len, buf, 1))
1406 +
1407 #define SPINAND_PAGE_READ_FROM_CACHE_X2_OP(addr, ndummy, buf, len) \
1408 SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
1409 SPI_MEM_OP_ADDR(2, addr, 1), \
1410 SPI_MEM_OP_DUMMY(ndummy, 1), \
1411 SPI_MEM_OP_DATA_IN(len, buf, 2))
1412
1413 +#define SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(addr, ndummy, buf, len) \
1414 + SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
1415 + SPI_MEM_OP_ADDR(3, addr, 1), \
1416 + SPI_MEM_OP_DUMMY(ndummy, 1), \
1417 + SPI_MEM_OP_DATA_IN(len, buf, 2))
1418 +
1419 #define SPINAND_PAGE_READ_FROM_CACHE_X4_OP(addr, ndummy, buf, len) \
1420 SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
1421 SPI_MEM_OP_ADDR(2, addr, 1), \
1422 SPI_MEM_OP_DUMMY(ndummy, 1), \
1423 SPI_MEM_OP_DATA_IN(len, buf, 4))
1424
1425 +#define SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(addr, ndummy, buf, len) \
1426 + SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
1427 + SPI_MEM_OP_ADDR(3, addr, 1), \
1428 + SPI_MEM_OP_DUMMY(ndummy, 1), \
1429 + SPI_MEM_OP_DATA_IN(len, buf, 4))
1430 +
1431 #define SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(addr, ndummy, buf, len) \
1432 SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
1433 SPI_MEM_OP_ADDR(2, addr, 2), \
1434 @@ -153,37 +171,46 @@ struct spinand_device;
1435 * @data: buffer containing the id bytes. Currently 4 bytes large, but can
1436 * be extended if required
1437 * @len: ID length
1438 - *
1439 - * struct_spinand_id->data contains all bytes returned after a READ_ID command,
1440 - * including dummy bytes if the chip does not emit ID bytes right after the
1441 - * READ_ID command. The responsibility to extract real ID bytes is left to
1442 - * struct_manufacurer_ops->detect().
1443 */
1444 struct spinand_id {
1445 u8 data[SPINAND_MAX_ID_LEN];
1446 int len;
1447 };
1448
1449 +enum spinand_readid_method {
1450 + SPINAND_READID_METHOD_OPCODE,
1451 + SPINAND_READID_METHOD_OPCODE_ADDR,
1452 + SPINAND_READID_METHOD_OPCODE_DUMMY,
1453 +};
1454 +
1455 +/**
1456 + * struct spinand_devid - SPI NAND device id structure
1457 + * @id: device id of current chip
1458 + * @len: number of bytes in device id
1459 + * @method: method to read chip id
1460 + * There are 3 possible variants:
1461 + * SPINAND_READID_METHOD_OPCODE: chip id is returned immediately
1462 + * after read_id opcode.
1463 + * SPINAND_READID_METHOD_OPCODE_ADDR: chip id is returned after
1464 + * read_id opcode + 1-byte address.
1465 + * SPINAND_READID_METHOD_OPCODE_DUMMY: chip id is returned after
1466 + * read_id opcode + 1 dummy byte.
1467 + */
1468 +struct spinand_devid {
1469 + const u8 *id;
1470 + const u8 len;
1471 + const enum spinand_readid_method method;
1472 +};
1473 +
1474 /**
1475 * struct manufacurer_ops - SPI NAND manufacturer specific operations
1476 - * @detect: detect a SPI NAND device. Every time a SPI NAND device is probed
1477 - * the core calls the struct_manufacurer_ops->detect() hook of each
1478 - * registered manufacturer until one of them return 1. Note that
1479 - * the first thing to check in this hook is that the manufacturer ID
1480 - * in struct_spinand_device->id matches the manufacturer whose
1481 - * ->detect() hook has been called. Should return 1 if there's a
1482 - * match, 0 if the manufacturer ID does not match and a negative
1483 - * error code otherwise. When true is returned, the core assumes
1484 - * that properties of the NAND chip (spinand->base.memorg and
1485 - * spinand->base.eccreq) have been filled
1486 * @init: initialize a SPI NAND device
1487 * @cleanup: cleanup a SPI NAND device
1488 *
1489 * Each SPI NAND manufacturer driver should implement this interface so that
1490 - * NAND chips coming from this vendor can be detected and initialized properly.
1491 + * NAND chips coming from this vendor can be initialized properly.
1492 */
1493 struct spinand_manufacturer_ops {
1494 - int (*detect)(struct spinand_device *spinand);
1495 int (*init)(struct spinand_device *spinand);
1496 void (*cleanup)(struct spinand_device *spinand);
1497 };
1498 @@ -192,11 +219,16 @@ struct spinand_manufacturer_ops {
1499 * struct spinand_manufacturer - SPI NAND manufacturer instance
1500 * @id: manufacturer ID
1501 * @name: manufacturer name
1502 + * @devid_len: number of bytes in device ID
1503 + * @chips: supported SPI NANDs under current manufacturer
1504 + * @nchips: number of SPI NANDs available in chips array
1505 * @ops: manufacturer operations
1506 */
1507 struct spinand_manufacturer {
1508 u8 id;
1509 char *name;
1510 + const struct spinand_info *chips;
1511 + const size_t nchips;
1512 const struct spinand_manufacturer_ops *ops;
1513 };
1514
1515 @@ -268,7 +300,7 @@ struct spinand_ecc_info {
1516 */
1517 struct spinand_info {
1518 const char *model;
1519 - u8 devid;
1520 + struct spinand_devid devid;
1521 u32 flags;
1522 struct nand_memory_organization memorg;
1523 struct nand_ecc_req eccreq;
1524 @@ -282,6 +314,13 @@ struct spinand_info {
1525 unsigned int target);
1526 };
1527
1528 +#define SPINAND_ID(__method, ...) \
1529 + { \
1530 + .id = (const u8[]){ __VA_ARGS__ }, \
1531 + .len = sizeof((u8[]){ __VA_ARGS__ }), \
1532 + .method = __method, \
1533 + }
1534 +
1535 #define SPINAND_INFO_OP_VARIANTS(__read, __write, __update) \
1536 { \
1537 .read_cache = __read, \
1538 @@ -440,9 +479,10 @@ static inline void spinand_set_ofnode(st
1539 }
1540 #endif /* __UBOOT__ */
1541
1542 -int spinand_match_and_init(struct spinand_device *dev,
1543 +int spinand_match_and_init(struct spinand_device *spinand,
1544 const struct spinand_info *table,
1545 - unsigned int table_size, u8 devid);
1546 + unsigned int table_size,
1547 + enum spinand_readid_method rdid_method);
1548
1549 int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val);
1550 int spinand_select_target(struct spinand_device *spinand, unsigned int target);
Staging tree of Piotr Dymacz