1 From c53d249df9a75f77f5d0abb986a8913bc13070d0 Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Wed, 31 Aug 2022 19:05:09 +0800
4 Subject: [PATCH 24/32] clk: mediatek: add infrasys clock mux support
6 This patch adds infrasys clock mux support for mediatek clock drivers.
8 Reviewed-by: Simon Glass <sjg@chromium.org>
9 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
11 drivers/clk/mediatek/clk-mtk.c | 71 ++++++++++++++++++++++++++++++++++
12 drivers/clk/mediatek/clk-mtk.h | 4 +-
13 2 files changed, 74 insertions(+), 1 deletion(-)
15 --- a/drivers/clk/mediatek/clk-mtk.c
16 +++ b/drivers/clk/mediatek/clk-mtk.c
17 @@ -303,6 +303,24 @@ static ulong mtk_topckgen_get_factor_rat
18 return mtk_factor_recalc_rate(fdiv, rate);
21 +static ulong mtk_infrasys_get_factor_rate(struct clk *clk, u32 off)
23 + struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
24 + const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off];
27 + switch (fdiv->flags & CLK_PARENT_MASK) {
28 + case CLK_PARENT_TOPCKGEN:
29 + rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
33 + rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
36 + return mtk_factor_recalc_rate(fdiv, rate);
39 static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
41 struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
42 @@ -331,6 +349,33 @@ static ulong mtk_topckgen_get_mux_rate(s
43 return priv->tree->xtal_rate;
46 +static ulong mtk_infrasys_get_mux_rate(struct clk *clk, u32 off)
48 + struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
49 + const struct mtk_composite *mux = &priv->tree->muxes[off];
52 + index = readl(priv->base + mux->mux_reg);
53 + index &= mux->mux_mask << mux->mux_shift;
54 + index = index >> mux->mux_shift;
56 + if (mux->parent[index] > 0 ||
57 + (mux->parent[index] == CLK_XTAL &&
58 + priv->tree->flags & CLK_BYPASS_XTAL)) {
59 + switch (mux->flags & CLK_PARENT_MASK) {
60 + case CLK_PARENT_TOPCKGEN:
61 + return mtk_clk_find_parent_rate(clk, mux->parent[index],
65 + return mtk_clk_find_parent_rate(clk, mux->parent[index],
73 static ulong mtk_topckgen_get_rate(struct clk *clk)
75 struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
76 @@ -345,6 +390,25 @@ static ulong mtk_topckgen_get_rate(struc
77 priv->tree->muxes_offs);
80 +static ulong mtk_infrasys_get_rate(struct clk *clk)
82 + struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
86 + if (clk->id < priv->tree->fdivs_offs) {
87 + rate = priv->tree->fclks[clk->id].rate;
88 + } else if (clk->id < priv->tree->muxes_offs) {
89 + rate = mtk_infrasys_get_factor_rate(clk, clk->id -
90 + priv->tree->fdivs_offs);
92 + rate = mtk_infrasys_get_mux_rate(clk, clk->id -
93 + priv->tree->muxes_offs);
99 static int mtk_clk_mux_enable(struct clk *clk)
101 struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
102 @@ -493,6 +557,13 @@ const struct clk_ops mtk_clk_topckgen_op
103 .set_parent = mtk_common_clk_set_parent,
106 +const struct clk_ops mtk_clk_infrasys_ops = {
107 + .enable = mtk_clk_mux_enable,
108 + .disable = mtk_clk_mux_disable,
109 + .get_rate = mtk_infrasys_get_rate,
110 + .set_parent = mtk_common_clk_set_parent,
113 const struct clk_ops mtk_clk_gate_ops = {
114 .enable = mtk_clk_gate_enable,
115 .disable = mtk_clk_gate_disable,
116 --- a/drivers/clk/mediatek/clk-mtk.h
117 +++ b/drivers/clk/mediatek/clk-mtk.h
120 #define CLK_PARENT_APMIXED BIT(4)
121 #define CLK_PARENT_TOPCKGEN BIT(5)
122 -#define CLK_PARENT_MASK GENMASK(5, 4)
123 +#define CLK_PARENT_INFRASYS BIT(6)
124 +#define CLK_PARENT_MASK GENMASK(6, 4)
126 #define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34
128 @@ -220,6 +221,7 @@ struct mtk_cg_priv {
130 extern const struct clk_ops mtk_clk_apmixedsys_ops;
131 extern const struct clk_ops mtk_clk_topckgen_ops;
132 +extern const struct clk_ops mtk_clk_infrasys_ops;
133 extern const struct clk_ops mtk_clk_gate_ops;
135 int mtk_common_clk_init(struct udevice *dev,