package/boot/uboot-mediatek/patches/001-mtk-0009-reset-mtmips-add-reset-controller-support-for-MediaT.patch

   1 From 03035a6566300808c8845799b2f9ceca471aa61a Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Fri, 20 May 2022 11:22:41 +0800
   4 Subject: [PATCH 09/25] reset: mtmips: add reset controller support for
   5  MediaTek MT7621 SoC
   6
   7 This patch adds reset controller bits definition header file for MediaTek
   8 MT7621 SoC
   9
  10 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  11 ---
  12  include/dt-bindings/reset/mt7621-reset.h | 38 ++++++++++++++++++++++++
  13  1 file changed, 38 insertions(+)
  14  create mode 100644 include/dt-bindings/reset/mt7621-reset.h
  15
  16 diff --git a/include/dt-bindings/reset/mt7621-reset.h b/include/dt-bindings/reset/mt7621-reset.h
  17 new file mode 100644
  18 index 0000000000..8e4341f040
  19 --- /dev/null
  20 +++ b/include/dt-bindings/reset/mt7621-reset.h
  21 @@ -0,0 +1,38 @@
  22 +/* SPDX-License-Identifier: GPL-2.0 */
  23 +/*
  24 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
  25 + *
  26 + * Author: Weijie Gao <weijie.gao@mediatek.com>
  27 + */
  28 +
  29 +#ifndef _DT_BINDINGS_MT7621_RESET_H_
  30 +#define _DT_BINDINGS_MT7621_RESET_H_
  31 +
  32 +#define RST_PPE                        31
  33 +#define RST_SDXC               30
  34 +#define RST_CRYPTO             29
  35 +#define RST_AUX_STCK           28
  36 +#define RST_PCIE2              26
  37 +#define RST_PCIE1              25
  38 +#define RST_PCIE0              24
  39 +#define RST_GMAC               23
  40 +#define RST_UART3              21
  41 +#define RST_UART2              20
  42 +#define RST_UART1              19
  43 +#define RST_SPI                        18
  44 +#define RST_I2S                        17
  45 +#define RST_I2C                        16
  46 +#define RST_NFI                        15
  47 +#define RST_GDMA               14
  48 +#define RST_PIO                        13
  49 +#define RST_PCM                        11
  50 +#define RST_MC                 10
  51 +#define RST_INTC               9
  52 +#define RST_TIMER              8
  53 +#define RST_SPDIFTX            7
  54 +#define RST_FE                 6
  55 +#define RST_HSDMA              5
  56 +#define RST_MCM                        2
  57 +#define RST_SYS                        0
  58 +
  59 +#endif /* _DT_BINDINGS_MT7621_RESET_H_ */
  60 --
  61 2.36.1
  62