package/boot/uboot-mediatek/patches/001-mtk-0006-mips-mtmips-add-two-reference-boards-for-mt7621.patch

   1 From b1549087ecd1eb53f6173b17b473134fd6cca157 Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Fri, 20 May 2022 11:22:26 +0800
   4 Subject: [PATCH 06/25] mips: mtmips: add two reference boards for mt7621
   5
   6 The mt7621_rfb board supports integrated giga PHYs plus one external
   7 giga PHYs. It also has up to 512MiB DDR3, 16MB SPI-NOR, 3 mini PCI-e x1
   8 slots, SDXC and USB.
   9
  10 The mt7621_nand_rfb board is almost the same as mt7621_rfb board, but it
  11 uses NAND flash and SDXC is not available.
  12
  13 Reviewed-by: Stefan Roese <sr@denx.de>
  14 Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
  15 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  16 ---
  17  arch/mips/dts/Makefile                     |  2 +
  18  arch/mips/dts/mediatek,mt7621-nand-rfb.dts | 67 +++++++++++++++++
  19  arch/mips/dts/mediatek,mt7621-rfb.dts      | 82 +++++++++++++++++++++
  20  arch/mips/mach-mtmips/mt7621/Kconfig       | 20 +++++
  21  board/mediatek/mt7621/MAINTAINERS          |  8 ++
  22  board/mediatek/mt7621/Makefile             |  3 +
  23  board/mediatek/mt7621/board.c              |  6 ++
  24  configs/mt7621_nand_rfb_defconfig          | 85 ++++++++++++++++++++++
  25  configs/mt7621_rfb_defconfig               | 82 +++++++++++++++++++++
  26  9 files changed, 355 insertions(+)
  27  create mode 100644 arch/mips/dts/mediatek,mt7621-nand-rfb.dts
  28  create mode 100644 arch/mips/dts/mediatek,mt7621-rfb.dts
  29  create mode 100644 board/mediatek/mt7621/MAINTAINERS
  30  create mode 100644 board/mediatek/mt7621/Makefile
  31  create mode 100644 board/mediatek/mt7621/board.c
  32  create mode 100644 configs/mt7621_nand_rfb_defconfig
  33  create mode 100644 configs/mt7621_rfb_defconfig
  34
  35 --- a/arch/mips/dts/Makefile
  36 +++ b/arch/mips/dts/Makefile
  37 @@ -16,6 +16,8 @@ dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) +=
  38  dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
  39  dtb-$(CONFIG_BOARD_MT7620_RFB) += mediatek,mt7620-rfb.dtb
  40  dtb-$(CONFIG_BOARD_MT7620_MT7530_RFB) += mediatek,mt7620-mt7530-rfb.dtb
  41 +dtb-$(CONFIG_BOARD_MT7621_RFB) += mediatek,mt7621-rfb.dtb
  42 +dtb-$(CONFIG_BOARD_MT7621_NAND_RFB) += mediatek,mt7621-nand-rfb.dtb
  43  dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
  44  dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY_MT7688) += gardena-smart-gateway-mt7688.dtb
  45  dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += linkit-smart-7688.dtb
  46 --- /dev/null
  47 +++ b/arch/mips/dts/mediatek,mt7621-nand-rfb.dts
  48 @@ -0,0 +1,67 @@
  49 +// SPDX-License-Identifier: GPL-2.0
  50 +/*
  51 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
  52 + *
  53 + * Author: Weijie Gao <weijie.gao@mediatek.com>
  54 + */
  55 +
  56 +/dts-v1/;
  57 +
  58 +#include "mt7621.dtsi"
  59 +
  60 +/ {
  61 +       compatible = "mediatek,mt7621-nand-rfb", "mediatek,mt7621-soc";
  62 +       model = "MediaTek MT7621 RFB (NAND)";
  63 +
  64 +       aliases {
  65 +               serial0 = &uart0;
  66 +       };
  67 +
  68 +       chosen {
  69 +               stdout-path = &uart0;
  70 +       };
  71 +};
  72 +
  73 +&pinctrl {
  74 +       state_default: pin_state {
  75 +               nand {
  76 +                       groups = "spi", "sdxc";
  77 +                       function = "nand";
  78 +               };
  79 +
  80 +               gpios {
  81 +                       groups = "i2c", "uart3", "pcie reset";
  82 +                       function = "gpio";
  83 +               };
  84 +
  85 +               wdt {
  86 +                       groups = "wdt";
  87 +                       function = "wdt rst";
  88 +               };
  89 +
  90 +               jtag {
  91 +                       groups = "jtag";
  92 +                       function = "jtag";
  93 +               };
  94 +       };
  95 +};
  96 +
  97 +&uart0 {
  98 +       status = "okay";
  99 +};
 100 +
 101 +&gpio {
 102 +       status = "okay";
 103 +};
 104 +
 105 +&eth {
 106 +       status = "okay";
 107 +};
 108 +
 109 +&ssusb {
 110 +       status = "okay";
 111 +};
 112 +
 113 +&u3phy {
 114 +       status = "okay";
 115 +};
 116 --- /dev/null
 117 +++ b/arch/mips/dts/mediatek,mt7621-rfb.dts
 118 @@ -0,0 +1,82 @@
 119 +// SPDX-License-Identifier: GPL-2.0
 120 +/*
 121 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
 122 + *
 123 + * Author: Weijie Gao <weijie.gao@mediatek.com>
 124 + */
 125 +
 126 +/dts-v1/;
 127 +
 128 +#include "mt7621.dtsi"
 129 +
 130 +/ {
 131 +       compatible = "mediatek,mt7621-rfb", "mediatek,mt7621-soc";
 132 +       model = "MediaTek MT7621 RFB (SPI-NOR)";
 133 +
 134 +       aliases {
 135 +               serial0 = &uart0;
 136 +               spi0 = &spi;
 137 +       };
 138 +
 139 +       chosen {
 140 +               stdout-path = &uart0;
 141 +       };
 142 +};
 143 +
 144 +&pinctrl {
 145 +       state_default: pin_state {
 146 +               gpios {
 147 +                       groups = "i2c", "uart3", "pcie reset";
 148 +                       function = "gpio";
 149 +               };
 150 +
 151 +               wdt {
 152 +                       groups = "wdt";
 153 +                       function = "wdt rst";
 154 +               };
 155 +
 156 +               jtag {
 157 +                       groups = "jtag";
 158 +                       function = "jtag";
 159 +               };
 160 +       };
 161 +};
 162 +
 163 +&uart0 {
 164 +       status = "okay";
 165 +};
 166 +
 167 +&gpio {
 168 +       status = "okay";
 169 +};
 170 +
 171 +&spi {
 172 +       status = "okay";
 173 +       num-cs = <2>;
 174 +
 175 +       spi-flash@0 {
 176 +               #address-cells = <1>;
 177 +               #size-cells = <1>;
 178 +               compatible = "jedec,spi-nor";
 179 +               spi-max-frequency = <25000000>;
 180 +               reg = <0>;
 181 +       };
 182 +};
 183 +
 184 +&eth {
 185 +       status = "okay";
 186 +};
 187 +
 188 +&mmc {
 189 +       cap-sd-highspeed;
 190 +
 191 +       status = "okay";
 192 +};
 193 +
 194 +&ssusb {
 195 +       status = "okay";
 196 +};
 197 +
 198 +&u3phy {
 199 +       status = "okay";
 200 +};
 201 --- a/arch/mips/mach-mtmips/mt7621/Kconfig
 202 +++ b/arch/mips/mach-mtmips/mt7621/Kconfig
 203 @@ -79,6 +79,26 @@ config MT7621_BOOT_FROM_NAND
 204  choice
 205         prompt "Board select"
 206
 207 +config BOARD_MT7621_RFB
 208 +       bool "MediaTek MT7621 RFB (SPI-NOR)"
 209 +       help
 210 +         The reference design of MT7621A (WS3010) booting from SPI-NOR flash.
 211 +         The board can be configured with DDR2 (64MiB~256MiB) or DDR3
 212 +         (128MiB~512MiB). The board has 16 MiB SPI-NOR flash, built-in MT7530
 213 +         GbE switch, 1 UART, 1 USB 2.0 host, 1 USB 3.0 host, 1 SDXC, 3 PCIe
 214 +         sockets, 1 RGMII to external GbE PHY, 2 audio jacks (in/out),
 215 +         JTAG pins and expansion GPIO pins.
 216 +
 217 +config BOARD_MT7621_NAND_RFB
 218 +       bool "MediaTek MT7621 RFB (NAND)"
 219 +       help
 220 +         The reference design of MT7621A (WS3010) booting from NAND flash.
 221 +         The board can be configured with DDR2 (64MiB~256MiB) or DDR3
 222 +         (128MiB~512MiB). The board has 128 MiB parallel NAND flash, built-in
 223 +         MT7530 GbE switch, 1 UART, 1 USB 2.0 host, 1 USB 3.0 host, 3 PCIe
 224 +         sockets, 1 RGMII to external GbE PHY, 2 audio jacks (in/out),
 225 +         JTAG pins and expansion GPIO pins.
 226 +
 227  endchoice
 228
 229  config SYS_CONFIG_NAME
 230 --- /dev/null
 231 +++ b/board/mediatek/mt7621/MAINTAINERS
 232 @@ -0,0 +1,8 @@
 233 +MT7621_RFB BOARD
 234 +M:     Weijie Gao <weijie.gao@mediatek.com>
 235 +S:     Maintained
 236 +F:     board/mediatek/mt7621
 237 +F:     configs/mt7621_rfb_defconfig
 238 +F:     configs/mt7621_nand_rfb_defconfig
 239 +F:     arch/mips/dts/mediatek,mt7621-rfb.dts
 240 +F:     arch/mips/dts/mediatek,mt7621-nand-rfb.dts
 241 --- /dev/null
 242 +++ b/board/mediatek/mt7621/Makefile
 243 @@ -0,0 +1,3 @@
 244 +# SPDX-License-Identifier: GPL-2.0
 245 +
 246 +obj-y += board.o
 247 --- /dev/null
 248 +++ b/board/mediatek/mt7621/board.c
 249 @@ -0,0 +1,6 @@
 250 +// SPDX-License-Identifier: GPL-2.0
 251 +/*
 252 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
 253 + *
 254 + * Author: Weijie Gao <weijie.gao@mediatek.com>
 255 + */
 256 --- /dev/null
 257 +++ b/configs/mt7621_nand_rfb_defconfig
 258 @@ -0,0 +1,85 @@
 259 +CONFIG_MIPS=y
 260 +CONFIG_SYS_MALLOC_LEN=0x100000
 261 +CONFIG_SPL_LIBCOMMON_SUPPORT=y
 262 +CONFIG_SPL_LIBGENERIC_SUPPORT=y
 263 +CONFIG_NR_DRAM_BANKS=1
 264 +CONFIG_ENV_SIZE=0x1000
 265 +CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7621-nand-rfb"
 266 +CONFIG_SPL_SERIAL=y
 267 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
 268 +CONFIG_SPL=y
 269 +CONFIG_DEBUG_UART_BASE=0xbe000c00
 270 +CONFIG_DEBUG_UART_CLOCK=50000000
 271 +CONFIG_SYS_LOAD_ADDR=0x83000000
 272 +CONFIG_ARCH_MTMIPS=y
 273 +CONFIG_SOC_MT7621=y
 274 +CONFIG_MT7621_BOOT_FROM_NAND=y
 275 +CONFIG_BOARD_MT7621_NAND_RFB=y
 276 +# CONFIG_MIPS_CACHE_SETUP is not set
 277 +# CONFIG_MIPS_CACHE_DISABLE is not set
 278 +CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
 279 +CONFIG_MIPS_BOOT_FDT=y
 280 +CONFIG_DEBUG_UART=y
 281 +CONFIG_FIT=y
 282 +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
 283 +CONFIG_SYS_CONSOLE_INFO_QUIET=y
 284 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 285 +CONFIG_SPL_NAND_SUPPORT=y
 286 +CONFIG_SPL_NAND_BASE=y
 287 +CONFIG_SPL_NAND_IDENT=y
 288 +# CONFIG_BOOTM_NETBSD is not set
 289 +# CONFIG_BOOTM_PLAN9 is not set
 290 +# CONFIG_BOOTM_RTEMS is not set
 291 +# CONFIG_BOOTM_VXWORKS is not set
 292 +# CONFIG_CMD_ELF is not set
 293 +# CONFIG_CMD_XIMG is not set
 294 +# CONFIG_CMD_CRC32 is not set
 295 +# CONFIG_CMD_DM is not set
 296 +# CONFIG_CMD_FLASH is not set
 297 +CONFIG_CMD_GPIO=y
 298 +# CONFIG_CMD_LOADS is not set
 299 +CONFIG_CMD_MMC=y
 300 +CONFIG_CMD_MTD=y
 301 +CONFIG_CMD_PART=y
 302 +# CONFIG_CMD_PINMUX is not set
 303 +CONFIG_CMD_USB=y
 304 +# CONFIG_CMD_NFS is not set
 305 +CONFIG_CMD_FAT=y
 306 +CONFIG_CMD_FS_GENERIC=y
 307 +# CONFIG_SPL_DOS_PARTITION is not set
 308 +# CONFIG_ISO_PARTITION is not set
 309 +CONFIG_EFI_PARTITION=y
 310 +# CONFIG_SPL_EFI_PARTITION is not set
 311 +CONFIG_PARTITION_TYPE_GUID=y
 312 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 313 +CONFIG_NET_RANDOM_ETHADDR=y
 314 +# CONFIG_I2C is not set
 315 +# CONFIG_INPUT is not set
 316 +CONFIG_MMC=y
 317 +# CONFIG_MMC_QUIRKS is not set
 318 +# CONFIG_MMC_HW_PARTITIONING is not set
 319 +CONFIG_MMC_MTK=y
 320 +CONFIG_MTD=y
 321 +CONFIG_DM_MTD=y
 322 +CONFIG_MTD_RAW_NAND=y
 323 +CONFIG_NAND_MT7621=y
 324 +CONFIG_SYS_NAND_ONFI_DETECTION=y
 325 +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
 326 +CONFIG_SYS_NAND_U_BOOT_OFFS=0x0
 327 +CONFIG_MEDIATEK_ETH=y
 328 +CONFIG_PHY=y
 329 +CONFIG_PHY_MTK_TPHY=y
 330 +CONFIG_DEBUG_UART_SHIFT=2
 331 +CONFIG_SYSRESET=y
 332 +CONFIG_SYSRESET_RESETCTL=y
 333 +CONFIG_USB=y
 334 +CONFIG_USB_XHCI_HCD=y
 335 +CONFIG_USB_XHCI_MTK=y
 336 +CONFIG_USB_STORAGE=y
 337 +CONFIG_WDT=y
 338 +CONFIG_WDT_MT7621=y
 339 +CONFIG_FAT_WRITE=y
 340 +# CONFIG_BINMAN_FDT is not set
 341 +CONFIG_LZMA=y
 342 +# CONFIG_GZIP is not set
 343 +CONFIG_SPL_LZMA=y
 344 --- /dev/null
 345 +++ b/configs/mt7621_rfb_defconfig
 346 @@ -0,0 +1,82 @@
 347 +CONFIG_MIPS=y
 348 +CONFIG_SYS_MALLOC_LEN=0x100000
 349 +CONFIG_SPL_LIBCOMMON_SUPPORT=y
 350 +CONFIG_SPL_LIBGENERIC_SUPPORT=y
 351 +CONFIG_NR_DRAM_BANKS=1
 352 +CONFIG_ENV_SIZE=0x1000
 353 +CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7621-rfb"
 354 +CONFIG_SPL_SERIAL=y
 355 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000
 356 +CONFIG_SPL=y
 357 +CONFIG_DEBUG_UART_BASE=0xbe000c00
 358 +CONFIG_DEBUG_UART_CLOCK=50000000
 359 +CONFIG_SYS_LOAD_ADDR=0x83000000
 360 +CONFIG_ARCH_MTMIPS=y
 361 +CONFIG_SOC_MT7621=y
 362 +# CONFIG_MIPS_CACHE_SETUP is not set
 363 +# CONFIG_MIPS_CACHE_DISABLE is not set
 364 +CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y
 365 +CONFIG_MIPS_BOOT_FDT=y
 366 +CONFIG_DEBUG_UART=y
 367 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000
 368 +CONFIG_FIT=y
 369 +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
 370 +CONFIG_SYS_CONSOLE_INFO_QUIET=y
 371 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 372 +CONFIG_SPL_NOR_SUPPORT=y
 373 +CONFIG_TPL=y
 374 +# CONFIG_TPL_FRAMEWORK is not set
 375 +# CONFIG_BOOTM_NETBSD is not set
 376 +# CONFIG_BOOTM_PLAN9 is not set
 377 +# CONFIG_BOOTM_RTEMS is not set
 378 +# CONFIG_BOOTM_VXWORKS is not set
 379 +# CONFIG_CMD_ELF is not set
 380 +# CONFIG_CMD_XIMG is not set
 381 +# CONFIG_CMD_CRC32 is not set
 382 +# CONFIG_CMD_DM is not set
 383 +CONFIG_CMD_GPIO=y
 384 +# CONFIG_CMD_LOADS is not set
 385 +CONFIG_CMD_MMC=y
 386 +CONFIG_CMD_PART=y
 387 +# CONFIG_CMD_PINMUX is not set
 388 +CONFIG_CMD_SPI=y
 389 +# CONFIG_CMD_NFS is not set
 390 +CONFIG_DOS_PARTITION=y
 391 +# CONFIG_SPL_DOS_PARTITION is not set
 392 +# CONFIG_ISO_PARTITION is not set
 393 +CONFIG_EFI_PARTITION=y
 394 +# CONFIG_SPL_EFI_PARTITION is not set
 395 +CONFIG_PARTITION_TYPE_GUID=y
 396 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 397 +CONFIG_NET_RANDOM_ETHADDR=y
 398 +# CONFIG_I2C is not set
 399 +# CONFIG_INPUT is not set
 400 +CONFIG_MMC=y
 401 +# CONFIG_MMC_QUIRKS is not set
 402 +# CONFIG_MMC_HW_PARTITIONING is not set
 403 +CONFIG_MMC_MTK=y
 404 +CONFIG_SF_DEFAULT_SPEED=20000000
 405 +CONFIG_SPI_FLASH_BAR=y
 406 +CONFIG_SPI_FLASH_EON=y
 407 +CONFIG_SPI_FLASH_GIGADEVICE=y
 408 +CONFIG_SPI_FLASH_ISSI=y
 409 +CONFIG_SPI_FLASH_MACRONIX=y
 410 +CONFIG_SPI_FLASH_SPANSION=y
 411 +CONFIG_SPI_FLASH_STMICRO=y
 412 +CONFIG_SPI_FLASH_WINBOND=y
 413 +CONFIG_SPI_FLASH_XMC=y
 414 +CONFIG_SPI_FLASH_XTX=y
 415 +CONFIG_MEDIATEK_ETH=y
 416 +CONFIG_PHY=y
 417 +CONFIG_PHY_MTK_TPHY=y
 418 +CONFIG_DEBUG_UART_SHIFT=2
 419 +CONFIG_SPI=y
 420 +CONFIG_MT7621_SPI=y
 421 +CONFIG_SYSRESET=y
 422 +CONFIG_SYSRESET_RESETCTL=y
 423 +CONFIG_WDT=y
 424 +CONFIG_WDT_MT7621=y
 425 +# CONFIG_BINMAN_FDT is not set
 426 +CONFIG_LZMA=y
 427 +# CONFIG_GZIP is not set
 428 +CONFIG_SPL_LZMA=y