package/boot/uboot-mediatek/patches/001-mtk-0002-mips-add-more-definitions-for-asm-cm.h.patch

   1 From be570e7b0ce004127a7cc97bfae30037fc42a340 Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Fri, 20 May 2022 11:21:39 +0800
   4 Subject: [PATCH 02/25] mips: add more definitions for asm/cm.h
   5
   6 This patch add more definitions needed for MT7621 initialization.
   7 MT7621 needs to initialize GIC/CPC and other related parts.
   8
   9 Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
  10 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  11 ---
  12  arch/mips/include/asm/cm.h | 67 ++++++++++++++++++++++++++++++++++++++
  13  1 file changed, 67 insertions(+)
  14
  15 diff --git a/arch/mips/include/asm/cm.h b/arch/mips/include/asm/cm.h
  16 index 99ddbccd80..5cc8c09621 100644
  17 --- a/arch/mips/include/asm/cm.h
  18 +++ b/arch/mips/include/asm/cm.h
  19 @@ -8,9 +8,23 @@
  20  #define __MIPS_ASM_CM_H__
  21
  22  /* Global Control Register (GCR) offsets */
  23 +#define GCR_CONFIG                     0x0000
  24  #define GCR_BASE                       0x0008
  25  #define GCR_BASE_UPPER                 0x000c
  26 +#define GCR_CONTROL                    0x0010
  27 +#define GCR_ACCESS                     0x0020
  28  #define GCR_REV                                0x0030
  29 +#define GCR_GIC_BASE                   0x0080
  30 +#define GCR_CPC_BASE                   0x0088
  31 +#define GCR_REG0_BASE                  0x0090
  32 +#define GCR_REG0_MASK                  0x0098
  33 +#define GCR_REG1_BASE                  0x00a0
  34 +#define GCR_REG1_MASK                  0x00a8
  35 +#define GCR_REG2_BASE                  0x00b0
  36 +#define GCR_REG2_MASK                  0x00b8
  37 +#define GCR_REG3_BASE                  0x00c0
  38 +#define GCR_REG3_MASK                  0x00c8
  39 +#define GCR_CPC_STATUS                 0x00f0
  40  #define GCR_L2_CONFIG                  0x0130
  41  #define GCR_L2_TAG_ADDR                        0x0600
  42  #define GCR_L2_TAG_ADDR_UPPER          0x0604
  43 @@ -19,10 +33,59 @@
  44  #define GCR_L2_DATA                    0x0610
  45  #define GCR_L2_DATA_UPPER              0x0614
  46  #define GCR_Cx_COHERENCE               0x2008
  47 +#define GCR_Cx_OTHER                   0x2018
  48 +#define GCR_Cx_ID                      0x2028
  49 +#define GCR_CO_COHERENCE               0x4008
  50 +
  51 +/* GCR_CONFIG fields */
  52 +#define GCR_CONFIG_NUM_CLUSTERS_SHIFT  23
  53 +#define GCR_CONFIG_NUM_CLUSTERS                (0x7f << 23)
  54 +#define GCR_CONFIG_NUMIOCU_SHIFT       8
  55 +#define GCR_CONFIG_NUMIOCU             (0xff << 8)
  56 +#define GCR_CONFIG_PCORES_SHIFT                0
  57 +#define GCR_CONFIG_PCORES              (0xff << 0)
  58 +
  59 +/* GCR_BASE fields */
  60 +#define GCR_BASE_SHIFT                 15
  61 +#define CCA_DEFAULT_OVR_SHIFT          5
  62 +#define CCA_DEFAULT_OVR_MASK           (0x7 << 5)
  63 +#define CCA_DEFAULT_OVREN              (0x1 << 4)
  64 +#define CM_DEFAULT_TARGET_SHIFT                0
  65 +#define CM_DEFAULT_TARGET_MASK         (0x3 << 0)
  66 +
  67 +/* GCR_CONTROL fields */
  68 +#define GCR_CONTROL_SYNCCTL            (0x1 << 16)
  69
  70  /* GCR_REV CM versions */
  71  #define GCR_REV_CM3                    0x0800
  72
  73 +/* GCR_GIC_BASE fields */
  74 +#define GCR_GIC_BASE_ADDRMASK_SHIFT    7
  75 +#define GCR_GIC_BASE_ADDRMASK          (0x1ffffff << 7)
  76 +#define GCR_GIC_EN                     (0x1 << 0)
  77 +
  78 +/* GCR_CPC_BASE fields */
  79 +#define GCR_CPC_BASE_ADDRMASK_SHIFT    15
  80 +#define GCR_CPC_BASE_ADDRMASK          (0x1ffff << 15)
  81 +#define GCR_CPC_EN                     (0x1 << 0)
  82 +
  83 +/* GCR_REGn_MASK fields */
  84 +#define GCR_REGn_MASK_ADDRMASK_SHIFT   16
  85 +#define GCR_REGn_MASK_ADDRMASK         (0xffff << 16)
  86 +#define GCR_REGn_MASK_CCAOVR_SHIFT     5
  87 +#define GCR_REGn_MASK_CCAOVR           (0x7 << 5)
  88 +#define GCR_REGn_MASK_CCAOVREN         (1 << 4)
  89 +#define GCR_REGn_MASK_DROPL2           (1 << 2)
  90 +#define GCR_REGn_MASK_CMTGT_SHIFT      0
  91 +#define GCR_REGn_MASK_CMTGT            (0x3 << 0)
  92 +#define  GCR_REGn_MASK_CMTGT_DISABLED  0x0
  93 +#define  GCR_REGn_MASK_CMTGT_MEM       0x1
  94 +#define  GCR_REGn_MASK_CMTGT_IOCU0     0x2
  95 +#define  GCR_REGn_MASK_CMTGT_IOCU1     0x3
  96 +
  97 +/* GCR_CPC_STATUS fields */
  98 +#define GCR_CPC_EX                     (0x1 << 0)
  99 +
 100  /* GCR_L2_CONFIG fields */
 101  #define GCR_L2_CONFIG_ASSOC_SHIFT      0
 102  #define GCR_L2_CONFIG_ASSOC_BITS       8
 103 @@ -36,6 +99,10 @@
 104  #define GCR_Cx_COHERENCE_DOM_EN                (0xff << 0)
 105  #define GCR_Cx_COHERENCE_EN            (0x1 << 0)
 106
 107 +/* GCR_Cx_OTHER fields */
 108 +#define GCR_Cx_OTHER_CORENUM_SHIFT     16
 109 +#define GCR_Cx_OTHER_CORENUM           (0xffff << 16)
 110 +
 111  #ifndef __ASSEMBLY__
 112
 113  #include <asm/io.h>
 114 --
 115 2.36.1
 116