package/boot/uboot-kirkwood/patches/0001-cosmetic-kirkwood-style-fixes-in-kwbimage.cfg-files.patch

   1 From 76a9fed9e5580945827a82963ac7315186fd0ebe Mon Sep 17 00:00:00 2001
   2 From: Luka Perkov <luka@openwrt.org>
   3 Date: Mon, 11 Nov 2013 06:45:44 +0100
   4 Subject: [PATCH 1/9] cosmetic: kirkwood: style fixes in kwbimage.cfg files
   5
   6 When diffing through the changes only the relevant changes
   7 should be displayed.
   8
   9 Signed-off-by: Luka Perkov <luka@openwrt.org>
  10 ---
  11  board/iomega/iconnect/kwbimage.cfg  |  4 ++--
  12  board/raidsonic/ib62x0/kwbimage.cfg | 22 +++++++++++-----------
  13  2 files changed, 13 insertions(+), 13 deletions(-)
  14
  15 --- a/board/iomega/iconnect/kwbimage.cfg
  16 +++ b/board/iomega/iconnect/kwbimage.cfg
  17 @@ -20,7 +20,7 @@ NAND_PAGE_SIZE        0x0800
  18  # Configure RGMII-0 interface pad voltage to 1.8V
  19  DATA 0xffd100e0 0x1b1b1b9b
  20
  21 -#Dram initalization for SINGLE x16 CL=5 @ 400MHz
  22 +# Dram initalization for SINGLE x16 CL=5 @ 400MHz
  23  DATA 0xffd01400 0x43000c30     # DDR Configuration register
  24  # bit13-0:  0xc30, (3120 DDR2 clks refresh rate)
  25  # bit23-14: 0x0,
  26 @@ -87,7 +87,7 @@ DATA 0xffd0141c 0x00000c52    # DDR Mode
  27  # bit6-4:   0x4, CL=5
  28  # bit7:     0x0, TestMode=0 normal
  29  # bit8:     0x0, DLL reset=0 normal
  30 -# bit11-9:  0x6, auto-precharge write recovery ????????????
  31 +# bit11-9:  0x6, auto-precharge write recovery
  32  # bit12:    0x0, PD must be zero
  33  # bit31-13: 0x0, required
  34
  35 --- a/board/raidsonic/ib62x0/kwbimage.cfg
  36 +++ b/board/raidsonic/ib62x0/kwbimage.cfg
  37 @@ -11,7 +11,7 @@
  38  #
  39
  40  # Boot Media configurations
  41 -BOOT_FROM      nand    # change from nand to uart if building UART image
  42 +BOOT_FROM      nand
  43  NAND_ECC_MODE  default
  44  NAND_PAGE_SIZE 0x0800
  45
  46 @@ -21,12 +21,12 @@ NAND_PAGE_SIZE      0x0800
  47  # Configure RGMII-0 interface pad voltage to 1.8V
  48  DATA 0xffd100e0 0x1b1b1b9b
  49
  50 -#Dram initalization for SINGLE x16 CL=5 @ 400MHz
  51 +# Dram initalization for SINGLE x16 CL=5 @ 400MHz
  52  DATA 0xffd01400 0x43000c30     # DDR Configuration register
  53  # bit13-0:  0xc30, (3120 DDR2 clks refresh rate)
  54  # bit23-14: 0x0,
  55 -# bit24:    0x1,     enable exit self refresh mode on DDR access
  56 -# bit25:    0x1,     required
  57 +# bit24:    0x1,   enable exit self refresh mode on DDR access
  58 +# bit25:    0x1,   required
  59  # bit29-26: 0x0,
  60  # bit31-30: 0x1,
  61
  62 @@ -64,10 +64,10 @@ DATA 0xffd01410 0x0000000c  # DDR Address
  63  # bit3-2:   11,  Cs0size (1Gb)
  64  # bit5-4:   00,  Cs1width (x8)
  65  # bit7-6:   11,  Cs1size (1Gb)
  66 -# bit9-8:   00,  Cs2width (nonexistent
  67 -# bit11-10: 00,  Cs2size  (nonexistent
  68 -# bit13-12: 00,  Cs3width (nonexistent
  69 -# bit15-14: 00,  Cs3size  (nonexistent
  70 +# bit9-8:   00,  Cs2width (nonexistent)
  71 +# bit11-10: 00,  Cs2size (nonexistent)
  72 +# bit13-12: 00,  Cs3width (nonexistent)
  73 +# bit15-14: 00,  Cs3size (nonexistent)
  74  # bit16:    0,   Cs0AddrSel
  75  # bit17:    0,   Cs1AddrSel
  76  # bit18:    0,   Cs2AddrSel
  77 @@ -88,7 +88,7 @@ DATA 0xffd0141c 0x00000c52    # DDR Mode
  78  # bit6-4:   0x4, CL=5
  79  # bit7:     0x0, TestMode=0 normal
  80  # bit8:     0x0, DLL reset=0 normal
  81 -# bit11-9:  0x6, auto-precharge write recovery ????????????
  82 +# bit11-9:  0x6, auto-precharge write recovery
  83  # bit12:    0x0, PD must be zero
  84  # bit31-13: 0x0, required
  85
  86 @@ -148,8 +148,8 @@ DATA 0xffd0149c 0x0000e803  # CPU ODT Con
  87  DATA 0xffd01480 0x00000001     # DDR Initialization Control
  88  # bit0: 0x1, enable DDR init upon this register write
  89
  90 -DATA 0xFFD20134 0x66666666      # L2 RAM Timing 0 Register
  91 -DATA 0xFFD20138 0x66666666      # L2 RAM Timing 1 Register
  92 +DATA 0xffd20134 0x66666666     # L2 RAM Timing 0 Register
  93 +DATA 0xffd20138 0x66666666     # L2 RAM Timing 1 Register
  94
  95  # End of Header extension
  96  DATA 0x0 0x0