2 * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
10 #include <lib/utils_def.h>
12 /*******************************************************************************
13 * MIDR bit definitions
14 ******************************************************************************/
15 #define MIDR_IMPL_MASK U(0xff)
16 #define MIDR_IMPL_SHIFT U(24)
17 #define MIDR_VAR_SHIFT U(20)
18 #define MIDR_VAR_BITS U(4)
19 #define MIDR_REV_SHIFT U(0)
20 #define MIDR_REV_BITS U(4)
21 #define MIDR_PN_MASK U(0xfff)
22 #define MIDR_PN_SHIFT U(4)
24 /*******************************************************************************
26 ******************************************************************************/
27 #define MPIDR_MT_MASK (U(1) << 24)
28 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
29 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
30 #define MPIDR_AFFINITY_BITS U(8)
31 #define MPIDR_AFFLVL_MASK U(0xff)
32 #define MPIDR_AFFLVL_SHIFT U(3)
33 #define MPIDR_AFF0_SHIFT U(0)
34 #define MPIDR_AFF1_SHIFT U(8)
35 #define MPIDR_AFF2_SHIFT U(16)
36 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
37 #define MPIDR_AFFINITY_MASK U(0x00ffffff)
38 #define MPIDR_AFFLVL0 U(0)
39 #define MPIDR_AFFLVL1 U(1)
40 #define MPIDR_AFFLVL2 U(2)
41 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
43 #define MPIDR_AFFLVL0_VAL(mpidr) \
44 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
45 #define MPIDR_AFFLVL1_VAL(mpidr) \
46 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
47 #define MPIDR_AFFLVL2_VAL(mpidr) \
48 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
49 #define MPIDR_AFFLVL3_VAL(mpidr) U(0)
51 #define MPIDR_AFF_ID(mpid, n) \
52 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
54 #define MPID_MASK (MPIDR_MT_MASK |\
55 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\
56 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)|\
57 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
60 * An invalid MPID. This value can be used by functions that return an MPID to
63 #define INVALID_MPID U(0xFFFFFFFF)
66 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
67 * add one while using this macro to define array sizes.
69 #define MPIDR_MAX_AFFLVL U(2)
71 /* Data Cache set/way op type defines */
72 #define DC_OP_ISW U(0x0)
73 #define DC_OP_CISW U(0x1)
75 #define DC_OP_CSW DC_OP_CISW
77 #define DC_OP_CSW U(0x2)
80 /*******************************************************************************
81 * Generic timer memory mapped registers & offsets
82 ******************************************************************************/
83 #define CNTCR_OFF U(0x000)
84 /* Counter Count Value Lower register */
85 #define CNTCVL_OFF U(0x008)
86 /* Counter Count Value Upper register */
87 #define CNTCVU_OFF U(0x00C)
88 #define CNTFID_OFF U(0x020)
90 #define CNTCR_EN (U(1) << 0)
91 #define CNTCR_HDBG (U(1) << 1)
92 #define CNTCR_FCREQ(x) ((x) << 8)
94 /*******************************************************************************
95 * System register bit definitions
96 ******************************************************************************/
97 /* CLIDR definitions */
98 #define LOUIS_SHIFT U(21)
99 #define LOC_SHIFT U(24)
100 #define CLIDR_FIELD_WIDTH U(3)
102 /* CSSELR definitions */
103 #define LEVEL_SHIFT U(1)
105 /* ID_MMFR4 definitions */
106 #define ID_MMFR4_CNP_SHIFT U(12)
107 #define ID_MMFR4_CNP_LENGTH U(4)
108 #define ID_MMFR4_CNP_MASK U(0xf)
110 /* ID_PFR0 definitions */
111 #define ID_PFR0_AMU_SHIFT U(20)
112 #define ID_PFR0_AMU_LENGTH U(4)
113 #define ID_PFR0_AMU_MASK U(0xf)
115 #define ID_PFR0_DIT_SHIFT U(24)
116 #define ID_PFR0_DIT_LENGTH U(4)
117 #define ID_PFR0_DIT_MASK U(0xf)
118 #define ID_PFR0_DIT_SUPPORTED (U(1) << ID_PFR0_DIT_SHIFT)
120 /* ID_PFR1 definitions */
121 #define ID_PFR1_VIRTEXT_SHIFT U(12)
122 #define ID_PFR1_VIRTEXT_MASK U(0xf)
123 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
124 & ID_PFR1_VIRTEXT_MASK)
125 #define ID_PFR1_GENTIMER_SHIFT U(16)
126 #define ID_PFR1_GENTIMER_MASK U(0xf)
127 #define ID_PFR1_GIC_SHIFT U(28)
128 #define ID_PFR1_GIC_MASK U(0xf)
130 /* SCTLR definitions */
131 #define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \
133 #if ARM_ARCH_MAJOR == 7
134 #define SCTLR_RES1 SCTLR_RES1_DEF
136 #define SCTLR_RES1 (SCTLR_RES1_DEF | (U(1) << 11))
138 #define SCTLR_M_BIT (U(1) << 0)
139 #define SCTLR_A_BIT (U(1) << 1)
140 #define SCTLR_C_BIT (U(1) << 2)
141 #define SCTLR_CP15BEN_BIT (U(1) << 5)
142 #define SCTLR_ITD_BIT (U(1) << 7)
143 #define SCTLR_Z_BIT (U(1) << 11)
144 #define SCTLR_I_BIT (U(1) << 12)
145 #define SCTLR_V_BIT (U(1) << 13)
146 #define SCTLR_RR_BIT (U(1) << 14)
147 #define SCTLR_NTWI_BIT (U(1) << 16)
148 #define SCTLR_NTWE_BIT (U(1) << 18)
149 #define SCTLR_WXN_BIT (U(1) << 19)
150 #define SCTLR_UWXN_BIT (U(1) << 20)
151 #define SCTLR_EE_BIT (U(1) << 25)
152 #define SCTLR_TRE_BIT (U(1) << 28)
153 #define SCTLR_AFE_BIT (U(1) << 29)
154 #define SCTLR_TE_BIT (U(1) << 30)
155 #define SCTLR_DSSBS_BIT (U(1) << 31)
156 #define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \
157 SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT)
159 /* SDCR definitions */
160 #define SDCR_SPD(x) ((x) << 14)
161 #define SDCR_SPD_LEGACY U(0x0)
162 #define SDCR_SPD_DISABLE U(0x2)
163 #define SDCR_SPD_ENABLE U(0x3)
164 #define SDCR_SCCD_BIT (U(1) << 23)
165 #define SDCR_SPME_BIT (U(1) << 17)
166 #define SDCR_RESET_VAL U(0x0)
168 /* HSCTLR definitions */
169 #define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
170 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
171 (U(1) << 11) | (U(1) << 4) | (U(1) << 3))
173 #define HSCTLR_M_BIT (U(1) << 0)
174 #define HSCTLR_A_BIT (U(1) << 1)
175 #define HSCTLR_C_BIT (U(1) << 2)
176 #define HSCTLR_CP15BEN_BIT (U(1) << 5)
177 #define HSCTLR_ITD_BIT (U(1) << 7)
178 #define HSCTLR_SED_BIT (U(1) << 8)
179 #define HSCTLR_I_BIT (U(1) << 12)
180 #define HSCTLR_WXN_BIT (U(1) << 19)
181 #define HSCTLR_EE_BIT (U(1) << 25)
182 #define HSCTLR_TE_BIT (U(1) << 30)
184 /* CPACR definitions */
185 #define CPACR_FPEN(x) ((x) << 20)
186 #define CPACR_FP_TRAP_PL0 U(0x1)
187 #define CPACR_FP_TRAP_ALL U(0x2)
188 #define CPACR_FP_TRAP_NONE U(0x3)
190 /* SCR definitions */
191 #define SCR_TWE_BIT (U(1) << 13)
192 #define SCR_TWI_BIT (U(1) << 12)
193 #define SCR_SIF_BIT (U(1) << 9)
194 #define SCR_HCE_BIT (U(1) << 8)
195 #define SCR_SCD_BIT (U(1) << 7)
196 #define SCR_NET_BIT (U(1) << 6)
197 #define SCR_AW_BIT (U(1) << 5)
198 #define SCR_FW_BIT (U(1) << 4)
199 #define SCR_EA_BIT (U(1) << 3)
200 #define SCR_FIQ_BIT (U(1) << 2)
201 #define SCR_IRQ_BIT (U(1) << 1)
202 #define SCR_NS_BIT (U(1) << 0)
203 #define SCR_VALID_BIT_MASK U(0x33ff)
204 #define SCR_RESET_VAL U(0x0)
206 #define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT)
208 /* HCR definitions */
209 #define HCR_TGE_BIT (U(1) << 27)
210 #define HCR_AMO_BIT (U(1) << 5)
211 #define HCR_IMO_BIT (U(1) << 4)
212 #define HCR_FMO_BIT (U(1) << 3)
213 #define HCR_RESET_VAL U(0x0)
215 /* CNTHCTL definitions */
216 #define CNTHCTL_RESET_VAL U(0x0)
217 #define PL1PCEN_BIT (U(1) << 1)
218 #define PL1PCTEN_BIT (U(1) << 0)
220 /* CNTKCTL definitions */
221 #define PL0PTEN_BIT (U(1) << 9)
222 #define PL0VTEN_BIT (U(1) << 8)
223 #define PL0PCTEN_BIT (U(1) << 0)
224 #define PL0VCTEN_BIT (U(1) << 1)
225 #define EVNTEN_BIT (U(1) << 2)
226 #define EVNTDIR_BIT (U(1) << 3)
227 #define EVNTI_SHIFT U(4)
228 #define EVNTI_MASK U(0xf)
230 /* HCPTR definitions */
231 #define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff))
232 #define TCPAC_BIT (U(1) << 31)
233 #define TAM_BIT (U(1) << 30)
234 #define TTA_BIT (U(1) << 20)
235 #define TCP11_BIT (U(1) << 11)
236 #define TCP10_BIT (U(1) << 10)
237 #define HCPTR_RESET_VAL HCPTR_RES1
239 /* VTTBR defintions */
240 #define VTTBR_RESET_VAL ULL(0x0)
241 #define VTTBR_VMID_MASK ULL(0xff)
242 #define VTTBR_VMID_SHIFT U(48)
243 #define VTTBR_BADDR_MASK ULL(0xffffffffffff)
244 #define VTTBR_BADDR_SHIFT U(0)
246 /* HDCR definitions */
247 #define HDCR_HLP_BIT (U(1) << 26)
248 #define HDCR_HPME_BIT (U(1) << 7)
249 #define HDCR_RESET_VAL U(0x0)
251 /* HSTR definitions */
252 #define HSTR_RESET_VAL U(0x0)
254 /* CNTHP_CTL definitions */
255 #define CNTHP_CTL_RESET_VAL U(0x0)
257 /* NSACR definitions */
258 #define NSASEDIS_BIT (U(1) << 15)
259 #define NSTRCDIS_BIT (U(1) << 20)
260 #define NSACR_CP11_BIT (U(1) << 11)
261 #define NSACR_CP10_BIT (U(1) << 10)
262 #define NSACR_IMP_DEF_MASK (U(0x7) << 16)
263 #define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT)
264 #define NSACR_RESET_VAL U(0x0)
266 /* CPACR definitions */
267 #define ASEDIS_BIT (U(1) << 31)
268 #define TRCDIS_BIT (U(1) << 28)
269 #define CPACR_CP11_SHIFT U(22)
270 #define CPACR_CP10_SHIFT U(20)
271 #define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\
272 (U(0x3) << CPACR_CP10_SHIFT))
273 #define CPACR_RESET_VAL U(0x0)
275 /* FPEXC definitions */
276 #define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8))
277 #define FPEXC_EN_BIT (U(1) << 30)
278 #define FPEXC_RESET_VAL FPEXC_RES1
280 /* SPSR/CPSR definitions */
281 #define SPSR_FIQ_BIT (U(1) << 0)
282 #define SPSR_IRQ_BIT (U(1) << 1)
283 #define SPSR_ABT_BIT (U(1) << 2)
284 #define SPSR_AIF_SHIFT U(6)
285 #define SPSR_AIF_MASK U(0x7)
287 #define SPSR_E_SHIFT U(9)
288 #define SPSR_E_MASK U(0x1)
289 #define SPSR_E_LITTLE U(0)
290 #define SPSR_E_BIG U(1)
292 #define SPSR_T_SHIFT U(5)
293 #define SPSR_T_MASK U(0x1)
294 #define SPSR_T_ARM U(0)
295 #define SPSR_T_THUMB U(1)
297 #define SPSR_MODE_SHIFT U(0)
298 #define SPSR_MODE_MASK U(0x7)
300 #define SPSR_SSBS_BIT BIT_32(23)
302 #define DISABLE_ALL_EXCEPTIONS \
303 (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT)
305 #define CPSR_DIT_BIT (U(1) << 21)
309 #define TTBCR_EAE_BIT (U(1) << 31)
311 #define TTBCR_SH1_NON_SHAREABLE (U(0x0) << 28)
312 #define TTBCR_SH1_OUTER_SHAREABLE (U(0x2) << 28)
313 #define TTBCR_SH1_INNER_SHAREABLE (U(0x3) << 28)
315 #define TTBCR_RGN1_OUTER_NC (U(0x0) << 26)
316 #define TTBCR_RGN1_OUTER_WBA (U(0x1) << 26)
317 #define TTBCR_RGN1_OUTER_WT (U(0x2) << 26)
318 #define TTBCR_RGN1_OUTER_WBNA (U(0x3) << 26)
320 #define TTBCR_RGN1_INNER_NC (U(0x0) << 24)
321 #define TTBCR_RGN1_INNER_WBA (U(0x1) << 24)
322 #define TTBCR_RGN1_INNER_WT (U(0x2) << 24)
323 #define TTBCR_RGN1_INNER_WBNA (U(0x3) << 24)
325 #define TTBCR_EPD1_BIT (U(1) << 23)
326 #define TTBCR_A1_BIT (U(1) << 22)
328 #define TTBCR_T1SZ_SHIFT U(16)
329 #define TTBCR_T1SZ_MASK U(0x7)
330 #define TTBCR_TxSZ_MIN U(0)
331 #define TTBCR_TxSZ_MAX U(7)
333 #define TTBCR_SH0_NON_SHAREABLE (U(0x0) << 12)
334 #define TTBCR_SH0_OUTER_SHAREABLE (U(0x2) << 12)
335 #define TTBCR_SH0_INNER_SHAREABLE (U(0x3) << 12)
337 #define TTBCR_RGN0_OUTER_NC (U(0x0) << 10)
338 #define TTBCR_RGN0_OUTER_WBA (U(0x1) << 10)
339 #define TTBCR_RGN0_OUTER_WT (U(0x2) << 10)
340 #define TTBCR_RGN0_OUTER_WBNA (U(0x3) << 10)
342 #define TTBCR_RGN0_INNER_NC (U(0x0) << 8)
343 #define TTBCR_RGN0_INNER_WBA (U(0x1) << 8)
344 #define TTBCR_RGN0_INNER_WT (U(0x2) << 8)
345 #define TTBCR_RGN0_INNER_WBNA (U(0x3) << 8)
347 #define TTBCR_EPD0_BIT (U(1) << 7)
348 #define TTBCR_T0SZ_SHIFT U(0)
349 #define TTBCR_T0SZ_MASK U(0x7)
354 #define HTCR_RES1 ((U(1) << 31) | (U(1) << 23))
356 #define HTCR_SH0_NON_SHAREABLE (U(0x0) << 12)
357 #define HTCR_SH0_OUTER_SHAREABLE (U(0x2) << 12)
358 #define HTCR_SH0_INNER_SHAREABLE (U(0x3) << 12)
360 #define HTCR_RGN0_OUTER_NC (U(0x0) << 10)
361 #define HTCR_RGN0_OUTER_WBA (U(0x1) << 10)
362 #define HTCR_RGN0_OUTER_WT (U(0x2) << 10)
363 #define HTCR_RGN0_OUTER_WBNA (U(0x3) << 10)
365 #define HTCR_RGN0_INNER_NC (U(0x0) << 8)
366 #define HTCR_RGN0_INNER_WBA (U(0x1) << 8)
367 #define HTCR_RGN0_INNER_WT (U(0x2) << 8)
368 #define HTCR_RGN0_INNER_WBNA (U(0x3) << 8)
370 #define HTCR_T0SZ_SHIFT U(0)
371 #define HTCR_T0SZ_MASK U(0x7)
373 #define MODE_RW_SHIFT U(0x4)
374 #define MODE_RW_MASK U(0x1)
375 #define MODE_RW_32 U(0x1)
377 #define MODE32_SHIFT U(0)
378 #define MODE32_MASK U(0x1f)
379 #define MODE32_usr U(0x10)
380 #define MODE32_fiq U(0x11)
381 #define MODE32_irq U(0x12)
382 #define MODE32_svc U(0x13)
383 #define MODE32_mon U(0x16)
384 #define MODE32_abt U(0x17)
385 #define MODE32_hyp U(0x1a)
386 #define MODE32_und U(0x1b)
387 #define MODE32_sys U(0x1f)
389 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
391 #define SPSR_MODE32(mode, isa, endian, aif) \
392 ((MODE_RW_32 << MODE_RW_SHIFT | \
393 ((mode) & MODE32_MASK) << MODE32_SHIFT | \
394 ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \
395 ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \
396 ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) & \
402 #define TTBR_CNP_BIT ULL(0x1)
407 #define CTR_CWG_SHIFT U(24)
408 #define CTR_CWG_MASK U(0xf)
409 #define CTR_ERG_SHIFT U(20)
410 #define CTR_ERG_MASK U(0xf)
411 #define CTR_DMINLINE_SHIFT U(16)
412 #define CTR_DMINLINE_WIDTH U(4)
413 #define CTR_DMINLINE_MASK ((U(1) << 4) - U(1))
414 #define CTR_L1IP_SHIFT U(14)
415 #define CTR_L1IP_MASK U(0x3)
416 #define CTR_IMINLINE_SHIFT U(0)
417 #define CTR_IMINLINE_MASK U(0xf)
419 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
421 /* PMCR definitions */
422 #define PMCR_N_SHIFT U(11)
423 #define PMCR_N_MASK U(0x1f)
424 #define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT)
425 #define PMCR_LP_BIT (U(1) << 7)
426 #define PMCR_LC_BIT (U(1) << 6)
427 #define PMCR_DP_BIT (U(1) << 5)
428 #define PMCR_RESET_VAL U(0x0)
430 /*******************************************************************************
431 * Definitions of register offsets, fields and macros for CPU system
433 ******************************************************************************/
435 #define TLBI_ADDR_SHIFT U(0)
436 #define TLBI_ADDR_MASK U(0xFFFFF000)
437 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
439 /*******************************************************************************
440 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
441 * system level implementation of the Generic Timer.
442 ******************************************************************************/
443 #define CNTCTLBASE_CNTFRQ U(0x0)
444 #define CNTNSAR U(0x4)
445 #define CNTNSAR_NS_SHIFT(x) (x)
447 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
448 #define CNTACR_RPCT_SHIFT U(0x0)
449 #define CNTACR_RVCT_SHIFT U(0x1)
450 #define CNTACR_RFRQ_SHIFT U(0x2)
451 #define CNTACR_RVOFF_SHIFT U(0x3)
452 #define CNTACR_RWVT_SHIFT U(0x4)
453 #define CNTACR_RWPT_SHIFT U(0x5)
455 /*******************************************************************************
456 * Definitions of register offsets and fields in the CNTBaseN Frame of the
457 * system level implementation of the Generic Timer.
458 ******************************************************************************/
459 /* Physical Count register. */
460 #define CNTPCT_LO U(0x0)
461 /* Counter Frequency register. */
462 #define CNTBASEN_CNTFRQ U(0x10)
463 /* Physical Timer CompareValue register. */
464 #define CNTP_CVAL_LO U(0x20)
465 /* Physical Timer Control register. */
466 #define CNTP_CTL U(0x2c)
468 /* Physical timer control register bit fields shifts and masks */
469 #define CNTP_CTL_ENABLE_SHIFT 0
470 #define CNTP_CTL_IMASK_SHIFT 1
471 #define CNTP_CTL_ISTATUS_SHIFT 2
473 #define CNTP_CTL_ENABLE_MASK U(1)
474 #define CNTP_CTL_IMASK_MASK U(1)
475 #define CNTP_CTL_ISTATUS_MASK U(1)
478 #define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3)))
479 #define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << U(3)))
481 /* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */
482 #define SCR p15, 0, c1, c1, 0
483 #define SCTLR p15, 0, c1, c0, 0
484 #define ACTLR p15, 0, c1, c0, 1
485 #define SDCR p15, 0, c1, c3, 1
486 #define MPIDR p15, 0, c0, c0, 5
487 #define MIDR p15, 0, c0, c0, 0
488 #define HVBAR p15, 4, c12, c0, 0
489 #define VBAR p15, 0, c12, c0, 0
490 #define MVBAR p15, 0, c12, c0, 1
491 #define NSACR p15, 0, c1, c1, 2
492 #define CPACR p15, 0, c1, c0, 2
493 #define DCCIMVAC p15, 0, c7, c14, 1
494 #define DCCMVAC p15, 0, c7, c10, 1
495 #define DCIMVAC p15, 0, c7, c6, 1
496 #define DCCISW p15, 0, c7, c14, 2
497 #define DCCSW p15, 0, c7, c10, 2
498 #define DCISW p15, 0, c7, c6, 2
499 #define CTR p15, 0, c0, c0, 1
500 #define CNTFRQ p15, 0, c14, c0, 0
501 #define ID_MMFR4 p15, 0, c0, c2, 6
502 #define ID_PFR0 p15, 0, c0, c1, 0
503 #define ID_PFR1 p15, 0, c0, c1, 1
504 #define MAIR0 p15, 0, c10, c2, 0
505 #define MAIR1 p15, 0, c10, c2, 1
506 #define TTBCR p15, 0, c2, c0, 2
507 #define TTBR0 p15, 0, c2, c0, 0
508 #define TTBR1 p15, 0, c2, c0, 1
509 #define TLBIALL p15, 0, c8, c7, 0
510 #define TLBIALLH p15, 4, c8, c7, 0
511 #define TLBIALLIS p15, 0, c8, c3, 0
512 #define TLBIMVA p15, 0, c8, c7, 1
513 #define TLBIMVAA p15, 0, c8, c7, 3
514 #define TLBIMVAAIS p15, 0, c8, c3, 3
515 #define TLBIMVAHIS p15, 4, c8, c3, 1
516 #define BPIALLIS p15, 0, c7, c1, 6
517 #define BPIALL p15, 0, c7, c5, 6
518 #define ICIALLU p15, 0, c7, c5, 0
519 #define HSCTLR p15, 4, c1, c0, 0
520 #define HCR p15, 4, c1, c1, 0
521 #define HCPTR p15, 4, c1, c1, 2
522 #define HSTR p15, 4, c1, c1, 3
523 #define CNTHCTL p15, 4, c14, c1, 0
524 #define CNTKCTL p15, 0, c14, c1, 0
525 #define VPIDR p15, 4, c0, c0, 0
526 #define VMPIDR p15, 4, c0, c0, 5
527 #define ISR p15, 0, c12, c1, 0
528 #define CLIDR p15, 1, c0, c0, 1
529 #define CSSELR p15, 2, c0, c0, 0
530 #define CCSIDR p15, 1, c0, c0, 0
531 #define HTCR p15, 4, c2, c0, 2
532 #define HMAIR0 p15, 4, c10, c2, 0
533 #define ATS1CPR p15, 0, c7, c8, 0
534 #define ATS1HR p15, 4, c7, c8, 0
535 #define DBGOSDLR p14, 0, c1, c3, 4
537 /* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
538 #define HDCR p15, 4, c1, c1, 1
539 #define PMCR p15, 0, c9, c12, 0
540 #define CNTHP_TVAL p15, 4, c14, c2, 0
541 #define CNTHP_CTL p15, 4, c14, c2, 1
543 /* AArch32 coproc registers for 32bit MMU descriptor support */
544 #define PRRR p15, 0, c10, c2, 0
545 #define NMRR p15, 0, c10, c2, 1
546 #define DACR p15, 0, c3, c0, 0
548 /* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
549 #define ICC_IAR1 p15, 0, c12, c12, 0
550 #define ICC_IAR0 p15, 0, c12, c8, 0
551 #define ICC_EOIR1 p15, 0, c12, c12, 1
552 #define ICC_EOIR0 p15, 0, c12, c8, 1
553 #define ICC_HPPIR1 p15, 0, c12, c12, 2
554 #define ICC_HPPIR0 p15, 0, c12, c8, 2
555 #define ICC_BPR1 p15, 0, c12, c12, 3
556 #define ICC_BPR0 p15, 0, c12, c8, 3
557 #define ICC_DIR p15, 0, c12, c11, 1
558 #define ICC_PMR p15, 0, c4, c6, 0
559 #define ICC_RPR p15, 0, c12, c11, 3
560 #define ICC_CTLR p15, 0, c12, c12, 4
561 #define ICC_MCTLR p15, 6, c12, c12, 4
562 #define ICC_SRE p15, 0, c12, c12, 5
563 #define ICC_HSRE p15, 4, c12, c9, 5
564 #define ICC_MSRE p15, 6, c12, c12, 5
565 #define ICC_IGRPEN0 p15, 0, c12, c12, 6
566 #define ICC_IGRPEN1 p15, 0, c12, c12, 7
567 #define ICC_MGRPEN1 p15, 6, c12, c12, 7
569 /* 64 bit system register defines The format is: coproc, opt1, CRm */
570 #define TTBR0_64 p15, 0, c2
571 #define TTBR1_64 p15, 1, c2
572 #define CNTVOFF_64 p15, 4, c14
573 #define VTTBR_64 p15, 6, c2
574 #define CNTPCT_64 p15, 0, c14
575 #define HTTBR_64 p15, 4, c2
576 #define CNTHP_CVAL_64 p15, 6, c14
577 #define PAR_64 p15, 0, c7
579 /* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */
580 #define ICC_SGI1R_EL1_64 p15, 0, c12
581 #define ICC_ASGI1R_EL1_64 p15, 1, c12
582 #define ICC_SGI0R_EL1_64 p15, 2, c12
584 /*******************************************************************************
585 * Definitions of MAIR encodings for device and normal memory
586 ******************************************************************************/
588 * MAIR encodings for device memory attributes.
590 #define MAIR_DEV_nGnRnE U(0x0)
591 #define MAIR_DEV_nGnRE U(0x4)
592 #define MAIR_DEV_nGRE U(0x8)
593 #define MAIR_DEV_GRE U(0xc)
596 * MAIR encodings for normal memory attributes.
610 * RWA: Read and Write Allocate
613 #define MAIR_NORM_WT_TR_WA U(0x1)
614 #define MAIR_NORM_WT_TR_RA U(0x2)
615 #define MAIR_NORM_WT_TR_RWA U(0x3)
616 #define MAIR_NORM_NC U(0x4)
617 #define MAIR_NORM_WB_TR_WA U(0x5)
618 #define MAIR_NORM_WB_TR_RA U(0x6)
619 #define MAIR_NORM_WB_TR_RWA U(0x7)
620 #define MAIR_NORM_WT_NTR_NA U(0x8)
621 #define MAIR_NORM_WT_NTR_WA U(0x9)
622 #define MAIR_NORM_WT_NTR_RA U(0xa)
623 #define MAIR_NORM_WT_NTR_RWA U(0xb)
624 #define MAIR_NORM_WB_NTR_NA U(0xc)
625 #define MAIR_NORM_WB_NTR_WA U(0xd)
626 #define MAIR_NORM_WB_NTR_RA U(0xe)
627 #define MAIR_NORM_WB_NTR_RWA U(0xf)
629 #define MAIR_NORM_OUTER_SHIFT U(4)
631 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
632 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
635 #define PAR_F_SHIFT U(0)
636 #define PAR_F_MASK ULL(0x1)
637 #define PAR_ADDR_SHIFT U(12)
638 #define PAR_ADDR_MASK (BIT_64(40) - ULL(1)) /* 40-bits-wide page address */
640 /*******************************************************************************
641 * Definitions for system register interface to AMU for ARMv8.4 onwards
642 ******************************************************************************/
643 #define AMCR p15, 0, c13, c2, 0
644 #define AMCFGR p15, 0, c13, c2, 1
645 #define AMCGCR p15, 0, c13, c2, 2
646 #define AMUSERENR p15, 0, c13, c2, 3
647 #define AMCNTENCLR0 p15, 0, c13, c2, 4
648 #define AMCNTENSET0 p15, 0, c13, c2, 5
649 #define AMCNTENCLR1 p15, 0, c13, c3, 0
650 #define AMCNTENSET1 p15, 0, c13, c3, 1
652 /* Activity Monitor Group 0 Event Counter Registers */
653 #define AMEVCNTR00 p15, 0, c0
654 #define AMEVCNTR01 p15, 1, c0
655 #define AMEVCNTR02 p15, 2, c0
656 #define AMEVCNTR03 p15, 3, c0
658 /* Activity Monitor Group 0 Event Type Registers */
659 #define AMEVTYPER00 p15, 0, c13, c6, 0
660 #define AMEVTYPER01 p15, 0, c13, c6, 1
661 #define AMEVTYPER02 p15, 0, c13, c6, 2
662 #define AMEVTYPER03 p15, 0, c13, c6, 3
664 /* Activity Monitor Group 1 Event Counter Registers */
665 #define AMEVCNTR10 p15, 0, c4
666 #define AMEVCNTR11 p15, 1, c4
667 #define AMEVCNTR12 p15, 2, c4
668 #define AMEVCNTR13 p15, 3, c4
669 #define AMEVCNTR14 p15, 4, c4
670 #define AMEVCNTR15 p15, 5, c4
671 #define AMEVCNTR16 p15, 6, c4
672 #define AMEVCNTR17 p15, 7, c4
673 #define AMEVCNTR18 p15, 0, c5
674 #define AMEVCNTR19 p15, 1, c5
675 #define AMEVCNTR1A p15, 2, c5
676 #define AMEVCNTR1B p15, 3, c5
677 #define AMEVCNTR1C p15, 4, c5
678 #define AMEVCNTR1D p15, 5, c5
679 #define AMEVCNTR1E p15, 6, c5
680 #define AMEVCNTR1F p15, 7, c5
682 /* Activity Monitor Group 1 Event Type Registers */
683 #define AMEVTYPER10 p15, 0, c13, c14, 0
684 #define AMEVTYPER11 p15, 0, c13, c14, 1
685 #define AMEVTYPER12 p15, 0, c13, c14, 2
686 #define AMEVTYPER13 p15, 0, c13, c14, 3
687 #define AMEVTYPER14 p15, 0, c13, c14, 4
688 #define AMEVTYPER15 p15, 0, c13, c14, 5
689 #define AMEVTYPER16 p15, 0, c13, c14, 6
690 #define AMEVTYPER17 p15, 0, c13, c14, 7
691 #define AMEVTYPER18 p15, 0, c13, c15, 0
692 #define AMEVTYPER19 p15, 0, c13, c15, 1
693 #define AMEVTYPER1A p15, 0, c13, c15, 2
694 #define AMEVTYPER1B p15, 0, c13, c15, 3
695 #define AMEVTYPER1C p15, 0, c13, c15, 4
696 #define AMEVTYPER1D p15, 0, c13, c15, 5
697 #define AMEVTYPER1E p15, 0, c13, c15, 6
698 #define AMEVTYPER1F p15, 0, c13, c15, 7
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