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[openwrt/staging/blogic.git] / dma / tegra20-apb-dma.c
1 /*
2 * DMA driver for Nvidia's Tegra20 APB DMA controller.
3 *
4 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include <linux/bitops.h>
20 #include <linux/clk.h>
21 #include <linux/delay.h>
22 #include <linux/dmaengine.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/err.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/mm.h>
29 #include <linux/module.h>
30 #include <linux/of.h>
31 #include <linux/of_device.h>
32 #include <linux/of_dma.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/reset.h>
37 #include <linux/slab.h>
38
39 #include "dmaengine.h"
40
41 #define TEGRA_APBDMA_GENERAL 0x0
42 #define TEGRA_APBDMA_GENERAL_ENABLE BIT(31)
43
44 #define TEGRA_APBDMA_CONTROL 0x010
45 #define TEGRA_APBDMA_IRQ_MASK 0x01c
46 #define TEGRA_APBDMA_IRQ_MASK_SET 0x020
47
48 /* CSR register */
49 #define TEGRA_APBDMA_CHAN_CSR 0x00
50 #define TEGRA_APBDMA_CSR_ENB BIT(31)
51 #define TEGRA_APBDMA_CSR_IE_EOC BIT(30)
52 #define TEGRA_APBDMA_CSR_HOLD BIT(29)
53 #define TEGRA_APBDMA_CSR_DIR BIT(28)
54 #define TEGRA_APBDMA_CSR_ONCE BIT(27)
55 #define TEGRA_APBDMA_CSR_FLOW BIT(21)
56 #define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT 16
57 #define TEGRA_APBDMA_CSR_REQ_SEL_MASK 0x1F
58 #define TEGRA_APBDMA_CSR_WCOUNT_MASK 0xFFFC
59
60 /* STATUS register */
61 #define TEGRA_APBDMA_CHAN_STATUS 0x004
62 #define TEGRA_APBDMA_STATUS_BUSY BIT(31)
63 #define TEGRA_APBDMA_STATUS_ISE_EOC BIT(30)
64 #define TEGRA_APBDMA_STATUS_HALT BIT(29)
65 #define TEGRA_APBDMA_STATUS_PING_PONG BIT(28)
66 #define TEGRA_APBDMA_STATUS_COUNT_SHIFT 2
67 #define TEGRA_APBDMA_STATUS_COUNT_MASK 0xFFFC
68
69 #define TEGRA_APBDMA_CHAN_CSRE 0x00C
70 #define TEGRA_APBDMA_CHAN_CSRE_PAUSE (1 << 31)
71
72 /* AHB memory address */
73 #define TEGRA_APBDMA_CHAN_AHBPTR 0x010
74
75 /* AHB sequence register */
76 #define TEGRA_APBDMA_CHAN_AHBSEQ 0x14
77 #define TEGRA_APBDMA_AHBSEQ_INTR_ENB BIT(31)
78 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8 (0 << 28)
79 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16 (1 << 28)
80 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32 (2 << 28)
81 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64 (3 << 28)
82 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128 (4 << 28)
83 #define TEGRA_APBDMA_AHBSEQ_DATA_SWAP BIT(27)
84 #define TEGRA_APBDMA_AHBSEQ_BURST_1 (4 << 24)
85 #define TEGRA_APBDMA_AHBSEQ_BURST_4 (5 << 24)
86 #define TEGRA_APBDMA_AHBSEQ_BURST_8 (6 << 24)
87 #define TEGRA_APBDMA_AHBSEQ_DBL_BUF BIT(19)
88 #define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT 16
89 #define TEGRA_APBDMA_AHBSEQ_WRAP_NONE 0
90
91 /* APB address */
92 #define TEGRA_APBDMA_CHAN_APBPTR 0x018
93
94 /* APB sequence register */
95 #define TEGRA_APBDMA_CHAN_APBSEQ 0x01c
96 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8 (0 << 28)
97 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16 (1 << 28)
98 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32 (2 << 28)
99 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64 (3 << 28)
100 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128 (4 << 28)
101 #define TEGRA_APBDMA_APBSEQ_DATA_SWAP BIT(27)
102 #define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1 (1 << 16)
103
104 /* Tegra148 specific registers */
105 #define TEGRA_APBDMA_CHAN_WCOUNT 0x20
106
107 #define TEGRA_APBDMA_CHAN_WORD_TRANSFER 0x24
108
109 /*
110 * If any burst is in flight and DMA paused then this is the time to complete
111 * on-flight burst and update DMA status register.
112 */
113 #define TEGRA_APBDMA_BURST_COMPLETE_TIME 20
114
115 /* Channel base address offset from APBDMA base address */
116 #define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET 0x1000
117
118 #define TEGRA_APBDMA_SLAVE_ID_INVALID (TEGRA_APBDMA_CSR_REQ_SEL_MASK + 1)
119
120 struct tegra_dma;
121
122 /*
123 * tegra_dma_chip_data Tegra chip specific DMA data
124 * @nr_channels: Number of channels available in the controller.
125 * @channel_reg_size: Channel register size/stride.
126 * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
127 * @support_channel_pause: Support channel wise pause of dma.
128 * @support_separate_wcount_reg: Support separate word count register.
129 */
130 struct tegra_dma_chip_data {
131 int nr_channels;
132 int channel_reg_size;
133 int max_dma_count;
134 bool support_channel_pause;
135 bool support_separate_wcount_reg;
136 };
137
138 /* DMA channel registers */
139 struct tegra_dma_channel_regs {
140 unsigned long csr;
141 unsigned long ahb_ptr;
142 unsigned long apb_ptr;
143 unsigned long ahb_seq;
144 unsigned long apb_seq;
145 unsigned long wcount;
146 };
147
148 /*
149 * tegra_dma_sg_req: Dma request details to configure hardware. This
150 * contains the details for one transfer to configure DMA hw.
151 * The client's request for data transfer can be broken into multiple
152 * sub-transfer as per requester details and hw support.
153 * This sub transfer get added in the list of transfer and point to Tegra
154 * DMA descriptor which manages the transfer details.
155 */
156 struct tegra_dma_sg_req {
157 struct tegra_dma_channel_regs ch_regs;
158 int req_len;
159 bool configured;
160 bool last_sg;
161 struct list_head node;
162 struct tegra_dma_desc *dma_desc;
163 };
164
165 /*
166 * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
167 * This descriptor keep track of transfer status, callbacks and request
168 * counts etc.
169 */
170 struct tegra_dma_desc {
171 struct dma_async_tx_descriptor txd;
172 int bytes_requested;
173 int bytes_transferred;
174 enum dma_status dma_status;
175 struct list_head node;
176 struct list_head tx_list;
177 struct list_head cb_node;
178 int cb_count;
179 };
180
181 struct tegra_dma_channel;
182
183 typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
184 bool to_terminate);
185
186 /* tegra_dma_channel: Channel specific information */
187 struct tegra_dma_channel {
188 struct dma_chan dma_chan;
189 char name[30];
190 bool config_init;
191 int id;
192 int irq;
193 void __iomem *chan_addr;
194 spinlock_t lock;
195 bool busy;
196 struct tegra_dma *tdma;
197 bool cyclic;
198
199 /* Different lists for managing the requests */
200 struct list_head free_sg_req;
201 struct list_head pending_sg_req;
202 struct list_head free_dma_desc;
203 struct list_head cb_desc;
204
205 /* ISR handler and tasklet for bottom half of isr handling */
206 dma_isr_handler isr_handler;
207 struct tasklet_struct tasklet;
208
209 /* Channel-slave specific configuration */
210 unsigned int slave_id;
211 struct dma_slave_config dma_sconfig;
212 struct tegra_dma_channel_regs channel_reg;
213 };
214
215 /* tegra_dma: Tegra DMA specific information */
216 struct tegra_dma {
217 struct dma_device dma_dev;
218 struct device *dev;
219 struct clk *dma_clk;
220 struct reset_control *rst;
221 spinlock_t global_lock;
222 void __iomem *base_addr;
223 const struct tegra_dma_chip_data *chip_data;
224
225 /*
226 * Counter for managing global pausing of the DMA controller.
227 * Only applicable for devices that don't support individual
228 * channel pausing.
229 */
230 u32 global_pause_count;
231
232 /* Some register need to be cache before suspend */
233 u32 reg_gen;
234
235 /* Last member of the structure */
236 struct tegra_dma_channel channels[0];
237 };
238
239 static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
240 {
241 writel(val, tdma->base_addr + reg);
242 }
243
244 static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
245 {
246 return readl(tdma->base_addr + reg);
247 }
248
249 static inline void tdc_write(struct tegra_dma_channel *tdc,
250 u32 reg, u32 val)
251 {
252 writel(val, tdc->chan_addr + reg);
253 }
254
255 static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
256 {
257 return readl(tdc->chan_addr + reg);
258 }
259
260 static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
261 {
262 return container_of(dc, struct tegra_dma_channel, dma_chan);
263 }
264
265 static inline struct tegra_dma_desc *txd_to_tegra_dma_desc(
266 struct dma_async_tx_descriptor *td)
267 {
268 return container_of(td, struct tegra_dma_desc, txd);
269 }
270
271 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
272 {
273 return &tdc->dma_chan.dev->device;
274 }
275
276 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx);
277 static int tegra_dma_runtime_suspend(struct device *dev);
278 static int tegra_dma_runtime_resume(struct device *dev);
279
280 /* Get DMA desc from free list, if not there then allocate it. */
281 static struct tegra_dma_desc *tegra_dma_desc_get(
282 struct tegra_dma_channel *tdc)
283 {
284 struct tegra_dma_desc *dma_desc;
285 unsigned long flags;
286
287 spin_lock_irqsave(&tdc->lock, flags);
288
289 /* Do not allocate if desc are waiting for ack */
290 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
291 if (async_tx_test_ack(&dma_desc->txd)) {
292 list_del(&dma_desc->node);
293 spin_unlock_irqrestore(&tdc->lock, flags);
294 dma_desc->txd.flags = 0;
295 return dma_desc;
296 }
297 }
298
299 spin_unlock_irqrestore(&tdc->lock, flags);
300
301 /* Allocate DMA desc */
302 dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
303 if (!dma_desc) {
304 dev_err(tdc2dev(tdc), "dma_desc alloc failed\n");
305 return NULL;
306 }
307
308 dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
309 dma_desc->txd.tx_submit = tegra_dma_tx_submit;
310 dma_desc->txd.flags = 0;
311 return dma_desc;
312 }
313
314 static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
315 struct tegra_dma_desc *dma_desc)
316 {
317 unsigned long flags;
318
319 spin_lock_irqsave(&tdc->lock, flags);
320 if (!list_empty(&dma_desc->tx_list))
321 list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req);
322 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
323 spin_unlock_irqrestore(&tdc->lock, flags);
324 }
325
326 static struct tegra_dma_sg_req *tegra_dma_sg_req_get(
327 struct tegra_dma_channel *tdc)
328 {
329 struct tegra_dma_sg_req *sg_req = NULL;
330 unsigned long flags;
331
332 spin_lock_irqsave(&tdc->lock, flags);
333 if (!list_empty(&tdc->free_sg_req)) {
334 sg_req = list_first_entry(&tdc->free_sg_req,
335 typeof(*sg_req), node);
336 list_del(&sg_req->node);
337 spin_unlock_irqrestore(&tdc->lock, flags);
338 return sg_req;
339 }
340 spin_unlock_irqrestore(&tdc->lock, flags);
341
342 sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_NOWAIT);
343 if (!sg_req)
344 dev_err(tdc2dev(tdc), "sg_req alloc failed\n");
345 return sg_req;
346 }
347
348 static int tegra_dma_slave_config(struct dma_chan *dc,
349 struct dma_slave_config *sconfig)
350 {
351 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
352
353 if (!list_empty(&tdc->pending_sg_req)) {
354 dev_err(tdc2dev(tdc), "Configuration not allowed\n");
355 return -EBUSY;
356 }
357
358 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
359 if (tdc->slave_id == TEGRA_APBDMA_SLAVE_ID_INVALID) {
360 if (sconfig->slave_id > TEGRA_APBDMA_CSR_REQ_SEL_MASK)
361 return -EINVAL;
362 tdc->slave_id = sconfig->slave_id;
363 }
364 tdc->config_init = true;
365 return 0;
366 }
367
368 static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
369 bool wait_for_burst_complete)
370 {
371 struct tegra_dma *tdma = tdc->tdma;
372
373 spin_lock(&tdma->global_lock);
374
375 if (tdc->tdma->global_pause_count == 0) {
376 tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);
377 if (wait_for_burst_complete)
378 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
379 }
380
381 tdc->tdma->global_pause_count++;
382
383 spin_unlock(&tdma->global_lock);
384 }
385
386 static void tegra_dma_global_resume(struct tegra_dma_channel *tdc)
387 {
388 struct tegra_dma *tdma = tdc->tdma;
389
390 spin_lock(&tdma->global_lock);
391
392 if (WARN_ON(tdc->tdma->global_pause_count == 0))
393 goto out;
394
395 if (--tdc->tdma->global_pause_count == 0)
396 tdma_write(tdma, TEGRA_APBDMA_GENERAL,
397 TEGRA_APBDMA_GENERAL_ENABLE);
398
399 out:
400 spin_unlock(&tdma->global_lock);
401 }
402
403 static void tegra_dma_pause(struct tegra_dma_channel *tdc,
404 bool wait_for_burst_complete)
405 {
406 struct tegra_dma *tdma = tdc->tdma;
407
408 if (tdma->chip_data->support_channel_pause) {
409 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE,
410 TEGRA_APBDMA_CHAN_CSRE_PAUSE);
411 if (wait_for_burst_complete)
412 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
413 } else {
414 tegra_dma_global_pause(tdc, wait_for_burst_complete);
415 }
416 }
417
418 static void tegra_dma_resume(struct tegra_dma_channel *tdc)
419 {
420 struct tegra_dma *tdma = tdc->tdma;
421
422 if (tdma->chip_data->support_channel_pause) {
423 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0);
424 } else {
425 tegra_dma_global_resume(tdc);
426 }
427 }
428
429 static void tegra_dma_stop(struct tegra_dma_channel *tdc)
430 {
431 u32 csr;
432 u32 status;
433
434 /* Disable interrupts */
435 csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
436 csr &= ~TEGRA_APBDMA_CSR_IE_EOC;
437 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
438
439 /* Disable DMA */
440 csr &= ~TEGRA_APBDMA_CSR_ENB;
441 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
442
443 /* Clear interrupt status if it is there */
444 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
445 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
446 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
447 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
448 }
449 tdc->busy = false;
450 }
451
452 static void tegra_dma_start(struct tegra_dma_channel *tdc,
453 struct tegra_dma_sg_req *sg_req)
454 {
455 struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
456
457 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);
458 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq);
459 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr);
460 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq);
461 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr);
462 if (tdc->tdma->chip_data->support_separate_wcount_reg)
463 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, ch_regs->wcount);
464
465 /* Start DMA */
466 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
467 ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
468 }
469
470 static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
471 struct tegra_dma_sg_req *nsg_req)
472 {
473 unsigned long status;
474
475 /*
476 * The DMA controller reloads the new configuration for next transfer
477 * after last burst of current transfer completes.
478 * If there is no IEC status then this makes sure that last burst
479 * has not be completed. There may be case that last burst is on
480 * flight and so it can complete but because DMA is paused, it
481 * will not generates interrupt as well as not reload the new
482 * configuration.
483 * If there is already IEC status then interrupt handler need to
484 * load new configuration.
485 */
486 tegra_dma_pause(tdc, false);
487 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
488
489 /*
490 * If interrupt is pending then do nothing as the ISR will handle
491 * the programing for new request.
492 */
493 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
494 dev_err(tdc2dev(tdc),
495 "Skipping new configuration as interrupt is pending\n");
496 tegra_dma_resume(tdc);
497 return;
498 }
499
500 /* Safe to program new configuration */
501 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
502 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
503 if (tdc->tdma->chip_data->support_separate_wcount_reg)
504 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
505 nsg_req->ch_regs.wcount);
506 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
507 nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
508 nsg_req->configured = true;
509
510 tegra_dma_resume(tdc);
511 }
512
513 static void tdc_start_head_req(struct tegra_dma_channel *tdc)
514 {
515 struct tegra_dma_sg_req *sg_req;
516
517 if (list_empty(&tdc->pending_sg_req))
518 return;
519
520 sg_req = list_first_entry(&tdc->pending_sg_req,
521 typeof(*sg_req), node);
522 tegra_dma_start(tdc, sg_req);
523 sg_req->configured = true;
524 tdc->busy = true;
525 }
526
527 static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
528 {
529 struct tegra_dma_sg_req *hsgreq;
530 struct tegra_dma_sg_req *hnsgreq;
531
532 if (list_empty(&tdc->pending_sg_req))
533 return;
534
535 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
536 if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
537 hnsgreq = list_first_entry(&hsgreq->node,
538 typeof(*hnsgreq), node);
539 tegra_dma_configure_for_next(tdc, hnsgreq);
540 }
541 }
542
543 static inline int get_current_xferred_count(struct tegra_dma_channel *tdc,
544 struct tegra_dma_sg_req *sg_req, unsigned long status)
545 {
546 return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
547 }
548
549 static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
550 {
551 struct tegra_dma_sg_req *sgreq;
552 struct tegra_dma_desc *dma_desc;
553
554 while (!list_empty(&tdc->pending_sg_req)) {
555 sgreq = list_first_entry(&tdc->pending_sg_req,
556 typeof(*sgreq), node);
557 list_move_tail(&sgreq->node, &tdc->free_sg_req);
558 if (sgreq->last_sg) {
559 dma_desc = sgreq->dma_desc;
560 dma_desc->dma_status = DMA_ERROR;
561 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
562
563 /* Add in cb list if it is not there. */
564 if (!dma_desc->cb_count)
565 list_add_tail(&dma_desc->cb_node,
566 &tdc->cb_desc);
567 dma_desc->cb_count++;
568 }
569 }
570 tdc->isr_handler = NULL;
571 }
572
573 static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
574 struct tegra_dma_sg_req *last_sg_req, bool to_terminate)
575 {
576 struct tegra_dma_sg_req *hsgreq = NULL;
577
578 if (list_empty(&tdc->pending_sg_req)) {
579 dev_err(tdc2dev(tdc), "Dma is running without req\n");
580 tegra_dma_stop(tdc);
581 return false;
582 }
583
584 /*
585 * Check that head req on list should be in flight.
586 * If it is not in flight then abort transfer as
587 * looping of transfer can not continue.
588 */
589 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
590 if (!hsgreq->configured) {
591 tegra_dma_stop(tdc);
592 dev_err(tdc2dev(tdc), "Error in dma transfer, aborting dma\n");
593 tegra_dma_abort_all(tdc);
594 return false;
595 }
596
597 /* Configure next request */
598 if (!to_terminate)
599 tdc_configure_next_head_desc(tdc);
600 return true;
601 }
602
603 static void handle_once_dma_done(struct tegra_dma_channel *tdc,
604 bool to_terminate)
605 {
606 struct tegra_dma_sg_req *sgreq;
607 struct tegra_dma_desc *dma_desc;
608
609 tdc->busy = false;
610 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
611 dma_desc = sgreq->dma_desc;
612 dma_desc->bytes_transferred += sgreq->req_len;
613
614 list_del(&sgreq->node);
615 if (sgreq->last_sg) {
616 dma_desc->dma_status = DMA_COMPLETE;
617 dma_cookie_complete(&dma_desc->txd);
618 if (!dma_desc->cb_count)
619 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
620 dma_desc->cb_count++;
621 list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
622 }
623 list_add_tail(&sgreq->node, &tdc->free_sg_req);
624
625 /* Do not start DMA if it is going to be terminate */
626 if (to_terminate || list_empty(&tdc->pending_sg_req))
627 return;
628
629 tdc_start_head_req(tdc);
630 }
631
632 static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
633 bool to_terminate)
634 {
635 struct tegra_dma_sg_req *sgreq;
636 struct tegra_dma_desc *dma_desc;
637 bool st;
638
639 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
640 dma_desc = sgreq->dma_desc;
641 dma_desc->bytes_transferred += sgreq->req_len;
642
643 /* Callback need to be call */
644 if (!dma_desc->cb_count)
645 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
646 dma_desc->cb_count++;
647
648 /* If not last req then put at end of pending list */
649 if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
650 list_move_tail(&sgreq->node, &tdc->pending_sg_req);
651 sgreq->configured = false;
652 st = handle_continuous_head_request(tdc, sgreq, to_terminate);
653 if (!st)
654 dma_desc->dma_status = DMA_ERROR;
655 }
656 }
657
658 static void tegra_dma_tasklet(unsigned long data)
659 {
660 struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data;
661 dma_async_tx_callback callback = NULL;
662 void *callback_param = NULL;
663 struct tegra_dma_desc *dma_desc;
664 unsigned long flags;
665 int cb_count;
666
667 spin_lock_irqsave(&tdc->lock, flags);
668 while (!list_empty(&tdc->cb_desc)) {
669 dma_desc = list_first_entry(&tdc->cb_desc,
670 typeof(*dma_desc), cb_node);
671 list_del(&dma_desc->cb_node);
672 callback = dma_desc->txd.callback;
673 callback_param = dma_desc->txd.callback_param;
674 cb_count = dma_desc->cb_count;
675 dma_desc->cb_count = 0;
676 spin_unlock_irqrestore(&tdc->lock, flags);
677 while (cb_count-- && callback)
678 callback(callback_param);
679 spin_lock_irqsave(&tdc->lock, flags);
680 }
681 spin_unlock_irqrestore(&tdc->lock, flags);
682 }
683
684 static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
685 {
686 struct tegra_dma_channel *tdc = dev_id;
687 unsigned long status;
688 unsigned long flags;
689
690 spin_lock_irqsave(&tdc->lock, flags);
691
692 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
693 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
694 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
695 tdc->isr_handler(tdc, false);
696 tasklet_schedule(&tdc->tasklet);
697 spin_unlock_irqrestore(&tdc->lock, flags);
698 return IRQ_HANDLED;
699 }
700
701 spin_unlock_irqrestore(&tdc->lock, flags);
702 dev_info(tdc2dev(tdc),
703 "Interrupt already served status 0x%08lx\n", status);
704 return IRQ_NONE;
705 }
706
707 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
708 {
709 struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
710 struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan);
711 unsigned long flags;
712 dma_cookie_t cookie;
713
714 spin_lock_irqsave(&tdc->lock, flags);
715 dma_desc->dma_status = DMA_IN_PROGRESS;
716 cookie = dma_cookie_assign(&dma_desc->txd);
717 list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
718 spin_unlock_irqrestore(&tdc->lock, flags);
719 return cookie;
720 }
721
722 static void tegra_dma_issue_pending(struct dma_chan *dc)
723 {
724 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
725 unsigned long flags;
726
727 spin_lock_irqsave(&tdc->lock, flags);
728 if (list_empty(&tdc->pending_sg_req)) {
729 dev_err(tdc2dev(tdc), "No DMA request\n");
730 goto end;
731 }
732 if (!tdc->busy) {
733 tdc_start_head_req(tdc);
734
735 /* Continuous single mode: Configure next req */
736 if (tdc->cyclic) {
737 /*
738 * Wait for 1 burst time for configure DMA for
739 * next transfer.
740 */
741 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
742 tdc_configure_next_head_desc(tdc);
743 }
744 }
745 end:
746 spin_unlock_irqrestore(&tdc->lock, flags);
747 }
748
749 static int tegra_dma_terminate_all(struct dma_chan *dc)
750 {
751 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
752 struct tegra_dma_sg_req *sgreq;
753 struct tegra_dma_desc *dma_desc;
754 unsigned long flags;
755 unsigned long status;
756 unsigned long wcount;
757 bool was_busy;
758
759 spin_lock_irqsave(&tdc->lock, flags);
760 if (list_empty(&tdc->pending_sg_req)) {
761 spin_unlock_irqrestore(&tdc->lock, flags);
762 return 0;
763 }
764
765 if (!tdc->busy)
766 goto skip_dma_stop;
767
768 /* Pause DMA before checking the queue status */
769 tegra_dma_pause(tdc, true);
770
771 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
772 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
773 dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
774 tdc->isr_handler(tdc, true);
775 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
776 }
777 if (tdc->tdma->chip_data->support_separate_wcount_reg)
778 wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
779 else
780 wcount = status;
781
782 was_busy = tdc->busy;
783 tegra_dma_stop(tdc);
784
785 if (!list_empty(&tdc->pending_sg_req) && was_busy) {
786 sgreq = list_first_entry(&tdc->pending_sg_req,
787 typeof(*sgreq), node);
788 sgreq->dma_desc->bytes_transferred +=
789 get_current_xferred_count(tdc, sgreq, wcount);
790 }
791 tegra_dma_resume(tdc);
792
793 skip_dma_stop:
794 tegra_dma_abort_all(tdc);
795
796 while (!list_empty(&tdc->cb_desc)) {
797 dma_desc = list_first_entry(&tdc->cb_desc,
798 typeof(*dma_desc), cb_node);
799 list_del(&dma_desc->cb_node);
800 dma_desc->cb_count = 0;
801 }
802 spin_unlock_irqrestore(&tdc->lock, flags);
803 return 0;
804 }
805
806 static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
807 dma_cookie_t cookie, struct dma_tx_state *txstate)
808 {
809 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
810 struct tegra_dma_desc *dma_desc;
811 struct tegra_dma_sg_req *sg_req;
812 enum dma_status ret;
813 unsigned long flags;
814 unsigned int residual;
815
816 ret = dma_cookie_status(dc, cookie, txstate);
817 if (ret == DMA_COMPLETE)
818 return ret;
819
820 spin_lock_irqsave(&tdc->lock, flags);
821
822 /* Check on wait_ack desc status */
823 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
824 if (dma_desc->txd.cookie == cookie) {
825 residual = dma_desc->bytes_requested -
826 (dma_desc->bytes_transferred %
827 dma_desc->bytes_requested);
828 dma_set_residue(txstate, residual);
829 ret = dma_desc->dma_status;
830 spin_unlock_irqrestore(&tdc->lock, flags);
831 return ret;
832 }
833 }
834
835 /* Check in pending list */
836 list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
837 dma_desc = sg_req->dma_desc;
838 if (dma_desc->txd.cookie == cookie) {
839 residual = dma_desc->bytes_requested -
840 (dma_desc->bytes_transferred %
841 dma_desc->bytes_requested);
842 dma_set_residue(txstate, residual);
843 ret = dma_desc->dma_status;
844 spin_unlock_irqrestore(&tdc->lock, flags);
845 return ret;
846 }
847 }
848
849 dev_dbg(tdc2dev(tdc), "cookie %d does not found\n", cookie);
850 spin_unlock_irqrestore(&tdc->lock, flags);
851 return ret;
852 }
853
854 static inline int get_bus_width(struct tegra_dma_channel *tdc,
855 enum dma_slave_buswidth slave_bw)
856 {
857 switch (slave_bw) {
858 case DMA_SLAVE_BUSWIDTH_1_BYTE:
859 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8;
860 case DMA_SLAVE_BUSWIDTH_2_BYTES:
861 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16;
862 case DMA_SLAVE_BUSWIDTH_4_BYTES:
863 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
864 case DMA_SLAVE_BUSWIDTH_8_BYTES:
865 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64;
866 default:
867 dev_warn(tdc2dev(tdc),
868 "slave bw is not supported, using 32bits\n");
869 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
870 }
871 }
872
873 static inline int get_burst_size(struct tegra_dma_channel *tdc,
874 u32 burst_size, enum dma_slave_buswidth slave_bw, int len)
875 {
876 int burst_byte;
877 int burst_ahb_width;
878
879 /*
880 * burst_size from client is in terms of the bus_width.
881 * convert them into AHB memory width which is 4 byte.
882 */
883 burst_byte = burst_size * slave_bw;
884 burst_ahb_width = burst_byte / 4;
885
886 /* If burst size is 0 then calculate the burst size based on length */
887 if (!burst_ahb_width) {
888 if (len & 0xF)
889 return TEGRA_APBDMA_AHBSEQ_BURST_1;
890 else if ((len >> 4) & 0x1)
891 return TEGRA_APBDMA_AHBSEQ_BURST_4;
892 else
893 return TEGRA_APBDMA_AHBSEQ_BURST_8;
894 }
895 if (burst_ahb_width < 4)
896 return TEGRA_APBDMA_AHBSEQ_BURST_1;
897 else if (burst_ahb_width < 8)
898 return TEGRA_APBDMA_AHBSEQ_BURST_4;
899 else
900 return TEGRA_APBDMA_AHBSEQ_BURST_8;
901 }
902
903 static int get_transfer_param(struct tegra_dma_channel *tdc,
904 enum dma_transfer_direction direction, unsigned long *apb_addr,
905 unsigned long *apb_seq, unsigned long *csr, unsigned int *burst_size,
906 enum dma_slave_buswidth *slave_bw)
907 {
908
909 switch (direction) {
910 case DMA_MEM_TO_DEV:
911 *apb_addr = tdc->dma_sconfig.dst_addr;
912 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
913 *burst_size = tdc->dma_sconfig.dst_maxburst;
914 *slave_bw = tdc->dma_sconfig.dst_addr_width;
915 *csr = TEGRA_APBDMA_CSR_DIR;
916 return 0;
917
918 case DMA_DEV_TO_MEM:
919 *apb_addr = tdc->dma_sconfig.src_addr;
920 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
921 *burst_size = tdc->dma_sconfig.src_maxburst;
922 *slave_bw = tdc->dma_sconfig.src_addr_width;
923 *csr = 0;
924 return 0;
925
926 default:
927 dev_err(tdc2dev(tdc), "Dma direction is not supported\n");
928 return -EINVAL;
929 }
930 return -EINVAL;
931 }
932
933 static void tegra_dma_prep_wcount(struct tegra_dma_channel *tdc,
934 struct tegra_dma_channel_regs *ch_regs, u32 len)
935 {
936 u32 len_field = (len - 4) & 0xFFFC;
937
938 if (tdc->tdma->chip_data->support_separate_wcount_reg)
939 ch_regs->wcount = len_field;
940 else
941 ch_regs->csr |= len_field;
942 }
943
944 static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg(
945 struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len,
946 enum dma_transfer_direction direction, unsigned long flags,
947 void *context)
948 {
949 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
950 struct tegra_dma_desc *dma_desc;
951 unsigned int i;
952 struct scatterlist *sg;
953 unsigned long csr, ahb_seq, apb_ptr, apb_seq;
954 struct list_head req_list;
955 struct tegra_dma_sg_req *sg_req = NULL;
956 u32 burst_size;
957 enum dma_slave_buswidth slave_bw;
958
959 if (!tdc->config_init) {
960 dev_err(tdc2dev(tdc), "dma channel is not configured\n");
961 return NULL;
962 }
963 if (sg_len < 1) {
964 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
965 return NULL;
966 }
967
968 if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
969 &burst_size, &slave_bw) < 0)
970 return NULL;
971
972 INIT_LIST_HEAD(&req_list);
973
974 ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
975 ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
976 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
977 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
978
979 csr |= TEGRA_APBDMA_CSR_ONCE | TEGRA_APBDMA_CSR_FLOW;
980 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
981 if (flags & DMA_PREP_INTERRUPT)
982 csr |= TEGRA_APBDMA_CSR_IE_EOC;
983
984 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
985
986 dma_desc = tegra_dma_desc_get(tdc);
987 if (!dma_desc) {
988 dev_err(tdc2dev(tdc), "Dma descriptors not available\n");
989 return NULL;
990 }
991 INIT_LIST_HEAD(&dma_desc->tx_list);
992 INIT_LIST_HEAD(&dma_desc->cb_node);
993 dma_desc->cb_count = 0;
994 dma_desc->bytes_requested = 0;
995 dma_desc->bytes_transferred = 0;
996 dma_desc->dma_status = DMA_IN_PROGRESS;
997
998 /* Make transfer requests */
999 for_each_sg(sgl, sg, sg_len, i) {
1000 u32 len, mem;
1001
1002 mem = sg_dma_address(sg);
1003 len = sg_dma_len(sg);
1004
1005 if ((len & 3) || (mem & 3) ||
1006 (len > tdc->tdma->chip_data->max_dma_count)) {
1007 dev_err(tdc2dev(tdc),
1008 "Dma length/memory address is not supported\n");
1009 tegra_dma_desc_put(tdc, dma_desc);
1010 return NULL;
1011 }
1012
1013 sg_req = tegra_dma_sg_req_get(tdc);
1014 if (!sg_req) {
1015 dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
1016 tegra_dma_desc_put(tdc, dma_desc);
1017 return NULL;
1018 }
1019
1020 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1021 dma_desc->bytes_requested += len;
1022
1023 sg_req->ch_regs.apb_ptr = apb_ptr;
1024 sg_req->ch_regs.ahb_ptr = mem;
1025 sg_req->ch_regs.csr = csr;
1026 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
1027 sg_req->ch_regs.apb_seq = apb_seq;
1028 sg_req->ch_regs.ahb_seq = ahb_seq;
1029 sg_req->configured = false;
1030 sg_req->last_sg = false;
1031 sg_req->dma_desc = dma_desc;
1032 sg_req->req_len = len;
1033
1034 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1035 }
1036 sg_req->last_sg = true;
1037 if (flags & DMA_CTRL_ACK)
1038 dma_desc->txd.flags = DMA_CTRL_ACK;
1039
1040 /*
1041 * Make sure that mode should not be conflicting with currently
1042 * configured mode.
1043 */
1044 if (!tdc->isr_handler) {
1045 tdc->isr_handler = handle_once_dma_done;
1046 tdc->cyclic = false;
1047 } else {
1048 if (tdc->cyclic) {
1049 dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
1050 tegra_dma_desc_put(tdc, dma_desc);
1051 return NULL;
1052 }
1053 }
1054
1055 return &dma_desc->txd;
1056 }
1057
1058 static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic(
1059 struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len,
1060 size_t period_len, enum dma_transfer_direction direction,
1061 unsigned long flags)
1062 {
1063 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1064 struct tegra_dma_desc *dma_desc = NULL;
1065 struct tegra_dma_sg_req *sg_req = NULL;
1066 unsigned long csr, ahb_seq, apb_ptr, apb_seq;
1067 int len;
1068 size_t remain_len;
1069 dma_addr_t mem = buf_addr;
1070 u32 burst_size;
1071 enum dma_slave_buswidth slave_bw;
1072
1073 if (!buf_len || !period_len) {
1074 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
1075 return NULL;
1076 }
1077
1078 if (!tdc->config_init) {
1079 dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
1080 return NULL;
1081 }
1082
1083 /*
1084 * We allow to take more number of requests till DMA is
1085 * not started. The driver will loop over all requests.
1086 * Once DMA is started then new requests can be queued only after
1087 * terminating the DMA.
1088 */
1089 if (tdc->busy) {
1090 dev_err(tdc2dev(tdc), "Request not allowed when dma running\n");
1091 return NULL;
1092 }
1093
1094 /*
1095 * We only support cycle transfer when buf_len is multiple of
1096 * period_len.
1097 */
1098 if (buf_len % period_len) {
1099 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
1100 return NULL;
1101 }
1102
1103 len = period_len;
1104 if ((len & 3) || (buf_addr & 3) ||
1105 (len > tdc->tdma->chip_data->max_dma_count)) {
1106 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
1107 return NULL;
1108 }
1109
1110 if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
1111 &burst_size, &slave_bw) < 0)
1112 return NULL;
1113
1114 ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
1115 ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
1116 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
1117 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
1118
1119 csr |= TEGRA_APBDMA_CSR_FLOW;
1120 if (flags & DMA_PREP_INTERRUPT)
1121 csr |= TEGRA_APBDMA_CSR_IE_EOC;
1122 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
1123
1124 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
1125
1126 dma_desc = tegra_dma_desc_get(tdc);
1127 if (!dma_desc) {
1128 dev_err(tdc2dev(tdc), "not enough descriptors available\n");
1129 return NULL;
1130 }
1131
1132 INIT_LIST_HEAD(&dma_desc->tx_list);
1133 INIT_LIST_HEAD(&dma_desc->cb_node);
1134 dma_desc->cb_count = 0;
1135
1136 dma_desc->bytes_transferred = 0;
1137 dma_desc->bytes_requested = buf_len;
1138 remain_len = buf_len;
1139
1140 /* Split transfer equal to period size */
1141 while (remain_len) {
1142 sg_req = tegra_dma_sg_req_get(tdc);
1143 if (!sg_req) {
1144 dev_err(tdc2dev(tdc), "Dma sg-req not available\n");
1145 tegra_dma_desc_put(tdc, dma_desc);
1146 return NULL;
1147 }
1148
1149 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
1150 sg_req->ch_regs.apb_ptr = apb_ptr;
1151 sg_req->ch_regs.ahb_ptr = mem;
1152 sg_req->ch_regs.csr = csr;
1153 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
1154 sg_req->ch_regs.apb_seq = apb_seq;
1155 sg_req->ch_regs.ahb_seq = ahb_seq;
1156 sg_req->configured = false;
1157 sg_req->last_sg = false;
1158 sg_req->dma_desc = dma_desc;
1159 sg_req->req_len = len;
1160
1161 list_add_tail(&sg_req->node, &dma_desc->tx_list);
1162 remain_len -= len;
1163 mem += len;
1164 }
1165 sg_req->last_sg = true;
1166 if (flags & DMA_CTRL_ACK)
1167 dma_desc->txd.flags = DMA_CTRL_ACK;
1168
1169 /*
1170 * Make sure that mode should not be conflicting with currently
1171 * configured mode.
1172 */
1173 if (!tdc->isr_handler) {
1174 tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
1175 tdc->cyclic = true;
1176 } else {
1177 if (!tdc->cyclic) {
1178 dev_err(tdc2dev(tdc), "DMA configuration conflict\n");
1179 tegra_dma_desc_put(tdc, dma_desc);
1180 return NULL;
1181 }
1182 }
1183
1184 return &dma_desc->txd;
1185 }
1186
1187 static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
1188 {
1189 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1190 struct tegra_dma *tdma = tdc->tdma;
1191 int ret;
1192
1193 dma_cookie_init(&tdc->dma_chan);
1194 tdc->config_init = false;
1195
1196 ret = pm_runtime_get_sync(tdma->dev);
1197 if (ret < 0)
1198 return ret;
1199
1200 return 0;
1201 }
1202
1203 static void tegra_dma_free_chan_resources(struct dma_chan *dc)
1204 {
1205 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
1206 struct tegra_dma *tdma = tdc->tdma;
1207
1208 struct tegra_dma_desc *dma_desc;
1209 struct tegra_dma_sg_req *sg_req;
1210 struct list_head dma_desc_list;
1211 struct list_head sg_req_list;
1212 unsigned long flags;
1213
1214 INIT_LIST_HEAD(&dma_desc_list);
1215 INIT_LIST_HEAD(&sg_req_list);
1216
1217 dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
1218
1219 if (tdc->busy)
1220 tegra_dma_terminate_all(dc);
1221
1222 spin_lock_irqsave(&tdc->lock, flags);
1223 list_splice_init(&tdc->pending_sg_req, &sg_req_list);
1224 list_splice_init(&tdc->free_sg_req, &sg_req_list);
1225 list_splice_init(&tdc->free_dma_desc, &dma_desc_list);
1226 INIT_LIST_HEAD(&tdc->cb_desc);
1227 tdc->config_init = false;
1228 tdc->isr_handler = NULL;
1229 spin_unlock_irqrestore(&tdc->lock, flags);
1230
1231 while (!list_empty(&dma_desc_list)) {
1232 dma_desc = list_first_entry(&dma_desc_list,
1233 typeof(*dma_desc), node);
1234 list_del(&dma_desc->node);
1235 kfree(dma_desc);
1236 }
1237
1238 while (!list_empty(&sg_req_list)) {
1239 sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);
1240 list_del(&sg_req->node);
1241 kfree(sg_req);
1242 }
1243 pm_runtime_put(tdma->dev);
1244
1245 tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID;
1246 }
1247
1248 static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
1249 struct of_dma *ofdma)
1250 {
1251 struct tegra_dma *tdma = ofdma->of_dma_data;
1252 struct dma_chan *chan;
1253 struct tegra_dma_channel *tdc;
1254
1255 if (dma_spec->args[0] > TEGRA_APBDMA_CSR_REQ_SEL_MASK) {
1256 dev_err(tdma->dev, "Invalid slave id: %d\n", dma_spec->args[0]);
1257 return NULL;
1258 }
1259
1260 chan = dma_get_any_slave_channel(&tdma->dma_dev);
1261 if (!chan)
1262 return NULL;
1263
1264 tdc = to_tegra_dma_chan(chan);
1265 tdc->slave_id = dma_spec->args[0];
1266
1267 return chan;
1268 }
1269
1270 /* Tegra20 specific DMA controller information */
1271 static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
1272 .nr_channels = 16,
1273 .channel_reg_size = 0x20,
1274 .max_dma_count = 1024UL * 64,
1275 .support_channel_pause = false,
1276 .support_separate_wcount_reg = false,
1277 };
1278
1279 /* Tegra30 specific DMA controller information */
1280 static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
1281 .nr_channels = 32,
1282 .channel_reg_size = 0x20,
1283 .max_dma_count = 1024UL * 64,
1284 .support_channel_pause = false,
1285 .support_separate_wcount_reg = false,
1286 };
1287
1288 /* Tegra114 specific DMA controller information */
1289 static const struct tegra_dma_chip_data tegra114_dma_chip_data = {
1290 .nr_channels = 32,
1291 .channel_reg_size = 0x20,
1292 .max_dma_count = 1024UL * 64,
1293 .support_channel_pause = true,
1294 .support_separate_wcount_reg = false,
1295 };
1296
1297 /* Tegra148 specific DMA controller information */
1298 static const struct tegra_dma_chip_data tegra148_dma_chip_data = {
1299 .nr_channels = 32,
1300 .channel_reg_size = 0x40,
1301 .max_dma_count = 1024UL * 64,
1302 .support_channel_pause = true,
1303 .support_separate_wcount_reg = true,
1304 };
1305
1306 static int tegra_dma_probe(struct platform_device *pdev)
1307 {
1308 struct resource *res;
1309 struct tegra_dma *tdma;
1310 int ret;
1311 int i;
1312 const struct tegra_dma_chip_data *cdata;
1313
1314 cdata = of_device_get_match_data(&pdev->dev);
1315 if (!cdata) {
1316 dev_err(&pdev->dev, "Error: No device match data found\n");
1317 return -ENODEV;
1318 }
1319
1320 tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
1321 sizeof(struct tegra_dma_channel), GFP_KERNEL);
1322 if (!tdma) {
1323 dev_err(&pdev->dev, "Error: memory allocation failed\n");
1324 return -ENOMEM;
1325 }
1326
1327 tdma->dev = &pdev->dev;
1328 tdma->chip_data = cdata;
1329 platform_set_drvdata(pdev, tdma);
1330
1331 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1332 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
1333 if (IS_ERR(tdma->base_addr))
1334 return PTR_ERR(tdma->base_addr);
1335
1336 tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);
1337 if (IS_ERR(tdma->dma_clk)) {
1338 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1339 return PTR_ERR(tdma->dma_clk);
1340 }
1341
1342 tdma->rst = devm_reset_control_get(&pdev->dev, "dma");
1343 if (IS_ERR(tdma->rst)) {
1344 dev_err(&pdev->dev, "Error: Missing reset\n");
1345 return PTR_ERR(tdma->rst);
1346 }
1347
1348 spin_lock_init(&tdma->global_lock);
1349
1350 pm_runtime_enable(&pdev->dev);
1351 if (!pm_runtime_enabled(&pdev->dev))
1352 ret = tegra_dma_runtime_resume(&pdev->dev);
1353 else
1354 ret = pm_runtime_get_sync(&pdev->dev);
1355
1356 if (ret < 0) {
1357 pm_runtime_disable(&pdev->dev);
1358 return ret;
1359 }
1360
1361 /* Reset DMA controller */
1362 reset_control_assert(tdma->rst);
1363 udelay(2);
1364 reset_control_deassert(tdma->rst);
1365
1366 /* Enable global DMA registers */
1367 tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
1368 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1369 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1370
1371 pm_runtime_put(&pdev->dev);
1372
1373 INIT_LIST_HEAD(&tdma->dma_dev.channels);
1374 for (i = 0; i < cdata->nr_channels; i++) {
1375 struct tegra_dma_channel *tdc = &tdma->channels[i];
1376
1377 tdc->chan_addr = tdma->base_addr +
1378 TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET +
1379 (i * cdata->channel_reg_size);
1380
1381 res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
1382 if (!res) {
1383 ret = -EINVAL;
1384 dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
1385 goto err_irq;
1386 }
1387 tdc->irq = res->start;
1388 snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i);
1389 ret = request_irq(tdc->irq, tegra_dma_isr, 0, tdc->name, tdc);
1390 if (ret) {
1391 dev_err(&pdev->dev,
1392 "request_irq failed with err %d channel %d\n",
1393 ret, i);
1394 goto err_irq;
1395 }
1396
1397 tdc->dma_chan.device = &tdma->dma_dev;
1398 dma_cookie_init(&tdc->dma_chan);
1399 list_add_tail(&tdc->dma_chan.device_node,
1400 &tdma->dma_dev.channels);
1401 tdc->tdma = tdma;
1402 tdc->id = i;
1403 tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID;
1404
1405 tasklet_init(&tdc->tasklet, tegra_dma_tasklet,
1406 (unsigned long)tdc);
1407 spin_lock_init(&tdc->lock);
1408
1409 INIT_LIST_HEAD(&tdc->pending_sg_req);
1410 INIT_LIST_HEAD(&tdc->free_sg_req);
1411 INIT_LIST_HEAD(&tdc->free_dma_desc);
1412 INIT_LIST_HEAD(&tdc->cb_desc);
1413 }
1414
1415 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
1416 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
1417 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
1418
1419 tdma->global_pause_count = 0;
1420 tdma->dma_dev.dev = &pdev->dev;
1421 tdma->dma_dev.device_alloc_chan_resources =
1422 tegra_dma_alloc_chan_resources;
1423 tdma->dma_dev.device_free_chan_resources =
1424 tegra_dma_free_chan_resources;
1425 tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
1426 tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
1427 tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1428 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1429 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1430 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
1431 tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1432 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1433 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
1434 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
1435 tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1436 /*
1437 * XXX The hardware appears to support
1438 * DMA_RESIDUE_GRANULARITY_BURST-level reporting, but it's
1439 * only used by this driver during tegra_dma_terminate_all()
1440 */
1441 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
1442 tdma->dma_dev.device_config = tegra_dma_slave_config;
1443 tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
1444 tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
1445 tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
1446
1447 ret = dma_async_device_register(&tdma->dma_dev);
1448 if (ret < 0) {
1449 dev_err(&pdev->dev,
1450 "Tegra20 APB DMA driver registration failed %d\n", ret);
1451 goto err_irq;
1452 }
1453
1454 ret = of_dma_controller_register(pdev->dev.of_node,
1455 tegra_dma_of_xlate, tdma);
1456 if (ret < 0) {
1457 dev_err(&pdev->dev,
1458 "Tegra20 APB DMA OF registration failed %d\n", ret);
1459 goto err_unregister_dma_dev;
1460 }
1461
1462 dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n",
1463 cdata->nr_channels);
1464 return 0;
1465
1466 err_unregister_dma_dev:
1467 dma_async_device_unregister(&tdma->dma_dev);
1468 err_irq:
1469 while (--i >= 0) {
1470 struct tegra_dma_channel *tdc = &tdma->channels[i];
1471
1472 free_irq(tdc->irq, tdc);
1473 tasklet_kill(&tdc->tasklet);
1474 }
1475
1476 pm_runtime_disable(&pdev->dev);
1477 if (!pm_runtime_status_suspended(&pdev->dev))
1478 tegra_dma_runtime_suspend(&pdev->dev);
1479 return ret;
1480 }
1481
1482 static int tegra_dma_remove(struct platform_device *pdev)
1483 {
1484 struct tegra_dma *tdma = platform_get_drvdata(pdev);
1485 int i;
1486 struct tegra_dma_channel *tdc;
1487
1488 dma_async_device_unregister(&tdma->dma_dev);
1489
1490 for (i = 0; i < tdma->chip_data->nr_channels; ++i) {
1491 tdc = &tdma->channels[i];
1492 free_irq(tdc->irq, tdc);
1493 tasklet_kill(&tdc->tasklet);
1494 }
1495
1496 pm_runtime_disable(&pdev->dev);
1497 if (!pm_runtime_status_suspended(&pdev->dev))
1498 tegra_dma_runtime_suspend(&pdev->dev);
1499
1500 return 0;
1501 }
1502
1503 static int tegra_dma_runtime_suspend(struct device *dev)
1504 {
1505 struct tegra_dma *tdma = dev_get_drvdata(dev);
1506
1507 clk_disable_unprepare(tdma->dma_clk);
1508 return 0;
1509 }
1510
1511 static int tegra_dma_runtime_resume(struct device *dev)
1512 {
1513 struct tegra_dma *tdma = dev_get_drvdata(dev);
1514 int ret;
1515
1516 ret = clk_prepare_enable(tdma->dma_clk);
1517 if (ret < 0) {
1518 dev_err(dev, "clk_enable failed: %d\n", ret);
1519 return ret;
1520 }
1521 return 0;
1522 }
1523
1524 #ifdef CONFIG_PM_SLEEP
1525 static int tegra_dma_pm_suspend(struct device *dev)
1526 {
1527 struct tegra_dma *tdma = dev_get_drvdata(dev);
1528 int i;
1529 int ret;
1530
1531 /* Enable clock before accessing register */
1532 ret = pm_runtime_get_sync(dev);
1533 if (ret < 0)
1534 return ret;
1535
1536 tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);
1537 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1538 struct tegra_dma_channel *tdc = &tdma->channels[i];
1539 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1540
1541 /* Only save the state of DMA channels that are in use */
1542 if (!tdc->config_init)
1543 continue;
1544
1545 ch_reg->csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
1546 ch_reg->ahb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
1547 ch_reg->apb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBPTR);
1548 ch_reg->ahb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBSEQ);
1549 ch_reg->apb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBSEQ);
1550 if (tdma->chip_data->support_separate_wcount_reg)
1551 ch_reg->wcount = tdc_read(tdc,
1552 TEGRA_APBDMA_CHAN_WCOUNT);
1553 }
1554
1555 /* Disable clock */
1556 pm_runtime_put(dev);
1557 return 0;
1558 }
1559
1560 static int tegra_dma_pm_resume(struct device *dev)
1561 {
1562 struct tegra_dma *tdma = dev_get_drvdata(dev);
1563 int i;
1564 int ret;
1565
1566 /* Enable clock before accessing register */
1567 ret = pm_runtime_get_sync(dev);
1568 if (ret < 0)
1569 return ret;
1570
1571 tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen);
1572 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
1573 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
1574
1575 for (i = 0; i < tdma->chip_data->nr_channels; i++) {
1576 struct tegra_dma_channel *tdc = &tdma->channels[i];
1577 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
1578
1579 /* Only restore the state of DMA channels that are in use */
1580 if (!tdc->config_init)
1581 continue;
1582
1583 if (tdma->chip_data->support_separate_wcount_reg)
1584 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
1585 ch_reg->wcount);
1586 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_reg->apb_seq);
1587 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_reg->apb_ptr);
1588 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_reg->ahb_seq);
1589 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_reg->ahb_ptr);
1590 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
1591 (ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB));
1592 }
1593
1594 /* Disable clock */
1595 pm_runtime_put(dev);
1596 return 0;
1597 }
1598 #endif
1599
1600 static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
1601 SET_RUNTIME_PM_OPS(tegra_dma_runtime_suspend, tegra_dma_runtime_resume,
1602 NULL)
1603 SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
1604 };
1605
1606 static const struct of_device_id tegra_dma_of_match[] = {
1607 {
1608 .compatible = "nvidia,tegra148-apbdma",
1609 .data = &tegra148_dma_chip_data,
1610 }, {
1611 .compatible = "nvidia,tegra114-apbdma",
1612 .data = &tegra114_dma_chip_data,
1613 }, {
1614 .compatible = "nvidia,tegra30-apbdma",
1615 .data = &tegra30_dma_chip_data,
1616 }, {
1617 .compatible = "nvidia,tegra20-apbdma",
1618 .data = &tegra20_dma_chip_data,
1619 }, {
1620 },
1621 };
1622 MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
1623
1624 static struct platform_driver tegra_dmac_driver = {
1625 .driver = {
1626 .name = "tegra-apbdma",
1627 .pm = &tegra_dma_dev_pm_ops,
1628 .of_match_table = tegra_dma_of_match,
1629 },
1630 .probe = tegra_dma_probe,
1631 .remove = tegra_dma_remove,
1632 };
1633
1634 module_platform_driver(tegra_dmac_driver);
1635
1636 MODULE_ALIAS("platform:tegra20-apbdma");
1637 MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver");
1638 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1639 MODULE_LICENSE("GPL v2");
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