plat/bcm/include/bcm963xx/63148_map_part.h

   1 /*
   2 <:copyright-BRCM:2013:DUAL/GPL:standard
   3
   4    Copyright (c) 2013 Broadcom
   5    All Rights Reserved
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License, version 2, as published by
   9 the Free Software Foundation (the "GPL").
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16
  17 A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
  18 writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.
  20
  21 :>
  22 */
  23
  24 #ifndef __BCM63148_MAP_PART_H
  25 #define __BCM63148_MAP_PART_H
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 #include "bcmtypes.h"
  32
  33 #define PER_BASE                0xfffe0000
  34 #define REG_BASE                0x80000000
  35
  36 #define MEMC_PHYS_BASE          (REG_BASE + 0x00002000) /* DDR IO Buf Control */
  37 #define MEMC_SIZE               0x20000
  38
  39 #define PMC_PHYS_BASE           (REG_BASE + 0x00400000)
  40 #define PROC_MON_PHYS_BASE      (REG_BASE + 0x00480000)
  41 #define GICD_PHYS_BASE          (REG_BASE + 0x00031000)
  42 #define GICC_PHYS_BASE          (REG_BASE + 0x00032000)
  43
  44 #define B15_CTRL_PHYS_BASE      (REG_BASE + 0x00020000)
  45 #define B15_PHYS_BASE           (REG_BASE + 0x00030000)
  46
  47
  48 #define PERF_PHYS_BASE          (PER_BASE + 0x00008000) /* chip control */
  49 #define TIMR_PHYS_BASE          (PER_BASE + 0x00008080) /* timer registers */
  50 #define BOOTLUT_PHYS_BASE       (PER_BASE + 0x00010000)
  51
  52 #define PMC_BASE                PMC_PHYS_BASE
  53 #define PROC_MON_BASE           PROC_MON_PHYS_BASE
  54 #define TIMR_BASE               TIMR_PHYS_BASE
  55 #define BOOTLUT_BASE            BOOTLUT_PHYS_BASE
  56 #define B15_CTRL_BASE           B15_CTRL_PHYS_BASE
  57 #define B15_BASE                B15_PHYS_BASE
  58 #define GICC_BASE               GICC_PHYS_BASE
  59 #define GICD_BASE               GICD_PHYS_BASE
  60
  61 #ifndef __ASSEMBLER__
  62 /*
  63  * Power Management Control
  64  */
  65 typedef struct PmcCtrlReg {
  66         /* 0x00 */
  67         uint32 l1Irq4keMask;
  68         uint32 l1Irq4keStatus;
  69         uint32 l1IrqMipsMask;
  70         uint32 l1IrqMipsStatus;
  71         /* 0x10 */
  72         uint32 l2IrqGpMask;
  73         uint32 l2IrqGpStatus;
  74         uint32 gpTmr0Ctl;
  75         uint32 gpTmr0Cnt;
  76         /* 0x20 */
  77         uint32 gpTmr1Ctl;
  78         uint32 gpTmr1Cnt;
  79         uint32 hostMboxIn;
  80         uint32 hostMboxOut;
  81         /* 0x30 */
  82 #define PMC_CTRL_GP_FLASH_BOOT_STALL                  0x00000080
  83         uint32 gpOut;
  84         uint32 gpIn;
  85         uint32 gpInIrqMask;
  86         uint32 gpInIrqStatus;
  87         /* 0x40 */
  88         uint32 dmaCtrl;
  89         uint32 dmaStatus;
  90         uint32 dma0_3FifoStatus;
  91         uint32 unused0[3];      /* 0x4c-0x57 */
  92         /* 0x58 */
  93         uint32 l1IrqMips1Mask;
  94         uint32 diagControl;
  95         /* 0x60 */
  96         uint32 diagHigh;
  97         uint32 diagLow;
  98         uint32 badAddr;
  99         uint32 addr1WndwMask;
 100         /* 0x70 */
 101         uint32 addr1WndwBaseIn;
 102         uint32 addr1WndwBaseOut;
 103         uint32 addr2WndwMask;
 104         uint32 addr2WndwBaseIn;
 105         /* 0x80 */
 106         uint32 addr2WndwBaseOut;
 107         uint32 scratch;
 108         uint32 tm;
 109         uint32 softResets;
 110         /* 0x90 */
 111         uint32 eb2ubusTimeout;
 112         uint32 m4keCoreStatus;
 113         uint32 gpInIrqSense;
 114         uint32 ubSlaveTimeout;
 115         /* 0xa0 */
 116         uint32 diagEn;
 117         uint32 devTimeout;
 118         uint32 ubusErrorOutMask;
 119         uint32 diagCaptStopMask;
 120         /* 0xb0 */
 121         uint32 revId;
 122         uint32 gpTmr2Ctl;
 123         uint32 gpTmr2Cnt;
 124         uint32 legacyMode;
 125         /* 0xc0 */
 126         uint32 smisbMonitor;
 127         uint32 diagCtrl;
 128         uint32 diagStat;
 129         uint32 diagMask;
 130         /* 0xd0 */
 131         uint32 diagRslt;
 132         uint32 diagCmp;
 133         uint32 diagCapt;
 134         uint32 diagCnt;
 135         /* 0xe0 */
 136         uint32 diagEdgeCnt;
 137         uint32 unused1[4];      /* 0xe4-0xf3 */
 138         /* 0xf4 */
 139         uint32 iopPeriphBaseAddr;
 140         uint32 lfsr;
 141         uint32 unused2;         /* 0xfc-0xff */
 142 } PmcCtrlReg;
 143
 144 typedef struct PmcOutFifoReg {
 145         uint32 msgCtrl;         /* 0x00 */
 146         uint32 msgSts;          /* 0x04 */
 147         uint32 unused[14];      /* 0x08-0x3f */
 148         uint32 msgData[16];     /* 0x40-0x7c */
 149 } PmcOutFifoReg;
 150
 151 typedef struct PmcInFifoReg {
 152         uint32 msgCtrl;         /* 0x00 */
 153         uint32 msgSts;          /* 0x04 */
 154         uint32 unused[13];      /* 0x08-0x3b */
 155         uint32 msgLast;         /* 0x3c */
 156         uint32 msgData[16];     /* 0x40-0x7c */
 157 } PmcInFifoReg;
 158
 159 typedef struct PmcDmaReg {
 160         /* 0x00 */
 161         uint32 src;
 162         uint32 dest;
 163         uint32 cmdList;
 164         uint32 lenCtl;
 165         /* 0x10 */
 166         uint32 rsltSrc;
 167         uint32 rsltDest;
 168         uint32 rsltHcs;
 169         uint32 rsltLenStat;
 170 } PmcDmaReg;
 171
 172 typedef struct PmcTokenReg {
 173         /* 0x00 */
 174         uint32 bufSize;
 175         uint32 bufBase;
 176         uint32 idx2ptrIdx;
 177         uint32 idx2ptrPtr;
 178         /* 0x10 */
 179         uint32 unused[2];
 180         uint32 bufSize2;
 181 } PmcTokenReg;
 182
 183 typedef struct PmcPerfPowReg {
 184         /* 0x00 */
 185         uint32 dcacheHit;
 186         uint32 dcacheMiss;
 187         uint32 icacheHit;
 188         uint32 icacheMiss;
 189         /* 0x10 */
 190         uint32 instnComplete;
 191         uint32 wtbMerge;
 192         uint32 wtbNoMerge;
 193         uint32 itlbHit;
 194         /* 0x20 */
 195         uint32 itlbMiss;
 196         uint32 dtlbHit;
 197         uint32 dtlbMiss;
 198         uint32 jtlbHit;
 199         /* 0x30 */
 200         uint32 jtlbMiss;
 201         uint32 powerSubZone;
 202         uint32 powerMemPda;
 203         uint32 freqScalarCtrl;
 204         /* 0x40 */
 205         uint32 freqScalarMask;
 206 } PmcPerfPowReg;
 207
 208 typedef struct PmcDQMReg {
 209         /* 0x00 */
 210         uint32 cfg;
 211         uint32 _4keLowWtmkIrqMask;
 212         uint32 mipsLowWtmkIrqMask;
 213         uint32 lowWtmkIrqMask;
 214         /* 0x10 */
 215         uint32 _4keNotEmptyIrqMask;
 216         uint32 mipsNotEmptyIrqMask;
 217         uint32 notEmptyIrqSts;
 218         uint32 queueRst;
 219         /* 0x20 */
 220         uint32 notEmptySts;
 221         uint32 nextAvailMask;
 222         uint32 nextAvailQueue;
 223         uint32 mips1LowWtmkIrqMask;
 224         /* 0x30 */
 225         uint32 mips1NotEmptyIrqMask;
 226         uint32 autoSrcPidInsert;
 227 } PmcDQMReg;
 228
 229 typedef struct PmcCntReg {
 230         uint32 cntr[10];
 231         uint32 unused[6];       /* 0x28-0x3f */
 232         uint32 cntrIrqMask;
 233         uint32 cntrIrqSts;
 234 } PmcCntReg;
 235
 236 typedef struct PmcDqmQCtrlReg {
 237         uint32 size;
 238         uint32 cfga;
 239         uint32 cfgb;
 240         uint32 cfgc;
 241 } PmcDqmQCtrlReg;
 242
 243 typedef struct PmcDqmQDataReg {
 244         uint32 word[4];
 245 } PmcDqmQDataReg;
 246
 247 typedef struct PmcDqmQMibReg {
 248         uint32 qNumFull[32];
 249         uint32 qNumEmpty[32];
 250         uint32 qNumPushed[32];
 251 } PmcDqmQMibReg;
 252
 253 typedef struct Pmc {
 254         uint32 baseReserved;            /* 0x0000 */
 255         uint32 unused0[1023];
 256         PmcCtrlReg ctrl;                /* 0x1000 */
 257
 258         PmcOutFifoReg outFifo;          /* 0x1100 */
 259         uint32 unused1[32];             /* 0x1180-0x11ff */
 260         PmcInFifoReg inFifo;            /* 0x1200 */
 261         uint32 unused2[32];             /* 0x1280-0x12ff */
 262
 263         PmcDmaReg dma[2];               /* 0x1300 */
 264         uint32 unused3[48];             /* 0x1340-0x13ff */
 265
 266         PmcTokenReg token;              /* 0x1400 */
 267         uint32 unused4[121];            /* 0x141c-0x15ff */
 268
 269         PmcPerfPowReg perfPower;        /* 0x1600 */
 270         uint32 unused5[47];             /* 0x1644-0x16ff */
 271
 272         uint32 msgId[32];               /* 0x1700 */
 273         uint32 unused6[32];             /* 0x1780-0x17ff */
 274
 275         PmcDQMReg dqm;                  /* 0x1800 */
 276         uint32 unused7[50];             /* 0x1838-0x18ff */
 277
 278         PmcCntReg hwCounter;            /* 0x1900 */
 279         uint32 unused8[46];             /* 0x1948-0x19ff */
 280
 281         PmcDqmQCtrlReg dqmQCtrl[32];    /* 0x1a00 */
 282         PmcDqmQDataReg dqmQData[32];    /* 0x1c00 */
 283         uint32 unused9[64];             /* 0x1e00-0x1eff */
 284
 285         uint32 qStatus[32];             /* 0x1f00 */
 286         uint32 unused10[32];            /* 0x1f80-0x1fff */
 287
 288         PmcDqmQMibReg qMib;             /* 0x2000 */
 289         uint32 unused11[1952];          /* 0x2180-0x3ffff */
 290
 291         uint32 sharedMem[8192];         /* 0x4000-0xbffc */
 292 } Pmc;
 293
 294 #define PMC ((volatile Pmc * const) PMC_BASE)
 295
 296 /*
 297  * Process Monitor Module
 298  */
 299 typedef struct PMRingOscillatorControl {
 300         uint32 control;
 301         uint32 en_lo;
 302         uint32 en_mid;
 303         uint32 en_hi;
 304         uint32 idle_lo;
 305         uint32 idle_mid;
 306         uint32 idle_hi;
 307 } PMRingOscillatorControl;
 308
 309 #define RCAL_0P25UM_HORZ          0
 310 #define RCAL_0P25UM_VERT          1
 311 #define RCAL_0P5UM_HORZ           2
 312 #define RCAL_0P5UM_VERT           3
 313 #define RCAL_1UM_HORZ             4
 314 #define RCAL_1UM_VERT             5
 315 #define PMMISC_RMON_EXT_REG       ((RCAL_1UM_VERT + 1)/2)
 316 #define PMMISC_RMON_VALID_MASK    (0x1<<16)
 317 typedef struct PMMiscControl {
 318         uint32 gp_out;
 319         uint32 clock_select;
 320         uint32 unused[2];
 321         uint32 misc[4];
 322 } PMMiscControl;
 323
 324 typedef struct PMSSBMasterControl {
 325         uint32 control;
 326 #define PMC_SSBM_CONTROL_SSB_START      (1<<15)
 327 #define PMC_SSBM_CONTROL_SSB_ADPRE      (1<<13)
 328 #define PMC_SSBM_CONTROL_SSB_EN         (1<<12)
 329 #define PMC_SSBM_CONTROL_SSB_CMD_SHIFT  (10)
 330 #define PMC_SSBM_CONTROL_SSB_CMD_MASK   (0x3 << PMC_SSBM_CONTROL_SSB_CMD_SHIFT)
 331 #define PMC_SSBM_CONTROL_SSB_CMD_READ   (2)
 332 #define PMC_SSBM_CONTROL_SSB_CMD_WRITE  (1)
 333 #define PMC_SSBM_CONTROL_SSB_ADDR_SHIFT (0)
 334 #define PMC_SSBM_CONTROL_SSB_ADDR_MASK  (0x3ff << PMC_SSBM_CONTROL_SSB_ADDR_SHIFT)
 335         uint32 wr_data;
 336         uint32 rd_data;
 337 } PMSSBMasterControl;
 338
 339 typedef struct PMEctrControl {
 340         uint32 control;
 341         uint32 interval;
 342         uint32 thresh_lo;
 343         uint32 thresh_hi;
 344         uint32 count;
 345 } PMEctrControl;
 346
 347 typedef struct PMBMaster {
 348         uint32 ctrl;
 349 #define PMC_PMBM_START          (1 << 31)
 350 #define PMC_PMBM_TIMEOUT        (1 << 30)
 351 #define PMC_PMBM_SLAVE_ERR      (1 << 29)
 352 #define PMC_PMBM_BUSY           (1 << 28)
 353 #define PMC_PMBM_Read           (0 << 20)
 354 #define PMC_PMBM_Write          (1 << 20)
 355         uint32 wr_data;
 356         uint32 timeout;
 357         uint32 rd_data;
 358         uint32 unused[4];
 359 } PMBMaster;
 360
 361 typedef struct PMAPVTMONControl {
 362         uint32 control;
 363         uint32 reserved;
 364         uint32 cfg_lo;
 365         uint32 cfg_hi;
 366         uint32 data;
 367         uint32 vref_data;
 368         uint32 unused[2];
 369         uint32 ascan_cfg;
 370         uint32 warn_temp;
 371         uint32 reset_temp;
 372         uint32 temp_value;
 373         uint32 data1_value;
 374         uint32 data2_value;
 375         uint32 data3_value;
 376 } PMAPVTMONControl;
 377
 378 typedef struct PMUBUSCfg {
 379         uint32 window[8];
 380         uint32 control;
 381 } PMUBUSCfg;
 382
 383 typedef struct ProcessMonitorRegs {
 384         uint32 MonitorCtrl;             /* 0x00 */
 385         uint32 unused0[7];
 386         PMRingOscillatorControl ROSC;   /* 0x20 */
 387         uint32 unused1;
 388         PMMiscControl Misc;             /* 0x40 */
 389         PMSSBMasterControl SSBMaster;   /* 0x60 */
 390         uint32 unused2[5];
 391         PMEctrControl Ectr;             /* 0x80 */
 392         uint32 unused3[11];
 393         PMBMaster PMBM[2];              /* 0xc0 */
 394         PMAPVTMONControl APvtmonCtrl;   /* 0x100 */
 395         uint32 unused4[9];
 396         PMUBUSCfg UBUSCfg;              /* 0x160 */
 397 } ProcessMonitorRegs;
 398
 399 #define PROCMON ((volatile ProcessMonitorRegs * const) PROC_MON_BASE)
 400
 401
 402 /*
 403  * Timer
 404  */
 405 typedef struct Timer {
 406         uint32 TimerCtl0;       /* 0x00 */
 407         uint32 TimerCtl1;       /* 0x04 */
 408         uint32 TimerCtl2;       /* 0x08 */
 409         uint32 TimerCtl3;       /* 0x0c */
 410 #define TIMERENABLE             (1 << 31)
 411 #define RSTCNTCLR               (1 << 30)
 412
 413         uint32 TimerCnt0;       /* 0x10 */
 414         uint32 TimerCnt1;       /* 0x14 */
 415         uint32 TimerCnt2;       /* 0x18 */
 416         uint32 TimerCnt3;       /* 0x1c */
 417 #define TIMER_COUNT_MASK        0x3FFFFFFF
 418
 419         uint32 TimerMask;       /* 0x20 */
 420 #define TIMER0EN                (1 << 0)
 421 #define TIMER1EN                (1 << 1)
 422 #define TIMER2EN                (1 << 2)
 423 #define TIMER3EN                (1 << 3)
 424
 425         uint32 TimerInts;       /* 0x24 */
 426 #define TIMER0                  (1 << 0)
 427 #define TIMER1                  (1 << 1)
 428 #define TIMER2                  (1 << 2)
 429 #define TIMER3                  (1 << 3)
 430 #define WATCHDOG                (1 << 4)
 431
 432         uint32 WatchDogDefCount;        /* 0x28 */
 433
 434         /* Write 0xff00 0x00ff to Start timer
 435          * Write 0xee00 0x00ee to Stop and re-load default count
 436          * Read from this register returns current watch dog count
 437          */
 438         uint32 WatchDogCtl;     /* 0x2c */
 439
 440         /* Number of 50-MHz ticks for WD Reset pulse to last */
 441         uint32 WDResetCount;    /* 0x30 */
 442         uint32 SoftRst;         /* 0x34 */
 443 #define SOFT_RESET              (1 << 0)
 444         uint32 ResetStatus;     /* 0x38 */
 445 #define PCIE_RESET_STATUS       0x10000000
 446 #define SW_RESET_STATUS         0x20000000
 447 #define HW_RESET_STATUS         0x40000000
 448 #define POR_RESET_STATUS        0x80000000
 449 #define RESET_STATUS_MASK       0xF0000000
 450 } Timer;
 451
 452 #define TIMER ((volatile Timer * const) TIMR_BASE)
 453
 454 /*
 455  * B15 CFG
 456  */
 457 typedef struct B15ArchRegion {
 458         uint32 addr_ulimit;
 459         uint32 addr_llimit;
 460         uint32 permission;
 461         uint32 access_right_ctrl;
 462 } B15ArchRegion;
 463
 464 typedef struct B15Arch {
 465         B15ArchRegion region[8];
 466         uint32 unused[95];
 467         uint32 scratch;
 468 } B15Arch;
 469
 470 typedef struct B15CpuBusRange {
 471 #define ULIMIT_SHIFT 4
 472 #define BUSNUM_MASK 0x0000000FU
 473
 474 #define BUSNUM_UBUS 1
 475 #define BUSNUM_RBUS 2
 476 #define BUSNUM_RSVD 3
 477 #define BUSNUM_MCP0 4
 478 #define BUSNUM_MCP1 5
 479 #define BUSNUM_MCP2 6
 480
 481         uint32 ulimit;
 482         uint32 llimit;
 483 } B15CpuBusRange;
 484
 485 typedef struct B15CpuAccessRightViol {
 486         uint32 addr;
 487         uint32 upper_addr;
 488         uint32 detail_addr;
 489 } B15CpuAccessRightViol;
 490
 491 typedef struct B15CpuBPCMAVS {
 492         uint32 bpcm_id;
 493         uint32 bpcm_capability;
 494         uint32 bpcm_ctrl;
 495         uint32 bpcm_status;
 496         uint32 avs_rosc_ctrl;
 497         uint32 avs_rosc_threshold;
 498         uint32 avs_rosc_cnt;
 499         uint32 avs_pwd_ctrl;
 500 } B15CpuBPCMAVS;
 501
 502 typedef struct B15CpuCtrl {
 503         B15CpuBusRange bus_range[11];   /* 0x0 */
 504         uint32 secure_reset_hndshake;
 505         uint32 secure_soft_reset;
 506         B15CpuAccessRightViol access_right_viol[2];     /* 0x60 */
 507         uint32 rac_cfg0;
 508         uint32 rac_cfg1;
 509         uint32 rac_flush;               /* 0x80 */
 510         uint32 cpu_power_cfg;
 511         uint32 cpu0_pwr_zone_ctrl;
 512         uint32 cpu1_pwr_zone_ctrl;
 513         uint32 cpu2_pwr_zone_ctrl;      /* 0x90 */
 514         uint32 cpu3_pwr_zone_ctrl;
 515         uint32 l2biu_pwr_zone_ctrl;
 516         uint32 cpu0_pwr_zone_cfg1;
 517         uint32 cpu0_pwr_zone_cfg2;      /* 0xa0 */
 518         uint32 cpu1_pwr_zone_cfg1;
 519         uint32 cpu1_pwr_zone_cfg2;
 520         uint32 cpu2_pwr_zone_cfg1;
 521         uint32 cpu2_pwr_zone_cfg2;      /* 0xb0 */
 522         uint32 cpu3_pwr_zone_cfg1;
 523         uint32 cpu3_pwr_zone_cfg2;
 524         uint32 l2biu_pwr_zone_cfg1;
 525         uint32 l2biu_pwr_zone_cfg2;     /* 0xc0 */
 526         uint32 cpu0_pwr_freq_scalar_ctrl;
 527         uint32 cpu1_pwr_freq_scalar_ctrl;
 528         uint32 cpu2_pwr_freq_scalar_ctrl;
 529         uint32 cpu3_pwr_freq_scalar_ctrl;       /* 0xd0 */
 530         uint32 l2biu_pwr_freq_scalar_ctrl;
 531         B15CpuBPCMAVS cpu_bpcm_avs[4];  /* 0xd8 */
 532         B15CpuBPCMAVS l2biu_bpcm_avs;   /* 0x158 */
 533         uint32 reset_cfg;               /* 0x178 */
 534         uint32 clock_cfg;
 535         uint32 misc_cfg;                /* 0x180 */
 536         uint32 credit;
 537         uint32 therm_throttle_temp;
 538         uint32 term_throttle_irq_cfg;
 539         uint32 therm_irq_high;          /* 0x190 */
 540         uint32 therm_irq_low;
 541         uint32 therm_misc_threshold;
 542         uint32 therm_irq_misc;
 543         uint32 defeature;               /* 0x1a0 */
 544         uint32 defeature_key;
 545         uint32 debug_rom_addr;
 546         uint32 debug_self_addr;
 547         uint32 debug_tracectrl;         /* 0x1b0 */
 548         uint32 axi_cfg;
 549         uint32 revision;
 550         uint32 ubus_cfg_window[8];      /* 0x1bc */
 551         uint32 ubus_cfg;                /* 0x1dc */
 552         uint32 unused[135];
 553         uint32 scratch;                 /* 0x3fc */
 554 } B15CpuCtrl;
 555
 556 typedef struct B15Ctrl {
 557         uint32 unused0[1024];
 558         B15Arch arch;                   /* 0x1000 */
 559         uint32 unused1[896];
 560         B15CpuCtrl cpu_ctrl;            /* 0x2000 */
 561 } B15Ctrl;
 562
 563 #define B15CTRL ((volatile B15Ctrl *const) B15_CTRL_BASE)
 564
 565 #endif /* __ASSEMBLER__ */
 566
 567 #ifdef __cplusplus
 568 }
 569 #endif
 570
 571 #endif